16 bit alu in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( r : in std_logic_vector(15 downto 0);
w : in std_logic_vector(15 downto 0);
d : in std_logic_vector(3 downto 0);
clk : in std_logic;
f : out std_logic_vector(15 downto 0));
end alu;
architecture behavioral of alu is
begin
process(r,w,d,clk)
begin
if clk'event and clk='1' then
case d is
when "0000" =>f<= w and r;
when "0001" =>f<= w or r;
when "0010" =>f<= w nor r;
when "0011" =>f<= w xor r;
when "0100" =>f<= w xnor r;
when "0101" =>f<= w nand r;
when "0110" =>f<= not r;
when "0111" =>f<= w + r;
when "1000" =>f<= r - w;
when "1001" =>f<= r+"0000000000000001";
when "1010" =>f<= w-"0000000000000001";
when "1011" =>f<= r;
when others =>f<= "0000000000000000";
end case;
end if;
end process;
end behavioral;


test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY alut IS
END alut;

ARCHITECTURE behavior OF alut IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT alu
PORT(
r : IN std_logic_vector(15 downto 0);
w : IN std_logic_vector(15 downto 0);
d : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
f : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;


--Inputs
signal r : std_logic_vector(15 downto 0) := (others => '0');
signal w : std_logic_vector(15 downto 0) := (others => '0');
signal d : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal f : std_logic_vector(15 downto 0);

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
r => r,
w => w,
d => d,
clk => clk,
f => f
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;


-- insert stimulus here
r<="0000000000000010";
w<="0000000000000011";
wait for 20 ns;
d<="0000";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0001";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0010";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0011";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0100";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0101";
wait for 20 ns;
r<="0000000000000010";
d<="0110";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="0111";
wait for 20 ns;
r<="0000000000000010";
w<="0000000000000011";
d<="1000";
wait for 20 ns;
r<="0000000000000010";
d<="1001";
wait for 20 ns;
w<="0000000000000011";
d<="1010";
wait for 20 ns;
r<="0000000000000010";
d<="1011";
wait for 20 ns;
wait;
end process;
END;