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4 Chapter 3 PDF
4 Chapter 3 PDF
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Bias Connections [5]
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Diode Circuit Analysis [5], [6]
Figure 3.2 shows a Diode circuit containing a voltage source and a
resistor. Here, in order to analyze the current passing the diode (ID) and the voltage
across the diode (VD), we can use 4 methods as mentioned below.
Mathematical Model
Ideal Diode Model
Constant Voltage Drop (CVD) Model
Complete Diode Model
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3.3.1 Analysis Using the Mathematical Model
−10 + 104ID + VD = 0
104ID + VD = 10 (1)
Substitute (2) in (1) with IS = 10-13 A,VT = 0.025 V. (for Si diode @ room
temperature)
10 -9 [e 40VD 1] VD 10 (3)
Solve (3) for VD, then VD = 0.5742 V and ID = 9.426 10-4 A = 0.9426 mA
In Figure 3.5, the ideal V-I characteristic curve graphically depicts the
ideal diode operation. The diode is assumed to have a zero voltage across it when
forward-biased, as indicated by the portion of the curve on the positive vertical
axis. Since the reverse current is neglected, its value is assumed to be zero, as
indicated in Figure 3.5 by the portion of the curve on the negative horizontal axis.
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Figure 3.4 The ideal model of a diode. [5]
(a) Equivalent circuit under forward bias (on or short circuit).
(b) Equivalent circuit under reverse bias (off or open circuit).
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Figure 3.5 Ideal V-I characteristic curve (blue) [5]
Therefore, using ideal diode model under this diode circuit condition, we can
conclude that;
𝑉𝑆
For forward bias: 𝑉𝐹 = 0 V, and 𝐼𝐹 =
𝑅
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Example 2: Use ideal diode model to analyze ID and VD from Figure 3.3.
1. Use the ideal diode model for this circuit condition (from Figure 3.3)
(Figure 3.3)
2. Because the voltage source appears to be trying to forward bias the diode,
we assume that the diode is on or acts like a short circuit, see Figure 3.6.
𝑉𝑆 10 V
3. Find ID: 𝐼𝐷 = = = 1 mA
𝑅 10 k
4. The current ID > 0, which is consistent with the assumption that the diode
is on.
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Example 3: Use ideal diode model to analyze ID and VD of both diodes from
Figure 3.7.
Solution :
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First try : Both diodes are on. Under this assumption, the diode circuit from
Figure 3.7 becomes
The result ID1 < 0 is inconsistent with our assumption that D 1 is on. Our
assumption must be incorrect.
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Second try : D1 is off and D2 is on. Under this assumption, the diode circuit from
Figure 3.7 becomes
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Since ID2 > 0 (D2 is on) and VD1 < 0 (D1 is off or reverse biased), they are
consistent with our assumptions.
Example 4: Determine ID1, ID2 , VD1 and VD2, using ideal diode model.
First try : Assume diode 1 is on, diode 2 is off. Under this assumption, the diode
circuit from Figure 3.11 becomes
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Second try : Assume both diodes are off. Under this assumption, the diode circuit
from Figure 3.11 becomes
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3.3.3 Constant Voltage Drop (CVD) Model or Practical Diode Model
The Constant Voltage Drop (CVD) Model (or Practical Diode Model)
includes the barrier potential. When the diode is forward-biased, it is equivalent to
a closed switch in series with a small equivalent voltage source (V F) equal to the
barrier potential (0.7 V for Si diode, 0.3 V for Ge diode) with the positive side
toward the anode, as indicated in Figure 3.14(a). This equivalent voltage source
represents the barrier potential that must be exceeded by the bias voltage before the
diode will conduct and is not an active source of voltage. When conducting, a
voltage drop of 0.7 V appears across the Si diode or 0.3 V appears across the Ge
diodes.
The characteristic curve for the practical diode model is shown in Figure
3.15. Since the barrier potential is included, the diode is assumed to have a voltage
across it when forward-biased, as indicated by the portion of the curve to the right
of the origin.
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Figure 3.15 V-I characteristic curve (blue) of CVD model for Si diode. [5]
Therefore, using CVD model under this diode circuit condition, we can conclude
that;
𝑉𝑆 − 𝑉𝐹 − 𝑉𝑅𝐿𝑖𝑚𝑖𝑡 = 0
𝐼𝑅 = 0 A , and 𝑉𝑅 = − 𝑉𝑆
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Example 5: Use CVD model to analyze ID and VD from Figure 3.3.
Solution : Consider from 4 steps to analyze ID and VD in the diode circuit:
1. Use the CVD model for this circuit condition (from Figure 3.3)
(Figure 3.3)
2. Because the voltage source appears to be trying to forward bias the diode,
we assume that the diode is on, and we can replace Si diode by V F = 0.7 V,
see Figure 3.16.
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3. Find ID:
4. The current ID > 0, which is consistent with the assumption that the
diode is on.
Example 6: Use CVD model to analyze ID1, ID2, ID3, VD1, VD2, and VD3 .
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Solution : Here, we assume D1 = off, D2 = on, D3 = on.
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Example 7: Using CVD model, calculate VO, ID1, ID2, and I for the following
conditions:
(a) V1 = V2 = 0 V
(b) V1 = 20 V, V2 = 0 V
Solution :
10 5I 0.7 5* I / 2
I 1.24 A
I D1 I D2 I / 2 0.62 A
V0 0.7 5* I D1 (or I D2 ) 3.8 V
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Figure 3.20 For Example 7
I D1 = 0 A______#
I = I D2
10 = 5I + 0.7 + 5I D2
I = 9.3 A = I D2 ______#
V0 = 0.7 + 5I D2
= 0.7 + 5 (9.3)
= 5.35 V______#
1. Using ideal diode model, calculate the voltage across each diode and the current
flowing through each diode in Figure 3.22 (a), (b) and (c).
2. Using ideal diode model , calculate ID1, ID2 in the circuit for each case.
(1) VIN = 0 V
(2) VIN = 10 V
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Figure 3.23 For problem 2
3. Assume D1, D2 and D3 are Si diodes. Find ID1, ID2, ID3, VD1, VD2 and VD3 in the
circuit of Figure 3.24, using the ideal diode model.
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4. Assume D1 and D2 are Si diodes. Find ID1, ID2, VD1, VD2 and VO in the circuit of
Figure 3.25, using the ideal diode model.
ID1
2 k
-5V
_
+ VD1
_
+ VD2
0V VO
1 k
ID2
1 k
-5V
Figure 3.25 For problem 4
5. Assume D1 and D2 are Si diodes. Find ID1, ID2, VD1, VD2 and IO in the circuit of
Figure 3.26, using the ideal diode model.
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6. Using CVD model, assume D1, D2, D3 are Si diodes. Calculate VOUT and the
currents ID1, ID2, ID3 and I for the following input conditions:
(a) V1 = V2 = 0 V
(b) V1 = 5 V, V2 = 2 V
+ 10 V
I
0.55 K D1 10 K
V1
ID1
VOUT
ID2
V2 ID3
0.55 K
K D2 D3
+5V
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7. Let Von (or VF) = 0.6 V. Determine ID and VD in the circuit for each condition,
using the CVD model.
(a) V1 = 15 V, V2 = 10 V
(b) V1 = 10 V, V2 = 15 V
8. (a) Assume D1 and D2 are Si diode, Find I, VOUT, ID1 and ID2 in the circuit, using
the CVD model.
(b) Assume D1 is Si diode but D2 is Ge diode, Find I, VOUT, ID1 and ID2 in the
circuit, using CVD model.
+ 10 V
I
ID1 ID2
D1 D2
+
VOUT 5 K
+ 10 V
+ ID2
VD2
_
5A
5 10
VD1 +
10
5 ID1
_
VD3
+
ID3
+5V
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10. Assume the diode shown here is Ge diode. Find I D, VD and IX in the circuit of
Figure 3.31, using the CVD model.
11. Find ID1, ID2, VD1, VD2 and VO in the circuit of Figure 3.32, using the CVD
model. Assume D1 is Si diode and D2 is Ge diode.
As shown in Figure 3.33, the first block in a dc power supply is the power
transformer. This block provides the appropriate sinusoidal amplitude for the dc
power supply. Next, the diode rectifier converts the input sinusoid v s to a unipolar
pulsating waveform output. This pulsating waveform makes it unsuitable as a dc
source for electronic circuits, hence the need for a filter. The variations in the
magnitude of the rectifier output are considerably reduced by the filter. The output
of the rectifier filter still contains a time-component, known as ripple. To reduce
the ripple and to stabilized the magnitude of the dc output voltage, a voltage
regulator is employed.
Power Transformers
Basically, a transformer consists of at least two windings, or coils,
wrapped around a laminated iron core, see Figure 3.34. A transformer may have
multiple secondaries, and one or more of these windings may be center-tapped.
Here, the symbols of a normal transformer and a center-tapped transformer are
shown in Figure 3.35 (a) and (b), respectively.
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Figure 3.34 A transformer with two windings.
(a) (b)
Here, the dots are used to indicate the phase of the transformer. When the output
waveform is in phase with the input waveform, we can use Figure 3.36 (a) to
shows that condition. However, Figure 3.36 (b) is used when the output waveform
in 180 out of phase with the input waveform. Moreover, Figure 3.37 shows the
how to use 2 dots to indicate the phase of the output waveform for the center-
tapped transformer.
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(a) In Phase
(a) Referred to the end of each winding (b) Referred to the center tap
Rectifiers
A rectifier circuit converts an ac voltage to a pulsating DC voltage. Three
types of rectifier circuits are discussed here.
When the input voltage goes negative during the second half of its cycle,
the diode is reverse-biased. There is no current, so the voltage across the load
resistor is 0 V, as shown in Figure 3.38(b). The net result is that only the positive
half-cycles of the ac input voltage appear across the load. Since the output does not
change polarity, it is a pulsating dc voltage with a frequency of 60 Hz, as shown in
part (c).
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Figure 3.38 Half-wave rectifier operation. [5]
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The comparison between input and output waveform of the half-wave
rectifier using CVD diode model is shown in Figure 3.39.
VO(p)
Here, The average value of the half-wave rectified output voltage is the
value you would measure on a dc voltmeter. Mathematically, it is determined by
𝑉𝑂 (𝑝) 𝑉𝑝 −𝑉𝑜𝑛 𝑉𝑝 −0.7
𝑉𝑎𝑣 = = =
PIV = Vp
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Figure 3.40 PIV occurs at the peak of each negative half-cycle. [6]
(a)
V(t)
5V
0V t (s)
(b)
V(t)
20 V
10 V
0V t (s)
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(c)
V(t)
5V
0V t (s)
–15 V
Solution:
Vout(p) 5
(a) Vav = V
(20-10) 10
(b) Vav =10 + 10 V
(5-(-15)) 20
(c) Vav = -15 + 15 V
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Example 9: Draw the output voltages of each rectifier for the indicated input
voltages, as shown in Figure 3.42. The 1N4001 and 1N4003 are specific rectifier
diodes.
(a)
(b)
Solution :
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The output voltage waveforms are shown in Figure 3.43.
.
Example 10: Draw the output voltage waveform for the circuit and include the
voltage.
Si diode
5V
+ +
0V R = 1 kΩ Vout
Vin Vin
– –
−5 V
Solution :
5V
0V t (s)
–4.3 V
–5 V
Vout
Figure 3.45 Vout and Vin waveform
Example 11: Consider this circuit, assuming the practical diode model.
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Solution : (a) Vin ( pri ) 150 Vrms 150* 2
212.13 V( p )
1
Vin (sec) * 212.13 V( p )
4
53.03 V( p )
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Figure 3.48 For Example 11
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3.7.2 Center-tapped full-wave rectifiers
A full-wave rectifier allows unidirectional (one-way) current through the
load during the entire 360 of the input cycle, whereas a half-wave rectifier allows
current through the load only during one-half of the cycle. The result of full-wave
rectification is an output voltage with a frequency twice the input frequency and
that pulsates every half-cycle of the input, as shown in Figure 3.50.
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For a positive half-cycle of the input voltage, the polarities of the
secondary voltages are as shown in Figure 3.52(a). This condition forward-biases
diode D1 and reverse-biases diode D2. The current path is through D1 and the load
resistor RL, as indicated. For a negative half-cycle of the input voltage, the voltage
polarities on the secondary are as shown in Figure 3.52(b). This condition reverse-
biases D1 and forward-biases D2. The current path is through D2 and RL, as
indicated. Because the output current during both the positive and negative
portions of the input cycle is in the same direction through the load, the output
voltage developed across the load resistor is a full-wave rectified dc voltage, as
shown.
Figure 3.52 Basic operation of a center-tapped full-wave rectifier. Note that the
current through the load resistor is in the same direction during the entire input
cycle, so the output voltage always has the same polarity. [5]
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The comparison between input and output waveform of the center-tapped full-
wave rectifier using CVD diode model is shown in Figure 3.53.
The ripple frequency fr(FW) is doubled from the line frequency. Therefore,
fr (FW) = 2fline
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Since each diode conducts only each half of the cycles, the average current through
each diode is
When the total secondary voltage Vsec has the polarity shown, the
maximum anode voltage of D1 is +Vp(sec)/2 and the maximum anode voltage of D2
is –Vp(sec)/2. Since D1 is assumed to be forward-biased, its cathode is at the same
voltage as its anode minus the diode drop; this is also the voltage on the cathode of
D2.
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The peak inverse voltage across D2 is
Example 12:
(a) Show the voltage waveforms across each half of the secondary
winding and across RL when a 100 V peak sine wave is applied to the primary
winding in Figure 3.55.
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Solution:
(a) The transformer turns ratio n = 0.5. The total peak secondary voltage is
V p (sec) 0.5 (100 V ) 50 V
V p (sec)
25 V
2
This is a 25 V peak across each half of the secondary with respect to the
ground.
Vp (sec)
Vout ( peak ) Von
2
25 0.7 24.3 V
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Example 13: Consider this circuit, assuming the practical diode model.
Solution:
Vout ( p ) Vp 10 V 0.7 V
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Here, V pri ( p ) 120* 2 169.7V( p )
1
Vsec( p ) *169.7 42.43V( p )
4
Vsec( p )
Veach ( p ) Vs ( p ) V p
2
21.21 V( p )
Vout ( p ) V p 10 V 0.7 V
21.21 10 0.7
30.51 V( p )
30.51v
20.51v
Vav1
10v
Vav Vout(p)=30.51
v
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(b)
(c)
From Figure 3.61, two diodes are always in series with the load resistor
during both the positive and negative half-cycles. If these diode drops are taken
into account, the output voltage is
Figure 3.61 Bridge operation during a positive half-cycle of the primary and
secondary voltages. [5]
fr (FW) = 2fline
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The comparison between input and output waveform of the bridge full-wave
rectifier using CVD diode model is shown in Figure 3.62.
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Peak Inverse Voltage (PIV) for bridge full-wave rectifier:
To determine the peak inverse voltage (PIV) of each diode, consider the
circuit during the positive half cycles. Apply KVL to the loop formed by D 4, D2
and R.
Example 14: Determine the peak output voltage for the bridge rectifier in this
figure. Assuming the practical model, what PIV rating is required for the diode?
The transformer is specified to have a 12 Vrms secondary voltage for the standard
110 V across the primary.
Solution :
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The PIV rating for each diode is
Homework 4
1. Draw the output voltage of each rectifier for the indicated input voltages, as
shown in this figure 3.64.
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2. Determine the peak value of the output voltage if the turn ratio is 0.5.
3. Consider the circuit in Figure 3.66, assuming the practical diode model.
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4. Consider the circuit in Figure 3.67, assuming the practical diode model.
(b) Find the peak voltage across each half of the secondary.
15 : 2
1
120 Vrms
60 Hz
+
RL = 10
Vout
_
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7. (a) Consider the circuit in Figure 3.70 (a), assuming the practical diode model.
Sketch the output voltage waveform across RL. Assume Von = 0.7 V for each diode.
(b) Consider the circuit in Figure 3.70 (b), assuming the practical diode model.
Sketch the output voltage waveform across RL. Assume Von = 0.7 V for each diode.
45 turns
+ 10
120 Vrms
30 turns
- 45 turns +
RL = 15
VOUT
_
(a)
+ 60 turns 10
120 Vrms
30 turns
+
- +
30 turns
RL = 15
VOUT
_
(b)
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8. (a) Consider the circuit in Figure 3.71(a), assuming the CVD model. Sketch the
output voltage waveform across 10 Ω resistor, and then find the average voltage
(Vav). Assume Von = 0.7 V for each diode.
(b) Consider the circuit in Figure 3.71(b), assuming the CVD model. Sketch the
output voltage waveform across 10 Ω resistor, and then find the average voltage
(Vav). Assume Von = 0.7 V for each diode.
(a)
(b)
Figure 3.71 For problem 8.
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9. Consider the Center-tapped full wave rectifier circuits in Figure 3.72 (a) and that
in Figure 3.72 (b), then sketch the output waveform of the voltage across R L (VOUT)
in both circuits.
5 : 1
Si Diode
100 Vrms
Si Diode +
1 k VOUT
_
(a)
5 : 1 2 k
15
Si Diode
100 Vrms
Si Diode +
1 k VOUT
_
(b)
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10. Determine the peak output voltage for the bridge rectifier in this figure.
Assuming the practical model, what PIV rating is required for the diode? Assume
that the primary voltage of the transformer is 200 VP-P and the transformer turns
ratio n = 0.25.
11. Using practical diode model, find the output voltage across R L, PIV of each
diode and plot the output waveform of output voltage across RL.
10 : 1
150 Vrms 1
60 Hz
+
Vout
RL = 10 _
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12. (a) Sketch the output voltage of the bridge rectifier in Figure 3.75. Notice that
all the Si diodes are reversed from the normal full-wave bridge rectifier circuits.
4:1
120 V(p-p)
+
RL Vout
-
Si 5V
Ge
60 turns 15 turns
Ge +
Si
100 VOUT
_
200 Vp-p
60 Hz
Figure 3.76 For problem 13.
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Capacitive Filters [5], [6]
In most power supply applications, AC power line must be converted to
an approximately constant DC voltage. The pulsating DC output of a half-wave
rectifier or that of a full-wave rectifier must be filtered to reduce the large voltage
variations. Figure 3.77 illustrates the filtering concept showing a nearly smooth DC
output voltage from the filter. The small amount of fluctuation in the filter output
voltage is called ripple.
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During the first quarter of the next cycle, as illustrated in Figure 3.78 (c),
the diode will again become forward-biased when the input voltage exceeds the
capacitor voltage by 0.7 V.
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Ripple Voltage:
Figure 3.80 The period of a full-wave rectified voltage is half that of a half-wave
rectified voltage. The output frequency of a full-wave rectifier is twice that of
a half-wave rectifier. [5]
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Figure 3.81 Comparison of ripple voltages for half-wave and full-wave rectified
voltages with the same filter capacitor and load and derived from the same
sinusoidal input voltage. [5]
Ripple Factor:
The ripple factor (r) is an indication of the effectiveness of the filter and
is defined as
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From Figure 3.82, Vr(pp) is the peak-to-peak ripple voltage and VDC is the
dc (average) value of the filter’s output voltage. The lower the ripple factor, the
better the filter. The ripple factor can be lowered by increasing the value of the
filter capacitor or increasing the load resistance.
Example 15: Determine the ripple factor for the filtered bridge rectifier with a
load as indicated in Figure 3.83.
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Solution :
or
Example 16:
Consider the filtered half-wave rectifier in Figure 3.84. Assume fline = 60 Hz and
Von = 0.7 V. Given the following conditions:
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Determine
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(b)
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Voltage Regulators [5], [6]
The use of a filter will greatly reduce the variations in the output from a
rectifier. At the same time, the ideal power supply would provide a stable dc output
voltage that had no ripple voltage at all. While there will always be some ripple
voltage at the output, the use of a voltage regulator will reduce the filter output
ripple. The primary function of the voltage regulator is to maintain a constant DC
output voltage by rejecting any ripple voltage that is not removed by a filter. Here,
the simplest voltage regulator is the Zener diode. However, better regulation can be
obtained with integrated circuits that are specially designed for this purpose
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Here, the percent of voltage regulation (% VR) is given as
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A minimum value of reverse current, IZK, must be maintained in order to
keep the diode in breakdown of voltage regulation. Also, there is a maximum
current, IZM, above which the diode maybe damaged due to excessive power
dissipation. Therefore, the zener diode maintains a nearly contains a nearly
constant voltage across its terminal for values of reverse current ranging from I ZK
to IZM. Moreover, a nominal zener voltage, VZT, is usually specified on a data
sheet at a value of reverse current called the zener test current, IZT.
Figure 3.91 shows a zener voltage regulator with a variable load resistor
across the terminals. The zener diode maintains a nearly constant voltage across
RL as long as the zener current is greater than IZK and less than IZM.
When the output terminals of the zener regulator are open (R L= ), the
load current is zero and all of the current is through the zener. When a load resistor
RL is connected, part of the total current is through the zener and part through R L.
As RL is decreased, the load current IL increases and IZ decreases. The zener diode
continues to regulate the voltage until I Z reaches its minimum value, IZK. At this
point the load current is maximum. The total current trough R remains essentially
constant.
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Figure 3.92 Equivalent circuit of Zener diode regulation [6]
Example 17: Determine the minimum and the maximum load currents for which
the zener diode will maintain regulation. What is the minimum value of R L that can
be used? VZ = 12 V, IZK = 1 mA, and IZM = 50 mA. Assume ZZ = 0 and VZ
remains a constant 12 V over the range of current values, for simplicity.
When IL = 0 A (RL = ), IZ is maximum and equal to the total circuit IT.
Since IZ(max) < IZM, 0 A is an acceptable minimum value of IL because the Zener can
handle all of the 25.5 mA
IL(min) = 0 A
The maximum value of IL occurs when IZ is minimum (IZ = IZK), so solve for
IL(max):
*** Notice that if RL is less than 490 Ω, RL will make more current away from
the zener diode and IZ will be reduced below IZK. This will cause the zener to lose
regulation.***
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3.10.5 Terminal Voltage Regulator ICs
The most popular IC regulators have three terminals- an input terminal, an
output terminal, and a reference terminal. From Figure 3.94 (a), three-terminal
regulators designed for a fixed output voltage require only external capacitor to
complete the regulation portion of the power supply. Filtering is accomplished by a
large-value capacitor between the input voltage and ground. Finally, an output
capacitor (typically 0.1 F to 1.0 F) is placed in parallel with the output to
improve the transient response.
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output voltages of 5,6,8,9,12,15,18 and 24 V. Similarly, the LM79XX series has
output voltages of -5,-6,-8,-9,-12,-15,-18 and -24 V. Here, a basic fixed +5 V
power supply with a 7805 regulator is shown in Figure 3.95.
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We have discussed the operation of transformers, rectifiers, filters, and
zener regulators in detail. Now, it is time to put them all together into a basic
working power supply. The DC power supply shown in Figure 3.96 contains a
transformer, bridge rectifier, capacitive filter, and zener diode voltage regulator.
Example 18: Determine the values of VDC, Vr(out), and IL for the power supply
shown in Figure 3.97.
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Solution :
The dc output voltage (VDC) will equal the value of VZ, by formula:
𝑉𝐷𝐶 = 𝑉𝑍 = 30 V
And
Here,
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Example 19:
(a) Determine the values of VDC, Vr(out) , and IL for the power supply
shown in Figure 3.98.
(b) Can we use the zener diode in this circuit as the voltage regulator or
not? Why?
Solution :
(a)
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(b) IRS=IZ + IL
Here IZ = IRS – IL = 205.5 – 10 = 195.5 mA
*** As IZ < IZM (195.5 mA < 300 mA), we can use this zener diode as the
voltage regulator ***
Homework 5
1. Consider the filtered full-wave rectifier. Assume fline = 60 Hz and Von = 0.7 V.
Given the following conditions:
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Determine
2. Calculate the dc output voltage (VDC), dc output current (IDC) values and the
output ripple voltage (Vr(out)).
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3. Calculate the dc output voltage (VDC), dc output current (IDC) values and the
output ripple voltage (Vr(out)).
4. (a) From the circuit of Figure 3.102, Find the values of VDC , IL and Vr(out).
(b) Can we use this type of zener diode as the voltage regulator in this circuit?
Why?
2:1
100
110 Vrms
fline = 60 Hz IL
+
VDC
2000 F _ RL
1 k
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5. Consider the line−operated DC power supply circuit shown in Figure 3.103.
Assume Vr(out) at RL = 0.229 V(p-p), determine the turn ration N1:N2 in this circuit.
6. (a) Determine the values of VDC, Vr(out), and IL for the power supply shown in
Figure 3.103.
(b) Can we use the zener diode in this circuit as the voltage regulator or not?
Why?
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Diode Limiter [5]
Diode circuits, called limiters or clippers, are sometimes used to clip off
portions of signal voltages above or below certain levels. Figure 3.105(a) shows a
diode positive limiter (also called clipper) that limits or clips the positive part of
the input voltage. As the input voltage goes positive, the diode becomes forward
biased and conducts current. Point A is limited to +0.7 V when the input voltage
exceeds this value. When the input voltage goes back below 0.7 V, the diode is
reverse-biased and appears as an open. The output voltage looks like the negative
part of the input voltage, but with a magnitude determined by the voltage divider
formed by R1 and the load resistor, RL, as follows:
Solution:
The diode is forward-biased and conducts when the input voltage goes
below –0.7 V. So, for the negative limiter, determine the peak output voltage
across RL by the following equation:
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The output waveform is shown as:
Biased Limiters:
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To limit a voltage to a specified negative level, the diode and bias voltage
must be connected as in Figure 3.109. In this case, the voltage at point A must go
below –VBIAS – 0.7 V to forward-bias the diode and initiate limiting action as
shown.
Example 21: Figure 3.110 shows a circuit combining a positive limiter with a
negative limiter. Determine the output voltage waveform.
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Solution:
When the voltage at point A reaches +5.7 V, diode D1 conducts and limits
the waveform to +5.7 V. Diode D2 does not conduct until the voltage reaches
– 5.7 V. Therefore, positive voltages above + 5.7 V and negative voltages below
– 5.7 V are clipped off. The resulting output voltage waveform is
Homework 6
1. Draw the voltage waveform of VOUT and V10 in this circuit. Assume D1 and D2
are Si diode.
+ V10
+ 15 V 10
+
VIN 20 VOUT
_
5V
15 V
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2. Sketch the output waveforms of VOUT1, VOUT2. And determine the minimum and
maximum voltage of both waveforms.
VOUT1 _
+
+ 20 V D1, D2: Si diode
2 k
+
D1
VIN + 3 k V
_ _ OUT2
D2
- 20 V
3. Sketch the output waveforms of VOUT1, VOUT2. And determine the minimum and
maximum voltage of both waveforms.
VOUT1 _
+
+ 20 V D1, D2: Si diode
2 k
+
D1
VIN + 3 k V
_ _ OUT2
D2
- 20 V
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4. Determine the output waveform for the circuit in Figure 3.115(a) for each input
voltage in (b), (c), and (d).
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5. Determine the RL voltage waveform for each circuit in Figure 3.116(a), (b) and
(c).
6. Draw the output voltage waveform for each circuit in Figure 3.117(a) and (b).
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7. Sketch the output waveforms of VOUT 1, VOUT 2, and VOUT 3 in this circuit shown
in Figure 3.118. And also determine Vmax and Vmin of each voltage waveform.
Assuming CVD model, and D1 and D2 are Si diodes.
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