CH 8 - Transistors PDF

Bipolar Junction Transistors (BJTs)
• Basically two back-to-back diodes

• Immensely important device
• Name originates from Transfer of Resistor
• Three-Layer/Terminal [Emitter (E), Base
(B), Collector (C)] Two-Junction [Base-
Emitter (BE), Base-Collector (BC)] device
• Current through two terminals (E and C)
can be controlled by the current through the
third terminal (B)
Aloke Dutta/EE/IIT Kanpur 1
• Active device  capable of producing
voltage/current/power gain
• Two basic usage:
– Amplification (Analog Circuits)
– Switching (Digital Circuits)
• Two types: npn and pnp
• We will be discussing only npn BJTs
• Bipolar: both electrons and holes contribute
to current transport through the device
• Current controlled device
Symbol and Current /Voltage Convention:
* For an npn transistor, the collector and C
–
base currents (IC and I B respectively) VBC
n
IC
+
p
flow in and the emitter current (I E ) B
+ IB n IE
flows out of the transistor VBE –
 Applying KCL, treating the whole of the E
transistor as a big node:

IE = IC + IB
* E and C are n-type, while B is p-type
* Note the notational convention of the applied
voltages (VBE and VBC )  p-side first
Modes of Operation:
* BE and BC junctions can either be forward or
reverse biased  4 possible modes of operation
 Forward Active: BE junction forward biased
BC junction reverse biased
 Reverse Active: BE junction reverse biased
BC junction forward biased
 Saturation: Both junctions forward biased
 Cutoff : Both junctions reverse biased

VBC
quadrant II quadrant I
(reverse active) (saturation)
0
VBE
quadrant III quadrant IV
(cutoff) (forward active)
Quadrants III and IV: Analog Domain

Quadrants I and III: Digital Domain
Quadrant II: Finds use only in TTL circuits

Operation in the Forward Active (FA) Mode:
Depletion
Region
Emitter Collector
+ – –
n e e
IE – IC
1 e 3
p
E Base C
2
– –
+
h n
E
VBE IB VBC
(positive) (negative)
+ +
B
1 Injection Component
2 Recombination Component
3 Collection Component
* BE junction forward biased: electrons injected
from E to B, thus emitter current (I E ) flows out
of the emitter terminal
* In B, electrons diffuse towards the BC junction
due to the presence of diffusion gradient
Note: electrons are minority carriers in p-base
* In this process, some electrons will recombine
with the majority carriers (holes) present in B
* The holes lost due to this recom bination process
will be supplied by the external circuit , thus,
base current (I B ) flows into the base terminal
* Electrons, which did not recombine, will reach
the edge of the BC depletion region, and will
get swept to C by the junction electric field
* Thus, collector current (I C ) flows into the C
terminal
* A small change in I B can cause a large change in
I C to I E ratio, due to a phenomenon known as
base control
* For a good transistor, I B should be as small as
possible  the base region should be as thin
as possible
Current Gain:
* Note that the sum of the collection component and
the recombination component must always equal
the injection component (charge conservation)
 IE  IC  IB
* Common-Emitter Current Gain () = IC I B
* Common-Base Current Gain () = IC I E
* Thus, β = α  1  α  and α = β  β + 1 
* For a good transistor, I B should be as small as
possible  α  1, and β is quite large (~ 100 -500 )
* Closer is the value of α to 1, better is the BJT!
Current -Voltage Characteristic:
* Note that BE junction basically is a diode
 I E  I ES exp  VBE VT   1  I ES exp  VBE VT 
 BE junction is sufficiently forward biased
 The  1 term can be neglected
 I ES : Reverse saturation current of the BE junction
 VT : Thermal Voltage (= kT/q) = 26 mV at room
temperature (T = 300 K )
* Thus, IC = I E = IS exp  VBE VT 
 IS  I ES  saturation current of the BJT
 I B = I E  IC
Output Characteristic:
* Note: VC  VCE (variable), also I B is variable
* When BJT is in the forward active mode, VBE
VC
is assumed to get clamped at 0.7 V (about 100 IC
mV above Vγ )  Thumb rule +

Q VCE
* Now, VCE = VBE  VBC +
VBE –
IB
–
* Thus, for all values of VCE > 0.7 V , VBC is
negative, implying the BC junction remains
reverse biased , and forward active operation
is maintained

* For VCE = 0.7 V,VBC = 0
 BC junction is neither forward nor reverse
biased  it is actually under zero bias
* As soon as VCE drops below 0.7 V , VBC changes
sign and becomes positive
 BC junction is now forward biased, and
forward active mode of operation is lost
 BJT enters saturation mode of operation,
with both junctions forward biased
 VCE = 0.7 V is known as onset of saturation

* Once VCE drops below 0.7 V, the BJT enters the
saturation mode of operation
* With further reduction in VCE , the BJT moves deeper
into saturation
 This is the mode of operation of BJTs for digital
circuits, however, BJTs used in analog circuits
should never ever enter this mode of operation
  A quick check is needed to ensure that VCE is
greater than 0.7 V in analog circuits

saturation
IC forward active
IB4
IB3
IB2
IB1
0
VCE
IB4 > IB3 > IB2 > IB1
onset of
saturation
npn BJT Output Characteristic

Why VBE = 0.7 V?:
* Note: I E (and thus I C ) varies exponentially with
respect to VBE
 A small change in VBE can cause a very large
change in I C
* As a rule of thumb, VBE under the forward active
mode is assumed to get pinned at 0.7 V
 This is a heuristic used for quick estimate
 The answer may not be accurate, however,
good enough!

Degree of Saturation (DoS):
* In saturation, BC junction also becomes forward
biased and collector starts injecting electrons to base
* The base gets flooded with minority carriers
(electrons), with a corresponding increase in
recombination, and thus, the base current (I B,sat )
* Note that at the same time, the collector current (I C,sat )
starts to drop due to this reverse injection process
* The net effect is a drop in β  in the saturation
region, β is denoted by βsat (= IC,sat I B,sat ) , and
has a value smaller than that in the FA region
β
* DoS  , and has a value  1
βsat
* Note: At onset of saturation, DoS = 1, and as the
BJT is driven deeper and deeper into saturation,
the value of DoS keeps on increasing
* The value of DoS is a tell -tale sign of judging how
deeply the transistor is driven into saturation
* Commonly used values: VBE(FA) = 0.7 V, VCE(FA) > 0.7 V,
VCE(OS) = 0.7 V, VCE(HS) = 0.1 V, VBE(HS) = 0.8 V
OS : Onset of Saturation, HS : Hard Saturation

Load Line Analysis:
VCC
VB  VBE
* IB  , with VBE  0.7 V (FA mode )
RB RC
IC
* Also, IC = I B (Note: Independent of R C )

RB +
* Thus, for different values of VB , we VB Q
+
VCE
would get different values of I B , and IB VBE
–
–
correspondingly different values of IC
 A series of output characteristics (i.e., IC versus
VCE ) can be drawn
* The DC operating point or the Q -point can lie
anywhere on any of these curves
* Also, by varying VB smoothly, almost a continuous
variation of I B can be obtained, which would yield
almost continuous values of IC
* Thus, the output characteristics, in effect, completely
fill up quadrant I
* Now, to fix a unique bias point , we need to draw the
load line, and the intersection point of this load line
with the particular characteristic for a given VB and
I B would give us the information about the Q -point
VCC  VCE
* Load line equation: IC 
RC
* 2 boundary points:
 IC  0, VCE  VCC
 VCE  0, IC  VCC / R C
* Joining these two points by a straight line gives the
load line
* This line will intersect with the output characteristics
at infinite number of points
* Each of these points is a possible operating point
* The best choice for the operating point (or Q-point)
is right at the center of the load line:
 VCEQ(best )  VCC 2 and ICQ(best )  VCC  2R C 
* Justification:
 When this circuit is to be used as an amplifier ,
then an ac small -signal vi will be superimposed
on the DC bias voltage VB
 This would cause the dynamic operating point
to move along the load line in either direction
 As it shifts towards the VCE axis, Q moves
towards cutoff  since I C decreases  , and as it
moves towards the I C axis, Q moves towards
saturation  since VCE decreases 
 If Q enters either cutoff or saturation region,
then it would produce clipping  or distortion 
in the output voltage v 0
 If the Q -point is located exactly at the center
of the load line, then the maximum possible
undistorted peak -to-peak swing of the output
voltage v0 will be achieved
 Golden Rule of Thumb for BJT biasing

saturation
IC forward active
IC,max =
IB5 > IB4 > IB3 > IB2 > IB1
VCC/R C
IB5
vi
IC4 IB4
Q-point
ICQ IB3 = IBQ
t
IC2 IB2
IB1
VCEQ VCC
VCE
load
line
v0
DC (or Quiescent) Power Dissipation
of the Transistor = VCEQ  ICQ
t

What is the Role of RC?:
* For fixed VB (and thus, I B ):
 As R C decreases, IC,max will increase
 Q moves towards cutoff
 v 0 will get clipped during positive half cycle
 As R C increases, IC,max will decrease
 Q moves towards saturation
 v 0 will get clipped during negative half cycle
 In either of these two cases, the range of the
maximum undistorted peak -to-peak output
voltage swing will be correspondingly reduced
Observations:
* If R C is very high, then the load line may not
have any intersection point at all with the output
characteristics under the FA region, and the
Q-point will move to the saturation region
 Disastrous way to bias a transistor for analog
circuit applications
* A transistor biased in the FA region behaves like an
ideal current source with infinite output resistance
* However, if a transistor is biased in the saturation
region, it ceases to behave like a constant current source
* In the saturation region, IC becomes a strong function
of VCE , showing very small output resistance
* Transistors used in analog circuit applications like
amplifiers, should always be biased in the FA region,
where IC does not show any dependence on VCE
 I CQ would not change with any variation of VCE
* This is important to maintain constant values of all the
ac small -signal model parameters (to be discussed)
* If ICQ varied with VCE , then the behavior of the circuit
would become erratic

AC Small -Signal Model:
* Representation of the transistor as a linear network
* Actual model is quite tedious and complicated
* Here, we will present the simplest one, known as
the low -frequency T-model C
ic
* It consists of only 2 parameters:
  (or ): Common-Emitter (or B
ib ib = ie
Common-Base ) +
rE
Current Gain
vbe ie = ( + 1)ib
 rE : Incremental Emitter Resistance = ic/
– E
 dVBE dI E  VT I EQ  VT ICQ (    1)
* Note: rE is expressed in terms of ICQ (or I EQ )
 The linearization is done around the DC
bias point (Q-point )
  DC analysis must precede ac analysis
in order to obtain the bias point information,
and thus, the value of rE
* Also, note the v be = ie rE , which can also be written
as: v be = (+1)i b rE  i b rE  i b r , with r  rE
 r is another small -signal parameter , defined
as incremental base -emitter resistance
 Note that this resistance appears in the base lead
Analysis of Amplifiers Using Transistors:
* The analysis proceeds as follows:
 First, DC biasing analysis is done, which
yields the DC bias point (Q-point )
 Gives ICQ and VCEQ
 ICQ is needed to obain the values of the
small -signal parameters
 VCEQ is needed to ensure that the transistor is
biased in the FA region (VCEQ  0.7 V, and
ideally VCC /2, known as the best bias point )

* Then, the transistor is replaced by its ac small -
signal model
* Subsequently, usual network analysis is
done to obtain:
 Voltage Gain (A v )
 Current Gain (Ai )
 Power Gain (A p  A v  Ai )
 Input Resistance (R i )
 Output Resistance (R 0 )

Biasing:
* Fixing the DC operating point (known as the Q -
point or Quiescent Operating Point )
* Defined by two parameters: ICQ and VCEQ , with the
subscript Q denoting the Q -point values
* If the transistor is to be used as an amplifier (analog
application), then it must be biased in the FA region
* On the other hand, if the transistor is to be used as a
switch (digital application), then it must toggle
between cutoff and saturation modes of operation

Example: Fixed Resistor Bias:
VCC
5V
To start the DC bias analysis, assume
IC
that Q is in the FA region, with VBE = RB
IB
RC
100 k
0.7 V, and VCE  0.7 V
+
Q VCE
+
VCC  VBE 5  0.7 VBE
 I BQ    43 A –
–
RB 100 k
Now, to find I CQ , we need the value of 
Let 's assume  = 100  ICQ  IBQ  4.3 mA
Note that to find ICQ , we did not need the value of R C
This is true only if Q is in the FA region, where IC is
independent of RC  Extremely important observation
Now, VCEQ  VCC  ICQ R C
Thus, RC controls the value of VCE
Recall that VCEQ(best )  VCC 2  2.5 V
 Best value of R C   2.5 V   4.3 mA   581.4 
Note: For R C  581.4 , VCEQ would increase and
Q would move towards cutoff
On the other hand, if R C > 581.4 , VCEQ would
decrease and Q would move towards saturation
The value of R C to operate Q at onset of saturation
= (5  0.7) /  4.3 mA  =1 k
If the value of R C is more than 1 k, then Q will be
driven into saturation
As R C increases, Q will go into deep (or hard ) saturation
with VCE(HS) = 0.1 V and VBE(HS) = 0.8 V
The value of  will change to βsat , with DoS > 1
Example: Let's visit the scene for R C = 10 k
Obviously, Q will be under hard saturation
 I B,sat   VCC  VBE(HS)  R B   5  0.8  100 k   42 A
IC,sat   VCC  VCE(HS)  R C   5  0.1 10 k   490 A
 sat  IC,sat I B,sat  11.7 and DoS =  sat  8.6
How to Check the Mode of Operation?:
* Let's consider the same circuit with R C = 10 k, but
now we assume that Q is in the FA region
 I B and IC remain at 43 A and 4.3 mA respectively
* But, VCEQ  VCC  ICQ R C  5   4.3 mA   (10 k)
=  38 V!
* Now, in a circuit with bias voltages ranging from
ground (0 V) to VCC (5 V), it is impossible to have a
negative voltage at any node of the circuit
* Thus, the analysis is wrong , and Q is NOT in the FA
region, it's actually in hard saturation!
Useful Information for Transistor Circuit Analysis:
* All pure ac voltages (i.e., without any DC offset)
are DC short , since their average value is zero
* All pure DC voltages are ac short , since they don't
have any time variation
* In DC analysis, open up all capacitors
* In ac analysis, short all capacitors
* In ac analysis, null all independent sources, but
don't touch dependent sources

Amplifier Topologies:
* 4 basic topologies:
 CE (Common-Emitter )
 CB (Common-Base )
 CC (Common-Collector )
 CE(D) [Common-Emitter (Degeneration)]
* CE:
 Input at B, output from C, E grounded
 Ai large (= ), Av moderate to large, Ap huge
 180° phase shift between input and output

* CB:
 Input at E , output from C, B grounded with
or without a resistor
 Ai  1 (=  ), Av moderate , Ap moderate
 Input and output in phase
* CC:
 Input at B, output from E, C connected either
to ground (for negative supply circuits) or to the
positive power supply with or without a resistor
 Ai large (=  + 1), Av  1, Ap moderate
 Input and output in phase
* CE(D):
 Input at B, output from C, E grounded through
a resistor
 Ai large (= ), Av small , Ap moderate
 180° phase shift between input and output
 This topology has an advantage in that it
provides for an excellent frequency response
* As an example, we will discuss a very important
circuit block, known as RC -Coupled Amplifer ,
which provides both current as well as voltage
gain, and thus, large power gain
RC -Coupled Amplifier:
* Extremely powerful analog circuit amplifier module
* Core circuit for audio amplifiers
VCC
12 V
RC
R1 5 k CC CB: Base Blocking Capacitor
v0
90 k CE: Emitter Bypass Capacitor
VC
CB
vi CC: Collector Coupling Capacitor
RL
Q All are high-value capacitors (> µF)
VB 5 k
For DC Analysis: Treated as Open
VE
R2 For ac Analysis: Treated as Short
10 k RE
CE
500 

Purpose of the Capacitors:
* CB : Base Blocking Capacitor
 Isolates the ac signal source from the circuit core
 The DC level of the ac signal (i.e., the offset )
cannot affect the DC bias point of the circuit
* CE : Emitter Bypass Capacitor
 Plays no role in DC analysis, since it opens up
 For ac analysis, it shorts out R E , putting the
emitter of Q to ac ground
* CC : Collector Coupling Capacitor
 Isolates the load resistance R L from the circuit
core such that it cannot alter the DC bias point
DC Analysis:
* All capacitors open up VCC
12 V
* Note that typical value of  is  100, RC
ICQ
I1 R1 5 k
thus, I B is a miniscule fraction of IC 90 k
VC
IBQ +
 I E  IC Q VCEQ
VB +
* Also, I 2 = I1  I BQ VBE
– VE
–
I2 R2
* R1 and R 2 are chosen in such a way 10 k RE IEQ
500 
that I1  I BQ  I 2  I1
* Thus, VB  R 2 VCC  R1  R 2   1.2 V
 VE  VB  VBE  0.5 V and I EQ  ICQ  VE R E  1 mA
and VCEQ  VCC  ICQ  R C  R E   6.5 V (close to VCC 2)
ac Analysis: i0
v0
* All capacitors shorted
R" = R C||R L
 R E gets bypassed ic ie
2.5 k
* VCC nulled  R1 comes in vi

R' = R 1||R 2 rE ie
parallel to R 2 (R ), and R C 9 k 26 
comes in parallel with R L (R )

* Replace Q by its low -frequency T -model
 Note: i 0 = i c  i e ,  base current neglected
v0 i 0 R  2.5 k
* Voltage gain: A v =    96.2
vi i e rE 26 
 Note: rE  VT ICQ   26 mV  1 mA   26 
* The negative sign for A v implies that v0 is exactly
out -of -phase with vi (i.e., they are 180° apart )
* Note that the input vi appears at the base, while the
output v 0 is taken from collector , with emitter grounded
 Common-Emitter (CE) Amplifier
* For a CE amplifier , there is a phase shift of 180°
between the input and output
* To increase Av , either decrease rE , increase R, or both
* rE can be decreased by increasing I C (by a change in bias )
* R can be increased by making RL  RC (max. R = RC )
* Note: Power gain = A v  Ai  9620 (for  > 100)
i0
v0
What Happens if C E is not there?:
R" = R C||R L
ic ie
* DC bias point unchanged 2.5 k
* Due to the absence of C E , vi

R' = R 1||R 2 rE ie
RE unbypassed 9 k 26 
* Input is still at base, and output RE

500 
is still from the collector , but
now emitter is grounded through a resistor
 Common-Emitter (Degeneration) [CE(D)]
v0 i 0 R  2.5 k
* Voltage gain: A v =    4.75
vi i e  rE  R E  526 
* Note the drastic reduction in Av (gain degeneration!)
Simple BJT Inverter:
* Basic digital building block VCC
* Known as Inverter (or NOT Gate ) RC

V0
* Digital circuits have two levels: Vi RB

Q
 High (or Hi )  close or equal to VCC
 Low (or Lo)  close or equal to 0
* Operation:
 Vi = 0 (Lo), Q is off , V0 = VCC (Hi )
 Vi  VCC ( Hi ), Q is driven to hard saturation,
V0 = VCE(HS)  0.1 V (Lo)
 Inverter
Transition
Width (TW)
V0
VOH: Output Hi
VOH VOL: Output Lo
Idealized VIL: Input Lo
VTC VIH: Input Hi
Logic
Swing (LS) NMH: Noise Margin (High) = VOH – VIH
NML: Noise Margin (Low) = VIL – VOL
Actual
VTC TW: Transistion Width = VIH – VIL
VOL
LS: Logic Swing = VOH – VOL
0 VIL VIH
Vi
Voltage Transfer Characteristic

(VTC)

Design Example:
Choose VCC = 5 V, R C  2 k, and R B  20 k
Vi = 0 V , Q off  VOH = VCC = 5 V
Vi = 5 V , Q in hard saturation  VOL = VCE(HS) = 0.1 V
VIL : Maximum value of the input that would still
ensure that V0 remains at VOH
Taken to be equal to VBE = Vγ = 0.6 V
Note that Q just starts to conduct at this point
VIH : Minimum value of the input that would still
ensure that V0 remains at VOL
Actual computation is quite tedious
Analysis of VIH :
It is assumed that when Vi = VIH , Q is at the onset
of saturation with VBE = 0.7 V, but with VCE = 0.1 V
This is a clear contradiction, however, it gives a
sufficiently close estimate of VIH
VCC  VCE 5  0.1
 IC    2.45 mA
RC 2k
BJTs used in inverters typically have β ~ 50 -100
Also,  is assumed to have its nominal value (i.e.,
the value in the FA region) at this point
Choosing  = 80  I B  IC   30.6 A
 VIH = VBE  I B R B  0.7   30.6 A    20 k 
 1.3 V
Thus, LS = VOH  VOL = 4.9 V
TW = VIH  VIL = 0.7 V
NM H = VOH  VIH = 3.7 V
NM L = VIL  VOL = 0.5 V
dV0 VOH  VOL
Transition Region Gain  
dVi VIL  VIH
LS
  7
TW
* Note: Higher the magnitude of the gain, sharper is
the response
* The inverter is the heart of digital circuits, and can be
configured in various topologies to produce a variety
of digital gates, e.g., AND, OR, NAND, NOR, etc.
* One of the simplest digital blocks to design, and
works very well  pretty robust circuit
* Note: Q acts as a switch  either cutoff (with
output in the Hi state) or in hard saturation (with
output in the Lo state)  that's why it's a Gate!

Simple BJT Series Voltage Regulator:
* Extremely simple and I1 IC IE
+ VCE –
powerful circuit +
Q –
+
I2 VBE
R +
* Operates under the principle
IB
Vi RL V0
of negative feedback +
IZ VZ
* V0  VZ  VBE  I E R L – – –
* Recall: I E depends on VBE Unregulated Regulated

Input Output
exponentially
 Large change in I E can be accommodated by a
very small change in VBE , which can be assumed
to be clamped at ~ 0.7 V
* If for any reason, V0 tends to increase, then VBE
drops, which reduces IE , and thus, V0 reduces
* Similarly, if for any reason, V0 tends to decrease,
then VBE increases, which increases IE , and thus,
V0 increases
* Note that the cause and effect are opposite
 Negative Feedback
* Extremely robust circuit, with the output having
almost no ripple
* Note that Q should never saturate  VCE,min = 0.7 V

Design Issues & Constraints:
*  VZ has a constant value, let's say 5 V
 V0 will have a fixed and constant value of 4.3 V
Note: This is independent of the value of R L
* Minimum value of Vi should be  V0 +VCE(min)
* Q is known as series pass transistor , since it passes Vi
to output with a drop of VCE
* Current Relations: I1  IC  I 2 , I 2  I Z  I B , IC  I B ,
and IE     1 I B
* The role of R is very critical: it should be chosen
extremely carefully
* The output should never be short -circuited , i.e., R L
should never be made zero, since in that case, huge
current will flow at the output, which will completely
destroy the regulator due to over -heating
 Actual regulators have short -circuit protection
* If the minimum allowed value of R L is RL,min , which
leads to the maximum value of IE (I E,max = V0 R L,min )
and Vi is at its minimum value Vi,min , then the current
supplied by Vi should not only supply I B,max
 = I E,max    1  , but also the minimum required
Zener current I Z,min to sustain breakdown
Vi,min  VZ
 This gives Rmax 
IB,max  I Z,min
* With load removed, i.e., R L open-circuited,
I E  IC  I B  0
* Under this situation, with Vi at its maximum value
Vi,max , the Zener current should not exceed its
maximum limit of I Z,max
Vi,max  VZ
 This gives Rmin 
I Z,max
* Exercise: Verify that any value of R falling outside
this range will be detrimental for the circuit

CH 8 - Transistors PDF

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CH 8 - Transistors PDF

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Bipolar Junction Transistors (BJTs)

• Basically two back-to-back diodes

transistor as a big node:

Aloke Dutta/EE/IIT Kanpur 4

Quadrants III and IV: Analog Domain

Aloke Dutta/EE/IIT Kanpur 5

mV above Vγ )  Thumb rule +

Aloke Dutta/EE/IIT Kanpur 11

Aloke Dutta/EE/IIT Kanpur 12

Aloke Dutta/EE/IIT Kanpur 13

npn BJT Output Characteristic

Aloke Dutta/EE/IIT Kanpur 14

Aloke Dutta/EE/IIT Kanpur 15

Aloke Dutta/EE/IIT Kanpur 17

* Also, IC = I B (Note: Independent of R C )

Aloke Dutta/EE/IIT Kanpur 22

Aloke Dutta/EE/IIT Kanpur 23

Aloke Dutta/EE/IIT Kanpur 26

Aloke Dutta/EE/IIT Kanpur 29

Aloke Dutta/EE/IIT Kanpur 30

Aloke Dutta/EE/IIT Kanpur 31

Aloke Dutta/EE/IIT Kanpur 36

Aloke Dutta/EE/IIT Kanpur 37

Aloke Dutta/EE/IIT Kanpur 40

* VCC nulled  R1 comes in vi

comes in parallel with R L (R )

* Due to the absence of C E , vi

* Input is still at base, and output RE

* Known as Inverter (or NOT Gate ) RC

* Digital circuits have two levels: Vi RB

Voltage Transfer Characteristic

Aloke Dutta/EE/IIT Kanpur 47

Aloke Dutta/EE/IIT Kanpur 51

* Recall: I E depends on VBE Unregulated Regulated

Aloke Dutta/EE/IIT Kanpur 53

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