Description

The internal circuitry of the 555 timer consists of ________, an R-S flip-flop, a transistor, switch, an output buffer amplifier, an
An Astable multivibrator requires:
A Monostable 555 timer has the following number of stable states
The basic block diagram of PLL does not consists of
PLL does not operate in one of the following modes
Voltage Controlled Oscillator, IC 566 does not produce following wavefors at the output
565 PLL applications are
The operating frequency range of 565 PLL are
The type of filter used in PLL is
The drawback of binary weighted resistor type DAC is
The _____________ of a converter is the smallest change in voltage which may be produced at the output (or input) of the co
Flash type converter comes under
The range of frequencies over which the PLL can acquire lock with an input signal is called
Which of the following IC is Compatible to TTL and CMOS families
The output of a 555 timer can drive a transistor-transistor logic (TTL) due to its
For a simple 3 bit DAC, the input values of V0=V1=V2=1, then the output is eqal to ____________
In a 8-bit successive approximation type of Analog to Digital converter, the size of SAR and DAC should be equal to _________
From the internal structure of IC 555 timer, the function of Flip-Flop is _____________
To develop the 8 line to 3 line Flash ADC, the required number of comparators are ___________
When there is no input is give to PLL, it operates in __________ mode
An OR gate has 4 inputs. One input is high and the other three are low. The output
what are CMOS Electrical Characteristics for digital gates
The number of digits in octal system is
Digital technologies being used now-a-days are
In negative logic convention, the Boolean Logic [1] is equivalent to
In positive logic convention, the true state is represented as
74HCT00 series is
what are the CMOS voltage levels
Abbreviate HDL
what are the logic of a module can be described for Verilog HDL
what are all declared with the lowercase keywords for gate modeling
what are logical operator for data flow modeling
what are the keyword used forBehavioral descriptions model
what are the keyword used for data flow model
In Verilog
which logis'H1234' is a
is not supported in Verilog
which level of abstraction level is not uesd for HDL

what is interconnected keyword between input and output

What’s the keyword in Verilog testbenchesto indicate that interrupts the simulation with the possibility of resuming it?
what is possible output for this programmodule if A=1,B=1,C=0 Simple_Circuit (A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B);
not G2 (E, C);
or G3 (D, w1, E);
endmodule
The circuit output values are depends on only present inputs then the circuits are called
The circuit output values are depends on present and past inputs then the circuits are called
How many data select lines are required for selecting eight inputs?
A decoder can be used as a demultiplexer by ________.
a full adder has acarry input is zero what are the sum and carry when the a=1 and b=1
How many outputs would have 16 to 4 line encoder
How is a J-K flip-flop made to toggle?
Which of the following is correct for a gated D flip-flop?
A J-K flip-flop is in a "no change" condition when ________
The disadvantage of an S-R flip-flop
Half subtractor is used to perform subtraction of ___________
How many outputs are required for the implementation of a subtractor?
Let A and B is the input of a subtractor then the output will be ___________
A digital multiplexer is a combinational circuit that selects ___________
In a multiplexer, the selection of a particular input line is controlled by ___________
A decoder converts n inputs to __________ outputs.
Which of the following are building blocks of encoders?
Decoder is constructed from ________________
The truth table for an S-R flip-flop has how many VALID entries?
Whose operations are more faster among the following?