A B C D E

ZZZ8

DAZ@
DAZ04300100
PCB

1 1

ZZZ1
DA2@
MAIN BOARD

DA600007E10
PCB

ZZZ2
DA2@
E board

DA40000A910
PCB

ZZZ3

DA2@
FP board

DA600007D10
Compal Confidential
PCB

ZZZ4

KAQB0 M/B Schematics Document

2 DA2@ 2
Function board

DA40000AA10
PCB

ZZZ5
DA2@
USB board

DA40000AB10
Intel Penryn Processor with Cantiga + DDRIII + ICH9M
PCB

ZZZ6

DA2@
IO board

DA40000AC10
PCB

ZZZ7

3
DA2@
Power board

DA40000AD10
2009-03-27 3
PCB

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 1 of 43
A B C D E
 A B C D E

Compal Confidential Fan Control

page4 Intel Montevina Processor Thermal Sensor Clock Generator
Model Name : KAQB0 EMC1402-1-ACZL ICS9LPRS387
uPGA-478 Package page4 page15
File Name : LA5011P
LCD Conn. CRT Conn. (Socket P) page4,5,6
P/N:DA60000B110
1 1
page23 page24
FSB
H_A#(3..35) 800/1066MHz H_D#(0..63)

HDMI Conn. multiplex multiplex

page25 PI3LVD1012 PI3V512QE
Intel Cantiga DDR3 800 MHz 1.5/0.75V DDR3-SO-DIMM X2
5 IN 1 LVDS BANK 0, 1, 2, 3 page13,14

1394 Conn. TMDS LVDS uFCBGA-1329 Dual Channel

PCI-Express page7,8,9,10,11,12

Card Reader LS-501A MXM III VGA/B 16X LS-5015

UMA SKU
JMB380 HDMI board page21 DMI C-Link Finger Print
7318 Level shift SS801U
LS-5017 page32
page 21 PCI-Express USB Bus Bluetooth
PCI-Express
2
Intel ICH9-M Conn 2

page32
CMOS
LS-5017 port 0 S-ATA
BGA-676 Camera 1.3M
page23
New Card MINI Card 1,2 LAN(GbE) page16,17,18,19 USB conn x3
BROADCOM
Socket WLAN TV tuner BCM5764
3.3V 48MHz
page29 page20 port 2 port 3 page29
page26
SATA HDD E-SATA
Conn. Conn. page20
page20 3.3V 24.576MHz/48Mhz HD Audio
RJ45
page25
LPC BUS
CDROM
CONN page20
ENE KB926
3
page31 GMCH HDA HDA Codec MXM SPDIF 3
ALC889X
page7 UMA SKU page27 page27
RTC CKT. Touch Pad
page17
Int.KBD
LS-5011 LS-5015 page32 page31
Backlight sensor Conn Finger Print
Power On/Off CKT. ENE-SB3520 SS801U BIOS
page33 page32
page33 page30 APA2051 APA3011
LS-5012 LS-5017 Audio AMP Audio AMP
LS-5016
page28 page28
DC/DC Interface CKT. Launch sensor Conn MINI Card 1,2
USB & TV Conn
ENE-SB3520 page29 WLAN TV tuner
page34 page33
page20
Phone Jack x3 Subwoofer
LS-501A page28 page28
LS-5013 LS-5018
Power Circuit DC/DC
Media sensor Conn HDMI board
4 POWER SAVING Conn 4

page35,36,37,38,39,40,41 CYPRESS-CY8C20434 page32

7318 Level shift
page33 page 21
LS-5014
LS-5019
Security Classification Compal Secret Data Compal Electronics, Inc.
VR/B Conn Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

SW EC05E1210401 2
Touch pad Button Conn SCHEMATIC,MB A5011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LEVEL ALPS page28 page32 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 2 of 43
A B C D E
 A

O MEANS ON X MEANS OFF

Voltage Rails

Symbol Note :
+5VS
+3VS
+1.5VS
: means Digital Ground
power
plane +0.75V
+VCCP
+5VALW +1.5V +CPU_CORE : means Analog Ground
+B
+3VALW @ : means just reserve , no build
DEBUG@ : means just reserve for debug.
State +1.8VS

S0
O O O O
S1
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
1
don't exist X X X X SMBUS Control Table
1

THERMAL
SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD

SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
SMB_CK_DAT1 ICH9 X X X X V V V X
LCD_CLK
LCD_DAT Cantiga
X X X X X X X V

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100
CLOCK GENERATOR (EXT.) D2 11010010
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 3 of 43
A
 5 4 3 2 1

D D
+VCCP

XDP_TDI R60 1 2 150_0402_1%

XDP_TMS R50 1 2 39_0402_1%

(7) H_A#[3..16]

2
JCPU1A
H_A#3 J4 H1 H_ADS# D28
A[3]# ADS# H_ADS# (7)

ADDR GROUP 0
H_A#4 L5 E2 H_BNR# PJSOT05C-LF-T7_SOT23-3
A[4]# BNR# H_BNR# (7)
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# (7)
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 H5 H_DEFER# (7)

1
H_A#8 A[7]# DEFER# H_DRDY#
N2 A[8]# DRDY# F21 H_DRDY# (7)
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# (7)
H_A#10 N3
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# (7)
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# T1
H_A#14 A[13]# IERR# H_INIT# XDP_TRST# R62 56_0402_5%
P4 A[14]# INIT# B3 H_INIT# (17) 1 2
H_A#15 P1
H_A#16 A[15]# H_LOCK# XDP_TCK R49 54.9_0402_1%
R1 A[16]# LOCK# H4 H_LOCK# (7) 1 2
H_ADSTB#0 M1
(7) H_ADSTB#0 ADSTB[0]#

2
C1 H_RESET#
RESET# H_RESET# (7)
H_REQ#0 K3 F3 H_RS#0 D29
(7) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (7)
H_REQ#1 H2 F4 H_RS#1 PJSOT05C-LF-T7_SOT23-3
(7) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (7)
H_REQ#2 K2 G3 H_RS#2
(7) H_REQ#2 REQ[2]# RS[2]# H_RS#2 (7)
H_REQ#3 J3 G2 H_TRDY#
(7) H_REQ#3 REQ[3]# TRDY# H_TRDY# (7)
H_REQ#4 L1
(7) H_REQ#4

1
REQ[4]# H_HIT#
(7) H_A#[17..35] HIT# G6 H_HIT# (7)
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# (7) C
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4
ADDR GROUP 1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
XDP/ITP SIGNALS

H_A#23 A[22]# BPM[3]#

U1 A[23]# PRDY# AC2
H_A#24 R4 AC1 XDP_BPM#5
H_A#25 A[24]# PREQ# XDP_TCK +3VS
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI
H_A#27 A[26]# TDI
W2 A[27]# TDO AB3
H_A#28 W5 AB5 XDP_TMS
A[28]# TMS

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# (18)
H_A#31 V4 C2
H_A#32 A[31]# SA00001Z700
W3 A[32]#
H_A#33 2
AA4 A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 68_0402_5% U1
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 A[35]# PROCHOT# D21 1 VDD SCLK 8 SMB_EC_CK2 (31)
H_ADSTB#1 V1 A24 H_THERMDA_R R14 1 2 0_0402_5% H_THERMDA
(7) H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC_R R15 1 2 0_0402_5% H_THERMDC H_THERMDA 2 7 SMB_EC_DA2
THERMDC D+ SDATA SMB_EC_DA2 (31)
H_A20M# A6 C3
(17) H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 1 R195 2 +3VS

(17) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (7,17) D- ALERT/THERM2
H_IGNNE# C4 2200P_0402_50V7K 10K_0402_5%
(17) H_IGNNE# IGNNE#
4 THERM GND 5
H_STPCLK# D5
(17) H_STPCLK# STPCLK#
H_INTR C6 H CLK
(17) H_INTR LINT0 ADT7421ARMZ-REEL_MSOP8
H_NMI B4 A22 CLK_CPU_BCLK Address:100_1100
(17) H_NMI LINT1 BCLK[0] CLK_CPU_BCLK (15)
H_SMI# A3 A21 CLK_CPU_BCLK#
(17) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (15)
M4 RSVD[01]
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
B
V3
RSVD[03]
RSVD[04]
Trace width / Spacing = 10 / 10 mil 2007/09/011 FAN1 Conn B
RESERVED

B2 RSVD[05]
TEST7 C3
T6 RSVD[06] +5VS
D2 RSVD[07]
D22 C638 +5VS
RSVD[08]
D3 RSVD[09] 1 2
F6 RSVD[10]

1
10U_0805_10V4Z
U19 D53
1 8 1SS355_SOD323-2
FOX_PZ4782A-274M-41_Merom VEN GND
2 VIN GND 7
CONN@ +VCC_FAN1 3 6

2
EN_FAN1 1 VO GND D54
(31) EN_FAN1 2 4 VSET GND 5
0_0402_5% 1 1 2
+VCCP R1007 C949 G990P11U SOP
0.1U_0402_16V4Z BAS16_SOT23-3
2 SA00002GW00
C639
1

@ 1 2
R17 @ 10U_0805_10V4Z
56_0402_5% +3VS C640
1000P_0402_50V7K
1 2
2 2

1
B

R538
10K_0402_5%
E

H_PROCHOT# 3 1 OCP# 40mil

OCP# (18)
C

@ Q2 JP32

2
MMBT3904_SOT23 +VCC_FAN1 1 1
(31) FAN_SPEED1 2 2
3 3
+VCCP
1
A C641 A
4 GND
1000P_0402_50V7K 5 GND
2

R18 2 E&T_3801-F03N-01R
56_0402_5% CONN@
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
(7) H_D#[0..15] H_D#[32..47] (7)
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 D[8]# D[40]# Y25 A20 VCC[009] VCC[076] AC18
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]

DATA GRP 2
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
(7) H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 (7) B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
(7) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (7) VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
(7) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (7) VCC[019] VCC[086]
(7) H_D#[16..31] H_D#[48..63] (7) C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
DATA GRP 3
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21 R19 1 2 0_0402_5%
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 R20 1 2 0_0402_5%
C H_D#31 H_D#63 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
(7) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (7) VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
(7) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (7) VCC[039] VCCP[05] + C6
H_DINV#1 N24 AC20 H_DINV#3 E18 J21
(7) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (7) VCC[040] VCCP[06]
E20 K21 330U_D2E_2.5VM_R15
V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 GTLREF COMP[0] R26 F7 VCC[042] VCCP[08] M21
@ R21
@R21 2
1 2 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
@R22
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6 0814 Change to 220uF
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6 0819 Change to C_D2E
T3 TEST4 VCC[046] VCCP[12]
TEST5 AF1 E5 H_DPRSTP# R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# H_DPRSTP# (7,17,41) VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# (17) VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# (7) VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
(15) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD (17) VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
(15) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (7) VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
(15) CPU_BSEL2 BSEL[2] PSI# H_PSI# (41) VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M

0.01U_0402_16V7K
FOX_PZ4782A-274M-41_Merom AA12 VCC[054]
CONN@ AA13 VCC[055] VID[0] AD6 CPU_VID0 (41)
AA15 VCC[056] VID[1] AF5 CPU_VID1 (41) 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 (41)
AA18 AF4 C7 C8
VCC[058] VID[3] CPU_VID3 (41)
AA20 VCC[059] VID[4] AE3 CPU_VID4 (41) 2 2
Resistor placed within AB9 VCC[060] VID[5] AF3 CPU_VID5 (41)
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs 0.5" of CPU pin.Trace AC10 VCC[061] VID[6] AE2 CPU_VID6 (41)
AB10 VCC[062]
should be at least 25 AB12 VCC[063]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AB14 AF7 VCCSENSE VCCSENSE (41)
mils away from any other AB15
VCC[064] VCCSENSE
Near pin B26
VCC[065]
toggling signal. AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE (41)
COMP[0,2] trace width is VCC[067] VSSSENSE
166 0 1 1
B 18 mils. COMP[1,3] trace FOX_PZ4782A-274M-41_Merom B

width is 4 mils. .

200 0 0
CONN@ Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCCP
1

R27
1K_0402_1% +VCC_CORE
2

V_CPU_GTLREF
R28 1 2 100_0402_1% VCCSENSE
1

R29 R30 1 2 100_0402_1% VSSSENSE

2K_0402_1%
2

Close to CPU pin AD26

Close to CPU pin
within 500mils.
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 5 of 43
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1
C9
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M
2 2
1 1 1 1 1 1
C10 C11 C12 C13 C14 C15 C16
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2

D D
+VCC_CORE
JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21 1 1 1 1 1 1 1 1
A11 P24 C17 C18 C19 C20 C21 C22 C23 C24
VSS[003] VSS[084] Place these capacitors on L8
A14 VSS[004] VSS[085] R2
A16 R5 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[005] VSS[086] 2 2 2 2 2 2 2 2
A19 VSS[006] VSS[087] R22
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
+VCC_CORE
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6 1 1 1 1 1 1 1 1
B19 U21 C25 C26 C27 C28 C29 C30 C31 C32
VSS[014] VSS[095] Place these capacitors on L8
B21 VSS[015] VSS[096] U24
B24 V2 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[016] VSS[097] 2 2 2 2 2 2 2 2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
+VCC_CORE
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3 1 1 1 1 1 1 1 1
C25 Y6 C33 C34 C35 C36 C37 C38 C39 C40
VSS[025] VSS[106] Place these capacitors on L8
D1 VSS[026] VSS[107] Y21
D4 Y24 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[027] VSS[108] 2 2 2 2 2 2 2 2
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 Mid Frequence Decoupling
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
+VCC_CORE
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 AC14 330U_D2E_2.5VM_R9
VSS[050] VSS[131]
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24 1 1 1 1
G23 VSS[055] VSS[136] AD2
G26 AD5 C41 + C42 + C43 + C44 +
VSS[056] VSS[137] 330U_D2E_2.5VM_R9
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
2 2 2 2
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8 0814 Change to C_D2E
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16 Place these inside
L6 VSS[070] VSS[151] AE19 socket cavity on L8
L21 VSS[071] VSS[152] AE23 (North side
L24 VSS[072] VSS[153] AE26
M2 A2
Secondary)
VSS[073] VSS[154]
M5 VSS[074] VSS[155] AF6
M22 AF8 +VCCP
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16 1 1 1 1 1 1
N23 AF19 C45 C46 C47 C48 C49 C50
VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
P3 A25 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS[081] VSS[162] 2 2 2 2 2 2
VSS[163] AF25

FOX_PZ4782A-274M-41_Merom
.
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 6 of 43
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] (4) U2B

(5) H_D#[0..63] U2A
A14 H_A#3 M36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0

DDR CLK/ CONTROL/COMPENSATION

F2 H_D#_0 H_A#_4 C15 N36 RSVD2 SA_CK_0 AP24 M_CLK_DDR0 (13)

0.01U_0402_25V7K
H_D#1 H_A#5 M_CLK_DDR1

2.2U_0603_6.3V4Z
G8 H_D#_1 H_A#_5 F16 R33 RSVD3 SA_CK_1 AT21 M_CLK_DDR1 (13)
H_D#2 F8 H13 H_A#6 0915 ADD PM@ T33 AV24 M_CLK_DDR2
H_D#3 E6
H_D#_2 H_A#_6
C18 H_A#7 +1.5V DDR3 AH9
RSVD4 SB_CK_0
AU20 M_CLK_DDR3
M_CLK_DDR2
M_CLK_DDR3
(14)
(14)
H_D#4 H_D#_3 H_A#_7 H_A#8 RSVD5 SB_CK_1
G2 H_D#_4 H_A#_8 M16 AH10 RSVD6
H_D#5 H6 J13 H_A#9 1 1 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 RSVD7 SA_CK#_0 M_CLK_DDR#0 (13)

1
C51

C52
H_D#6 H2 P16 H_A#10 AH13 AR21 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SA_CK#_1 M_CLK_DDR#1 (13)
H_D#7 F6 R16 H_A#11 R31 K12 AU24 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SB_CK#_0 M_CLK_DDR#2 (14)
H_D#8 D4 N17 H_A#12 1K_0402_1% @ R71 AL34 AV20 M_CLK_DDR#3
H_D#_8 H_A#_12 2 2 RSVD10 SB_CK#_1 M_CLK_DDR#3 (14)
H_D#9 H3 M13 H_A#13 0_0402_5% AK34
H_D#10 H_D#_9 H_A#_13 H_A#14 CLK_MCH_DREFCLK 1 RSVD11 DDR_CKE0_DIMMA
M9 E17 2 AN35 BC28 DDR_CKE0_DIMMA (13)

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH @ R72 RSVD12 SA_CKE_0 DDR_CKE1_DIMMA
M11 H_D#_11 H_A#_15 P17 AM35 RSVD13 SA_CKE_1 AY28 DDR_CKE1_DIMMA (13)
D H_D#12 H_A#16 0_0402_5% DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 RSVD14 SB_CKE_0 AY36 DDR_CKE2_DIMMB (14)

1
H_D#13 J2 G20 H_A#17 CLK_MCH_DREFCLK# 1 2 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB (14)

RSVD
H_D#14 N12 B19 H_A#18 R32 @ R73 B31
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% 0_0402_5% RSVD15 DDR_CS0_DIMMA#
J6 H_D#_15 H_A#_19 J16 B2 RSVD16 SA_CS#_0 BA17 DDR_CS0_DIMMA# (13)
H_D#16 P2 E20 H_A#20 MCH_SSCDREFCLK 1 2 M1 AY16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 RSVD17 SA_CS#_1 DDR_CS1_DIMMA# (13)
H_D#17 L2 H16 H_A#21 @ R74 AV16 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# (14)

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL 0_0402_5% SB_CS#_0 DDR_CS3_DIMMB#
R2 H_D#_18 H_A#_22 J20 SB_CS#_1 AR13 DDR_CS3_DIMMB# (14)
H_D#19 N9 L17 H_A#23 MCH_SSCDREFCLK# 1 2 AY21
H_D#_19 H_A#_23 RSVD20

1
0.01U_0402_25V7K
H_D#20 H_A#24 M_ODT0

2.2U_0603_6.3V4Z
L6 H_D#_20 H_A#_24 A17 SA_ODT_0 BD17 M_ODT0 (13)
H_D#21 H_A#25 R33 M_ODT1
H_D#22
M5
J3
H_D#_21 H_A#_25 B17
L16 H_A#26
1 1
1K_0402_1% SA_ODT_1 AY17
BF15 M_ODT2
M_ODT1 (13) +1.5V DDR3
H_D#_22 H_A#_26 SB_ODT_0 M_ODT2 (14)

C53

C54
H_D#23 N2 C21 H_A#27 BG23 AY13 M_ODT3 M_ODT3 (14)
H_D#24 H_D#_23 H_A#_27 H_A#28 RSVD22 SB_ODT_1
R1 J17 BF23

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD23 SMRCOMP R34
N5 H_D#_25 H_A#_29 H20 BH18 RSVD24 SM_RCOMP BG22 1 2 80.6_0402_1%
H_D#26 H_A#30 SMRCOMP# R35 2 80.6_0402_1%
H_D#27
N6
P13
H_D#_26 H_A#_30 B18
K17 H_A#31
BF18 RSVD25 SM_RCOMP# BH21 1 DDR3
H_D#28 H_D#_27 H_A#_31 H_A#32 SMRCOMP_VOH R1101
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 SMRCOMP_VOL 1 2
H_D#_29 H_A#_33 SM_RCOMP_VOL DDR3_SM_PWROK (30,39)
H_D#30 N10 K21 H_A#34 0_0402_5%
H_D#31 H_D#_30 H_A#_34 H_A#35 +V_DDR3_MCH_REF
M3 H_D#_31 H_A#_35 L20 SM_VREF AV42
H_D#32 Y3 +3VS AR36 SM_PWROK
H_D#33 H_D#_32 H_ADS# R38 SM_PWROK SM_REXT R37
AD14 H_D#_33 H_ADS# H12 H_ADS# (4) SM_REXT BF17 1 2 499_0402_1%
H_D#34 Y6 B16 H_ADSTB#0 PM_EXTTS#0 1 2 BC36 SM_DRAMRST#
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (4) SM_DRAMRST# SM_DRAMRST# (13,14)
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 (4)
H_D#36 Y12 A9 H_BNR# 10K_0402_5% B38 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# (4) DPLL_REF_CLK CLK_MCH_DREFCLK (15)
H_D#37 Y14 F11 H_BPRI# A38 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# (4) DPLL_REF_CLK# CLK_MCH_DREFCLK# (15)
H_D#38 Y7 G12 H_BR0# R39 E41 MCH_SSCDREFCLK
HOST
H_D#_38 H_BREQ# H_BR0# (4) DPLL_REF_SSCLK MCH_SSCDREFCLK (15)
H_D#39 W2 E9 H_DEFER# PM_EXTTS#0_1 1 2 F41 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# (4) DPLL_REF_SSCLK# MCH_SSCDREFCLK# (15)
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# (4)
H_D#41 CLK_MCH_BCLK 10K_0402_5% CLK_MCH_3GPLL

CLK
Y9 H_D#_41 HPLL_CLK AH7 CLK_MCH_BCLK (15) PEG_CLK F43 CLK_MCH_3GPLL (15)
H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (15) PEG_CLK# CLK_MCH_3GPLL# (15)
H_D#43 AA9 J11 H_DPWR# R40
C H_D#_43 H_DPWR# H_DPWR# (5) C
H_D#44 AA11 F9 H_DRDY# CLKREQ#_7 1 2
H_D#_44 H_DRDY# H_DRDY# (4)
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# (4)
H_D#46 AD10 E12 H_HITM# 10K_0402_5% AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# (4) DMI_RXN_0 DMI_TXN0 (18)
H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# (4) DMI_RXN_1 DMI_TXN1 (18)
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# (4) DMI_RXN_2 DMI_TXN2 (18)
H_D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 (18)
H_D#50 AA2
H_D#51 H_D#_50 DMI_TXP0
AD8 H_D#_51 DMI_RXP_0 AE40 DMI_TXP0 (18)
H_D#52 AA3 MCH_CLKSEL0 T25 AE38 DMI_TXP1
H_D#_52 (15) MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 (18)
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1 R25 AE48 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 (5) (15) MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 (18)
H_D#54 AD7 L3 H_DINV#1 MCH_CLKSEL2 P25 AH40 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 (5) (15) MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 (18)
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 (5) CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 (5) CFG_4 DMI_TXN_0 DMI_RXN0 (18)
H_D#57 AC1 CFG5 C25 AE43 DMI_RXN1
H_D#_57 T75 CFG_5 DMI_TXN_1 DMI_RXN1 (18)
H_D#58 AE3 L10 H_DSTBN#0 CFG6 N24 AE46 DMI_RXN2
H_D#_58 H_DSTBN#_0 H_DSTBN#0 (5) T76 CFG_6 DMI_TXN_2 DMI_RXN2 (18)
H_D#59 AC3 M7 H_DSTBN#1 CFG7 M24 AH42 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (5) T77 CFG_7 DMI_TXN_3 DMI_RXN3 (18)
H_D#60 AE11 AA5 H_DSTBN#2 E21
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (5) CFG_8

DMI
CFG
H_D#61 AE8 AE6 H_DSTBN#3 R1432 1 2 2.2K_0402_5% CFG9 C23 AD35 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (5) CFG_9 DMI_TXP_0 DMI_RXP0 (18)
H_D#62 AG2 CFG10 C24 AE44 DMI_RXP1
H_D#_62 T80 CFG_10 DMI_TXP_1 DMI_RXP1 (18)
H_D#63 AD6 L9 H_DSTBP#0 N21 AF46 DMI_RXP2
H_D#_63 H_DSTBP#_0 H_DSTBP#0 (5) CFG_11 DMI_TXP_2 DMI_RXP2 (18)
M8 H_DSTBP#1 CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 (5) T82 CFG_12 DMI_TXP_3 DMI_RXP3 (18)
AA6 H_DSTBP#2 CFG13 T21
H_DSTBP#_2 H_DSTBP#2 (5) T83 CFG_13
H_SWNG C5 AE5 H_DSTBP#3 R20
H_SWING H_DSTBP#_3 H_DSTBP#3 (5) CFG_14
H_RCOMP E3 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 B15 H_REQ#0 (4) T86 L21 CFG_16
K13 H_REQ#1 H21
H_REQ#_1 H_REQ#1 (4) CFG_17
H_REQ#2 +3VS VGATE GMCH_PWROK

GRAPHICS VID
H_REQ#_2 F13 H_REQ#2 (4) P29 CFG_18 (18,41) VGATE 1 2
B13 H_REQ#3 CFG19 R28 R55 @ 0_0402_5%
H_REQ#_3 H_REQ#3 (4) T89 CFG_19
(4) H_RESET# H_RESET# C12 B14 H_REQ#4 1 2 CFG20 T28 B33 ICH_PWROK 1 2
H_CPURST# H_REQ#_4 H_REQ#4 (4) CFG_20 GFX_VID_0 (18) ICH_PWROK
(5) H_CPUSLP# H_CPUSLP# E11 R1843 4.02K_0402_1% @ B32 R66 0_0402_5%
H_CPUSLP# H_RS#0 GFX_VID_1
H_RS#_0 B6 H_RS#0 (4) GFX_VID_2 G33
F12 H_RS#1 H_RS#1 (4) F33
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
H_RS#_2 C8 H_RS#2 (4) (18) PM_BMBUSY# R29 PM_SYNC# GFX_VID_4 E33
H_VREF A11 H_DPRSTP# B7
B11
H_AVREF DDR3 (5,17,41) H_DPRSTP#
PM_EXTTS#0 N33
PM_DPRSTP#
H_DVREF PM_EXTTS#0_1 R67 1 PM_EXT_TS#_0
(13,14) PM_EXTTS#0_1 2 0_0402_5% P32 PM_EXT_TS#_1

PM
CANTIGA_1p0 GMCH_PWROK AT40 C34
PLT_RST# PLT_RST#_NB PWROK GFX_VR_EN +VCCP
(16,18,20,26) PLT_RST# 1 2 AT11 RSTIN#
(4,17) H_THERMTRIP# 1 2 R520 100_0402_5% THERMTRIP# T20
R41 0_0402_5% DPRSLPVR THERMTRIP#
(18,41) DPRSLPVR R32 DPRSLPVR CL_CLK0 (18)

1
Layout Note: CL_DATA0 (18)
CL_CLK0 R42
H_RCOMP / H_VREF / H_SWNG +1.5V DDR3 CL_CLK AH37

0.1U_0402_16V4Z
Layout Note: AH36 CL_DATA0 1K_0402_1%
CL_DATA ICH_PWROK
trace width and spacing is 10/20 V_DDR_MCH_REF 1 @ BG48 NC_1 CL_PWROK AN36 1 2 R51
C55 BF48 AJ35 CL_RST# 0_0402_5%
CL_RST# (18)

2
NC_2 CL_RST#
1

ME
trace width and BD48 AH34 CL_VREF
+VCCP R44 NC_3 CL_VREF
spacing is 20/20. BC48 NC_4

1
+VCCP 1K_0402_1% 2
BH47 NC_5 1
BG47 C56
NC_6 511_0402_1%
1K_0402_1%

221_0603_1%

BE47 N28 0.1U_0402_16V4Z

T36
2

NC_7 DDPC_CTRLCLK
1

+V_DDR3_MCH_REF BH46 M28 R43

NC_8 DDPC_CTRLDATA T37 2
R45 R46 BF46 G36 SDVO_SCLK
SDVO_SCLK (21)

2
NC_9 SDVO_CTRLCLK
1

NC
0.1U_0402_16V4Z

BG45 E36 SDVO_SDAT

NC_10 SDVO_CTRLDATA SDVO_SDAT (21)
1 R47 BH44 K36 CLKREQ#_7
NC_11 CLKREQ# CLKREQ#_7 (15)
C57 1K_0402_1% BH43 H36 MCH_ICH_SYNC#
MCH_ICH_SYNC# (18)
2

H_VREF H_RCOMP H_SWNG NC_12 ICH_SYNC#

BH6

MISC
NC_13
BH5
change logic
2

2 NC_14
24.9_0402_1%

0.1U_0402_16V4Z

BG4 B12 MCH_TSATN#

NC_15 TSATN#
1

1
100_0402_1%
0.1U_0402_16V4Z

1 1 BH3
define by EC NC_16
2K_0402_1%

R52 C58 R53 R54 C59 BF3 33_0402_5%

NC_17 UMA@ R109
BH2 NC_18
BG2 B28 HDA_BITCLK_MCH
2 2 +3VS NC_19 HDA_BCLK HDA_BITCLK_MCH (17)
BE2 B30 HDA_RST_MCH#
HDA_RST_MCH# (17)
2

NC_20 HDA_RST# HDA_SDIN1_MCH 1

BG1 NC_21 HDA_SDI B29 2 HDA_SDIN1 (17)
A HDA_SDOUT_MCH A
BF1 NC_22 HDA_SDO C29 HDA_SDOUT_MCH (17)
1

+VCCP

HDA
normal:low BD1 A28 HDA_SYNC_MCH HDA_SYNC_MCH (17)
R63 NC_23 HDA_SYNC
over temp:high BC1 NC_24
within 100 mils from NB Near B3 pin 1K_0402_5% F1 NC_25
1

A47 NC_26
R64
2

54.9_0402_1% MCH_TSATN_EC# (31) CANTIGA_1p0

R68 Security Classification Compal Secret Data Compal Electronics, Inc.
1

C
2

MCH_TSATN# 1 2 2 Q5 2007/09/29 2007/09/29 Title

B Issued Date Deciphered Date
MMBT3904_SOT23-3
330_0402_5% E
<BOM Structure>
SCHEMATIC,MB A5011
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 7 of 43
5 4 3 2 1
 5 4 3 2 1

D D

(13) DDR_A_D[0..63] (14) DDR_B_D[0..63]

U2D U2E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 (13) SB_DQ_0 SB_BS_0 DDR_B_BS0 (14)
DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 (13) SB_DQ_1 SB_BS_1 DDR_B_BS1 (14)
DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 (13) SB_DQ_2 SB_BS_2 DDR_B_BS2 (14)
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# (13) AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_B_D5 AJ48 AU17 DDR_B_RAS#
SA_DQ_5 SA_CAS# DDR_A_CAS# (13) SB_DQ_5 SB_RAS# DDR_B_RAS# (14)
DDR_A_D6 AM44 AY20 DDR_A_WE# DDR_A_WE# (13) DDR_B_D6 AM48 BG16 DDR_B_CAS#
SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# DDR_B_CAS# (14)
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14 DDR_B_WE# DDR_B_WE# (14)
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AN43 SA_DQ_8 AU47 SB_DQ_8
DDR_A_D9 AN44 DDR_B_D9 AU46
SA_DQ_9 DDR_A_DM[0..7] (13) SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 SA_DM_0 AM37 AY48 SB_DQ_11 DDR_B_DM[0..7] (14)
DDR_A_D12 AN41 AT41 DDR_A_DM1 DDR_B_D12 AT47 AM47 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
DDR_A_D18 BA40 AJ5 DDR_A_DM7 DDR_B_D18 BG43 AP1 DDR_B_DM6

B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BD43 SA_DQ_19 DDR_A_DQS[0..7] (13) BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] (14)
DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 MEMORY BC37 DDR_A_DQS3 DDR_B_D23 BF41 DDR_B_DQS2

MEMORY
SA_DQ_23 SA_DQS_3 SB_DQ_23 SB_DQS_2 BG41
DDR_A_D24 AY37 AW12 DDR_A_DQS4 DDR_B_D24 BG38 BG37 DDR_B_DQS3
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 DDR_A_DQS#[0..7] (13) BG35 SB_DQ_27 SB_DQS_6 AU1
DDR_A_D28 AY38 AJ43 DDR_A_DQS#0 DDR_B_D28 BH40 AN6 DDR_B_DQS7
C SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 DDR_B_DQS#[0..7] (14) C
DDR_A_D29 BB38 AT43 DDR_A_DQS#1 DDR_B_D29 BG39 AL46 DDR_B_DQS#0
DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
DDR_A_D31 AW36 BD37 DDR_A_DQS#3 DDR_B_D31 BH34 BH41 DDR_B_DQS#2
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
DDR_A_D35 BA12 AM8 DDR_A_DQS#7 DDR_B_D35 BG8 AT2 DDR_B_DQS#6
SYSTEM

SA_DQ_35 SA_DQS#_7 DDR_A_MA[0..14] (13) SB_DQ_35 SB_DQS#_6

DDR_A_D36 DDR_B_D36 DDR_B_DQS#7

SYSTEM
AU13 SA_DQ_36 BH12 SB_DQ_36 SB_DQS#_7 AN5
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11 DDR_B_MA[0..14] (14)
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 SA_DQ_38 SA_MA_1 BC24 BF8 SB_DQ_38 SB_MA_0 AV17
DDR_A_D39 BC12 BG24 DDR_A_MA2 DDR_B_D39 BG7 BA25 DDR_B_MA1
DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
BB9 SA_DQ_40 SA_MA_3 BH24 BC5 SB_DQ_40 SB_MA_2 BC25
DDR_A_D41 BA9 BG25 DDR_A_MA4 DDR_B_D41 BC6 AU25 DDR_B_MA3
DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
AU10 SA_DQ_42 SA_MA_5 BA24 AY3 SB_DQ_42 SB_MA_4 AW25
DDR_A_D43 AV9 BD24 DDR_A_MA6 DDR_B_D43 AY1 BB28 DDR_B_MA5
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 SA_DQ_44 SA_MA_7 BG27 BF6 SB_DQ_44 SB_MA_6 AU28
DDR_A_D45 BD9 BF25 DDR_A_MA8 DDR_B_D45 BF5 AW28 DDR_B_MA7
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 SA_DQ_46 SA_MA_9 AW24 BA1 SB_DQ_46 SB_MA_8 AT33
DDR_A_D47 BA6 BC21 DDR_A_MA10 DDR_B_D47 BD3 BD33 DDR_B_MA9
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
DDR

AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16

DDR_A_D49 DDR_A_MA12 DDR_B_D49 DDR_B_MA11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
DDR_A_D52 AU5 DDR_B_D52 AY2 AU33 DDR_B_MA14
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
DDR_A_D54 AT5 DDR_B_D54 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
DDR_A_D58 AJ9 DDR_B_D58 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
DDR_A_D60 AN12 DDR_B_D60 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 8 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS DPST_PWM U2C

(22) DPST_PWM
R227 2 1 100K_0402_5% PEGCOMP trace width Strap Pin Table
R56 +VCC_PEG and spacing is 20/25 mils.
L32 L_BKLT_CTRL 10mils 000 = FSB 1066MHz
2

2
(22) IGPU_L_BKLT_EN R91 0_0402_5% ENABLT_R G32 T37 1 2 CFG[2:0] FSB Freq select
R571 R570 R57 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 1 2 10K_0402_5% M32 L_CTRL_CLK PEG_COMPO T36 49.9_0402_1%
2.2K_0402_5% 2.2K_0402_5%
R58 1 2 10K_0402_5% M33
011 = FSB 667MHz
DDC2_CLK L_CTRL_DATA PCIE_GTX_C_MRX_N15
(22) DDC2_CLK K33 H44 Others = Reserved
1

1
DDC2_CLK DDC2_DATA L_DDC_CLK PEG_RX#_0 PCIE_GTX_C_MRX_N14
(22) DDC2_DATA J33 L_DDC_DATA PEG_RX#_1 J46
DDC2_DATA L44 PCIE_GTX_C_MRX_N13
PEG_RX#_2 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N[0..15]
PEG_RX#_3 L40 PCIE_GTX_C_MRX_N[0..15] (21) CFG[4:3] Reserved
(23) ENAVDD ENAVDD M29 N41 PCIE_GTX_C_MRX_N11
R59 L_VDD_EN PEG_RX#_4 PCIE_GTX_C_MRX_P[0..15]
1 2 2.37K_0402_1% C44 LVDS_IBG PEG_RX#_5 P48 PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P[0..15] (21) 0 = DMI x 2
D For Crestline:2.4kohm B43 N44 PCIE_GTX_C_MRX_N9 CFG5 (DMI select) D
LVDS_VBG PEG_RX#_6 1 = DMI x 4
For Calero: 1.5Kohm
For Cantiga: 2.37Kohm
R92 0_0402_5% E37
E38
LVDS_VREFH
LVDS_VREFL
PEG_RX#_7
PEG_RX#_8
T43
U43
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N7 *
0 = The iTPM Host Interface is enable

LVDS
LVDS_A_C- C41 Y43 PCIE_GTX_C_MRX_N6 PCIE_MTX_C_GRX_N[0..15] CFG6
(22) LVDS_A_C- LVDSA_CLK# PEG_RX#_9 PCIE_MTX_C_GRX_N[0..15] (21)
LVDS_A_C+ C40 Y48 PCIE_GTX_C_MRX_N5 1 = The iTPM Host Interface is disable
(22)
(22)
(22)
LVDS_A_C+
LVDS_B_C-
LVDS_B_C+
LVDS_B_C-
LVDS_B_C+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11 Y36
AA43
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N3
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_P[0..15] (21)
0 =(TLS)chiper suite with no confidentiality
*
LVDSB_CLK PEG_RX#_12 PCIE_GTX_C_MRX_N2
PEG_RX#_13 AD37 CFG7 (Intel Management
LVDS_A_0- H47 AC47 PCIE_GTX_C_MRX_N1 1 =(TLS)chiper suite with confidentiality
(22) LVDS_A_0-
(22) LVDS_A_1-
(22) LVDS_A_2-
LVDS_A_1-
LVDS_A_2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15 AD39 PCIE_GTX_C_MRX_N0 Engine Crypto strap)
*
LVDSA_DATA#_2 PCIE_GTX_C_MRX_P15
A40 LVDSA_DATA#_3 PEG_RX_0 H43

GRAPHICS
J44 PCIE_GTX_C_MRX_P14 CFG8 Reserved
LVDS_A_0+ PEG_RX_1 PCIE_GTX_C_MRX_P13
(22) LVDS_A_0+ H48 LVDSA_DATA_0 PEG_RX_2 L43
(22) LVDS_A_1+ LVDS_A_1+ D45 L41 PCIE_GTX_C_MRX_P12
LVDS_A_2+ LVDSA_DATA_1 PEG_RX_3 PCIE_GTX_C_MRX_P11
(22) LVDS_A_2+ F40 LVDSA_DATA_2 PEG_RX_4 N40 CFG9 0 = Reverse Lane,15->0, 14->1
B40 P47 PCIE_GTX_C_MRX_P10
LVDSA_DATA_3 PEG_RX_5 PCIE_GTX_C_MRX_P9
PEG_RX_6 N43 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
LVDS_B_0- A41 T42 PCIE_GTX_C_MRX_P8
(22) LVDS_B_0-
(22) LVDS_B_1-
(22) LVDS_B_2-
LVDS_B_1-
LVDS_B_2-
H38
G37
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_7
PEG_RX_8 U42
Y42
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P6 0 = Enable
*
LVDSB_DATA#_2 PEG_RX_9 PCIE_GTX_C_MRX_P5
J37 LVDSB_DATA#_3 PEG_RX_10 W47 CFG10 (PCIE Lookback enable)
Y37 PCIE_GTX_C_MRX_P4 1 = Disable
(22) LVDS_B_0+
(22) LVDS_B_1+
LVDS_B_0+
LVDS_B_1+
B42
G38
LVDSB_DATA_0
PEG_RX_11
PEG_RX_12 AA42
AD36
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P2 CFG11 Reserved
*
LVDS_B_2+ LVDSB_DATA_1 PEG_RX_13 PCIE_GTX_C_MRX_P1
(22) LVDS_B_2+ F37 LVDSB_DATA_2 PEG_RX_14 AC48

PCI-EXPRESS
K37 AD40 PCIE_GTX_C_MRX_P0 CFG[13:12] (XOR/ALLZ) 00 = Reserved
LVDSB_DATA_3 PEG_RX_15
01 = XOR Mode Enabled
J41 PCIE_MTX_GRX_N15 C264 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15 10 = All Z Mode Enabled
PEG_TX#_0 PCIE_MTX_GRX_N14 C260 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
M46 2 11 = Normal Operation(Default)
R880 2
R881 2
1 75_0402_1%
1 75_0402_1%
GMCH_TV_COMPS
GMCH_TV_LUMA
F25
H25
TVA_DAC
PEG_TX#_1
PEG_TX#_2 M47
M40
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N12
C252 1 2 0.1U_0402_16V7K
C309 1 2
PCIE_MTX_C_GRX_N13
0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 CFG[15:14] Reserved
*
R882 2 TVB_DAC PEG_TX#_3
C
1 75_0402_1% GMCH_TV_CRMA K25 TVC_DAC PEG_TX#_4 M42 PCIE_MTX_GRX_N11 C261 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
C

TV
R48 PCIE_MTX_GRX_N10 C265 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PEG_TX#_5 PCIE_MTX_GRX_N9 C308 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
H24 TV_RTN PEG_TX#_6 N38 2 CFG16 (FSB Dynamic ODT) 0 = Disabled
T40 PCIE_MTX_GRX_N8 C267 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PEG_TX#_7 PCIE_MTX_GRX_N7 C242 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 2 1 = Enabled
R87 0_0402_5% TV_DCONSEL_0 C31
PEG_TX#_8
PEG_TX#_9 U40
Y40
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N5 C235 1 2 0.1U_0402_16V7K
C237 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N5
*
R88 0_0402_5% TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N4 C231 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 CFG[18:17] Reserved
AA37 PCIE_MTX_GRX_N3 C229 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
M_BLUE PEG_TX#_12 PCIE_MTX_GRX_N2 C222 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
(24) M_BLUE PEG_TX#_13 AA40 2
M_GREEN AD43 PCIE_MTX_GRX_N1 C219 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 CFG19 (DMI Lane Reversal) 0 = Normal Operation
(24) M_GREEN
(24) M_RED M_RED
R552
PEG_TX#_14
PEG_TX#_15 AC46 PCIE_MTX_GRX_N0 C210 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
(Lane number in Order)
*
1 2 E28 J42 PCIE_MTX_GRX_P15 C251 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
R553 150_0402_1% CRT_BLUE PEG_TX_0 PCIE_MTX_GRX_P14 C255 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PEG_TX_1 L46 2 1 = Reverse Lane
1 2 G28 M48 PCIE_MTX_GRX_P13 C262 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R554 150_0402_1% CRT_GREEN PEG_TX_2 PCIE_MTX_GRX_P12 C254 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
M39 2
1 2 J28 CRT_RED
PEG_TX_3
PEG_TX_4 M43 PCIE_MTX_GRX_P11 C266 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11 CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational. *
150_0402_1%
G29 CRT_IRTN
VGA PEG_TX_5
PEG_TX_6
R47
N37
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P9 C250 1 2 0.1U_0402_16V7K
C263 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P9 1 = PCIE/SDVO are operating simu.
T39 PCIE_MTX_GRX_P8 C307 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
3VDDCCL PEG_TX_7 PCIE_MTX_GRX_P7 C238 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
(24) 3VDDCCL H32 CRT_DDC_CLK PEG_TX_8 U36 2
3VDDCDA J32 U39 PCIE_MTX_GRX_P6 C236 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
(24) 3VDDCDA CRT_DDC_DATA PEG_TX_9
(24) CRT_HSYNC CRT_HSYNC 1 2 R85 30.1_0402_1% J29 Y39 PCIE_MTX_GRX_P5 C232 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
CRT_HSYNC PEG_TX_10 PCIE_MTX_GRX_P4 C230 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
E29 CRT_TVO_IREF PEG_TX_11 Y46 2
(24) CRT_VSYNC CRT_VSYNC 1 2 R86 30.1_0402_1% L29 AA36 PCIE_MTX_GRX_P3 C223 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
CRT_VSYNC PEG_TX_12 PCIE_MTX_GRX_P2 C220 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PEG_TX_13 AA39 2
AD42 PCIE_MTX_GRX_P1 C218 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PEG_TX_14
2

R89 R90 R81 AD46 PCIE_MTX_GRX_P0 C208 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0

PEG_TX_15
0_0402_5%

0_0402_5%

1.02K_0402_1%
CANTIGA_1p0
1

B B

@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 9 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_CRT +3VS
L49
1 2
+VCCP +VCCP
0_0402_5% @

0.022U_0402_16V7K
BLM18PG181SN1D_0603 +V1.05VS_AXF

4.7U_0805_10V4Z

0.1U_0402_16V4Z
R99
R527 2

C871

C73

C74
1 1 1 U2H 1 2

10U_0805_10V4Z

1U_0603_10V4Z
220U_D2_4VM_R15 0_0603_5%
852mA U13
+1.05VS_PEGPLL VTT_1

4.7U_0805_10V4Z
+VCCP 73mA T13 1 1 1
2 2 2 VTT_2

C68

C69
L1 B27 U12 1
1

VCCA_CRT_DAC_1 VTT_3

C67
1 2 A26 T12 C64 +
+3VS_DAC_CRT VCCA_CRT_DAC_2 VTT_4
BLM18PG121SN1D_0603 U11
VTT_5 2 2

0.1U_0402_16V4Z

10U_0805_10V4Z
2.68mA T11
VTT_6 2 2
1 1 A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT_7

C98

C99
D
+3VS_DAC_BG B25 VSSA_DAC_BG VTT_8 T10 D
+3VS U9
L47 VTT_9
VTT_10 T9
2 2
1 2 VTT_11 U8
0_0402_5% @

0.022U_0402_16V7K

BLM18PG181SN1D_0603 +1.05VS_DPLLA F47 64.8mA T8

VCCA_DPLLA VTT_12 +1.5V_SM_CK
4.7U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
U7 DDR3 +1.5V

VTT
VTT_13
R528 2

1 1 1 1 +1.05VS_DPLLB L48 64.8mA T7 1 1 1 L50

VCCA_DPLLB VTT_14
C60

C61

C62

0.1U_0402_16V4Z
VTT_15 U6 1 2

10U_0805_10V4Z
C70

C71

C72
AD1 24mA T6 MBK1608121YZF_0603

PLL
+1.05VS_HPLL VCCA_HPLL VTT_16
VTT_17 U5 1 1

2
2 2 2 2 2 2 2

C77
C655

+1.05VS_MPLL AE1 139.2mA T5

1

VCCA_MPLL VTT_18 @ R883

VTT_19 V3

C75
13.2mA U3 1_0402_1%
VTT_20 2 2
+1.8V_TXLVDS J48 VCCA_LVDS VTT_21 V2
1 U2

A LVDS

1
VTT_22

10U_0805_10V4Z
C80 J47 T2
VSSA_LVDS VTT_23
VTT_24 V1 1

C76
@ R104 1000P_0402_50V7K 414uA U1
2 VTT_25
+3VS 1 2
0_0603_5% AD48
+1.05VS_DPLLA +1.5VS_PEG_BG VCCA_PEG_BG 2
+VCCP R105
L48 1 2

A PEG
+1.5VS
1 2 0_0603_5% 50mA
@

0_1210_5% 1 +1.05VS_PEGPLL AA48 VCCA_PEG_PLL

0.1U_0402_16V4Z

10U_0805_10V4Z

<BOM Structure>
220U_D2_4VM_R15

1 C81
R529 2

C65

C66

1 1
C63 + 0.1U_0402_16V4Z DDR3:747.5mA AR20
2 VCCA_SM_1
0_0402_5%

AP20 VCCA_SM_2
AN20 40 mils +1.8V_TXLVDS
2 2 2 AR17
VCCA_SM_3
POWER
1

VCCA_SM_4

@
AP17 R116
+VCCP VCCA_SM_5
+1.05VS_A_SM AN17 VCCA_SM_6 1 2 +1.8V

1000P_0402_50V7K
0_0402_5%
AT16 0_0603_5%
VCCA_SM_7

10U_0805_10V4Z
220U_D2_4VM_R15 R108 AR16

A SM
VCCA_SM_8

2
C C

C108
1 2 AP16 VCCA_SM_9 1 1

C107
1 0_0805_5%

22U_0805_6.3V6M

4.7U_0805_10V4Z
1 1 1
C86 + C800 C89
+1.05VS_DPLLB +VCCP 2 2

R531
C88 1U_0603_10V4Z

1
L51 DDR3:37.95mA
1 2 2 2 2 2 321.35mA
@

0.1U_0402_16V4Z

0_1210_5% AP28 VCCA_SM_CK_1

C78

C79

10U_0805_10V4Z

AN28 VCCA_SM_CK_2 VCC_AXF_1 B22 +V1.05VS_AXF

R530 2

1 1 AP25 B21

AXF
+1.05VS_A_SM_CK VCCA_SM_CK_3 VCC_AXF_2
0_0402_5%

R111 AN25 A21

VCCA_SM_CK_4 VCC_AXF_3
1 2 AN24 VCCA_SM_CK_5

1U_0603_10V4Z

0.1U_0402_16V4Z
0_0603_5% AM28 124mA +VCCP
2 2 VCCA_SM_CK_NCTF_1 +VCC_PEG J1
AM26

A CK
1

VCCA_SM_CK_NCTF_2 JUMP_43X79
1 1 1 1 AM25 VCCA_SM_CK_NCTF_3
C96

C97
C94 C802 AL25 BF21 +1.5V_SM_CK @
VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
AM24 BH20 1 1 2 2

SM CK
1U_0603_10V4Z VCCA_SM_CK_NCTF_5 VCC_SM_CK_2
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
2 2 2 2

10U_0805_10V4Z
AM23 BF20 220U_D2_4VM_R15 1
22U_0805_6.3V6M VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 DDR3

4.7U_0805_10V4Z
AL23 VCCA_SM_CK_NCTF_8 1 1

C91
DDR3:149.5mA C90 + C801
+1.05VS_HPLL +VCCP TVA 24.15mA
L52 TVB 39.48mA K47 +1.8V_TXLVDS
VCC_TX_LVDS 2 2 2
1 2 B24 TVX 24.15mA
VCCA_TV_DAC_1 +3VS_HV
MBK2012121YZF_2P +3VS_TVDAC A24 C35
VCCA_TV_DAC_2 VCC_HV_1

TV
105.3mA B35
VCC_HV_2
0.1U_0402_16V4Z

10U_0805_10V4Z

1 1 A35

HV
VCC_HV_3
C82

C83

R525

0.1U_0402_16V4Z
+1.5VS 1 2 VCC_HDA A32 50mA
VCC_HDA

HDA
0_0402_5% V48 +VCC_PEG 1
2 2 VCC_PEG_1
0.1U_0402_16V4Z

C101
1732mA U48
VCC_PEG_2
2
0_0402_5%

0814 Add R,C 1 V47

PEG
R533 C475 VCC_PEG_3
VCC_PEG_4 U47
2

D TV/CRT
+1.5VS_TVDAC M25 58.67mA U46
VCCD_TVDAC VCC_PEG_5 +1.05VS_DMI
@

B +VCC_PEG B
2 L28 48.363mA R112
+1.5VS_QDAC
1

VCCD_QDAC
VCC_DMI_1 AH48 +1.05VS_DMI 1 2
+1.05VS_MPLL +VCCP AF1 157.2mA AF48 0_0603_5%
+1.05VS_HPLL VCCD_HPLL VCC_DMI_2

0.1U_0402_16V4Z
L53 AH47

DMI
50mA VCC_DMI_3
1 2 +1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI_4 AG47
MBK2012121YZF_2P 1
1

C100
456mA
1 R884 M38 VCCD_LVDS_1

LVDS
C92 0.5_0603_1% +1.8V_LVDS L37 A8
VCCD_LVDS_2 VTTLF1 2
+1.5VS_TVDAC VTTLF2 L1
+1.5VS

VTTLF
0.1U_0402_16V4Z 60.31mA AB2
2

2 R107 VTTLF3
1

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K
1 2
0.022U_0402_16V7K

0.1U_0402_16V4Z

C803 0_0805_5% 1 1 1

C102

C103

C104
22U_0805_6.3V6M CANTIGA_1p0
2
1 1
+3VS
2 2 2
C84

C85

2 2 D3
R113 R114
+VCCP 2 1 1 2 1 2 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+1.8V_LVDS

R115
@

1 2 +1.8V
10U_0805_10V4Z

0_0603_5%
0_0402_5%

1 1
2

C105

C106

1U_0603_10V4Z

+1.5VS_QDAC +1.5VS
+3VS_TVDAC +3VS
L54 R120 2 2
A A
@ 1 2 1 2
1
0.022U_0402_16V7K

0.022U_0402_16V7K

R534

BLM18PG181SN1D_0603 100_0603_1%
0.1U_0402_16V4Z

0.1U_0402_16V4Z
0_0402_5%
2

C110

C111

C112

C113

1 1 1 1

2 2 2 2
1

Security Classification Compal Secret Data Compal Electronics, Inc.

R536

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 10 of 43
5 4 3 2 1
 5 4 3 2 1

U2G +VGFX_CORE

AP33 VCC_SM_1 VCC_AXG_NCTF_1 W28

DDR3:4140mA AN33 V28
VCC_SM_2 VCC_AXG_NCTF_2
+1.5V BH32 VCC_SM_3 VCC_AXG_NCTF_3 W26
U2F BG32 V26
+VCCP VCC_SM_4 VCC_AXG_NCTF_4

0.01U_0402_16V7K
DDR3 BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 VCC_SM_6 VCC_AXG_NCTF_6 V25
C117 1 1 2 BC32 W24
VCC_SM_7 VCC_AXG_NCTF_7

C118

C119

C120
D
AG34 + BB32 V24 D
VCC_1 VCC_SM_8 VCC_AXG_NCTF_8
AC34 VCC_2 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AB34 330U_D2E_2.5VM_R15 AY32 V23
VCC_3 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_10
AA34 VCC_4 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
Y34 VCC_5 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
V34 VCC_6 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
U34 VCC_7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AM33 0317 change value AR32 V21
VCC_8 VCC_SM_15 VCC_AXG_NCTF_15

POWER
AK33 VCC_9 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
AJ33 VCC_10 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC_11 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
10U_0805_10V4Z

220U_D2_4VM_R15 1 AF33 BG31 W20

VCC_12 VCC_SM_19 VCC_AXG_NCTF_19
1 1 1 1 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
+VCCP +VGFX_CORE
C122

C123

C124

C121 + C125
AE33 VCC_13 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19

VCC CORE
AC33 VCC_14 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
2 2 2 2 2
AA33 VCC_15 VCC_AXG: 6326.84mA BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
Y33 R106 BF29 AJ19
VCC_16 0.1U_0402_16V4Z 4.7U_0603_6.3V6M VCC_SM_24 VCC_AXG_NCTF_24
W33 VCC_17 1 2 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19

VCC SM
V33 0_0805_5% BC29 AG19
VCC_18 VCC_SM_26 VCC_AXG_NCTF_26

R537 2
0_0402_5%
U33 VCC_19 1 1 1 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19

@
AH28 @ C114 C115 C116 BA29 AE19
VCC_20 VCC_SM_28 VCC_AXG_NCTF_28
AF28 VCC_21 1 1 2 2 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AC28 VCC_22 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
J3 JUMP_43X79 2 2 2
AA28 AV29 Y19

1
VCC_23 VCC_SM_31 VCC_AXG_NCTF_31
AJ26 VCC_24 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AG26 0.22U_0402_10V4Z AT29 V19
VCC_25 VCC_SM_33 VCC_AXG_NCTF_33
AE26 VCC_26 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
AC26 VCC_27 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17
AH25 VCC_28 VCC_AXG_NCTF_36 AK17
AG25 VCC_SM_BA36 BA36 AH17
VCC_29 VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_37
AF25 VCC_30 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AG24 VCC_SM_BD16 BD16 AF17
C VCC_31 +VCCP VCC_SM_38/NC VCC_AXG_NCTF_39 C
AJ23 VCC_32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
AH23 VCC_SM_AW16 AW16 AC17
VCC_33 POWER VCC_SM_40/NC VCC_AXG_NCTF_41
AF23 VCC_34 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
AM32 VCC_SM_AT13 AT13 Y17
VCC_NCTF_1 VCC_SM_42/NC VCC_AXG_NCTF_43
T32 VCC_35 VCC_NCTF_2 AL32 VCC_AXG_NCTF_44 W17
AK32 6326.84mA V17

VCC GFX NCTF

VCC_NCTF_3 VCC_AXG_NCTF_45
VCC_NCTF_4 AJ32 VCC_AXG_NCTF_46 AM16
VCC_NCTF_5 AH32 Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
VCC_NCTF_6 AG32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_7 AE32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
AC32 +VGFX_CORE AA25 AH16
VCC_NCTF_8 VCC_AXG_4 VCC_AXG_NCTF_50
VCC_NCTF_9 AA32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
Y32 10U_0805_10V4Z 0.1U_0402_16V4Z AC24 AF16
VCC_NCTF_10 VCC_AXG_6 VCC_AXG_NCTF_52
VCC_NCTF_11 W32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_12 U32 1 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_13 AM30 1 1 1 1 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
AL30 C126 + C128 C129 C130 AC23 AA16
VCC_NCTF_14 VCC_AXG_10 VCC_AXG_NCTF_56
VCC_NCTF_15 AK30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
AH30 1U_0603_10V4Z C127 AA23 W16
VCC_NCTF_16 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_58
VCC_NCTF_17 AG30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_18 AF30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
AE30 10U_0805_10V4Z AE21
VCC_NCTF_19 330U_D2E_2.5VM_R15 VCC_AXG_15
VCC_NCTF_20 AC30 AC21 VCC_AXG_16
VCC_NCTF_21 AB30 AA21 VCC_AXG_17
VCC_NCTF_22 AA30 Y21 VCC_AXG_18
VCC_NCTF_23 Y30 AH20 VCC_AXG_19
VCC_NCTF_24 W30 AF20 VCC_AXG_20
VCC NCTF

VCC_NCTF_25 V30 AE20 VCC_AXG_21

VCC_NCTF_26 U30 AC20 VCC_AXG_22
VCC_NCTF_27 AL29 AB20 VCC_AXG_23
VCC_NCTF_28 AK29 AA20 VCC_AXG_24
VCC_NCTF_29 AJ29 T17 VCC_AXG_25
B B
VCC_NCTF_30 AH29 T16 VCC_AXG_26
VCC_NCTF_31 AG29 AM15 VCC_AXG_27
VCC_NCTF_32 AE29 AL15 VCC_AXG_28
VCC_NCTF_33 AC29 AE15 VCC_AXG_29
VCC_NCTF_34 AA29 AJ15 VCC_AXG_30
VCC_NCTF_35 Y29 AH15 VCC_AXG_31
VCC_NCTF_36 W29 AG15 VCC_AXG_32
VCC_NCTF_37 V29 AF15 VCC_AXG_33
VCC_NCTF_38 AL28 AB15 VCC_AXG_34
VCC_NCTF_39 AK28 AA15 VCC_AXG_35

VCC GFX
VCC_NCTF_40 AL26 Y15 VCC_AXG_36
VCC_NCTF_41 AK26 V15 VCC_AXG_37
VCC_NCTF_42 AK25 U15 VCC_AXG_38
VCC_NCTF_43 AK24 AN14 VCC_AXG_39
VCC_NCTF_44 AK23 AM14 VCC_AXG_40
U14 VCC_AXG_41 VCC_SM_LF1 AV44 VCCSM_LF1

VCC SM LF
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5
VCC_SM_LF6 AM10 VCCSM_LF6
CANTIGA_1p0
VCC_SM_LF7 BB13 VCCSM_LF7

C131 0.1U_0402_16V4Z

C132 0.1U_0402_16V4Z

C133

C134

C135

C136

C137
1 1 1 1 1 1 1
VCC_SM_BA36
VCC_SM_BB24 PAD T42 AJ14
VCC_SM_BD16 VCC_AXG_SENSE
PAD T43 AH14 VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
VCC_SM_AW16
VCC_SM_AT13

1 1 1 1 1
C875 C876 C877 C878 C879
@ @ @ @ @
A 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K A
2 2 2 2 2
0.1U_0402_16V7K 0.1U_0402_16V7K CANTIGA_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 11 of 43
5 4 3 2 1
 5 4 3 2 1

U2J
U2I BG21 AH8
VSS_199 VSS_297
L12 VSS_200 VSS_298 Y8
AU48 VSS_1 VSS_100 AM36 AW21 VSS_201 VSS_299 L8
AR48 VSS_2 VSS_101 AE36 AU21 VSS_202 VSS_300 E8
AL48 VSS_3 VSS_102 P36 AP21 VSS_203 VSS_301 B8
BB47 VSS_4 VSS_103 L36 AN21 VSS_204 VSS_302 AY7
AW47 VSS_5 VSS_104 J36 AH21 VSS_205 VSS_303 AU7
AN47 VSS_6 VSS_105 F36 AF21 VSS_206 VSS_304 AN7
AJ47 VSS_7 VSS_106 B36 AB21 VSS_207 VSS_305 AJ7
AF47 VSS_8 VSS_107 AH35 R21 VSS_208 VSS_306 AE7
D D
AD47 VSS_9 VSS_108 AA35 M21 VSS_209 VSS_307 AA7
AB47 VSS_10 VSS_109 Y35 J21 VSS_210 VSS_308 N7
Y47 VSS_11 VSS_110 U35 G21 VSS_211 VSS_309 J7
T47 VSS_12 VSS_111 T35 BC20 VSS_212 VSS_310 BG6
N47 VSS_13 VSS_112 BF34 BA20 VSS_213 VSS_311 BD6
L47 VSS_14 VSS_113 AM34 AW20 VSS_214 VSS_312 AV6
G47 VSS_15 VSS_114 AJ34 AT20 VSS_215 VSS_313 AT6
BD46 VSS_16 VSS_115 AF34 AJ20 VSS_216 VSS_314 AM6
BA46 VSS_17 VSS_116 AE34 AG20 VSS_217 VSS_315 M6
AY46 VSS_18 VSS_117 W34 Y20 VSS_218 VSS_316 C6
AV46 VSS_19 VSS_118 B34 N20 VSS_219 VSS_317 BA5
AR46 VSS_20 VSS_119 A34 K20 VSS_220 VSS_318 AH5
AM46 VSS_21 VSS_120 BG33 F20 VSS_221 VSS_319 AD5
V46 VSS_22 VSS_121 BC33 C20 VSS_222 VSS_320 Y5
R46 VSS_23 VSS_122 BA33 A20 VSS_223 VSS_321 L5
P46 VSS_24 VSS_123 AV33 BG19 VSS_224 VSS_322 J5
H46 VSS_25 VSS_124 AR33 A18 VSS_225 VSS_323 H5
F46 VSS_26 VSS_125 AL33 BG17 VSS_226 VSS_324 F5
BF44 VSS_27 VSS_126 AH33 BC17 VSS_227 VSS_325 BE4
AH44 VSS_28 VSS_127 AB33 AW17 VSS_228
AD44 P33 AT17 BC3
AA44
Y44
VSS_29
VSS_30
VSS_31
VSS_128
VSS_129
VSS_130
L33
H33
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
U44 VSS_32 VSS_131 N32 H17 VSS_232 VSS_330 R3
T44 K32 C17 P3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32 BA16
VSS_233

VSS_235
VSS_331
VSS_332
VSS_333
F3
BA2
BC43 VSS_36 VSS_135 A31 VSS_334 AW2
AV43 VSS_37 VSS_136 AN29 AU16 VSS_237 VSS_335 AU2
AU43 VSS_38 VSS_137 T29 AN16 VSS_238 VSS_336 AR2
AM43 VSS_39 VSS_138 N29 N16 VSS_239 VSS_337 AP2
J43 VSS_40 VSS_139 K29 K16 VSS_240 VSS_338 AJ2
C C
C43 VSS_41 VSS_140 H29 G16 VSS_241 VSS_339 AH2
BG42 VSS_42 VSS_141 F29 E16 VSS_242 VSS_340 AF2
AY42 VSS_43 VSS_142 A29 BG15 VSS_243 VSS_341 AE2
AT42 VSS_44 VSS_143 BG28 AC15 VSS_244 VSS_342 AD2
AN42 VSS_45 VSS_144 BD28 W15 VSS_245 VSS_343 AC2
AJ42 VSS_46 VSS_145 BA28 A15 VSS_246 VSS_344 Y2
AE42 VSS_47 VSS_146 AV28 BG14 VSS_247 VSS_345 M2
N42 VSS_48 VSS_147 AT28 AA14 VSS_248 VSS_346 K2
L42 VSS_49 VSS_148 AR28 C14 VSS_249 VSS_347 AM1
BD41 VSS_50 VSS_149 AJ28 BG13 VSS_250 VSS_348 AA1
AU41 VSS_51 VSS_150 AG28 BC13 VSS_251 VSS_349 P1
AM41 VSS_52 VSS_151 AE28 BA13 VSS_252 VSS_350 H1
AH41 VSS_53 VSS_152 AB28
AD41 VSS_54 VSS_153 Y28 VSS_351 U24
AA41 VSS_55 VSS_154 P28 AN13 VSS_255 VSS_352 U28
Y41 VSS_56 VSS_155 K28 AJ13 VSS_256 VSS_353 U25
U41 VSS_57 VSS_156 H28 AE13 VSS_257 VSS_354 U29
T41 VSS_58 VSS_157 F28 N13 VSS_258
M41 VSS_59 VSS_158 C28 L13 VSS_259
G41 VSS_60 VSS_159 BF26 G13 VSS_260 VSS_NCTF_1 AF32
B41 VSS_61 VSS_160 AH26 E13 VSS_261 VSS_NCTF_2 AB32
BG40 VSS_62 VSS_161 AF26 BF12 VSS_262 VSS_NCTF_3 V32
BB40 VSS_63 VSS_162 AB26 AV12 VSS_263 VSS_NCTF_4 AJ30
AV40 VSS_64 VSS_163 AA26 AT12 VSS_264 VSS_NCTF_5 AM29
AN40 VSS_65 VSS_164 C26 AM12 VSS_265 VSS_NCTF_6 AF29
H40 B26 AA12 AB29

VSS NCTF
VSS_66 VSS_165 VSS_266 VSS_NCTF_7
E40 VSS_67 VSS_166 BH25 J12 VSS_267 VSS_NCTF_8 U26
AT39 VSS_68 VSS_167 BD25 A12 VSS_268 VSS_NCTF_9 U23
AM39 VSS_69 VSS_168 BB25 BD11 VSS_269 VSS_NCTF_10 AL20
AJ39 VSS_70 VSS_169 AV25 BB11 VSS_270 VSS_NCTF_11 V20
AE39 VSS_71 VSS_170 AR25 AY11 VSS_271 VSS_NCTF_12 AC19
N39 VSS_72 VSS_171 AJ25 AN11 VSS_272 VSS_NCTF_13 AL17
B B
L39 VSS_73 VSS_172 AC25 AH11 VSS_273 VSS_NCTF_14 AJ17
B39 VSS_74 VSS_173 Y25 VSS_NCTF_15 AA17
BH38 VSS_75 VSS_174 N25 Y11 VSS_275 VSS_NCTF_16 U17
BC38 VSS_76 VSS_175 L25 N11 VSS_276
BA38 VSS_77 VSS_176 J25 G11 VSS_277
AU38 G25 C11 BH48

VSS SCB
VSS_78 VSS_177 VSS_278 VSS_SCB_1
AH38 VSS_79 VSS_178 E25 BG10 VSS_279 VSS_SCB_2 BH1
AD38 VSS_80 VSS_179 BF24 AV10 VSS_280 VSS_SCB_3 A48
AA38 VSS_81 VSS_180 AD12 AT10 VSS_281 VSS_SCB_4 C1
Y38 VSS_82 VSS_181 AY24 AJ10 VSS_282 VSS_SCB_5 A3
U38 VSS_83 VSS_182 AT24 AE10 VSS_283
T38 VSS_84 VSS_183 AJ24 AA10 VSS_284 NC_26 E1
J38 VSS_85 VSS_184 AH24 M10 VSS_285 NC_27 D2
F38 VSS_86 VSS_185 AF24 BF9 VSS_286 NC_28 C3
C38 VSS_87 VSS_186 AB24 BC9 VSS_287 NC_29 B4
BF37 VSS_88 VSS_187 R24 AN9 VSS_288 NC_30 A5
BB37 VSS_89 VSS_188 L24 AM9 VSS_289 NC_31 A6
AW37 VSS_90 VSS_189 K24 AD9 VSS_290 NC_32 A43
AT37 VSS_91 VSS_190 J24 G9 VSS_291 NC_33 A44
AN37 G24 B9 B45

NC
VSS_92 VSS_191 VSS_292 NC_34
AJ37 VSS_93 VSS_192 F24 BH8 VSS_293 NC_35 C46
H37 VSS_94 VSS_193 E24 BB8 VSS_294 NC_36 D47
C37 VSS_95 VSS_194 BH23 AV8 VSS_295 NC_37 B47
BG36 VSS_96 VSS_195 AG23 AT8 VSS_296 NC_38 A46
BD36 VSS_97 VSS_196 Y23 NC_39 F48
AK15 VSS_98 VSS_197 B23 NC_40 E48
AU36 VSS_99 VSS_198 A23 NC_41 C48
VSS_199 AJ6 NC_42 B48

CANTIGA_1p0 CANTIGA_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 12 of 43
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

+V_DDR3_DIMM_REF
(8) DDR_A_DQS#[0..7]
JDIMM2
(8) DDR_A_D[0..63] 1 VREF_DQ VSS 2
3 4 DDR_A_D4
+1.5V DDR_A_D0 VSS DQ4 DDR_A_D5
(8) DDR_A_DM[0..7] 5 DQ0 DQ5 6
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
(8) DDR_A_DQS[0..7] 9 VSS DQS0# 10

1
DDR_A_DM0 11 12 DDR_A_DQS0
R540 DM0 DQS0
(8) DDR_A_MA[0..14] 13 VSS VSS 14
1K_0402_1% DDR_A_D2 15 16 DDR_A_D6
+V_DDR3_DIMM_REF DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 20

2
D DDR_A_D8 VSS VSS DDR_A_D12 D
21 DQ8 DQ12 22

0.1U_0402_16V4Z
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13

1
2.2U_0805_16V4Z
25 VSS VSS 26

C209
1 1 R541 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# (7,14)

C642
1K_0402_1% 31 32
DDR_A_D10 VSS VSS DDR_A_D14
33 34

2
2 2 DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
R1102 J2 DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
+RTCVCC 1 2 1 2 61 62 DDR_A_DQS#3
100_0402_5% DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
JOPEN @ 65 66
DDR_A_D26 VSS VSS DDR_A_D30
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
71 VSS VSS 72
for Clear CMOS
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
(7) DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA (7)
Layout Note: 75 VDD VDD 76
77 NC A15 78
Place near JP4 (8) DDR_A_BS2
DDR_A_BS2 79 80 DDR_A_MA14
C BA2 A14 C
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
Layout Note: Place these 4 Caps near Command 85 A9 A7 86
87 88
and Control signals of DIMMA DDR_A_MA8 89
VDD VDD
90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
+1.5V 93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 M_CLK_DDR0 101 102 M_CLK_DDR1

(7) M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 (7)
1 1 1 1 1 1 1 1 1 1 M_CLK_DDR#0 103 104 M_CLK_DDR#1
(7) M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 (7)
C146

C147

C148

C149
C784

C785

C786

C787

C788

C789

+ C140 105 106

330U_D2E_2.5VM_R7 DDR_A_MA10 VDD VDD DDR_A_BS1
107 A10/AP BA1 108 DDR_A_BS1 (8)
DDR_A_BS0 109 110 DDR_A_RAS#
2 2 2 2 2 2 2 2 2 2 2 (8) DDR_A_BS0 BA0 RAS# DDR_A_RAS# (8)
111 VDD VDD 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
(8) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (7)
DDR_A_CAS# 115 116 M_ODT0
(8) DDR_A_CAS# CAS# ODT0 M_ODT0 (7)
117 VDD VDD 118
DDR_A_MA13 M_ODT1 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT1 (7)
DDR_CS1_DIMMA# 121 122
(7) DDR_CS1_DIMMA# S1# NC R542
123 VDD VDD 124
125 126 DDR_VREF_CA_DIMMA 1 2
TEST VREF_CA
127 VSS VSS 128
DDR_A_D32 129 130 DDR_A_D36 0_0402_5%
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132
Layout Note: 133 VSS VSS 134

0.1U_0402_16V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4
Place near JP4.203 & JP4.204 DQS4# DM4

2.2U_0603_6.3V4Z
DDR_A_DQS4 137 138 1 1
DQS4 VSS DDR_A_D38
139 VSS DQ38 140

C790

C791
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
B DDR_A_D44 2 2 B
145 VSS DQ44 146
+0.75V DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

155 VSS VSS 156

DDR_A_D42 157 158 DDR_A_D46
DQ42 DQ46
10U_0805_6.3V6M

2 2 2 2 1 DDR_A_D43 159 160 DDR_A_D47

DQ43 DQ47
C804

161 VSS VSS 162

DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
1 1 1 1 2
C159

C160

C161

C162

167 VSS VSS 168

DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
+1.5V DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 196
EMI 1215 +3VS
R124 1 2 10K_0402_5% 197
199
VSS
SA0
VDDSPD
VSS
EVENT#
SDA
198
200
PM_EXTTS#0_1
CLK_SMBDATA
PM_EXTTS#0_1 (7,14)
CLK_SMBDATA (14,15)
0.1U_0402_16V4Z

201 202 CLK_SMBCLK

SA1 SCL CLK_SMBCLK (14,15)
2.2U_0603_6.3V4Z

1 1 203 VTT VTT 204 +0.75V

1
10K_0402_5%

1 1
1

C671 C672 C163 C164 205 206

GND1 BOSS1
R123

A C675 A
207 GND2 BOSS2 208
2 2
10P_0402_50V8J

47P_0402_50V8J

120P_0402_50V8
DDR3 SO-DIMM A
2

2 2
2

FOX_AS0A626-U2RN-7F
CONN@ +0.75V REVERSE
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 13 of 43
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
(8) DDR_B_DQS#[0..7]
+V_DDR3_DIMM_REF
(8) DDR_B_D[0..63]
JDIMM1
(8) DDR_B_DM[0..7] 1 VREF_DQ VSS 2
3 4 DDR_B_D4
DDR_B_D0 VSS DQ4 DDR_B_D5
(8) DDR_B_DQS[0..7] 5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
(8) DDR_B_MA[0..14] 9 VSS DQS0# 10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6

C165

C166
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
19 VSS VSS 20
D 2 2 DDR_B_D8 DDR_B_D12 D
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# (7,13)
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
Layout Note: DDR_B_D19
51 DQ18 DQ23 52
53 DQ19 VSS 54
Place near JP5 55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58
Layout Note: Place these 4 Caps near Command DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3
61 62
and Control signals of DIMMA DDR_B_DM3 63
VSS DQS3#
64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
+1.5V DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
10U_0603_6.3V6M

10U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1 1 1 1 1 1 1 1 1 1 DDR_CKE2_DIMMB
73 74 DDR_CKE3_DIMMB
(7) DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB (7)
C172

C173

C174

C175
C792

C793

C794

C795

C796

C797

+ C643 75 76
330U_D2E_2.5VM_R7 VDD VDD
77 NC A15 78
DDR_B_BS2 79 80 DDR_B_MA14
C 2 2 2 2 2 2 2 2 2 2 2 (8) DDR_B_BS2 BA2 A14 C
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
<BOM Structure>
<BOM Structure>
<BOM Structure>
<BOM Structure> 99 VDD VDD 100
Layout Note: M_CLK_DDR2 101 102 M_CLK_DDR3
(7) M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 (7)
M_CLK_DDR#2 103 104 M_CLK_DDR#3
Place near JP5.203 & JP5.204 (7) M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 (7)
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 (8)
DDR_B_BS0 109 110 DDR_B_RAS#
(8) DDR_B_BS0 BA0 RAS# DDR_B_RAS# (8)
111 VDD VDD 112
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
+0.75V (8) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (7)
DDR_B_CAS# 115 116 M_ODT2
(8) DDR_B_CAS# CAS# ODT0 M_ODT2 (7)
117 VDD VDD 118
DDR_B_MA13 M_ODT3 +V_DDR3_DIMM_REF
119 A13 ODT1 120 M_ODT3 (7)
DDR_CS3_DIMMB# 121 122
(7) DDR_CS3_DIMMB# S1# NC
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

123 124 R543

VDD VDD DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5%
10U_0805_6.3V6M

2 2 2 2 1 127 VSS VSS 128

C805

DDR_B_D32 129 130 DDR_B_D36

DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS VSS 134
1 1 1 1 2
C185

C186

C187

C188

0.1U_0402_16V4Z
DDR_B_DQS#4 135 136 DDR_B_DM4
DQS4# DM4

2.2U_0603_6.3V4Z
DDR_B_DQS4 137 138 1 1
DQS4 VSS

C798
139 140 DDR_B_D38
VSS DQ38

C799
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS 144
B DDR_B_D44 2 2 B
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
+1.5V 161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
EMI 1215 DDR_B_DQS#6
167
169
DQ49
VSS
DQS6#
DQ53
VSS
DM6
168
170 DDR_B_DM6
DDR_B_DQS6 171 172
DQS6 VSS DDR_B_D54
173 VSS DQ54 174
1 1 DDR_B_D50 175 176 DDR_B_D55
DQ50 DQ55
1

C676 C688 DDR_B_D51 177 178

C687 DQ51 VSS DDR_B_D60
179 VSS DQ60 180
10P_0402_50V8J

47P_0402_50V8J

120P_0402_50V8 DDR_B_D56 181 182 DDR_B_D61

2

2 2 DDR_B_D57 DQ56 DQ61

183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
195
DQ59
VSS
DQ63
VSS 196 same with intel DDR3 CRB connection
R127 1 2 10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 (7,13)
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA (13,15)
1 2 201 202 CLK_SMBCLK
SA1 SCL CLK_SMBCLK (13,15)
0.1U_0402_16V4Z

R126 10K_0402_5% 203

2.2U_0603_6.3V4Z

204

C189
1 1
C190
VTT VTT +0.75V
DDR3 SO-DIMM B
205 206
A
2 2
207
GND1
GND2
BOSS1
BOSS2 208 REVERSE A

FOX_AS0A626-U2RN-7F
+0.75V
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 14 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
Routing the trace at least 10mil R129
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2
+3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz CLK_XTAL_OUT 0_0805_5% 1
C191
1
C192
1
C193
1
C194
1
C195
1
C196
1
C197
CLK_XTAL_IN
0 0 0 266 100 33.3 14.318 96.0 48.0 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2

0 0 1 133 100 33.3 14.318 96.0 48.0 14.31818MHZ_16P

Y1
+VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 2 1
Place close to U3
D R130 D
0 1 1 166 100 33.3 14.318 96.0 48.0 2 2
C205 C206 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
18P_0402_50V8J 18P_0402_50V8J 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 C198 C199 C200 C201 C202 C203 C204
1 1

2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 0 400 100 33.3 14.318 96.0 48.0

CLK_PCIE_READER (20)
CLK_PCIE_READER# (20) Card reader
1 1 1 Reserved +3VS_CK505 +1.05VS_CK505

R131
CLK_MCH_3GPLL (7)
1 2 +VCCP CLK_MCH_3GPLL# (7) 3G_PLL
R155 1 2 475_0402_1% R_CLKREQ#_7
(7) CLKREQ#_7
@ 56_0402_5% R875 1 2 +3VS
(7) CLK_MCH_BCLK#
NB R_CLKREQ#_6 R154 1 2 10K_0402_5%
(7) CLK_MCH_BCLK MCARD_CLKREQ# (20)
475_0402_1%
(4) CLK_CPU_BCLK# CLK_PCIE_MCARD1 (20) MiniCard
R132 CPU (4) CLK_CPU_BCLK CLK_PCIE_MCARD1# (20)
FSA 1 2 1 2 +3VS_CK505
MCH_CLKSEL0 (7)
2.2K_0402_5% R133
R134 1K_0402_5%

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
(5) CPU_BSEL0 1 2
0_0402_5% U3
+1.05VS_CK505
1

+3VS_CK505

BODY

SRC_8/CPU_ITP
VDD_CPU

CPU_0#
VSS_CPU

CPU_1#
VDD_CPU_IO

VDD_SRC_IO

VDD_SRC
CPU_0

CPU_1

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
@
R137
1K_0402_5%
C C
2

R138 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#

(18) CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# (18)
FSB 2 53 H_STP_CPU#
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# (18)
3 VSS_REF VDD_SRC_IO 52
+VCCP CLK_XTAL_OUT 4 XTAL_OUT SRC_10# 51 CLK_PCIE_MCARD2# (20) MiniCard (TV tuner)
CLK_XTAL_IN 5 50
XTAL_IN SRC_10 CLK_PCIE_MCARD2 (20)
6 VDD_REF CLKREQ_10# 49 1 R1103 2 MCARD_CLKREQ2# (20) MCARD_CLKREQ2# 1 R886 2 +3VS
2

@ R158 1 2 33_0402_1% FSC 7 48 475_0402_1% 10K_0402_5%

(18) CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_PCIE_CARD (29)
R150 PAD T98 8 REF_1 SRC_11# 47 CLK_PCIE_CARD# (29) New card
1K_0402_5% (13,14) CLK_SMBDATA CLK_SMBDATA 9 46 1 R156 2 EXP_CLKREQ# 1 R876 2 +3VS
SDA CLKREQ_11# EXP_CLKREQ# (29)
CLK_SMBCLK 10 45 475_0402_1% 10K_0402_5%
(13,14) CLK_SMBCLK SCL SRC_9# CLK_PCIE_VGA# (21)
11 44 CLK_PCIE_VGA (21)
1

FSB NC SRC_9
1 2 MCH_CLKSEL1 (7) 0905 Connect PCI_CLK 12 VDD_PCI CLKREQ_9# 43 1 R1409 2 VGA_CLKREQ# (21)
VGA_CLKREQ# 1 R889 2 +3VS
R157 13 42 475_0402_1% 10K_0402_5%
R162 1K_0402_5% PCI2_TME PCI_1 VSS_SRC
14 PCI_2 CLKREQ_4# 41 1 R877 2 LAN_CLKREQ# (26)
(5) CPU_BSEL1 1 2 R142 1 2 33_0402_1% 27_SEL 15 PCI_3 SRC_4# 40 475_0402_1%
CLK_PCIE_LAN# (26) GLAN
0_0402_5% (31) CLK_PCI_EC R873 PCI_CLK4 LAN_CLKREQ#
16 PCI_4/SEL_LCDCL SRC_4 39 CLK_PCIE_LAN (26) 1 R890 2 +3VS
1

USB_1/CLKREQ_A#
PCI_CLK 1 2 ITP_EN 17 38 10K_0402_5%

LCDCLK#/27M_SS
(16) PCI_CLK PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
@ 33_0402_1% 18 37 R_CLKREQ#_C 1 2 475_0402_1%
VSS_PCI CLKREQ_3# CLKREQ#_C (18)

SRC_0/DOT_96
R165 R149

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
0_0402_5%

VDD_PLL3

VSS_PLL3

VSS_SRC
2

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48

VSS_IO

SRC_2

SRC_3
+VCCP
SA000020H10 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
+3VS_CK505
1

@
R177
1K_0402_5% CLK_PCIE_SATA# (17)
R151 1 2 33_0402_1% FSA SATA
(18) CLK_48M_ICH CLK_PCIE_SATA (17)
PAD T112
B R182 B
CLK_PCIE_ICH# (18)
2

FSC 1 2 1 2 +1.05VS_CK505 ICH

MCH_CLKSEL2 (7) CLK_PCIE_ICH (18)
10K_0402_5% R183 +1.05VS_CK505
R187 1K_0402_5%
(7) CLK_MCH_DREFCLK
(5) CPU_BSEL2 1 2 NB (UMA) (7) CLK_MCH_DREFCLK# MCH_SSCDREFCLK# (7)
0_0402_5% NB_SSC (UMA)
MCH_SSCDREFCLK (7)
1

@
R188
0_0402_5%
0 = SRC8/SRC8#
ITP_EN
2

1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
PCI_CLK3 +3VS
+3VS 1 = Enable SRC0 & 27MHz(DIS) +3VS
1

+3VS
R208 0820 R192 @ +3VS R189 R190
10K_0402_5%
1

@ 2.2K_0402_5% 2.2K_0402_5%
R192
2

10K_0402_5%

5
PCI2_TME
2

ITP_EN (18,20,25,26,29) ICH_SMBDATA 3 4 CLK_SMBDATA

1

PCI_CLK4
2
R207 SB, MINI PCI Q3B
1

@ 10K_0402_5%
1

R193 6 1 2N7002DW T/R7_SOT363-6 CLK_SMBCLK

A 10K_0402_5% (18,20,25,26,29) ICH_SMBCLK A
R194
2

10K_0402_5% 2N7002DW T/R7_SOT363-6

Q3A
2

for ICS Overclocking setting

0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 15 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS

RP29
1 8 PCI_PIRQF#
2 7 PCI_SERR#
3 6 PCI_PIRQA#
4 5 PCI_PIRQH#

RP30 8.2K_1206_8P4R_5%
1 8 PCI_PLOCK# U6B
2 7 PCI_IRDY# D11 F1 PCI_REQ0#
PCI_PIRQC# AD0 REQ0# PCI_GNT0#
D
3
4
6
5 PCI_TRDY#
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1# D
AD2 REQ1#/GPIO50
E12 AD3 GNT1#/GPIO51 A7 T65 PAD
8.2K_1206_8P4R_5% E9 F13 PCI_REQ2# R1424 1 2 0_0402_5%
AD4 REQ2#/GPIO52 DGPU_SELECT# (22,23,24,25)
C9 AD5 GNT2#/GPIO53 F12 T66 PAD
E10 E6 PCI_REQ3#
AD6 REQ3#/GPIO54 PCI_GNT3#
B7 AD7 GNT3#/GPIO55 F6
C7 AD8
C5 AD9 C/BE0# D8 T67 PAD
G11 AD10 C/BE1# B4 T68 PAD
F8 AD11 C/BE2# D6 T69 PAD
+3VS F11 A5
AD12 C/BE3# T70 PAD
E7 AD13
RP31 A3 D3 PCI_IRDY#
PCI_STOP# AD14 IRDY#
1 8 D2 AD15 PAR E3 T71 PAD
2 7 PCI_PIRQD# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# (29,31)
3 6 PCI_FRAME# D5 C6 PCI_DEVSEL#
AD17 DEVSEL#

1
4 5 PCI_PERR# D10 E4 PCI_PERR#
AD18 PERR# PCI_PLOCK# R942
B3 AD19 PLOCK# C2
RP32 8.2K_1206_8P4R_5% F7 J4 PCI_SERR# 100K_0402_5%
PCI_REQ0# AD20 SERR# PCI_STOP#
1 8 C3 AD21 STOP# A4
2 7 PCI_PIRQG# F3 F5 PCI_TRDY#

2
PCI_PIRQE# AD22 TRDY# PCI_FRAME#
3 6 F4 AD23 FRAME# D7
4 5 PCI_PIRQB# C1 AD24 PLT_RST#
G7 AD25 PLTRST# C14 PLT_RST# (7,18,20,26)
RP33 8.2K_1206_8P4R_5% H7 D4 PCI_CLK
AD26 PCICLK PCI_CLK (15)
1 8 PCI_REQ3# D1 R2 T72 PAD
PCI_REQ1# AD27 PME#
2 7 G5 AD28
3 6 PCI_DEVSEL# H6
PCI_REQ2# AD29
4 5 G1 AD30
H3 AD31
8.2K_1206_8P4R_5%

C PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# C
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2

ICH9M REV 1.0

+3VS

5
U7 NC7SZ08P5X_NL_SC70-5
PLT_RST# 2

P
R1425 B
1 2 1
Y 4 2
R70
1
100_0402_5%
PEG_RST# (21) For VGA/B
(18) DGPU_HOLD_RST# A

G
0_0402_5% VGA@

1
VGA@

3
R36
100K_0402_5%
VGA@
VGA@

2
A16 swap override Strap Boot BIOS Strap
B B
Low= A16 swap override Enble
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location

@ R249 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%

1 0 PCI

1 1 LPC *
@ R944
@R944 1K_0402_5%
1 2 +3VALW

@ R250
SPI_CS1#_R 1 2
(18) SPI_CS1#_R
1K_0402_5%
@ R251
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 16 of 43
5 4 3 2 1
 5 4 3 2 1

ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN Low = Internal VR Disabled +3VS

+RTCVCC
High = Internal VR Enabled(Default) R253
GATEA20 1 2
1 2 SM_INTRUDER# 10K_0402_5%
R252 1M_0402_5% ICH8M LAN100 SLP Strap
1 2 LAN100_SLP R256
R254 330K_0402_1% (Internal VR for VccLAN1.05 and VccCL1.05) KB_RST# 1 2
1 2 ICH_INTVRMEN C340 10K_0402_5%
R255 R279 330K_0402_1% 15P_0402_50V8J
D ICH_SRTCRST# ICH_RTCX1 D
1 2 1 2 ICH_LAN100_SLP Low = Internal VR Disabled
20K_0402_5% +VCCP
High = Internal VR Enabled(Default)

10M_0402_5%
1U_0603_10V4Z
1 32.768KHZ_12.5P_MC-306
1

1
CLRP3 @ @ 3 NC @ R260
@R260
OUT 4

R270
SHORT PADS C253 R258 R259 H_DPRSTP# 1 2
0_0402_5% 2 1 56_0402_5%
2

2 NC IN

0_0402_5%
LPC_AD[0..3] (31)

2
X1 C339 U6A @ R261
@R261

2
12P_0402_50V8J C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
2 1 C24 RTCX2 FWH1/LAD1 K4
R262 L6 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTCVCC 1 2 A25 RTCRST# FWH3/LAD3 K2
ICH_SRTCRST#

RTC
LPC
20K_0402_5% F20
<BOM Structure> SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# (31)
1 +VCCP

1
C243 CLRP2 ICH_INTVRMEN B22 J3
SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z

2
2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 (31)
AJ27 H_A20M# R263
A20M# H_A20M# (4)
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R264 H_DPRSTP#
MB ID(PROJECT ID) AJ25 1 2 H_DPRSTP# (5,7,41)
+3VALW DPRSTP# H_DPSLP# 0_0402_5%
F14 AE23

LAN / GLAN
H_DPSLP# (5)

1
ID2 ID1 ID0 LAN_RXD0 DPSLP#
G13 LAN_RXD1
D14 AJ26 R_H_FERR# R265 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# (4)

2
56_0402_5%
1 1 0 VGA R946 D13 AD22 H_PWRGOOD 3/28 add 56ohm
LAN_TXD0 CPUPWRGD H_PWRGOOD (5)
10K_0402_5% D12 LAN_TXD1
VGA@ E13 AF25 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# (4)

CPU
0 1 0 UMA R268 within 2" from R1557

1
+1.5VS 1 2 PROJECT_ID2 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# (4) +VCCP
0_0402_5% UMA@ AG25 H_INTR
C INTR H_INTR (4) C
B28 L3 KB_RST#
GLAN_COMPI RCIN# KB_RST# (31)
R266 24.9_0402_1% 1 2 GLAN_COMP B27 GLAN_COMPO

1
AF23 H_NMI
NMI H_NMI (4)
R267 33_0402_5% 1 2 HDA_BITCLK AF6 AF24 H_SMI# R269
(27) HDA_BITCLK_CODEC HDA_BIT_CLK SMI# H_SMI# (4)
R271 33_0402_5% 1 2 HDA_SYNC AH4 56_0402_5%
(27) HDA_SYNC_CODEC HDA_SYNC
AH27 H_STPCLK#
STPCLK# H_STPCLK# (4)
R272 33_0402_5% 1 2 HDARST# AE7
(27) HDA_RST#_CODEC

2
HDA_RST# THRMTRIP_ICH# R274
THRMTRIP# AG26 1 2 54.9_0402_1% H_THERMTRIP# (4,7)
CODEC HDA_SDIN0 AF4
(27) HDA_SDIN0 HDA_SDIN0
GMCH HDA_SDIN1 AG4 AG27 placed within 2" from
(7) HDA_SDIN1 HDA_SDIN1 TP12
HDA_SDIN2

IHDA
PAD T74 AH3 HDA_SDIN2 ICH8M
PAD T78 HDA_SDIN3 AE5 HDA_SDIN3
SATA4RXN AH11 SATA_RXN2_C
R276 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11 0.01U_0402_16V7K
(27) HDA_SDOUT_CODEC HDA_SDOUT SATA4RXP SATA_RXP2_C
AG12 SATA_TXN2_C 2 1 C346 SATA_TXN2
SATA4TXN SATA_TXN2
R522 R1453 1 2 0_0402_5% AG7 AF12 SATA_TXP2_C 2 1 C347 SATA_TXP2
(22,24,25) DGPU_EDIDSEL# HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP2
+3VS 1 2 R1454 1 2 0_0402_5% AE8
(22) DGPU_PWMSEL# HDA_DOCK_RST#/GPIO34
10K_0402_5% AH9 0.01U_0402_16V7K
SATA5RXN SATA_RXN3_C (20)
SATA_LED# AG8 AJ9 0.01U_0402_16V7K
(33) SATA_LED# SATALED# SATA5RXP SATA_RXP3_C (20)
SATA_TXN3_C C348 SATA_TXN3
AJ16
SATA5TXN AE10
AF10 SATA_TXP3_C
2
2
1
1 C349 SATA_TXP3
SATA_TXN3 (20) e-SATA
(20) SATA_RXN0_C SATA0RXN SATA5TXP SATA_TXP3 (20)
0.01U_0402_16V7K AH16
(20) SATA_RXP0_C

SATA
SATA_TXN0 C248 SATA_TXN0_C SATA0RXP CLK_PCIE_SATA# 0.01U_0402_16V7K
S-HDD (20) SATA_TXN0
SATA_TXP0 C249
1
1
2
2 SATA_TXP0_C
AF17
AG17
SATA0TXN SATA_CLKN AH18
AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA# (15)
(20) SATA_TXP0 SATA0TXP SATA_CLKP CLK_PCIE_SATA (15)
0.01U_0402_16V7K AH13 AJ7
(20) SATA_RXN4_C SATA1RXN SATARBIAS#
0.01U_0402_16V7K AJ13 AH7 R277 1 2
(20) SATA_RXP4_C SATA1RXP SATARBIAS
SATA_TXN4 C244 SATA_TXN4_C
ODD (20) SATA_TXN4
SATA_TXP4 C245
1
1
2
2 SATA_TXP4_C
AG14
AF14
SATA1TXN 24.9_0402_1%
(20) SATA_TXP4 SATA1TXP
0.01U_0402_16V7K ICH9M REV 1.0
Within 500 mils
B B

+RTCBATT

UMA@ 1 2 HDA_BITCLK
(7) HDA_BITCLK_MCH

2
R408 33_0402_5%
+3VS UMA@ 1 2 HDA_SYNC R48
(7) HDA_SYNC_MCH
R410 33_0402_5% 1K_0402_5%
HDA for GMCH UMA@ 1 2 HDARST#
(7) HDA_RST_MCH#
@ R280 R411 33_0402_5%

1 1
1 2 HDA_SDOUT (7) HDA_SDOUT_MCH UMA@ 1 2 HDA_SDOUT
1K_0402_5% R409 33_0402_5% D8

@ R281
1 2 ICH_RSVD +RTCVCC
ICH_RSVD (18)
1K_0402_5%

2
BAS40-04_SOT23-3
XOR CHAIN ENTRANCE STRAP:RSVD 1
+CHGRTC
C109

0.1U_0402_16V4Z
2
ICH_RSVD HDA_SDOUT_CODEC

A 0 0 Change BATT1 P/N : SP093PA0200 (Panasonic) A

SP093MX0000 (MAXELL)
0 1
1 0
1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 17 of 43
5 4 3 2 1
 5 4 3 2 1

SIRQ +3VS
+3VS
R286
1 2
10K_0402_5% R287 1
Place closely pin AF3 Place closely pin H1
+3VALW 2 2.2K_0402_5%
1 2 PM_CLKRUN# R289 1 2 2.2K_0402_5% GPIO36 R945 1 2 10K_0402_5%
R288 8.2K_0402_5% U6C GPIO37 R947 1 2 10K_0402_5% CLK_48M_ICH CLK_14M_ICH
1 2 GPIO39 ICH_SMBCLK G16 AH23 PROJECT_ID1 @
(15,20,25,26,29) ICH_SMBCLK SMBCLK SATA0GP/GPIO21
@R290
@ R290 10K_0402_5% ICH_SMBDATA A13 AF19 PROJECT_ID0
(15,20,25,26,29) ICH_SMBDATA SMBDATA SATA1GP/GPIO19

1
1 2 THERM_SCI# LINKALERT# E17 AE21 GPIO36 R313 1 2 0_0402_5% @ @

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 DGPU_PRSNT (21)
ME_EC_CLK1

SMB
@R291
@ R291 8.2K_0402_5% C17 SMLINK0 SATA5GP/GPIO37 AD20 GPIO37 R317 1 2 0_0402_5% DGPU_PWROK (21)
R292 R293
1 2 CLKREQ#_C ME_EC_DATA1 B18
R294 10K_0402_5% SMLINK1 CLK_14M_ICH 10_0402_5% 10_0402_5%
CLK14 H1 CLK_14M_ICH (15)
@ 1 2 DGPU_PWR_EN +3VS EC_SWI# F19 AF3 CLK_48M_ICH

Clocks
CLK_48M_ICH (15)

2
R295 8.2K_0402_5% (31) EC_SWI# RI# CLK48
1 2 CR_WAKE# PAD T47 SUS_STAT# R4 P1 ICH_SUSCLK T48 PAD 1 @ 1 @
R296 8.2K_0402_5% XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK C256 C257
(4) XDP_DBRESET# G19 SYS_RESET#

1
1 2 GPIO27 @ @ C16 SLP_S3#
D SLP_S3# SLP_S3# (31) D
@R297
@ R297 8.2K_0402_5% R298 R299 PM_BMBUSY# M6 E16 SLP_S4# 4.7P_0402_50V8C 4.7P_0402_50V8C
(7) PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# (31) 2 2
1 2 OCP# 10K_0402_5% 10K_0402_5% G17 SLP_S5#
SLP_S5# SLP_S5# (31)
R300 10K_0402_5% (31) EC_LID_OUT# EC_LID_OUT# A17
PM_BMBUSY# SMBALERT#/GPIO11 S4_STATE#
1 2 C10

2
@ R301 8.2K_0402_5% H_STP_PCI# S4_STATE#/GPIO26
(15) H_STP_PCI# A14 STP_PCI#
R303 2 0_0402_5% R_STP_CPU# ICH_PWROK

SYS GPIO
(15) H_STP_CPU# 1 E19 STP_CPU# PWROK G20 ICH_PWROK (7)
1 2 EC_SCI# (31) PM_CLKRUN# PM_CLKRUN# L4 M2 1 2 0_0402_5%
CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR (7,41)
@R305
@ R305 8.2K_0402_5% R306
1 2 DGPU_HOLD_RST# ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT# ICH_PWROK 1 2

Power MGT
(20,26,29) ICH_PCIE_WAKE# WAKE# BATLOW#
R307 8.2K_0402_5% SIRQ M5 R302 R304 10K_0402_5%
(31) SIRQ SERIRQ
THERM_SCI# AJ23 R3 PWRBTN_OUT# 0_0402_5%
(31) THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# (31)
1 2 CR_CPPE# 1 2 PLT_RST# (7,16,20,26)
R949 10K_0402_5% VGATE D21 D20 1 2
(7,41) VGATE VRMPWRGD LAN_RST# R526 0_0402_5% @
1 2 GPIO48 R311 1 2 PAD T49 ICH_TP11 A20 D22 SB_RSMRST# PM_PWROK 1 2
@R310
@ R310 8.2K_0402_5% 100K_0402_5% TP11 RSMRST# R312 10K_0402_5%
1 2 PROJECT_ID1 OCP# AG19 R5 CK_PWRGD_R R315 1 2 0_0402_5%
(4) OCP# GPIO1 CK_PWRGD CK_PWRGD (15)
R314 8.2K_0402_5% CRT_DET AH21
CR_CPPE# GPIO6 R351 1 ICH_PWROK
(20) CR_CPPE# AG21 GPIO7 CLPWROK R6 2
(31) EC_SMI# EC_SMI# A21 0_0402_5%
EC_SCI# GPIO8 PM_SLP_M# +3VS
(31) EC_SCI# C12 GPIO12 SLP_M# B16 T92 PAD
(26) ENERGY_DET C21 GPIO13
PAD T53 R330 1 2 0_0402_5% AE18 F24 CL_CLK0 R319
GPIO17 CL_CLK0 CL_CLK0 (7)
1 2 PROJECT_ID0 DGPU_PWR_EN K1 B19 0.1U_0402_16V4Z 1 2
(21,34) DGPU_PWR_EN GPIO18 CL_CLK1
R316 8.2K_0402_5% DGPU_HOLD_RST# AF8 3.24K_0402_1%
(16) DGPU_HOLD_RST# GPIO20

1
1 2 GPIO49 CR_WAKE# AJ22 F22 CL_DATA0 1
(20) CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 (7)
R318 10K_0402_5% @ PAD T52 GPIO27 A9 C19 C258 R320

GPIO
Controller Link
GPIO27 CL_DATA1 453_0402_1%
(26) LAN_LOWPWR D19 GPIO28
CLKREQ#_C L1 C25 CL_VREF0_ICH
(15) CLKREQ#_C SATACLKREQ#/GPIO35 CL_VREF0 2
0812 No install +3VS 1 2 GPIO38 AE19 A19 CL_VREF1_ICH NA lead free

2
R321 @ 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1
AG22 SDATAOUT0/GPIO39
C GPIO48 AF21 F21 CL_RST# +3VALW C
SDATAOUT1/GPIO48 CL_RST0# CL_RST# (7)
R323 GPIO49 AH24 D18
LINKALERT# 1K_0402_5% @ GPIO57 GPIO49 CL_RST1# R324
+3VALW 1 2 A8 GPIO57/CLGPIO5
R322 10K_0402_5% +3VS 1 2 A16 GPIO24 1 2
ICH_PCIE_WAKE# SB_SPKR MEM_LED/GPIO24 GPIO10 3.24K_0402_1%
1 2 (27) SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18

1
R326 1K_0402_5% MCH_ICH_SYNC# AJ24 C11 1 C259
(7) MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
1 2 EC_SMI# ICH_RSVD B21 C20 R327
(17) ICH_RSVD TP3 WOL_EN/GPIO9

0.1U_0402_16V4Z
R336 8.2K_0402_5% @ ICH_TP8 453_0402_1%

MISC
PAD T95 AH20 TP8 2 1 +3VALW
1 2 ICH_LOW_BAT# PAD T96 ICH_TP9 AJ20 R329 100K_0402_5%
R325 8.2K_0402_5% ICH_TP10 TP9 ICH_ACIN 2
PAD T97 AJ21 2 1

2
S4_STATE# TP10 D10 ACIN (21,31,33,35)
1 2
R331 10K_0402_5% @ ICH9M REV 1.0 CH751H-40PT_SOD323-2
RP34 GPIO9 1 2 HDMI_HPD# (25)
4 5 XDP_DBRESET# U6D 0_0402_5% R1431
3 6 EC_SWI# PCIE_RXN1 N29 V27 DMI_RXN0 DMI_RXN0 (7) @
(29) PCIE_RXN1 PERN1 DMI0RXN
2 7 ME_EC_DATA1 PCIE_RXP1 N28 V26 DMI_RXP0 DMI_RXP0 (7) R355 2 1 0_0402_5%
(29) PCIE_RXP1 PERP1 DMI0RXP

Direct Media Interface

ME_EC_CLK1 C682 1 2 0.1U_0402_16V7K PCIE_C_TXN1 DMI_TXN0
1 8 New Card (29) PCIE_TXN1
C680 1 2 0.1U_0402_16V7K PCIE_C_TXP1
P27
P26
PETN1 DMI0TXN U29
U28 DMI_TXP0
DMI_TXN0 (7) +3VALW
(29) PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 (7)
10K_1206_8P4R_5%
4 5 GPIO24 PCIE_RXN2 L29 Y27 DMI_RXN1 DMI_RXN1 (7)
(20) PCIE_RXN2 PERN2 DMI1RXN

5
3 6 EC_LID_OUT# PCIE_RXP2 L28 Y26 DMI_RXP1 DMI_RXP1 (7) U23
(20) PCIE_RXP2 PERP2 DMI1RXP
GPIO10 C683 1 2 0.1U_0402_16V7K PCIE_C_TXN2 DMI_TXN1 PM_PWROK
2 7 WLAN M27 W29 2

P
(20) PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 (7) B PM_PWROK (30,31)
1 8 GPIO9 (20) PCIE_TXP2 C681 1 2 0.1U_0402_16V7K PCIE_C_TXP2 M26 W28 DMI_TXP1 DMI_TXP1 (7) ICH_PWROK 4
PETP2 DMI1TXP Y VGATE
A 1

G
10K_1206_8P4R_5% PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 (7)
(26) PCIE_RXN3 PERN3 DMI2RXN
RP35 PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 (7) NC7SZ08P5X_NL_SC70-5 2 1 +3VS
(26) PCIE_RXP3

3
PERP3 DMI2RXP

PCI-Express
C268 1 2 0.1U_0402_16V7K PCIE_C_TXN3 DMI_TXN2 R337 @ 2K_0402_1%
GIGA LAN (26) PCIE_TXN3
C269 1 2 0.1U_0402_16V7K PCIE_C_TXP3
K27
K26
PETN3 DMI2TXN AA29
AA28 DMI_TXP2
DMI_TXN2 (7)
(26) PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 (7)
PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 (7) @
(20) PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 G28 AD26 DMI_RXP3 R353 2 1 0_0402_5%
RP27
MINI CARD
(TV Tuner)
(20) PCIE_RXP4
C684 1 2 0.1U_0402_16V7K PCIE_C_TXN4 H27
PERP4 DMI3RXP
AC29 DMI_TXN3
DMI_RXP3 (7)
Q21
B
(20) PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 (7) B
4 5 (20) PCIE_TXP4 C685 1 2 0.1U_0402_16V7K PCIE_C_TXP4 H26 AC28 DMI_TXP3 DMI_TXP3 (7) MMBT3906_SOT23-3
+3VALW PETP4 DMI3TXP
USB_OC#3 3 6 SB_RSMRST# 1 3

C
EC_RSMRST# (31)
USB_OC#7 2 7 PCIE_RXN5 E29 T26 CLK_PCIE_ICH#

E
(20) PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# (15)
USB_OC#4 1 8 PCIE_RXP5 E28 T25 CLK_PCIE_ICH
CARD READER (20) PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH (15)

1
C693 1 2 0.1U_0402_16V7K PCIE_C_TXN5 F27

B
(20) PCIE_TXN5

2
10K_1206_8P4R_5% C692 1 PETN5
(20) PCIE_TXP5 2 0.1U_0402_16V7K PCIE_C_TXP5 F26 PETP5 DMI_ZCOMP AF29 R338 24.9_0402_1% Within 500 mils R357 1 2 +3VALW
AF28 DMI_IRCOMP 1 2 +1.5VS 10K_0402_5% R358 4.7K_0402_5%
RP28 DMI_IRCOMP
C29 PERN6/GLAN_RXN

U
S
B
p
o
r
t
1
USB_OC#11 4 5 +3VALW C28 AC5 USB20_N0 D51A
USB20_N0 (29)

2
USB_OC#5 PERP6/GLAN_RXP USBP0N USB20_P0
3 6 D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 (29) 1

U
S
B
P
o
r
t
2
USB_OC#9 2 7 D26 AD3 USB20_N1 6
PETP6/GLAN_TXP USBP1N USB20_N1 (29)
2

USB_OC#8 1 8 @ AD2 USB20_P1 2

USBP1P USB20_P1 (29)

e
S
A
T
A
R309 ICH_SPI_CLK R641 1 2 33_0402_5% ICH_SPI_CLK_R D23 AC1 USB20_N2
SPI_CLK USBP2N USB20_N2 (20)
10K_1206_8P4R_5% 10K_0402_5% ICH_SPI_CS0# R649 1 2 33_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 BAV99DW-7_SOT363
SPI_CS0# USBP2P USB20_P2 (20)

C Ce
a a
m r
e
r
a
(16) SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3
SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB20_N3 (23)
RP36 AA4 USB20_P3 D51B
USB20_P3 (23)
1

USBP3P

dd
USB_OC#10 4 5 GPIO57 GLAN ICH_SPI_MOSI R650 1 2 33_0402_5% ICH_SPI_MOSI_R D25 AB2 USB20_N4 4
SPI_MOSI USBP4N USB20_N4

rNCU(
aE
e
r P
SPI

USB_OC#1 3 6 ICH_SPI_MISO R651 1 2 33_0402_5% ICH_SPI_MISO_R E23 AB3 USB20_P4 3

SPI_MISO USBP4P USB20_P4

Wr
2

USB_OC#0 2 7 AA1 USB20_N5 5

USBP5N USB20_N5 (29)

1
aSH
dBS
USB_OC#2 1 8 USB_OC#0 N4 AA2 USB20_P5
100K_0402_5% (29) USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 (29)

o
r
t
3
USB_OC#1 USB20_N6 +3VS BAV99DW-7_SOT363 R354
(29) USB_OC#1 N5 OC1#/GPIO40 USBP6N W5 USB20_N6 (29)
R524

)
10K_1206_8P4R_5% USB_OC#2 USB20_P6 2.2K_0402_5%
(20) USB_OC#2
USB_OC#3
N6
P6
OC2#/GPIO41 USBP6P USB W4
Y3
USB20_P6 (29)
1

OC3#/GPIO42 USBP7N

2
USB_OC#4 M1 Y2

2
OC4#/GPIO43 USBP7P

B F W
T P L
USB_OC#5 N2 W1 USB20_N8 R360
(29) CP_PE# OC5#/GPIO29 USBP8N USB20_N8 (32)
USB_OC#6 M4 W2 USB20_P8 10K_0402_5%
(29) USB_OC#6 OC6#/GPIO30 USBP8P USB20_P8 (32)
0814 UPDATE USB_OC#7 M3 V2 USB20_N9 High: CRT Plugged
OC7#/GPIO31 USBP9N USB20_N9 (32)
USB_OC#8 N3 V3 USB20_P9
USB20_P9 (32)

1
OC8#/GPIO44 USBP9P

A
N
USB_OC#9 N1 U5 USB20_N10 CRT_DET
OC9#/GPIO45 USBP10N USB20_N10 (20)
USB_OC#10 P5 U4 USB20_P10
OC10#/GPIO46 USBP10P USB20_P10 (20)

T
V
T
u
n
e
r

1
USB_OC#11 USB20_N11 D
P3 OC11#/GPIO47 USBP11N U1 USB20_N11 (20)
U2 USB20_P11 2 2N7002_SOT23
A +3VS USBP11P USB20_P11 (20) (24) CRT_DET# A
ICH SPI ROM for HDCP @ USBRBIAS AG2 Q22G
U40 USBRBIAS
AG1 S

3
USBRBIAS#
1

ICH_SPI_CS0# 1 8 Within 500 mils

R652 1 CS# VCC
+3VS 2 3.3K_0402_5% ICH_SPI_WP# 3 WP# SCLK 6 ICH_SPI_CLK ICH9M REV 1.0
R653 1 2 3.3K_0402_5% ICH_SPI_HOLD# 7 5 ICH_SPI_MOSI R340
HOLD# SI ICH_SPI_MISO 22.6_0402_1%
4 GND SO 2
2

MX25L512AMC-12G_SO8
SA000022S00 Security Classification Compal Secret Data Compal Electronics, Inc.
If ICH SPI not used, Left NC SPI ROM Footprint 150mil Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 18 of 43
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U6E

20 mils U6F AA26 H5
VSS[1] VSS[107]
A23 VCCRTC
G3: 6uA VCC1_05[1] A15 AA27 VSS[2] VSS[108] J23

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA
VCC1_05[2] B15 AA3 VSS[3] VSS[109] J26
1 1 ICH_V5REF_RUN A6 2mA C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[3] VSS[4] VSS[110]

C270

C271
VCC1_05[4] D15 1 1 AB1 VSS[5] VSS[111] AC22
ICH_V5REF_SUS AE1 2mA E15 C272 C273 AA23 K28
V5REF_SUS VCC1_05[5] VSS[6] VSS[112]
VCC1_05[6] F15 AB28 VSS[7] VSS[113] K29
2 2
AA24 VCC1_5_B[1] VCC1_05[7] L11 AB29 VSS[8] VSS[114] L13
646mA 2 2
0820 Change to 0805 AA25 VCC1_5_B[2] VCC1_05[8] L12 AB4 VSS[9] VSS[115] L15
AB24 VCC1_5_B[3] VCC1_05[9] L14 AB5 VSS[10] VSS[116] L2
AB25 VCC1_5_B[4] VCC1_05[10] L16 AC17 VSS[11] VSS[117] L26
R341 40 mils AC24 L17 R342 AC26 L27
VCC1_5_B[5] VCC1_05[11] VSS[12] VSS[118]

<BOM Structure>
+1.5VS 1 2 10U_0805_10V4Z AC25 L18 +1.5VS_VCCDMIPLL 1 2 +1.5VS AC27 L5
0_0805_5% VCC1_5_B[6] VCC1_05[12] MBK1608301YZF_0603 VSS[13] VSS[119]
1 AD24 VCC1_5_B[7] VCC1_05[13] M11 AC3 VSS[14] VSS[120] L7
D D
1 1 1 AD25 VCC1_5_B[8] VCC1_05[14] M18 1 1 AD1 VSS[15] VSS[121] M12
+

220U_D2_4VM_R15
C275 C276 C277 AE25 P11 C278 C279 AD10 M13
VCC1_5_B[9] VCC1_05[15] VSS[16] VSS[122]

C274
AE26 VCC1_5_B[10] VCC1_05[16] P18 AD12 VSS[17] VSS[123] M14
AE27 T11 0.01U_0402_16V7K AD13 M15
2 2 2 2 VCC1_5_B[11] VCC1_05[17] 2 2 VSS[18] VSS[124]
0816 Change to 10 ohm AE28 VCC1_5_B[12] VCC1_05[18] T18 AD14 VSS[19] VSS[125] M16
AE29 U11 AD17 M17

CORE
10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[19] 10U_0805_10V4Z VSS[20] VSS[126]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD18 VSS[21] VSS[127] M23
+5VS +3VS G25 V11 AD21 M28
VCC1_5_B[15] VCC1_05[21] VSS[22] VSS[128]
H24 VCC1_5_B[16] VCC1_05[22] V12 AD28 VSS[23] VSS[129] M29
H25 VCC1_5_B[17] VCC1_05[23] V14 +VCCP AD29 VSS[24] VSS[130] N11
1

22U_0805_6.3VAM
J24 VCC1_5_B[18] VCC1_05[24] V16 AD4 VSS[25] VSS[131] N12
R343 D11 J25 V17 1 0905 Connect to +VCCP AD5 N13
VCC1_5_B[19] VCC1_05[25] C280 VSS[26] VSS[132]
K24 VCC1_5_B[20] VCC1_05[26] V18 AD6 VSS[27] VSS[133] N14
100_0402_5% CH751H-40PT_SOD323-2 K25 AD7 N15
VCC1_5_B[21] VSS[28] VSS[134]
L23 R29 AD9 N16
2

VCC1_5_B[22] VCCDMIPLL 2 VSS[29] VSS[135]

L24 VCC1_5_B[23] AE12 VSS[30] VSS[136] N17
SD028100080 ICH_V5REF_RUN L25 23mA W23 AE13 N18
VCC1_5_B[24] VCC_DMI[1] +VCCP VSS[31] VSS[137]
1 20 mils M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE14 VSS[32] VSS[138] N26
C281 M25 AE16 N27
VCC1_5_B[26] 48mA VSS[33] VSS[139]
N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE17 VSS[34] VSS[140] P12
1U_0402_6.3V4Z N24 AC23 AE2 P13
2 SE100105Z80 VCC1_5_B[28] V_CPU_IO[2] VSS[35] VSS[141]

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N25 VCC1_5_B[29] AE20 VSS[36] VSS[142] P14
P24 2mA AG29 +3VS AE24 P15
VCC1_5_B[30] VCC3_3[1] 1 1 1 VSS[37] VSS[143]

C282

C283

C284
P25 VCC1_5_B[31] AE3 VSS[38] VSS[144] P16

VCCA3GP
R24 VCC1_5_B[32] VCC3_3[2] AJ6 AE4 VSS[39] VSS[145] P17
+5VALW +3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R25 VCC1_5_B[33] AE6 VSS[40] VSS[146] P2
2 2 2
R26 VCC1_5_B[34] VCC3_3[7] AC10 1 1 1 AE9 VSS[41] VSS[147] P23
R27 VCC1_5_B[35] AF13 VSS[42] VSS[148] P28
1

C285

C286

C287
D12 T24 AD19 AF16 P29
R344 VCC1_5_B[36] VCC3_3[3] VSS[43] VSS[149]

VCCP_CORE
T27 VCC1_5_B[37] VCC3_3[4] AF20 AF18 VSS[44] VSS[150] P4
2 2 2 (DMI)
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF22 VSS[45] VSS[151] P7
100_0402_5% CH751H-40PT_SOD323-2 T29 AC20 +3VS AH26 R11
C VCC1_5_B[39] VCC3_3[6] VSS[46] VSS[152] C
U24 AF26 R12
2

ICH_V5REF_SUS VCC1_5_B[40] 0.1U_0402_16V4Z VSS[47] VSS[153]

U25 VCC1_5_B[41]
308mA
VCC3_3[8] B9 AF27 VSS[48] VSS[154] R13
20 mils V24 VCC1_5_B[42] VCC3_3[9] F9 1 1 0816 Add 0.1uF AF5 VSS[49] VSS[155] R14
SD028100080 1 V25 G3 C288 C479 AF7 R15
C289 VCC1_5_B[43] VCC3_3[10] VSS[50] VSS[156]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF9 VSS[51] VSS[157] R16
W24 J2 0.1U_0402_16V4Z AG13 R17
1U_0402_6.3V4Z VCC1_5_B[45] VCC3_3[12] 2 2 VSS[52] VSS[158]

PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG16 VSS[53] VSS[159] R18
2 SE100105Z80 R964
K23 VCC1_5_B[47] VCC3_3[14] K7 AG18 VSS[54] VSS[160] R28
Y24 VGA@ 0_0402_5% AG20 T12
VCC1_5_B[48] +VCCHDA 0.1U_0402_16V4Z VSS[55] VSS[161]
Y25 VCC1_5_B[49] VCCHDA AJ4 1 2 +3VS AG23 VSS[56] VSS[162] T13
R345 VGA@ R965 0_0402_5% 1 1 2 +1.5VS AG3 T14
47mA 11mA +VCCSUSHDA C290 UMA@ R966 VSS[57] VSS[163]
+1.5VS 1 2 AJ19 VCCSATAPLL VCCSUSHDA AJ3 1 2 +3VALW AG6 VSS[58] VSS[164] T15
1U_0603_10V4Z

MBK1608301YZF_0603 0.1U_0402_16V4Z 1 1 2 +1.5V 0_0402_5% AG9 T16

11mA VSS[59] VSS[165]
10U_0805_10V4Z

AC16 UMA@R967
UMA@ R967
+1.5VS VCC1_5_A[1] VCCSUS1_05[1] AC8 T55 0_0402_5% 2
AH12 VSS[60] VSS[166] T17
1 1 AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 AH14 VSS[61] VSS[167] T23
T56
C292

C293

1 AD16 C291 AH17 B26

VCC1_5_A[3] 2 VSS[62] VSS[168]
ARX

C294 AE15 VCCSUS1_5_ICH_1

VCC1_5_A[4] VCCSUS1_5[1] AD8 T57
AH19 VSS[63] VSS[169] U12
AF15 VCC1_5_A[5] AH2 VSS[64] VSS[170] U13
2 2 1U_0603_10V4Z VCCSUS1_5_ICH_2
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH22 VSS[65] VSS[171] U14
2 T58
AH15 VCC1_5_A[7] 1 AH25 VSS[66] VSS[172] U15
AJ15 +3VALW C480 AH28 U16
VCC1_5_A[8] 0.1U_0402_16V4Z VSS[67] VSS[173]
VCCSUS3_3[1] A18 AH5 U17
VCCPSUS

VSS[68] VSS[174]

0.1U_0402_16V4Z
AC11 0.1U_0402_16V4Z
+1.5VS VCC1_5_A[9] VCCSUS3_3[2] D16 1 1 2
AH8 VSS[69] VSS[175] AD23
1 AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AJ12 VSS[70] VSS[176] U26

C295

C296
C297 AE11 VCC1_5_A[11] VCCSUS3_3[4] E22 AJ14 VSS[71] VSS[177] U27
ATX

AF11 VCC1_5_A[12] AJ17 VSS[72] VSS[178] U3

1U_0603_10V4Z 2 2
2
AG10 VCC1_5_A[13]
212mA 0816 Add 0.1uF AJ8 VSS[73] VSS[179] V1
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 B11 VSS[74] VSS[180] V13
AH10 VCC1_5_A[15] B14 VSS[75] VSS[181] V15
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 B17 VSS[76] VSS[182] V23
VCCSUS3_3[7] T2 B2 VSS[77] VSS[183] V28
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 B20 VSS[78] VSS[184] V29
B
T4 +3VALW B23 V4 B
VCCSUS3_3[9] VSS[79] VSS[185]
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 B5 VSS[80] VSS[186] V5
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B8 VSS[81] VSS[187] W26
1342mA U6 1 C26 W27
VCCPUSB

+1.5VS VCCSUS3_3[12] VSS[82] VSS[188]

AC21 U7 C298 C27 W3
VCC1_5_A[20] VCCSUS3_3[13] VSS[83] VSS[189]
1 VCCSUS3_3[14] V6 E11 VSS[84] VSS[190] Y1
C299 G10 V7 4.7U_0603_6.3V6M E14 Y28
VCC1_5_A[21] VCCSUS3_3[15] 2 VSS[85] VSS[191]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z W7 E2 Y4
2 VCCSUS3_3[17] VSS[87] VSS[193]
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E21 VSS[88] VSS[194] Y5
AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 E24 VSS[89] VSS[195] AG28
+1.5VS AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E5 VSS[90] VSS[196] AH6
1 11mA 11mA E8 AF2
C300 VCCCL1_05_ICH VSS[91] VSS[197]
AJ5 VCCUSBPLL VCCCL1_05 G22 F16 VSS[92] VSS[198] B25
1 F28 VSS[93]
0.1U_0402_16V4Z AA7 G23 C481 F29 A1
2 VCC1_5_A[26] VCCCL1_5 VSS[94] VSS_NCTF[1]
USB CORE

AB6 VCC1_5_A[27]
19/73/73mA G12 VSS[95] VSS_NCTF[2] A2
AB7 VCC1_5_A[28] VCCCL3_3[1] A24 +3VS 1 @ 2
0.1U_0402_16V4Z G14 VSS[96] VSS_NCTF[3] A28
AC6 B24 C301 G18 A29
VCC1_5_A[29] VCCCL3_3[2] 1U_0603_10V4Z VSS[97] VSS_NCTF[4]
AC7 VCC1_5_A[30] G21 VSS[98] VSS_NCTF[5] AH1
G24 VSS[99] VSS_NCTF[6] AH29
T60 VCC_LAN1_05_INT_ICH_1 2
+3VS
A10 VCCLAN1_05[1] 0816 Add 0.1uF G26 VSS[100] VSS_NCTF[7] AJ1
T61 VCC_LAN1_05_INT_ICH_2 A11 G27 AJ2
R535 0_0603_5% VCCLAN1_05[2] VSS[101] VSS_NCTF[8]
G8 VSS[102] VSS_NCTF[9] AJ28
1 2 +3VS_VCCLAN A12 H2 AJ29
VCCLAN3_3[1] VSS[103] VSS_NCTF[10]
0.1U_0402_16V4Z

1 B12 19/78/78mA H23 B1

C302 R346 0_0603_5% VCCLAN3_3[2] VSS[104] VSS_NCTF[11]
23mA H28 VSS[105] VSS_NCTF[12] B29
1 2 +1.5VS_VCCGLANPLL A27 H29
R347 VCCGLANPLL VSS[106]
+1.5VS 80mA
2
GLAN POWER
10U_0805_10V4Z

2+1.5VS_VCCGLAND28 ICH9M REV 1.0

2.2U_0603_6.3V4Z

+1.5VS 1 VCCGLAN1_5[1]
D29 VCCGLAN1_5[2]
1 1 0_0603_5% 1 E26
A C303 C304 VCCGLAN1_5[3] A
E27 VCCGLAN1_5[4]
1mA
+3VS A26 VCCGLAN3_3
2 2 2
0316 change design C305 ICH9M REV 1.0
4.7U_0805_10V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 19 of 43
5 4 3 2 1
 5 4 3 2 1

+5VS
JSATA1 eSATA w/ USB port
1
GND
A+ 2 SATA_TXP0
SATA_TXP0 (17) +5VALW
80mil +ESATA_VCCA
10U_0805_10V4Z

0.1U_0402_16V4Z
3 SATA_TXN0
1 1 1 1
A-
GND 4 0.01U_0402_16V7K
SATA_TXN0 (17) +ESATA_VCCA 60mil
C311

C314
5 SATA_RXN0 2 1 C306 SATA_RXN0_C U67
B- SATA_RXN0_C (17)
C312 C313 6 SATA_RXP0 2 1 C315 SATA_RXP0_C 1 8 1
B+ SATA_RXP0_C (17) GND OUT
7 0.01U_0402_16V7K C1109 0.1U_0402_16V4Z 2 7 1 1
2 2 2 2 GND IN OUT C806 +
2 1 3 IN OUT 6
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4 5 150U_B_6.3VM_R40M C808 C807 D
EN# FLG R1406 1000P_0402_50V7K
TPS2061DRG4_SO8 100K_0402_5% 2 2 2
VCC3.3 8
9 +3VS_HDD1 1 2 +3VALW 0.1U_0402_16V4Z
VCC3.3 SYSON#
VCC3.3 10 (29,34,40) SYSON#
11 JESATA
GND USB_OC#2 (18) USB
+3VS 12 1
R348 @ +3VS_HDD1 GND USBP20_N2 VBUS
GND 13 (18) USB20_N2 2 D-
2 1 14 USBP20_P2 3
VCC5 (18) USB20_P2 D+
0.1U_0402_16V4Z 15 +5VS 4
0_0805_5% 1 VCC5 GND
1 1 VCC5 16
GND 17 5 GND
@C319
@ C319 @C320
@ C320 @ C321 18 SATA_TXP3 6
RESERVED (17) SATA_TXP3 A+ ESATA
19 D40 SATA_TXN3 7
2 2 2 GND (17) SATA_TXN3 A-
23 20 USBP20_N2 2 8
1000P_0402_50V7K 1U_0603_10V4Z G1 VCC12 C390 2 SATA_RXN3 GND
24 G2 VCC12 21 1 (17) SATA_RXN3_C 1 0.01U_0402_25V7K 9 B-
22 USBP20_P2 3 C391 2 1 0.01U_0402_25V7K SATA_RXP3 10
VCC12 (17) SATA_RXP3_C B+
11 GND
PJDLC05_SOT23-3
SUYIN_127077MA022G206_NR 12 GND
@ 13 GND
14
CONN@
HDD Connector 15
GND
GND
T-SOL_199-2000000903
CONN@

C C

+5VS Card Reader & MINI CARD x2(WLAN & TV)

JSATA2
JP3
1 60 59 RCIRRX
GND (18) PCIE_TXP5 60 59 RCIRRX (31)
2 SATA_TXP4 58 57 WL_OFF#
A+ SATA_TXP4 (17) (18) PCIE_TXN5 58 57 WL_OFF# (31)
3 SATA_TXN4 56 55 PLT_RST# (7,16,18,26)
A- SATA_TXN4 (17) 56 55
0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z

4 0.01U_0402_16V7K (18) PCIE_RXP5 54 53 MCARD_CLKREQ2# (15)

GND SATA_RXN4 54 53
1 1 1 1 B- 5 2 1 C322 SATA_RXN4_C SATA_RXN4_C (17) (18) PCIE_RXN5 52 52 51 51 URX
URX (31)
C324

6 SATA_RXP4 2 1 C323 SATA_RXP4_C 50 49 UTX UTX (31)

B+ SATA_RXP4_C (17) 50 49
C325

C326

C327 7 0.01U_0402_16V7K 48 47
10U_0805_10V4Z GND (18) PCIE_TXP4 48 47 CLK_PCIE_MCARD2# (15)
(18) PCIE_TXN4 46 46 45 45 CLK_PCIE_MCARD2 (15)
2 2 2 2
44 44 43 43
DP 8 (18) PCIE_RXN4 42 42 41 41 CLK_PCIE_MCARD1# (15)
+5V 9 +5VS (18) PCIE_RXP4 40 40 39 39 CLK_PCIE_MCARD1 (15)
17 GND +5V 10 38 38 37 37
16 GND MD 11 (18) PCIE_TXN2 36 36 35 35 CLK_PCIE_READER# (15)
15 GND GND 12 (18) PCIE_TXP2 34 34 33 33 CLK_PCIE_READER (15)
B B
14 GND GND 13 32 32 31 31
(18) PCIE_RXN2 30 29 ICH_PCIE_WAKE#
30 29 ICH_PCIE_WAKE# (18,26,29)
(18) PCIE_RXP2 28 28 27 27 CR_CPPE# (18)
OCTEK_SLS-13SB1G_RV 26 25 CR_WAKE# (18)
USB20_N11 26 25
(18) USB20_N11 24 24 23 23 MCARD_CLKREQ# (15)
CONN@ (18) USB20_P11 USB20_P11 22 21 ICH_SMBDATA ICH_SMBDATA (15,18,25,26,29)
22 21 ICH_SMBCLK
20 20 19 19 ICH_SMBCLK (15,18,25,26,29)
USB20_N10 18 17
(18) USB20_N10 18 17
USB20_P10 16 15
CD-ROM Connector (18) USB20_P10

+3VALW
14
12
16
14
12
15
13
11
13
11 +1.5VS
5IN1_LED# (33)
MINI1_LED# (31)
10 10 9 9
+3VS 8 8 7 7
6 6 5 5 +3VS
4 4 3 3
2 2 1 1

ACES_88076-06071
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 20 of 43
5 4 3 2 1
 5 4 3 2 1

PCIE_GTX_C_MRX_N[0..15]
(9) PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15] +5VMXM_R +5VMXM
(9) PCIE_GTX_C_MRX_P[0..15]
+3VMXM_R +3VMXM R1413
R1414 1 2
PCIE_MTX_C_GRX_N[0..15] 0_1206_5%
(9) PCIE_MTX_C_GRX_N[0..15]
1 2 1 1
PCIE_MTX_C_GRX_P[0..15] 1 0_0805_5% C380 C180
(9) PCIE_MTX_C_GRX_P[0..15]
C410 0.1U_0402_16V4Z
10U_0805_6.3V6M
4.7U_0805_10V4Z VGA@ 2 2
2

D +MXM_B+_R D
L67 VGA@
1 2 B+
FBMA-L11-201209-221LMA30T_0805
2
1 2 L68 C958 +3VMXM_R
FBMA-L11-201209-221LMA30T_0805 0.1U_0603_25V7K
1 1 VGA@
C959 C960 1 VGA@ DGPU_PWROK R77 1 @ 2 10K_0402_5%
VGA_HDMI_CEC R80 1 @ 2 10K_0402_5% (Reserved)
680P_0603_50V7K 68P_0402_50V8J VGA_DISABLE# R78 1 @ 2 10K_0402_5% (Reserved)
2 2 VGA_WAKE# R82 1 2 10K_0402_5% (Reserved)
+MXM_B+_R +MXM_B+_R
VGA@ VGA@ JMXM2A +3VS JMXM2B
1 PWR_SRC PWR_SRC 2 167 GND GND 166
3 4 TH_OVERT# R79 1 2 10K_0402_5% PCIE_GTX_C_MRX_N2 0.1U_0402_16V7K VGA@ 2 1 C225 PCIE_GTX_MRX_N2 169 168 PCIE_MTX_C_GRX_N2
PWR_SRC PWR_SRC PCIE_GTX_C_MRX_P2 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P2 PEX_RX2# PEX_TX2# PCIE_MTX_C_GRX_P2
5 PWR_SRC PWR_SRC 6 2 1 C227 171 PEX_RX2 PEX_TX2 170
7 PWR_SRC PWR_SRC 8 173 GND GND 172
160mil(4A) 9 10 R110 PCIE_GTX_C_MRX_N1 0.1U_0402_16V7K VGA@ 2 1 C221 PCIE_GTX_MRX_N1 175 174 PCIE_MTX_C_GRX_N1
PWR_SRC PWR_SRC PCIE_GTX_C_MRX_P1 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P1 PEX_RX1# PEX_TX1# PCIE_MTX_C_GRX_P1
11 PWR_SRC E1 E2 PWR_SRC 12 1 2 +3VMXM_R 2 1 C226 177 PEX_RX1 PEX_TX1 176
13 14 100K_0402_5% VGA@ 179 178
PWR_SRC PWR_SRC AC_BATT# PCIE_GTX_C_MRX_N0 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N0 GND GND PCIE_MTX_C_GRX_N0
15 PWR_SRC PWR_SRC 16 2 1 ACIN (18,31,33,35) 2 1 C211 181 PEX_RX0# PEX_TX0# 180
17 18 PCIE_GTX_C_MRX_P0 0.1U_0402_16V7K VGA@ 2 1 C228 PCIE_GTX_MRX_P0 183 182 PCIE_MTX_C_GRX_P0
PWR_SRC PWR_SRC D1 PEX_RX0 PEX_TX0
19 PWR_SRC PWR_SRC 20 185 GND GND 184
21 22 CH751H-40PT_SOD323-2 VGA@ CLK_PCIE_VGA# 187 186 VGA_CLKREQ# VGA_CLKREQ# (15)
GND GND (15) CLK_PCIE_VGA# PEX_REFCLK# PEX_CLK_REQ#
23 24 2 1 CLK_PCIE_VGA 189 188 PEG_RST#
GND GND (15) CLK_PCIE_VGA PEX_REFCLK PEX_RST# PEG_RST# (16)
25 26 191 190 VGA_DDC_DATA VGA_DDC_DATA (24)
GND GND R117 GND VGA_DDC_DAT VGA_DDC_CLK
27 GND GND 28 193 RSVD VGA_DDC_CLK 192 VGA_DDC_CLK (24)
29 30 0_0402_5% 195 194 VGA_CRT_VSYNC VGA_CRT_VSYNC (24)
GND GND @ RSVD VGA_VSYNC VGA_CRT_HSYNC
31 GND E3 E4 GND 32 197 RSVD VGA_HSYNC 196 VGA_CRT_HSYNC (24)
33 GND GND 34 199 RSVD GND 198
35 36 201 200 VGA_CRT_R VGA_CRT_R (24)
GND GND VGA_TZCLK- RSVD VGA_RED VGA_CRT_G
37 GND GND 38 (22) VGA_TZCLK- 203 LVDS_UCLK# VGA_GREEN 202 VGA_CRT_G (24)
39 40 (Pull-UP 10K (22) VGA_TZCLK+ VGA_TZCLK+ 205 204 VGA_CRT_B VGA_CRT_B (24)
GND GND VGA_PRSNT_R LVDS_UCLK VGA_BLUE
+5VMXM_R 41 5V PRSNT_R# 42 at PCH) 207 GND GND 206
43 44 VGA_WAKE# 209 208 VGA_TXCLK- VGA_TXCLK- (22)
5V WAKE# LVDS_UTX3# LVDS_LCLK# VGA_TXCLK+
100mil(2.5A, 5VIA) 45 5V PWR_GOOD 46 DGPU_PWROK (18) 211 LVDS_UTX3 LVDS_LCLK 210 VGA_TXCLK+ (22)
C 47 5V PWR_EN 48 1 2 DGPU_PWR_EN (18,34) 213 GND GND 212 C
49 50 R101 0_0402_5% (22) VGA_TZOUT2- VGA_TZOUT2- 215 214
5V RSVD VGA_TZOUT2+ LVDS_UTX2# LVDS_LTX3#
51 GND RSVD 52 2 1 SUSP# (27,29,31,34,40) (22) VGA_TZOUT2+ 217 LVDS_UTX2 LVDS_LTX3 216
53 GND RSVD 54 219 GND GND 218
R76 55 56 D47 CH751H-40PT_SOD323-2 (22) VGA_TZOUT1- VGA_TZOUT1- 221 220 VGA_TXOUT2- VGA_TXOUT2- (22)
0_0402_5% @ GND RSVD AC_BATT# VGA_TZOUT1+ LVDS_UTX1# LVDS_LTX2# VGA_TXOUT2+
57 GND PWR_LEVEL 58 VGA@ (22) VGA_TZOUT1+ 223 LVDS_UTX1 LVDS_LTX2 222 VGA_TXOUT2+ (22)
1 2 59 60 TH_OVERT# TH_OVERT# (31) VGA_PWRGD/TH_OVERT# Connect to EC 225 224
VGA_DISABLE# PEX_STD_SW# TH_OVERT# R75 1 VGA_TZOUT0- GND GND VGA_TXOUT1-
61 VGA_DISABLE# TH_ALERT# 62 2 +3VMXM_R (22) VGA_TZOUT0- 227 LVDS_UTX0# LVDS_LTX1# 226 VGA_TXOUT1- (22)
63 64 10K_0402_5% (22) VGA_TZOUT0+ VGA_TZOUT0+ 229 228 VGA_TXOUT1+ VGA_TXOUT1+ (22)
(23) ENVDD PNL_PWR_EN TH_PWM LVDS_UTX0 LVDS_LTX1
(22) DGPU_L_BKL_EN 65 PNL_BL_EN GPIO0 66 231 GND GND 230
67 68 233 232 VGA_TXOUT0- VGA_TXOUT0- (22)
(22) VGA_PNL_PWM PNL_BL_PWM GPIO1 DP_C_L0# LVDS_LTX0#
VGA_HDMI_CEC 69 70 235 234 VGA_TXOUT0+ VGA_TXOUT0+ (22)
HDMI_CEC GPIO2 D_EC_SMB_DA1 DP_C_L0 LVDS_LTX0
71 DVI_HPD SMB_DAT 72 237 GND GND 236
Increase the rise time (22) I2CC_SDA I2CC_SDA 73 74 D_EC_SMB_CK1 SYSTEM 239 238
I2CC_SCL LVDS_DDC_DAT SMB_CLK DP_C_L1# DP_D_L0#
Ps. Module have 4.7K Pull-UP (22) I2CC_SCL 75 LVDS_DDC_CLK GND 76 241 DP_C_L1 DP_D_L0 240
77 GND OEM 78 243 GND GND 242
+3VS 1 2 79 OEM OEM 80 245 DP_C_L2# DP_D_L1# 244
R1841 10K_0402_5% @ 81 82 247 246
OEM OEM DP_C_L2 DP_D_L1
(27) SPDIF_MXM 83 OEM OEM 84 249 GND GND 248
1 2 85 OEM GND 86 251 DP_C_L3# DP_D_L2# 250
R1842 36K_0402_1% @ 87 88 PCIE_MTX_C_GRX_N15 253 252
PCIE_GTX_C_MRX_N15 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N15 GND PEX_TX15# PCIE_MTX_C_GRX_P15 DP_C_L3 DP_D_L2
2 1 C356 89 PEX_RX15# PEX_TX15 90 255 GND GND 254
PCIE_GTX_C_MRX_P15 0.1U_0402_16V7K VGA@ 2 1 C363 PCIE_GTX_MRX_P15 91 92 UMA@ R888 1 2 0_0402_5% 257 256
PEX_RX15 GND (31) HPD_7318_EC DP_C_AUX# DP_D_L3#
93 94 PCIE_MTX_C_GRX_N14 (31) HPD_7318_R_EC UMA@ R887 1 2 0_0402_5% 259 258
PCIE_GTX_C_MRX_N14 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N14 GND PEX_TX14# PCIE_MTX_C_GRX_P14 DP_C_AUX DP_D_L3
2 1 C353 95 PEX_RX14# PEX_TX14 96 261 RSVD GND 260
PCIE_GTX_C_MRX_P14 0.1U_0402_16V7K VGA@ 2 1 C366 PCIE_GTX_MRX_P14 97 98 263 262
PEX_RX14 GND PCIE_MTX_C_GRX_N13 UMA@ R891 1 RSVD DP_D_AUX#
99 GND PEX_TX13# 100 (7) SDVO_SDAT 2 0_0402_5% 265 RSVD DP_D_AUX 264
PCIE_GTX_C_MRX_N13 0.1U_0402_16V7K VGA@ 2 1 C351 PCIE_GTX_MRX_N13 101 102 PCIE_MTX_C_GRX_P13 UMA@ R892 1 2 0_0402_5% 267 266
PEX_RX13# PEX_TX13 (7) SDVO_SCLK RSVD DP_C_HPD
PCIE_GTX_C_MRX_P13 0.1U_0402_16V7K VGA@ 2 1 C368 PCIE_GTX_MRX_P13 103 104 269 268
PEX_RX13 GND PCIE_MTX_C_GRX_N12 RSVD DP_D_HPD
105 GND PEX_TX12# 106 271 RSVD RSVD 270
PCIE_GTX_C_MRX_N12 0.1U_0402_16V7K VGA@ 2 1 C362 PCIE_GTX_MRX_N12 107 108 PCIE_MTX_C_GRX_P12 273 272
PCIE_GTX_C_MRX_P12 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P12 PEX_RX12# PEX_TX12 RSVD RSVD
2 1 C371 109 PEX_RX12 GND 110 275 RSVD RSVD 274
111 112 PCIE_MTX_C_GRX_N11 277 276
PCIE_GTX_C_MRX_N11 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N11 GND PEX_TX11# PCIE_MTX_C_GRX_P11 RSVD GND
2 1 C352 113 PEX_RX11# PEX_TX11 114 279 RSVD DP_B_L0# 278
PCIE_GTX_C_MRX_P11 0.1U_0402_16V7K VGA@ 2 1 C377 PCIE_GTX_MRX_P11 115 116 281 280
PEX_RX11 GND PCIE_MTX_C_GRX_N10 RSVD DP_B_L0
117 GND PEX_TX10# 118 283 RSVD GND 282
PCIE_GTX_C_MRX_N10 0.1U_0402_16V7K VGA@ 2 1 C358 PCIE_GTX_MRX_N10 119 120 PCIE_MTX_C_GRX_P10 285 284
PCIE_GTX_C_MRX_P10 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P10 PEX_RX10# PEX_TX10 GND DP_B_L1#
B
2 1 C372 121 PEX_RX10 GND 122 (25) VGA_DVI_TXD2- 287 DP_A_L0# DP_B_L1 286 B
123 124 PCIE_MTX_C_GRX_N9 (25) VGA_DVI_TXD2+ 289 288
PCIE_GTX_C_MRX_N9 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N9 GND PEX_TX9# PCIE_MTX_C_GRX_P9 DP_A_L0 GND
2 1 C360 125 PEX_RX9# PEX_TX9 126 291 GND DP_B_L2# 290
PCIE_GTX_C_MRX_P9 0.1U_0402_16V7K VGA@ 2 1 C364 PCIE_GTX_MRX_P9 127 128 (25) VGA_DVI_TXD1- 293 292
PEX_RX9 GND PCIE_MTX_C_GRX_N8 DP_A_L1# DP_B_L2
129 GND PEX_TX8# 130 (25) VGA_DVI_TXD1+ 295 DP_A_L1 GND 294
PCIE_GTX_C_MRX_N8 0.1U_0402_16V7K VGA@ 2 1 C359 PCIE_GTX_MRX_N8 131 132 PCIE_MTX_C_GRX_P8 297 296
PCIE_GTX_C_MRX_P8 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P8 PEX_RX8# PEX_TX8 GND DP_B_L3#
2 1 C376 133 PEX_RX8 GND 134 (25) VGA_DVI_TXD0- 299 DP_A_L2# DP_B_L3 298
135 136 PCIE_MTX_C_GRX_N7 (25) VGA_DVI_TXD0+ 301 300
PCIE_GTX_C_MRX_N7 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N7 GND PEX_TX7# PCIE_MTX_C_GRX_P7 DP_A_L2 GND
2 1 C350 137 PEX_RX7# PEX_TX7 138 303 GND DP_B_AUX# 302
PCIE_GTX_C_MRX_P7 0.1U_0402_16V7K VGA@ 2 1 C379 PCIE_GTX_MRX_P7 139 140 (25) VGA_DVI_TXC- 305 304
PEX_RX7 GND PCIE_MTX_C_GRX_N6 DP_A_L3# DP_B_AUX
141 GND PEX_TX6# 142 (25) VGA_DVI_TXC+ 307 DP_A_L3 DP_B_HPD 306
PCIE_GTX_C_MRX_N6 0.1U_0402_16V7K VGA@ 2 1 C357 PCIE_GTX_MRX_N6 143 144 PCIE_MTX_C_GRX_P6 309 308 HDMI_DET (25)
PCIE_GTX_C_MRX_P6 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P6 PEX_RX6# PEX_TX6 GND DP_A_HPD
2 1 C373 145 PEX_RX6 GND 146 (25) VGA_DVI_SDATA 311 DP_A_AUX# 3V3 310 +3VMXM_R
147 148 PCIE_MTX_C_GRX_N5 (25) VGA_DVI_SCLK 313 312
PCIE_GTX_C_MRX_N5 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N5 GND PEX_TX5# PCIE_MTX_C_GRX_P5 VGA_PRSNT_L DP_A_AUX 3V3
2 1 C354 149 PEX_RX5# PEX_TX5 150 R118 314 PRSNT_L# 40mil(1A)
PCIE_GTX_C_MRX_P5 0.1U_0402_16V7K VGA@ 2 1 C365 PCIE_GTX_MRX_P5 151 152 0_0402_5% (Pull-UP 10K at PCH)
PEX_RX5 GND PCIE_MTX_C_GRX_N4 VGA_PRSNT_L
153 GND PEX_TX4# 154 (18) DGPU_PRSNT 2 1 315 GND GND 316
PCIE_GTX_C_MRX_N4 0.1U_0402_16V7K VGA@ 2 1 C361 PCIE_GTX_MRX_N4 155 156 PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_P4 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_P4 PEX_RX4# PEX_TX4
2 1 C367 157 PEX_RX4 GND 158 JAE_MM70-314-310B1-1
159 160 PCIE_MTX_C_GRX_N3 CONN@
PCIE_GTX_C_MRX_N3 0.1U_0402_16V7K VGA@ PCIE_GTX_MRX_N3 GND PEX_TX3# PCIE_MTX_C_GRX_P3
2 1 C355 161 PEX_RX3# PEX_TX3 162
PCIE_GTX_C_MRX_P3 0.1U_0402_16V7K VGA@ 2 1 C378 PCIE_GTX_MRX_P3 163 164
PEX_RX3 GND
165 GND
UMA MODE JAE_MM70-314-310B1-1
C378 change to 0 ohm(SD028000080) CONN@

C378
UMA@
+3VMXM_R +3VMXM_R

SD028000080 +3VMXM_R
1

0_0402_5% R84 R83

A 4.7K_0402_5% 4.7K_0402_5% A
2
G

1 3 D_EC_SMB_DA1
(31,36) SMB_EC_DA1
VGA@ VGA@
D

Q69
2N7002_SOT23 VGA@
2
G

1 3 D_EC_SMB_CK1
(31,36) SMB_EC_CK1
Compal Electronics, Inc.
D

Q70 Security Classification Compal Secret Data

2N7002_SOT23 VGA@ 2007/09/20 2008/09/20 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 21 of 43
5 4 3 2 1
 5 4 3 2 1

U64
R1447
16 DGPU_SELECT_R# 1 2 DGPU_SELECT#
SLE1 0_0402_5% VGA@

VGA_TXOUT0- 2 5 LVDS_A_0-_R
(21) VGA_TXOUT0- 0B1 A0 LVDS_A_0-_R (23)
VGA_TXOUT0+ 1 6 LVDS_A_0+_R
(21) VGA_TXOUT0+ 1B1 A1 LVDS_A_0+_R (23)
LVDS_A_0- 80
(9) LVDS_A_0- 0B2
LVDS_A_0+ 79
(9) LVDS_A_0+ 1B2
VGA_TXOUT1- 78 8 LVDS_A_1-_R
(21) VGA_TXOUT1- 2B1 A2 LVDS_A_1-_R (23)
VGA_TXOUT1+ 77 9 LVDS_A_1+_R R1426
(21) VGA_TXOUT1+ 3B1 A3 LVDS_A_1+_R (23)
(16,23,24,25) DGPU_SELECT# 1 2 VGA@
D LVDS_A_1- 76 0_0402_5% D
(9) LVDS_A_1- 2B2
LVDS_A_1+ 75
(9) LVDS_A_1+ 3B2 R1450
VGA_TXOUT2- 73 11 LVDS_A_2-_R 1 2
(21) VGA_TXOUT2- 4B1 A4 LVDS_A_2-_R (23) (17,24,25) DGPU_EDIDSEL# +3VS
VGA_TXOUT2+ 72 12 LVDS_A_2+_R 0_0402_5% @
(21) VGA_TXOUT2+ 5B1 A5 LVDS_A_2+_R (23)
C1115 0.1U_0402_16V4Z VGA@
LVDS_A_2- 71 1 2
(9) LVDS_A_2- 4B2
LVDS_A_2+ 70
(9) LVDS_A_2+ 5B2

1
VGA_TXCLK- 68 14 LVDS_A_C-_R U55
(21) VGA_TXCLK- 6B1 A6 LVDS_A_C-_R (23)
VGA_TXCLK+ 67 15 LVDS_A_C+_R

NC
(21) VGA_TXCLK+ 7B1 A7 LVDS_A_C+_R (23)
2 A Y 4 IGPU_SELECT# (24,25)
LVDS_A_C- 66
(9) LVDS_A_C- 6B2

G
LVDS_A_C+ 65
(9) LVDS_A_C+ 7B2 +3VMXM_R NC7SZ14P5X_NL_SC70-5

3
64 17 VGA@
8B1 A8
63 9B1 A9 18

1
62 R1415 +5VS
8B2 C1114
61 4.7K_0402_5%
9B2 VGA@
U41 1 2
34

2
SEL2 I2CC_SDA 0.1U_0402_16V4Z VGA@
(21) I2CC_SDA 2 1A VCC 8
DDC2_DATA 5 3 1 2
(9) DDC2_DATA 2A 1B LVDS_DDC2_DATA (23)
VGA_TZOUT0- 60 23 LVDS_B_0-_R 1 6 R1440 0_0402_5%
(21) VGA_TZOUT0- 10B1 A10 LVDS_B_0-_R (23) 1OE# 2B
VGA_TZOUT0+ 59 24 LVDS_B_0+_R 7 4
(21) VGA_TZOUT0+ 11B1 A11 LVDS_B_0+_R (23) 2OE# GND
LVDS_B_0- 58 +3VMXM_R SN74CBTD3306CPWR_TSSOP8
(9) LVDS_B_0- 10B2
LVDS_B_0+ 57 VGA@
(9) LVDS_B_0+ 11B2

1
VGA_TZOUT1- 56 26 LVDS_B_1-_R
(21) VGA_TZOUT1- 12B1 A12 LVDS_B_1-_R (23)
VGA_TZOUT1+ 55 27 LVDS_B_1+_R R1416 +5VS
C (21) VGA_TZOUT1+ 13B1 A13 LVDS_B_1+_R (23) C1116 C
4.7K_0402_5%
LVDS_B_1- 54 VGA@ 1 2
(9) LVDS_B_1- 12B2 U42
LVDS_B_1+ 53
(9) LVDS_B_1+

2
13B2 I2CC_SCL 0.1U_0402_16V4Z VGA@
(21) I2CC_SCL 2 1A VCC 8
VGA_TZOUT2- 51 29 LVDS_B_2-_R (9) DDC2_CLK DDC2_CLK 5 3 1 2
(21) VGA_TZOUT2- 14B1 A14 LVDS_B_2-_R (23) 2A 1B LVDS_DDC2_CLK (23)
VGA_TZOUT2+ 50 30 LVDS_B_2+_R 1 6 R1441 0_0402_5%
(21) VGA_TZOUT2+ 15B1 A15 LVDS_B_2+_R (23) 1OE# 2B
7 2OE# GND 4
LVDS_B_2- 49
(9) LVDS_B_2- 14B2
LVDS_B_2+ 48 SN74CBTD3306CPWR_TSSOP8
(9) LVDS_B_2+ 15B2 VGA@
VGA_TZCLK- 46 32 LVDS_B_C-_R
(21) VGA_TZCLK- 16B1 A16 LVDS_B_C-_R (23)
VGA_TZCLK+ 45 33 LVDS_B_C+_R
(21) VGA_TZCLK+ 17B1 A17 LVDS_B_C+_R (23)
LVDS_B_C- 44
(9) LVDS_B_C- 16B2
LVDS_B_C+ 43
(9) LVDS_B_C+ 17B2 +3VS
42 18B1 A18 35
41 19B1 A19 36

1
R1448
40 18B2 0_0402_5%
39 +3VS
19B2 VGA@ R1427 C1117 0.1U_0402_16V4Z VGA@
DGPU_SELECT# 1 2 @ 1 2
2

3 4 +3VS_SWITCH 0_0402_5%
GND1 VDD1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

13 GND2 VDD2 10

1
20 19 1 1 1 R1449 1 2 U61
GND3 VDD3 (17) DGPU_PWMSEL#
21 22 C779 C778 0_0402_5% VGA@

NC
GND4 VDD4 @ C777 IGPU_PWM_SELECT#
31 GND5 VDD5 28 2 A Y 4
38 37 4.7U_0603_6.3V6K
GND6 VDD6

G
2 2 2 VGA@
52 GND7 VDD7 47
74 69 +3VMXM_R NC7SZ14P5X_NL_SC70-5

3
GND8 VDD8 VGA@
25 OE2#
B 7 VGA@ B
OE1#

1
R93 R1418 +5VS
C1119
0_0402_5% @ 2.2K_0402_5%
PI3LVD1012BE_BQSOP80 1 2 @ 1 2 VGA@
(21) VGA_PNL_PWM U43
VGA@

2
1 2 2 8 0.1U_0402_16V4Z
(23,31) INV_PWM 1A VCC
R100 0_0402_5% 5 3
2A 1B LVDS_INV_PWM (23)
VGA@ 1 6
+3VS 1OE# 2B
7 2OE# GND 4

SN74CBTD3306CPWR_TSSOP8

1
U54 VGA@
UMA ONLY

NC
(9) DPST_PWM 2 A Y 4 1 2 LVDS_INV_PWM (23)
R1462 0_0402_5% UMA@

G
LVDS_A_0- RP3 4 1 LVDS_A_0-_R NC7SZ14P5X_NL_SC70-5
LVDS_A_0+ 3 2 LVDS_A_0+_R (9) IGPU_L_BKLT_EN 1 2 ENABLT (31)

3
UMA@ 0_0404_4P2R_5% R1463 0_0402_5% UMA@
LVDS_A_1- RP5 4 1 LVDS_A_1-_R
LVDS_A_1+ 3 2 LVDS_A_1+_R
UMA@ 0_0404_4P2R_5%
LVDS_A_2+ RP7 3 2 LVDS_A_2+_R +3VMXM_R
LVDS_A_2- 4 1 LVDS_A_2-_R
UMA@ 0_0404_4P2R_5%

1
LVDS_A_C- RP9 4 1 LVDS_A_C-_R
LVDS_A_C+ 3 2 LVDS_A_C+_R R1417 +5VS
C1118
UMA@ 0_0404_4P2R_5% 2.2K_0402_5%
LVDS_B_0+ RP11 3 2 LVDS_B_0+_R @ 1 2 VGA@
LVDS_B_0- LVDS_B_0-_R U46
4 1

2
UMA@ 0_0404_4P2R_5% (21) DGPU_L_BKL_EN 2 8 0.1U_0402_16V4Z
LVDS_B_1- RP13 4 LVDS_B_1-_R 1A VCC
1 (9) IGPU_L_BKLT_EN 5 2A 1B 3 1 2 ENABLT (31)
A LVDS_B_1+ 3 2 LVDS_B_1+_R R1455 1 2 0_0402_5% 1 6 R1442 0_0402_5% A
(16,23,24,25) DGPU_SELECT# 1OE# 2B
UMA@ 0_0404_4P2R_5% VGA@ 7 4
LVDS_B_2- RP15 4 LVDS_B_2-_R (23) IGPU_VCCEN_SEL# 2OE# GND
1
LVDS_B_2+ 3 2 LVDS_B_2+_R SN74CBTD3306CPWR_TSSOP8
UMA@ 0_0404_4P2R_5% VGA@
LVDS_B_C+ RP21 3 2 LVDS_B_C+_R
LVDS_B_C- 4 1 LVDS_B_C-_R
UMA@ 0_0404_4P2R_5%

DDC2_DATA
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 UMA@ LVDS_DDC2_DATA Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
R1460 0_0402_5%
DDC2_CLK 1 2 UMA@ LVDS_DDC2_CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
R1461 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 22 of 43
5 4 3 2 1
 5 4 3 2 1

+LCDVDD +LCDVDD +3VS

2N7002_SOT23-3
Q30

1
R563

S
1 3
300_0603_5% AO3413_SOT23
+5VALW
1 1 1

G
2

2
C669 C670

2
C668 4.7U_0603_6.3V6K

1+LCDVDD_R
R564 0.1U_0402_16V4Z 4.7U_0805_10V4Z
D 2 2 2 D
100K_0402_5%

1
R565
Q31 D
2 2 1
2N7002_SOT23 G
S 100K_0402_5% 2

3
+3VS C938
C1121 0.1U_0402_16V4Z 1U_0402_6.3V4Z
VGA@ 1
1 2

1
U68
R1428

NC
(16,22,24,25) DGPU_SELECT# 1 2 2 A Y 4 IGPU_VCCEN_SEL# (22)
0_0402_5%

G
VGA@
NC7SZ14P5X_NL_SC70-5

3
VGA@

+5VS
C1120
VGA@
U47 1 2
VGA@

1
R282 1 D
(21) ENVDD 2 0_0402_5% 2 1A VCC 8 0.1U_0402_16V4Z
R283 1 2 0_0402_5% 5 3 2 Q54
(9) ENAVDD 2A 1B
VGA@ DGPU_VCCEN_SEL# 1 6 G 2N7002_SOT23
1OE# 2B

1
7 4 S

3
2OE# GND
SN74CBTD3306CPWR_TSSOP8 R885
C VGA@ 100K_0402_5% C
R284 1 2 0_0402_5%
(9) ENAVDD

2
UMA@

LVDS and USB CAM connector

+LCDVDD
+INVPWR_B+ +3VS
10U_0805_10V4Z

L29 1 2 0.1U_0402_16V4Z
B+
W=40mils FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1
C663 C664 C943 C667
C665 L30 1 2 C868

390P_0402_50V7K
680P_0402_50V7k

FBMA-L11-201209-221LMA30T_0805 1800P_0402_50V7K 0.1U_0402_16V4Z

2 2 2 2 2
1 1
C666

68P_0402_50V8J
2 2

JLVDS
1 1 +INVPWR_B+
41 G1 2 2
42 G2 3 3
B R1004 B
43 G3 4 4 +LCDVDD W=60mils GMCH_INV_PWM 1 @
44 G4 5 5 2 INV_PWM (22,31)
45 6 0_0402_5%
G5 6
46 G6 7 7 +3VS
8 GMCH_INV_PWM 1 2
8 LVDS_INV_PWM (22)
9 DISPLAYOFF# R1010 0_0402_5%
9 LVDS_DDC2_CLK
10 10 LVDS_DDC2_CLK (22)
11 LVDS_DDC2_DATA
11 LVDS_DDC2_DATA (22)
12 12
13 LVDS_A_0-_R
13 LVDS_A_0-_R (22)
14 LVDS_A_0+_R
14 LVDS_A_0+_R (22)
15 +3VS
15 LVDS_A_1-_R
16 16 LVDS_A_1-_R (22)
17 LVDS_A_1+_R
17 LVDS_A_1+_R (22)
18 18 2
19 LVDS_A_2-_R R569
19 LVDS_A_2-_R (22)
20 LVDS_A_2+_R
20 LVDS_A_2+_R (22)
21 4.7K_0402_5%
21 LVDS_A_C-_R D43 R1008
22 LVDS_A_C-_R (22)
1

22 LVDS_A_C+_R DISPLAYOFF#
23 23 LVDS_A_C+_R (22) 2 1 1 2 BKOFF# (31)
24 0_0402_5%
24 LVDS_B_0-_R CH751H-40PT_SOD323-2
25 25 LVDS_B_0-_R (22)
26 LVDS_B_0+_R
26 LVDS_B_0+_R (22)
27 27
28 LVDS_B_1-_R
28 LVDS_B_1-_R (22)
29 LVDS_B_1+_R
29 LVDS_B_1+_R (22)
30 30
31 LVDS_B_2-_R
31 LVDS_B_2-_R (22)
32 LVDS_B_2+_R
32 LVDS_B_2+_R (22)
33 33
34 LVDS_B_C-_R GMCH_INV_PWM 1 2 220P_0402_50V7K
34 LVDS_B_C-_R (22)
35 LVDS_B_C+_R C673
A 35 LVDS_B_C+_R (22) A
36 DISPLAYOFF# 1 2 220P_0402_50V7K
36 C674
37 37 +3VS
38 USB20_CMOS_N3 0_0603_5%2 1 R567
38 USB20_N3 (18)
39 USB20_CMOS_P3 0_0603_5%2 1 R568
39 USB20_P3 (18)
40 40

IPEX_20143-040E-20F

CONN@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 23 of 43
5 4 3 2 1
 A B C D E

NOTE: L : A-->B1
H: A-->B2
+5VS +RCRT_VCC +CRTVDD

D4 F1
2 1 1 2 W=40mils
1
CH491D_SC59 1.1A_6VDC_FUSE C213
0.1U_0402_16V4Z

1 2 1
JCRT1
6 6
L24 11
CRT_R 1 2
FCM2012CF-800T06_2P
L26
RED 1
7
11
1
7
CRT Connector
12 12
CRT_G 1 2 GREEN 2
FCM2012CF-800T06_2P 2
8 8
L28 +CRTVDD
13 13
CRT_B 1 2 BLUE 3
FCM2012CF-800T06_2P 3
9 9

1
14 14 G 16

2
C661 4 17
R560 R561 R562 C6571 4 G
1 1 C659 1 1 1 10 10
R555
C658 22P_0402_50V8J C660 C662 15 100K_0402_5%
15

150_0402_1%

150_0402_1%

22P_0402_50V8J
5

2
10P_0402_50V8J 10P_0402_50V8J 5

1
150_0402_1% 2 2 2 2 2 2 ALLTO_C10532-11505-L
CRT_DET# (18)
22P_0402_50V8J CONN@
+3VS
+CRTVDD +CRTVDD +3VS
10P_0402_50V8J

1
R197 R198 R199 R200
10K_0402_5% 10K_0402_5%

2
+5VS +5VS 2.2K_0402_5% 2.2K_0402_5%
R350

2
C214 C215 D_DDCDATA 6 1 3VDDCDA_R 2 1 CRT_DDC_DATA
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0_0402_5%
1 2 1 2 2N7002DW T/R7_SOT363-6

5
2 2
Q4A
2 1 R352
R872 D_DDCCLK 3 4 3VDDCCL_R 2 1 CRT_DDC_CLK

5
1
10K_0402_5% U4 0_0402_5%
SN74AHCT1G125GW_SOT353-5 R196

P
OE#
CRT_HSYNC_R HSYNC_G_A DHSYNC Q4B
2 A Y 4 1 2 0_0603_5%
2N7002DW T/R7_SOT363-6

5
1
R202

P
OE#
CRT_VSYNC_R 3 2 A Y 4 VSYNC_G_A 1 2 0_0603_5% DVSYNC

G
U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C216 C217

3
1

R204 R205 5P_0402_50V8C 5P_0402_50V8C BLUE

51K_0402_5% 51K_0402_5% 2 2 GREEN
RED
2

Place close to JP6

1
@ D5
@D5 @ D6 @ D7

DAN217_SC59
+3VS

DAN217_SC59

DAN217_SC59
+CRTVDD
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

3
1 1 1 1
C780 C781 C782 C783
R1429
1 2 VGA@
2 2 2 2 (16,22,23,25) DGPU_SELECT# 0_0402_5%
R1451
3 3
(17,22,25) DGPU_EDIDSEL# 1 2
U66 0_0402_5% @
+3VS 1 R1430
VDD
4 VDD SEL 12 DGPU_SELECT# (16,22,23,25) 1 2
+3VMXM_R 0_0402_5% IGPU_SELECT# (22,25)
9 VDD
19 2 CRT_R VGA@
VDD YA CRT_G
YB 5

1
24 6 CRT_B
(21) VGA_CRT_R A0 YC
22 R1421 +5VS
(21) VGA_CRT_G B0 C1124
18 8 CRT_HSYNC_R 2.2K_0402_5%
(21) VGA_CRT_B C0 YD
17 11 CRT_VSYNC_R @ 1 2 VGA@
(21) VGA_CRT_HSYNC D0 YE U48
(21) VGA_CRT_VSYNC 14

2
E0 0.1U_0402_16V4Z
(21) VGA_DDC_DATA 2 1A VCC 8
23 3 5 3 CRT_DDC_DATA
(9) M_RED A1 GND (9) 3VDDCDA 2A 1B
(9) M_GREEN 21 B1 GND 7 1 1OE# 2B 6
16 10 7 4 R1464
(9) M_BLUE C1 GND 2OE# GND
15 20 1 2 CRT_DDC_DATA
(9) CRT_HSYNC D1 GND +3VMXM_R (9) 3VDDCDA
13 SN74CBTD3306CPWR_TSSOP8 0_0402_5% UMA@
(9) CRT_VSYNC E1 VGA@
PI3V512QE_QSOP24
1

R1420 +5VS
C1123
2.2K_0402_5%
@ 1 2 VGA@
U49
2

(21) VGA_DDC_CLK 2 8 0.1U_0402_16V4Z

1A VCC CRT_DDC_CLK
(9) 3VDDCCL 5 2A 1B 3
1 1OE# 2B 6
7 2OE# GND 4
R1465
SN74CBTD3306CPWR_TSSOP8 (9) 3VDDCCL 1 2 CRT_DDC_CLK
VGA@ 0_0402_5% UMA@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 24 of 43
A B C D E
 5 4 3 2 1

R1444 L25
+HDMI_5V_OUT
1 2 0_0402_5% VGA@ DDC to HDMI CONN UMA@
(16,22,23,24) DGPU_SELECT#
R1452
(17,22,24) DGPU_EDIDSEL# 1 2 0_0402_5% +3VS +HDMI_5V_OUT SD013000080 W=40mils F2 D64
@ R1443
1 2
IGPU_SELECT# (22,24) 5V Level 0_0603_5% 2 1 1 2 +5VS
+3VMXM_R 0_0402_5% 1

10K_0402_5%
VGA@ L27 1.1A_6VDC_FUSE SS1040_SOD123

1
+5VS UMA@ C957

1
R1456 UMA@ R1015 R203 R201 0.1U_0402_16V4Z
R1446 10K_0402_5% 2
2.2K_0402_5%
1
0_0402_5%
2 C1131 1
0_0402_5%
2
SD013000080

5
VGA@ 1 2 UMA@

2
U50
0_0603_5%

2
2 8 0.1U_0402_16V4Z DVI_DDC_DATA 4 3 DVI_SDATA_L 1 2 DVI_SDATA
(21) VGA_DVI_SCLK 1A VCC
1 2 5 3 DVI_DDC_CLK VGA@ L25 FCM2012CF-800T06_2P
D (15,18,20,26,29) ICH_SMBCLK 2A 1B D
R1458 @ 1 6 Q68B VGA@ +5VMXM
1OE# 2B

2
0_0402_5% 7 4 VGA@ 2N7002DW-T/R7_SOT363-6
2OE# GND
SN74CBTD3306CPWR_TSSOP8 DVI_DDC_CLK 1 6 DVI_SCLK_L 1 2 DVI_SCLK
VGA@ VGA@ L27 FCM2012CF-800T06_2P

2
+3VMXM_R

10P_0402_50V8J

10P_0402_50V8J

G
Q68A 2N7002DW-T/R7_SOT363-6 VGA@ 1 1 Q13 R1044 L31
Place closed to JHDMI1 C677 C678 MBK1608221YZF_2P
+5VS 1 2 (21) HDMI_DET 3 1 1 2 1 2 HP_DETECT
1 R1457 UMA@ R1016 10K_0402_5%

D
R1445 0_0402_5% 2 2
1 2 C1130 1

1
2.2K_0402_5% 0_0402_5% UMA@ 2N7002_SOT23

1
VGA@ 1 2 D65 C686
U51 220P_0402_50V7K
(18) HDMI_HPD# BAV99-7-F_SOT23-3
2

0.1U_0402_16V4Z R1422 2
(21) VGA_DVI_SDATA 2 1A VCC 8 @

1
(15,18,20,26,29) ICH_SMBDATA 1 2 5 3 DVI_DDC_DATA VGA@ VGA@ Q14 D 20K_0402_5%
R1459 @ 2A 1B
1 6 2

3
0_0402_5% 1OE# 2B VGA@ G
7 2OE# GND 4
S 2N7002_SOT23

3
SN74CBTD3306CPWR_TSSOP8
VGA@
+3VS

VGA_DVI_TXD2- C741 2 1 0.1U_0402_16V7K VGA@ DVI_TXD2-_R

HDMI Connector
(21) VGA_DVI_TXD2-
VGA_DVI_TXD2+ C747 2 1 0.1U_0402_16V7K VGA@ DVI_TXD2+_R DVI_TXD2-_R 1 2 C_DVI_R_TXD2- DVI_TXD0-_R 1 2 C_DVI_R_TXD0-
(21) VGA_DVI_TXD2+
R1032 5.6_0402_5% R1028 5.6_0402_5%
VGA_DVI_TXD1- C809 2 1 0.1U_0402_16V7K VGA@ DVI_TXD1-_R +HDMI_5V_OUT
(21) VGA_DVI_TXD1-
VGA_DVI_TXD1+ C765 2 1 0.1U_0402_16V7K VGA@ DVI_TXD1+_R L66 L65
(21) VGA_DVI_TXD1+
3 3 4 4 3 3 4 4
VGA_DVI_TXD0- C811 2 1 0.1U_0402_16V7K VGA@ DVI_TXD0-_R JHDMI1
(21) VGA_DVI_TXD0-
VGA_DVI_TXD0+ C810 2 1 0.1U_0402_16V7K VGA@ DVI_TXD0+_R HP_DETECT 19
(21) VGA_DVI_TXD0+ HP_DET
2 2 1 1 2 2 1 1 18 +5V
C741 VGA_DVI_TXC- C813 2 1 0.1U_0402_16V7K VGA@ DVI_TXC-_R 17
(21) VGA_DVI_TXC- DDC/CEC_GND
UMA@ VGA_DVI_TXC+ C812 2 1 0.1U_0402_16V7K VGA@ DVI_TXC+_R WCM-2012-900T_4P @ WCM-2012-900T_4P @ DVI_SDATA 16
(21) VGA_DVI_TXC+ SDA
DVI_SCLK 15
1 SCL

1
R1035
499_0402_1%

R1036
499_0402_1%

R1037
499_0402_1%

R1038
499_0402_1%

R1039
499_0402_1%

R1040
499_0402_1%

R1041
499_0402_1%

R1042
499_0402_1%
C811 DVI_TXD2+_R C_DVI_R_TXD2+ DVI_TXD0+_R C_DVI_R_TXD0+
C
SD028000080 UMA@
1
R1033
2
5.6_0402_5%
1
R1029
2
5.6_0402_5%
14
13
Reserved
C
C_DVI_R_TXC- CEC
12 CK- GND 20
0_0402_5% SD028000080 11 CK_shield GND 21
C_DVI_R_TXC+ 10 22
2

2
C747 C_DVI_R_TXD0- CK+ GND
9 D0- GND 23
UMA@ 0_0402_5% DVI_TXD1-_R 1 2 C_DVI_R_TXD1- DVI_TXC-_R 1 2 C_DVI_R_TXC- 8
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ R1030 5.6_0402_5% R1026 5.6_0402_5% C_DVI_R_TXD0+ D0_shield
7 D0+
C810 C_DVI_R_TXD1-
SD028000080 UMA@ L63 L64
6
5
D1-
0_0402_5% VGA@ C_DVI_R_TXD1+ D1_shield
2 2 1 1 2 2 1 1 4 D1+

1
D C_DVI_R_TXD2-
0_0402_5% SD028000080 3 D2-
+3VMXM_R 1 2 2 2 D2_shield
C809 R1181 G 3 4 3 4 C_DVI_R_TXD2+ 1
3 4 3 4 D2+
UMA@ 0_0402_5% 1 Q12 S

3
R1839 2N7002_SOT23 WCM-2012-900T_4P WCM-2012-900T_4P TAITW_PDVBR9-19FLBS4NN4N1
C813 100K_0402_5%
SD028000080 UMA@ DVI_TXD1+_R 1 2
@
C_DVI_R_TXD1+ DVI_TXC+_R 1 2
@
C_DVI_R_TXC+
VGA@ R1031 5.6_0402_5% R1027 5.6_0402_5%
2

0_0402_5% SD028000080
C765 VGA@
UMA@ 0_0402_5%
C812
SD028000080 UMA@

0_0402_5% SD028000080
0_0402_5%

LAN Connector
C947
B B
1 2
T105 JRJ45
1 24 RJ45_MIDI0+ 1 @ 68P_0402_50V8J
LAN_MIDI0+ TCT1 MCT1 RJ45_MIDI0+ TX0+ LAN_LINK#
(26) LAN_MIDI0+ 2 TD1+ MX1+ 23 LED_GREEN- 9 LAN_LINK# (26)
(26) LAN_MIDI0- LAN_MIDI0- 3 22 RJ45_MIDI0- RJ45_MIDI0- 2
TD1- MX1- TX0-
4 TCT2 MCT2 21 COMMON+ 10 2 1 +3V_LAN
(26) LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ RJ45_MIDI1+ 3 R328 @ 1 1K_0402_5% R1182
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- TX1+
(26) LAN_MIDI1- 6 TD2- MX2- 19 LED_ORANGE- 11 1 2
7 18 RJ45_MIDI2+ 4 0_0402_5% C138
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+ TX2+
(26) LAN_MIDI2+ 8 TD3+ MX3+ 17 LED_YELLOW+ 12 220P_0402_50V7K
LAN_MIDI2- RJ45_MIDI2- RJ45_MIDI2- 2
(26) LAN_MIDI2- 9 TD3- MX3- 16 5 TX2-
10 TCT4 MCT4 15 LED_YELLOW- 13
(26) LAN_MIDI3+ LAN_MIDI3+ 11 14 RJ45_MIDI3+ RJ45_MIDI1- 6 1 2
TD4+ MX4+ TX1- +3V_LAN
(26) LAN_MIDI3- LAN_MIDI3- 12 13 RJ45_MIDI3- 14 1 1K_0402_5% R308
TD4- MX4- RJ45_MIDI3+ GND
7 TX3+
350uH_GSL5009-1 LF 15 220P_0402_50V7K
RJ45_MIDI3- GND C440
8 TX3- 2
FOX_JM3611L-N3255-7F
1

LAN_ACTIVITY#
LAN_ACTIVITY# (26)
1 1 1 1 R921 R922
C863 C859 C864 C858 75_0402_1% 75_0402_1% @68P_0402_50V8J
1 2
2

0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 C945
R916 R915
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% LAN_ACTIVITY#
LAN_LINK# RJ45_GND 1 2 LANGND 40mil
2

1 1
RJ45_GND C87
Place close to TCT pin 1000P_1206_2KV7K C316 C233
4.7U_0805_10V4Z
40mil
3

2 2
D73
PJDLC05_SOT23-3 0.1U_0402_16V4Z
A @ A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 25 of 43
5 4 3 2 1
 5 4 3 2 1

0_1206_5%
+3VALW R1052 1 2 +3V_LAN

1
R1053
1.5_1206_5%

2
1 1
C970 C971

3
+3V_LAN 0.1U_0402_16V4Z
LAN_REGCTL12 1 2 2
D
60mil 4.7U_0805_10V4Z D
Q71 +1.2V_LAN
1 1 1 1 MMJT9435T1G_SOT223

2
4
C973 C979 C974 C975 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

4.7U_0805_10V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 C972 C976 C977 C978 C980 C981 C982 C983 C984 C1113 C1112
0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+3V_LAN

U56

2
41 LAN_MIDI0- R1055
TRD0_N LAN_MIDI0- (25)
28 40 LAN_MIDI0+
(15) CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_MIDI0+ (25)
42 +LAN_AVDD 4.7K_0402_5%
TRD1_N/AVDD
(15) CLK_PCIE_LAN 29 43 LAN_MIDI1- (25)

1
PCIE_REFCLK_P TRD1_P/T1_N +LAN_AVDD SPROM_DIN
TRD2_N/AVDD 48
(15) LAN_CLKREQ# 11 CLKREQ TRD2_P/T2_N 47 LAN_MIDI2- (25)
49 LAN_MIDI3-
TRD3_N LAN_MIDI3- (25)
R1058 1 2 0_0402_5% @ 50 LAN_MIDI3+
(18) LAN_LOWPWR TRD3_P LAN_MIDI3+ (25)
R1056 1 2 10K_0402_5% 3 LOW PWR +3V_LAN +3V_LAN +3V_LAN
+3VS R1059 1 2 1K_0402_5% 53 2 2 1 +3V_LAN
C VMAIN_PRSNT LINKLED R1060 LAN_LINK# (25) C
SPD100LED 1 1
+3V_LAN R1057 1 2 1K_0402_5% 54 67 0_0402_5% C985
VAUX_PRSNT SPD1000LED

2
TRAFFICLED 66 2 1 LAN_ACTIVITY# (25)
R1061 0.1U_0402_16V4Z R1062 R1063 R1064
0_0402_5% 2
4.7K_0402_5% 4.7K_0402_5%4.7K_0402_5%
59 65 SPROM_CLK U57
(18) ENERGY_DET ENERGY_DET SCLK(EECLK)
63 SPROM_DIN 1 8

1
+LAN_GPHYPLLVDD SI SPROM_DOUT A0 VCC SPROM_WP
35 GPHY_PLLVDD SO(EEDATA) 64 2 A1 WP 7
62 SPROM_CS R1065 1 2 4.7K_0402_5% 2 1 3 6 SPROM_CLK
CS R1066 0_0402_5% A2 SCL SPROM_DOUT
(18) PCIE_TXN3 32 PCIE_RXD_N 4 GND SDA 5

31 AT24C64AN-10SU-2.7_SO8
(18) PCIE_TXP3 PCIE_RXD_P
14 LAN_REGCTL12
C986 1 GLAN_RXN_C REGCTL12
(18) PCIE_RXN3 2 25 PCIE_TXD_N REGCTL25/12_IO 18 +Lan_VDDIO_1.2
0.1U_0402_16V7K 37 LAN_RDAC 1 2 20mil
C987 1 GLAN_RXP_C RDAC R1067 1.24K_0402_1% L70
(18) PCIE_RXP3 2 26 PCIE_TXD_P
0.1U_0402_16V7K +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
L69 1 1 BLM18AG601SN1D_2P
23 +LAN_XTALVDD 1 2 +3V_LAN C988 C989
R1068 1 0_0402_5% LAN_RESET# XTALVDD BLM18AG601SN1D_2P +Lan_VDDIO_1.2
(7,16,18,20) PLT_RST# 2 10 PERST VDDIO 6 +3V_LAN
15 1 0.1U_0402_16V4Z
R1069 1 @ VDDIO 2 2
(18,20,29) ICH_PCIE_WAKE# 2 0_0402_5% LAN_PME# 12 WAKE VDDIO 19 C990
(31) EC_LAN_PME# R1070 1 2 0_0402_5% 56 4.7U_0805_10V4Z
VDDIO 0.1U_0402_16V4Z
+3V_LAN 1 2 VDDIO 61 1 1
R1054 4.7K_0402_5% 2 C991 C992
LAN_SMBCLK +Lan_VDDIO_1.2
20mil L71
58 SMB_CLK VDDP 17
+3V_LAN 68 0.1U_0402_16V4Z 0.1U_0402_16V4Z +LAN_PCIEVDD 1 2
VDDP/DC 2 2 +1.2V_LAN
R1071 LAN_SMBDATA 57 1 1 BLM18AG601SN1D_2P
4.7K_0402_5% SMB_DATA C993 C994
VDDC 5
5

1 2 +3V_LAN VDDC 13 +1.2V_LAN

20 0.1U_0402_16V4Z
LAN_SMBDATA VDDC 2 2
(15,18,20,25,29) ICH_SMBDATA 3 4 4 GPIO_0(SERIAL_DO) VDDC 34
B 4.7U_0805_10V4Z B
VDDC 55
Q72B @ SPROM_WP 7 60
2N7002DW-T/R7_SOT363-6 GPIO_1(SERIAL_DI) VDDC L72
R1072 1 +LAN_BIASVDD
20mil
2 @ 8 GPIO_2 BIASVDD 36 1 2 +3V_LAN L73
0_0402_5% 30 +LAN_PCIEPLLVDD BLM18AG601SN1D_2P +LAN_AVDD 1 2 +3V_LAN
PCIE_PLLVDD BLM18AG601SN1D_2P
9 UART_MODE PCIE_VDD/PLL 27 1 1 1
+3V_LAN 33 +LAN_PCIEVDD C995 C996 C997
R1073 PCIE_VDD
4.7K_0402_5% 38 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AVDD/DC
2

LAN_XTALI 2 2 2
1 2 +3V_LAN 21 XTALI AVDD/AVDDL 45 +LAN_AVDDL
52 0.1U_0402_16V4Z
LAN_SMBCLK XTALO AVDD/DC
(15,18,20,25,29) ICH_SMBCLK 6 1 22 XTALO
AVDDL 39 +LAN_AVDDL 20mil
Q72A @ 0_0402_5% 44 L74
AVDDL/T1_P LAN_MIDI1+ (25)
2N7002DW-T/R7_SOT363-6 R1075 1 2 16 46 +LAN_AVDDL 1 2 +1.2V_LAN
REG_GND/S_IDDQ AVDDL/T2_P LAN_MIDI2+ (25)
R1074 1 2 @ 51 +LAN_AVDDL 1 1 BLM18AG601SN1D_2P
0_0402_5% +LAN_PCIEVDD AVDDL C998 C999
24 PCIE_GND/VDD E- PAD 69

0.1U_0402_16V4Z
BCM5764MKML_QFN68 2 2
4.7U_0805_10V4Z

20mil L75
LAN_XTALI +LAN_GPHYPLLVDD 1 2 +1.2V_LAN
1 1 BLM18AG601SN1D_2P
XTALO C1000 C1001
1

0.1U_0402_16V4Z
R1076 2 2
200_0402_1% 4.7U_0805_10V4Z

A A
2

Y6
1 2 LAN_XTALO

1 25MHZ_20P 1
Place closed to Pin2 & Pin59
C1002 C1003
27P_0402_50V8J 27P_0402_50V8J
2 2 Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29
SCHEMATIC,MB A5011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 26 of 43
5 4 3 2 1
 A B C D E F G H

+VDDA

Regulator for CODEC R1126 1 2 MBK1608121YZF_0603

1
R1105 Adjustable Output
10K_0402_5% +5VS +5VS_VDDA +VDDA
L87 60mil U58
1 2 4 5 40mil +VDDA

2
FBMA-L11-201209-221LMA30T_0805 VIN VOUT

2
0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 2 2 DELAY SENSE or ADJ 6

1
4.7U_0805_10V4Z
C1042 1U_0402_6.3V4Z R1173

0.1U_0402_16V4Z
7 1 69.8K_0603_1%
ERROR CNOISE

R1172
R1106 C1092
10K_0402_5% C1093 8 3

1
1 SD GND 1

0_0402_5% 2
SI9182DH-AD_MSOP8

2
C1046

1
1 2 MONO_IN SA091820030
1U_0402_6.3V4Z R1174
24K _0402_1% C1094

1
C 1 2 @
C1047 1 R1107 Q73 R1108 1.3K_0402_1% R1175 C1095
(31) BEEP# 2 1 2 2

2
1U_0402_6.3V4Z B 2 1
E (21,29,31,34,40) SUSP#
560_0402_5% 2SC2411K_SOT23

3
@
0_0402_5%

C1048 1 R1109
(18) SB_SPKR 2 1 2
1U_0402_6.3V4Z L78
10mil

1
560_0402_5% +3VS_DVDD 1 2

R1110
D70
CH751H-40PT_SOD323-2
HD Audio Codec 1 1
+3VS
MBK1608121YZF_0603

1
10K_0402_5% C1049 C1050
R1111
2

2
0.1U_0402_16V4Z 0_0603_5% VGA@
2 2
10U_0805_10V4Z

2
+AVDD_HDA L79
10mil +1.5VS_DVDD 1 2 +1.5VS
L80 MBK1608121YZF_0603
1 2 0.1U_0402_16V4Z 40mil 1 1 UMA@
+VDDA
FBMA-L11-160808-800LMT_0603 1 1 C1051 C1052
C1054
C1053 0.1U_0402_16V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2

25

38

9
2 2 U59

DVDD
AVDD1

AVDD2

DVDD_IO
WOOFER_MONO 14 35 AMP_LEFT
(28) WOOFER_MONO LINE2-L FRONT_L AMP_LEFT (28)
15 36 AMP_RIGHT
LINE2-R FRONT_R AMP_RIGHT (28)
16 39 HP_LEFT
MIC2_L SURR_L HP_LEFT (28)
17 41 HP_RIGHT
MIC2_R SURR_R HP_RIGHT (28)
LINE_L 1 2 LINE_C_L 23 45 C1055 1 2 10U_0805_10V4Z
(28) LINE_L LINE1_L SIDE_L
C1056 4.7U_0805_6.3V6K
LINE_R 1 2 LINE_C_R 24 46 R1124 1 2 C1136 1 2
(28) LINE_R LINE1_R SIDE_R SPDIF_MXM (21)
C1058 4.7U_0805_6.3V6K 0_0402_5% VGA@
18 43 For EMI 0.01U_0402_25V7K VGA@
CD_L CENTER
20 CD_R LFE 44 1 2 1 2 C1060
R1116 27_0402_5% 33P_0402_50V8K
19 CD_GND
BITCLK 6 HDA_BITCLK_CODEC (17)
MIC1_L 1 2 MIC1_C_L 21
(28) MIC1_L
MIC1_R
C1061
1 2
4.7U_0805_6.3V6K
MIC1_C_R 22
MIC1_L
8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0 (17)
Digital MIC
(28) MIC1_R MIC1_R SDATA_IN +3VS
C1062 4.7U_0805_6.3V6K R1117 33_0402_5%
MONO_IN 12 37
PCBEEP PIN37_VREFO L88
29 MBK1608121YZF_0603 JP54
LINE1_VREFO R1118 0_0603_5%
(17) HDA_RST#_CODEC 11 RESET# 1 2 1 1
3 DMIC_CLK DMIC_CLK_R 3
LINE2_VREFO 31 2 2
(17) HDA_SYNC_CODEC 10 10mil DMIC_DATA DMIC_DATA_R 3 3 G1 5
SYNC R1119 0_0603_5%
MIC1_VREFO_L 28 MIC1_VREFO_L 4 4 G2 6
(17) HDA_SDOUT_CODEC 5 SDATA_OUT 10mil ACES_88266-04001
MIC1_VREFO_R 32 MIC1_VREFO_R
Place close to Codec DMIC_CLK 2 CONN@
SPDIFO2

2
DMIC_DATA 3 30
R1120 2 GPIO0/DMIC_CLK MIC2_VREFO
(28) HP_PLUG# 1 39.2K_0402_1% SENSE_A 13 SENSE A 10mil D71
34 27 CODEC_VREF SM05T1G_SOT23-3
R1121 1 SENSE B VREF
(28) LINEIN_PLUG# 2 10K_0402_1% 1 1 @
R1122 2 1 20K_0402_1% 1 2 47 40
(28) MIC_PLUG# (31) CODEC_EAPD SPDIFI/EAPD JDREF
R1090 0_0402_5% C1065 C1066 For ESD 10/11

1
1
(28) SPDIF 1 2 SPDIF_R 48 SPDIFO SENSE C 33 0.1U_0402_16V4Z 10U_0805_10V4Z
R1123 0_0402_5% R1125 2 2
10P_0402_25V8K

10P_0402_25V8K

1 1 4 26 20K_0402_1%
GPIO1/DMIC_DATA AVSS1
7 DVSS AVSS2 42
C1133 C1132

2
IC ALC889X-GR_LQFP48_7x7
Sense Pin Impedance Codec Signals 2 2
1
R1127
2
0_0805_5%

39.2K PORT-A (PIN 39, 41) DGND AGND 1

R1128
2
0_0805_5%
@ @
20K PORT-B (PIN 21, 22) 1
R1130
2
0_0805_5%
SENSE A
10K PORT-C (PIN 23, 24)
1 2
R1132 0_0805_5%
5.1K PORT-D (PIN 35, 36)
4
GND GNDA 4
39.2K PORT-E (PIN 14, 15)

20K PORT-F (PIN 16, 17)

SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 27 of 43
A B C D E F G H
 A B C D E

+5VS_VDDA Int. Speaker Conn. SPK_L- 2

D74

L39 1
1 2 20mil SPK_L+ 3
W=40mil FBMA-L11-201209-221LMA30T_0805 JP55
+3VS SPKL+ R1138 1 2 0_0603_5% SPK_L+ 1 PJDLC05_SOT23-3
SPKL- R1139 1 0_0603_5% SPK_L- 1
2 2 2 @

10U_0805_10V4Z
0.1U_0402_16V4Z

1U_0402_6.3V4Z
1 1 2 1 SPKR+ R1140 1 2 0_0603_5% SPK_R+ 3 5
C1068 C1069 C1096 SPKR- R1144 1 0_0603_5% SPK_R- 3 G1 D75
2 4 4 G2 6
C1067 SPK_R+ 2
C1070 0.1U_0402_16V4Z ACES_88266-04001 1
0.47U_0603_16V4Z 2 2 1 2 CONN@ SPK_R- 3
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C
(27) AMP_RIGHT C1071 1U_0402_6.3V4Z PJDLC05_SOT23-3

15

17

25
8

7
1 AMP_LEFT_C-1 AMP_LEFT_C U60 1
(27) AMP_LEFT 1 2 1 2 @
C1072 C1073 1U_0402_6.3V4Z

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z
R1141 R1142
+5VS_VDDA
2.2K_0402_5% 2.2K_0402_5% 27 19 SPKR+
R1143 INR_A ROUT+ SPKR- +5VS_VDDA
1 18

2
100K_0402_5% INL_A ROUT- HP_PLUG#
HPF Fc = 154Hz HP_PLUG# (27)

2
1 2 24 5 SPKL+
/AMP EN LOUT+

3
6 SPKL- R1149
R1145 1 LOUT-
+5VS_VDDA 2 21 HP_EN 100K_0402_5%

2
+5VS_VDDA 100K_0402_5% 13 HPOUT_R Q67B
HP_RIGHT 1 HP_RIGHT_C 1 HP_RIGHT_R HP_R HPOUT_L R1150 2N7002DW-T/R7_SOT363-6
2 2 28 16 5

6 1
(27) HP_RIGHT C1074 4.7U_0805_6.3V6K R1146 39K_0402_5% HP_LEFT_R INR_H HP_L Q75
2 INL_H 100K_0402_5%
1

HP_LEFT 1 2 HP_LEFT_C 1 2 3 AO3413_SOT23-3

4
R1148 (27) HP_LEFT C1075 4.7U_0805_6.3V6K R1147 39K_0402_5% VOL_AMP NC
23 14

1
SET NC

3
S
43K_0402_1% G Q67A
2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6
12
2

VSS
1 9 1
D

1
VOL_AMP CP+ C1077
11 CP- GND 26
C1076 4 1U_0603_10V4Z +5VSPDIF
PGND
1

D
1U_0603_10V4Z 22 BIAS PGND 20
1

2 2
1 2 EC_MUTE EC_MUTE (31) CGND 10 20mil
R1151 G 1 29
100K_0402_1% C1078 S Q74 C1079 GND
S/PDIF Out JACK
3

2N7002_SOT23 APA2051QBI-TRG_TQFN28_4X4
2
0.01U_0402_16V7K 2.2U_0805_10V6K
LINE Out/Headphone Out
2

PJDLC05_SOT23~D
2 @ 2
2
Gain= 10dB 2 2 C1097 D60 1
C1080 C1081 1 2 3

330P_0402_50V7K 330P_0402_50V7K 0.1U_0402_16V4Z

R1152 1 1 JHP1
+5VS 82_0603_1% 1
C1098 HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 2
10U_0805_10V4Z Gain = 5.1dB(BTL Mode) L82 FBMA-L11-160808-700LMT_2P
1 2 HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 3
L81 FBMA-L11-160808-700LMT_2P
C1099 Fc(low)= 2KHz R1153 4
0.1U_0603_25V7K +5VS 82_0603_1%
1 2 R1177 1.8K_0402_5% SPDIF_PLUG# 5
1 2 EC_MUTE (31)

1
SPDIF 8
(27) SPDIF
C1100 0.01U_0603_50V7K R1178 +5VSPDIF 7 DRIVE IC
1 2 100K_0402_5% 6
Fc(high)= 482Hz

2
Q76

G
1
U44 C1082 9
Subwoofer Conn.
2
R1180 6 1 1 3 100P_0402_50V8J 10
1K_0402_1% R1179 VDD SHUTDOWN#

S
WOOFER_IN- 4 2N7002_SOT23 JP56 2
(27) WOOFER_MONO 1 2 1 2 1 2 IN- Vo+ 5
4.7K_0402_1% WOOFER+ 1 SINGA_2SJ-D373-B01
C1101 WOOFER_IN+ 3 WOOFER- 1
8 2
0.33U_0603_16V4Z
1
C1102 2
IN+ Vo-
7 30mil
2
LINE-IN JACK
0.068U_0603_16V7K BYPASS GND
3 G1
2 SINGA_2SJ-B351-S02
4 G2 LINEIN_PLUG# 5
(27) LINEIN_PLUG#
1 APA3011XA-TRL_MSOP8 ACES_88266-02001
4
3 C1103 3
2.2U_0603_6.3V4Z 3
2 R1161 L83 6
1K_0603_5% FBMA-L11-160808-700LMT_2P 2
1 2 LINE_R_1 1 2 LINE_R_R 1
(27) LINE_R
1 2 LINE_L_1 1 2 LINE_L_R 7
(27) LINE_L
1K_0603_5% FBMA-L11-160808-700LMT_2P
R1162 L84 1 1 8

Volume Control Circuit +3VS

C1083
220P_0402_50V7K
C1084
220P_0402_50V7K
JLINE1

+3VS 2 2 (HDA Jack)

For ESD
1

C1085
2 1 R1163 I/O status:
+3VS
MIC JACK
1

100K_0402_5% a. input/output mount 75 ohm (27) MIC_PLUG#

R1164 R1165 0.1U_0402_16V4Z b. input only mount 1K ohm
10K_0402_5% 10K_0402_5% SINGA_2SJ-B351-S01
2

+3VS MIC1_VREFO_L MIC1_VREFO_R 5

5

U62 1
2

JP33 C1086 4
P

NC

1
1 VR_A 1 2 2 4 0.1U_0402_16V4Z
1 R1166 10K_0402_5% A Y R1169 R1167
2 2 3
G

2 2.2K_0402_5% 2.2K_0402_5%
3 3 6
4 NC7SZ14P5X_NL_SC70-5 U63 R1170 L85 2
3

4 1K_0603_5% FBMA-L11-160808-700LMT_2P
5 1 14 1

2
G1 VR_B CD1# VCC
G2 6 1 2 2 D1 CD2# 13 (27) MIC1_R 1 2 MIC1_R_1 1 2 MIC1_R_R
R1168 10K_0402_5% 3 12 7
ACES_85201-0405N CP1 D2
4 SD1# CP2 11 (27) MIC1_L 1 2 MIC1_L_1 1 2 MIC1_L_R
1 1 5 10 1K_0603_5% FBMA-L11-160808-700LMT_2P 8
Q1 SD2#
0.01U_0402_16V7K

0.01U_0402_16V7K

C1087 C1088 6 09 1 R1171 L86 1 1

4 Q1# Q2 JMIC1 4
7 GND Q2# 08
C1089 C1090 C1091
2 2 TC74LCX74FT_TSSOP14 220P_0402_50V7K 220P_0402_50V7K
0.1U_0402_16V4Z
2 2 2
(HDA Jack)
ENCODER_DIR (31)
ENCODER_PULSE (31) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 28 of 43
A B C D E
 5 4 3 2 1

New Card Power Switch

New Card Socket (Left/TOP)
+3VALW_CARD +3VS_CARD +1.5VS_CARD
Imax = 0.275A Imax = 1.35A Imax = 0.75A JEXP1
+3VS +1.5VS
1 GND
1 1 1 1 1 1 (18) USB20_N5 2 USB_D-
D C435 C439 C369 C370 C436 C437 D
1 1 (18) USB20_P5 3 USB_D+
C375 C374 CP_USB# 4
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CPUSB#
5 RSV
10U_0805_10V4Z 10U_0805_10V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 6 RSV
2 2 U24 40mil (15,18,20,25,26) ICH_SMBCLK 7 SMB_CLK
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD (15,18,20,25,26) ICH_SMBDATA 8 SMB_DATA
14 1.5Vin 1.5Vout 13 +1.5VS_CARD 9 +1.5V
10 +1.5V
60mils (18,20,26) ICH_PCIE_WAKE# 11 WAKE#
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD +3VALW_CARD 12 +3.3VAUX
4 5 PERST1# 13
3.3Vin 3.3Vout PERST#
40mil +3VS
+3VS_CARD 14 +3.3V
+3VALW 17 AUX_IN AUX_OUT 15 +3VALW_CARD 15 +3.3V
R989 0_0402_5% CLKREQ1# 16
PCI_RST# CP_PE# 1 CLKREQ#
(16,31) PCI_RST# 6 SYSRST# OC# 19 (18) CP_PE# 2CP_PE#_R 17 CPPE#
+3VS 1 18
(15) CLK_PCIE_CARD# REFCLK-
SYSON 20 8 PERST1# C438 19
(30,31,34,39) SYSON SHDN# PERST# (15) CLK_PCIE_CARD REFCLK+
20 GND

1
SUSP# 1 16 0.1U_0402_16V4Z 21
(21,27,31,34,40) SUSP# STBY# NC 2 (18) PCIE_RXN1 PERn0
R339 22
(18) PCIE_RXP1 PERp0

5
CP_PE# 10 7 10K_0402_5% U15 23
(Internal Pull High to AUXIN) CPPE# GND CLKREQ1# GND
2 24

G Vcc
B (18) PCIE_TXN1 PETn0
CP_USB# 9 4 (18) PCIE_TXP1 25
EXP_CLKREQ# (15)

2
(Internal Pull High to AUXIN) CPUSB# Y PETp0
1 A 26 GND GND3 29
RCLKEN1 18 30
RCLKEN GND4

1
D NC7SZ32P5X_NL_SC70-5 27

3
R5538D001-TR-F_QFN20_4X4 RCLKEN1 2 Q15 GND1
28 GND2
G 2N7002_SOT23
S SANTA_131851-A_LT

3
C C

+USB_VCCB
ON board 80mil
1
C1104
1
+ C701
USB PORT Conn
150U_B_6.3VM_R40M
0.1U_0402_16V4Z
2 2 +5VALW
+USB_VCCA
JUSB2
80mil U26 JP48
60mil
1 VCC 1 GND OUT 8 1 1
USB20_N0 2 C568 0.1U_0402_16V4Z 2 7 2
(18) USB20_N0 USB20_P0 D- IN OUT USB20_N1 2
(18) USB20_P0 3 D+ 2 1 3 IN OUT 6 (18) USB20_N1 3 3
4 4 5 USB20_P1 4
GND EN# FLG (18) USB20_P1 4
3

R172 5 7
TPS2061DRG4_SO8 100K_0402_5% 5 G1
5 GND1 6 6 G2 8
+3VALW @D17
@ D17 6 1 2
GND2 +3VALW
PJDLC05_SOT23~D 7 SYSON# ACES_87213-0600G
+USB_VCCB GND3 (20,34,40) SYSON#
8 GND4 USB_OC#1 (18)
+5VALW
80mil
1
1

SUYIN_020173MR004G565ZR
U37 R206
1 8 100K_0402_5%
B C569 GND VOUT B
2 VIN VOUT 7
1 2 3 6 R209
2

VIN VOUT
4 EN FLG 5 1 2 USB_OC#0 (18)
10K_0402_5%
4.7U_0805_10V4Z RT9715BGS_SO8 R1188
1 2 USB_OC#6 (18)
SYSON# 1 0_0402_5%

C1108 0.1U_0402_16V4Z
2

+USB_VCCB

HS PORT 80mil
1
1
C1106 + C1107
150U_B_6.3VM_R40M
0.1U_0402_16V4Z
2 2

JUSB3
1 VCC
USB20_N6 2
(18) USB20_N6 USB20_P6 D-
(18) USB20_P6 3 D+
4 GND
3

5 GND1
@ D18 6
A PJDLC05_SOT23~D GND2 A
7 GND3
8 GND4
1

SUYIN_020173MR004G565ZR

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 29 of 43
5 4 3 2 1
 5 4 3 2 1

H1 H2 H3 H4 H5 H6 H7 H8
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

BIOS @ @ @ @ @ @ @ @

1
+3VALW FD1 FD2 FD3 FD4

C551 1 2 0.1U_0402_16V4Z
@ @ @ @ H9 H10 H12 H11

1
H_3P7 H_3P7 H_3P7 H_3P7
R444 @ C1134 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
10_0402_5% 10P_0402_25V8K @
(31) FSEL# U35
1 2 1 2 @ @ @ @

1
+3VALW 4.7K_0402_5% 1 8
R935 1 SPI_WP# CE# VDD R443 1
2 3 WP# SCK 6 2 0_0402_5% SPI_CLK (31)
D R936 1 SPI_HOLD# 7 R445 1 D
2 HOLD# SI 5 2 0_0402_5% FWR# (31)
4.7K_0402_5% 4 2 R442 1 2 0_0402_5% H13 H14 H15
VSS SO FRD# (31)
H_6P6 H_2P8 H_2P6N
MX25L8005M2C-15G_SOP8

@ @ @

1
H16 H24
H17 H18 H23 H_3P1X2P6N H_3P1X2P6N
H_3P2 H_3P2 H_3P2

@ @

1
@ @ @

1
H19 H20 H21 H22
H_4P2 H_4P2 H_4P2 H_4P2

+3VS @ @ @ @

1
+3VALW +3VALW
1

U45A U45B H25

R917 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 H_7P6
14

14
180K_0402_5%
D56 @
P

P
2

C SYS_PWROK @ C
(31,41) VR_ON 1 2 1 2 3 4 1 2 PM_PWROK (18,31)

1
I O I O R918 @ 0_0402_5%
G

G
CH751H-40PT_SOD323-2 2
@
7

7
C855
1U_0402_6.3V4Z
1
@

+3VALW
+3VALW +3VALW
1

R919
22K_0402_5% U45C U45D
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
P

P
2

5 I O 6 9 I O 8 1 2 VS_ON (39)
2 R920
1

D C856 0_0402_5%
SUSP 2
(34) SUSP
7

G
Q57 S 1
3

2N7002_SOT23
0.1U_0402_16V4Z

B B

+1.5V

+3VALW
2

0.1U_0402_16V4Z
+3VALW 2 R1104
C1039 U45E 10K_0402_5%
1

SN74LVC14APWLE_TSSOP14
R1399
1

47K_0402_5% 1 2N7002W-T/R7_SOT323-3
14

Q41
D69
2

CH751H-40PT_SOD323-2 D
P

SYSON 1 2 11 10 2
(29,31,34,39) SYSON I O DDR3_SM_PWROK (7,39)
1 G
G

S
3

0.1U_0603_25V7K C1040
7

+3VALW

A U45F A
14

SN74LVC14APWLE_TSSOP14
P

13 I O 12
7 G

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 30 of 43
5 4 3 2 1
 +3VALW_EC +3VALW_EC

0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K

1
1 1 1 1 1 Ra
C446 C447 C448 C449 C450 +3VALW +3VALW_EC +EC_AVCC R450
100K_0402_5%
2 2 2 2 2 R451

2
0.1U_0402_16V4Z 1000P_0402_50V7K 1 2 M/B_ID
0_0805_5%
Rb

1
1
C451 R452

111
125
+3VALW +3VS 0_0402_5%

22
33
96

67
9
U18 0.1U_0402_16V4Z
SMB_EC_DA1 R453 4.7K_0402_5% 2
1 2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
SMB_EC_CK1 R454 1 2 4.7K_0402_5%
SMB_EC_DA2 R455 1 2 4.7K_0402_5% VCC 3.3V+/-5%
SMB_EC_CK2 R456 1 2 4.7K_0402_5%
GATEA20 1 21 INV_PWM Ra 100K+/-5%
(17) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM (22,23)
KB_RST# 2 23 BEEP#
(17) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (27)
SIRQ 3 26 ENCODER_PULSE Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
(18) SIRQ SERIRQ# FANPWM1/GPIO12 ENCODER_PULSE (28)
LPC_FRAME# 4 27 ACOFF
(17) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (37)
C452 R457 (17) LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K 0 0 0V 0V 0.155V
LPC_AD2 LAD3 C453 ECAGND
1 2 1 2 (17) LPC_AD2 7 LAD2 PWM Output 1 2
33_0402_5%@ (17) LPC_AD1 LPC_AD1 8 63 BATT_TEMP 1 8.2K+/-5% 0.168V 0.250V 0.362V
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (36)
15P_0402_50V8J@ LPC_AD0 BATT_OVP
(17) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP (37)
ADP_I/AD2/GPIO3A 65 ADP_I (37) * 2 18K+/-5% 0.375V 0.503V 0.621V
CLK_PCI_EC 12 AD Input 66 M/B_ID
(15) CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75 3 33K+/-5% 0.634V 0.819V 0.945V
(16,29) PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 PWR_SAVING# (32)
+3VALW R458 1 2 ECRST# 37 76
ECRST# SELIO2#/AD5/GPIO43 PGD_IN (41)
1 2 47K_0402_5% EC_SCI# 20 2 1 4 56K+/-5% 0.958V 1.185V 1.359V
0.1U_0402_16V4Z (18) EC_SCI# SCI#/GPIO0E R474 MINI1_LED# (20)
38 CLKRUN#/GPIO1D
C454 1 2 PM_CLKRUN#_R 68 0_0402_5% 5 100K+/-5% 1.372V 1.650V 1.838V
(18) PM_CLKRUN# DAC_BRIG/DA0/GPIO3C KB_BL_LED1# (32)
R943 0_0402_5% 70 EN_FAN1
+3VALW EN_DFAN1/DA1/GPIO3D EN_FAN1 (4)
DA Output 71 IREF 6 200K+/-5% 1.851V 2.200V 2.420V
IREF/DA2/GPIO3E IREF (37)
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F Calibrate# (37)
KSI1 56 7 NC 2.433V 3.300V 3.300V
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE (28)
R585 2 1 47K_0402_5% KSO1 KSI4 59 84 HPD_7318_EC
KSI4/GPIO34 PSDAT1/GPIO4B HPD_7318_EC (21)
KSI5 60 85 +5VS
KSI5/GPIO35 PSCLK2/GPIO4C PWR_SAVE_LED# (32)
R586 2 1 47K_0402_5% KSO2 KSI6 61 PS2 Interface 86 T/P_LOCK_LED#
KSI6/GPIO36 PSDAT2/GPIO4D T/P_LOCK_LED# (33)
KSI7 62 87 TP_CLK TP_CLK R462 1 2 4.7K_0402_5%
R1435 2 @ KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (32)
1 4.7K_0402_5% EC_ESB_CK KSO0 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA (32)
KSO1 40 TP_DATA R463 1 2 4.7K_0402_5%
R1436 2 @ KSO1/GPIO21
1 4.7K_0402_5% EC_ESB_DA KSO2 41 KSO2/GPIO22
+3VALW KSO3 3S/4S#
42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# (37) select SPI ROM or LPC ROM
KSO4 43 98 65W90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W90W# (37)
KSO5 99 R475 2 1 0_0402_5% R213
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 LID_SW#
EC_ESB__RST# (33)
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# (33) +5VALW 1 2
5

KSO7 46 SPI Device Interface 10K_0402_5%

KSO8 KSO7/GPIO27 D13
47 KSO8/GPIO28
3 4 SMB_EC_DA1 KSO9 48 119 FRD# EC_RCIRRX 2 1
(33) EC_I2C_DA KSO9/GPIO29 SPIDI/RD# FRD# (30) RCIRRX (20)
KSO10 49 120 FWR#
KSO10/GPIO2A SPIDO/WR# FWR# (30)
Q80B KSO11 50 SPI Flash ROM 126 SPI_CLK CH751H-40PT_SOD323-2
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK (30)
2

2N7002DW-T/R7_SOT363-6 KSO12 51 128 FSEL#

KSO12/GPIO2C SPICS# FSEL# (30)
KSO13 52
SMB_EC_CK1 KSO14 KSO13/GPIO2D
(33) EC_I2C_CK 6 1 53 KSO14/GPIO2E
KSO15 54 73 EC_RCIRRX
2N7002DW-T/R7_SOT363-6 Q80A KSO16 KSO15/GPIO2F CIR_RX/GPIO40 C861 100P_0402_50V8J
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 EC_I2C_INT (32)
KSO17 82 89 BATT_OVP 2 1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG (37)
90 C862 100P_0402_50V8J
BATT_CHGI_LED#/GPIO52 BATT_BLUE_LED# (33)
91 CAPS_LED# ACIN 2 1
SMB_EC_CK1 CAPS_LED#/GPIO53 CAPS_LED# (33)
(21,36) SMB_EC_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# (33)
SMB_EC_DA1 78 93
(21,36) SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED (33)
SMB_EC_CK2 79 SM Bus 95 SYSON
(4) SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON (29,30,34,39)
SMB_EC_DA2 80 121 VR_ON
(4) SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (30,41)
127 ACIN
AC_IN/GPIO59 ACIN (18,21,33,35)
R469
2 1
10K_0402_5%
For EMI
SLP_S3# 6 100 EC_RSMRST# CP1
(18) SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# (18)
SLP_S5# 14 101 KSO0 1 8
(18) SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (18)
EC_SMI# 15 102 EC_ON KSO1 2 7
(18) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (32)
R1079 1 2 0_0402_5%16 103 KSO2 3 6
(21) TH_OVERT# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# (18)
EC_ESB_CK 17 104 PM_PWROK CP7 KSO3 4 5
(33) EC_ESB_CK SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PWROK (18,30)
EC_ESB_DA 18 GPO 105 BKOFF# 1 8
(33) EC_ESB_DA PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# (23)
19 GPIO 106 WL_OFF# 2 7 100P_1206_8P4C_50V8
(21) HPD_7318_R_EC EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# (20)
25 107 KSO17 3 6 CP2
(7) MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10 EC_CYP__RST# (33)
28 108 ENCODER_DIR KSO16 4 5 KSI0 1 8
(4) FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 ENCODER_DIR (28)
+3VS BT_ON# 29 KSI1 2 7
(32) BT_ON# FANFB2/GPIO15
UTX 30 100P_1206_8P4C_50V8 KSI2 3 6
+3VALW (20) UTX URX EC_TX/GPIO16 SLP_S4# KSI3
(20) URX 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# (18) 4 5
1 2 ENCODER_PULSE ON/OFF 32 112 ENABLT
10K_0402_5% R470
(32) ON/OFF
(33) PWR_SUSP_LED
PWR_SUSP_LED34 ON_OFF/GPIO18
PWR_LED#/GPIO19
ENBKL/GPXID2
GPXID3 114
ENABLT (22)
CODEC_EAPD (27)
2007/12/07 100P_1206_8P4C_50V8
1 2 PGD_IN NUM_LED# 36 GPI 115 THERM_SCI#
(33) NUM_LED# NUMLED#/GPIO1A GPXID4 THERM_SCI# (18)
10K_0402_5% R471 116 SUSP# (Left) JKB1 CP3
GPXID5 SUSP# (21,27,29,34,40)
C455 117 PWRBTN_OUT# KSO4 1 8
GPXID6 PWRBTN_OUT# (18)
100K_0402_5% 2 1 R459 3S/4S# 15P_0402_50V8J 118 EC_PME# 2 1 KSO0 26 28 KSO5 2 7
CRY2 GPXID7 R473 EC_LAN_PME# (26) (33) KSO0 KSO1 KSO0 G2 KSO6
1 2 122 XCLK1 25 KSO1 G1 27 3 6
100K_0402_5% 2 1 R460 65W90W# 123 XCLK0 V18R 124 0_0402_5% KSO2 24 KSO2
KSO7 4 5
1 KSO3 23
Y5 KSO3
1

AGND

KSO4 22 100P_1206_8P4C_50V8
GND
GND
GND
GND
GND

@ C478 KSO5 KSO4 CP4

2 NC IN 1 21 KSO5
R476 4.7U_0805_6.3V6K KSO6 20 KSI4 1 8
20M_0402_5% KB926QFB0_LQFP128_14X14 2 KSO7 KSO6 KSI5
3 4 19 2 7
11
24
35
94
113

69

NC OUT SA00001J540 KSO8 KSO7 KSI6

18 3 6
2

KSO8

TOP VIEW
32.768KHZ_12.5P_MC-306 KSO9 17 KSI7 4 5
KSO10 KSO9
16 KSO10
1 2 CRY1 For KB926 C0 reversion KSO11 15 100P_1206_8P4C_50V8
+3VALW_EC KSO12 KSO11
14 KSO12
C456 KSO13 13 CP5
EC DEBUG port
ECAGND

15P_0402_50V8J KSO14 KSO13 KSO8

12 KSO14 1 8
1

KSO15 11 KSO9 2 7
JP26 +EC_AVCC R1183 KSO16 KSO15 KSO10
10 KSO16 3 6
1 0_0603_5% KSO17 9 KSO11 4 5
1 +3VALW KSO17
2 UTX KSI0 8
2 URX R1184 KSI1 KSI0 100P_1206_8P4C_50V8
3 7
2

3 KSI2 KSI1 CP6

4 4 1 2 1 2 (33) KSI2 6 KSI2
C457 0.1U_0402_16V4Z 0_0603_5% KSI3 5 KSO12 1 8
ACES_85205-0400 KSI4 KSI3 KSO13
4 KSI4 2 7
CONN@ KSI5 3 KSO14 3 6
KSI6 KSI5 KSO15
2 KSI6 4 5
KSI7 1 KSI7 100P_1206_8P4C_50V8
(Right)
ACES_88747-2601

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 31 of 43
 A B C D E

Power Button Logic TOP Side

+3VALW
BT
1 2 +BT_VCC
R578 @ 10K_0603_5%

2
JP37
1 2 R580 1 9
(18) USB20_P8 1 GND
R579 @ 10K_0603_5% 2
(18) USB20_N8 2
100K_0402_5% 3 3
ON/OFF switch Bottom Side 0_0402_5% 4

1
D44 R996 1 WLAN_BT_DATA_R 4
2 @ 5 5
2 +3VS 1 2 @ WLAN_BT_CLK_R 6
ON/OFF (31) 6
ON/OFFBTN# 1 R997 0_0402_5% 7
1 (33) ON/OFFBTN# 7 1
3 51ON# (35) 8 8 GND 10

DAN202UT106_SC70-3 1 ACES_87213-0800G
C698 C699 CONN@
0.1U_0402_16V4Z
1U_0603_10V4Z

3
2
S

1
G
2 1 2 2 Q33
(31) BT_ON#
C704 D45 R575 10K_0402_5% AO3413_SOT23 USB20_P8
D USB20_N8

1
1000P_0402_50V7K RLZ20A_LL34
1
W=40mils

2
+BT_VCC

1
D D62
1

1
EC_ON 2 Q36 C702 C703 PJDLC05_SOT23~D
(31) EC_ON
G R576

2
S 2N7002_SOT23 4.7U_0805_10V4Z 300_0603_5%

1
R581 2 0.1U_0402_16V4Z

2
10K_0402_5%

1
D
2 Q34
G 2N7002_SOT23
S

3
Finger Print /TP Left & Right Conn +5V_FP

2 2
R1005 1 2 0_0603_5% +5V_FP
+5VS
R1006 1 2 0_0603_5% @
+5VALW
1 1
KB back light Conn
C700 C462
USB20_N9 +5VS
USB20_P9 1U_0603_10V4Z 0.1U_0402_16V4Z
2 2 JP44

1
1 1
3

USB20_N9 R1014
D26
EMI (18) USB20_N9
USB20_P9
2
3
2 0_0805_5%
(18) USB20_P9 3
PSOT24C-LF-T7_SOT23-3 4 4
BTN_L 5 JP34

2
BTN_R 5 R1009 1
6 6 1 1 2 300_0402_5%
7 2 R1011 1 2 300_0402_5%
1

7 2 2N7002_SOT23
8 8 3 3

S
9 GND 4 4 1 3
@ 10 5
GND G1 R1012 1 Q39
G2 6 2 300_0402_5%
ACES_85201-08051 R1013 1 2 300_0402_5%

G
2
ACES_88514-0441 KB_BL_LED1# (31)

+5VS TP_DATA
T/P Board Conn TP_CLK
3

1 @ D25
C459 PSOT24C-LF-T7_SOT23-3
3 JP47 0.1U_0402_16V4Z @ 3
2
1
1

1
2 2
3 3 TP_DATA (31)
4 4 TP_CLK (31)
5 BTN_R
5 BTN_L
6 6
7 BTN_R
7
8 8 1 1
3

9 @ @ +MCVCC
9 C460 C461 D27 51ON#
10 10

1
13 11 100P_0402_50V8J 100P_0402_50V8J PSOT24C-LF-T7_SOT23-3
G13 11 BTN_L 2 2 R1836
14 G14 12 12
@ 510K_0402_5%
ACES_87151-1207G
1

1
CONN@ +MCVCC D

2
2 Q124

2
G
R1838 S 2N7002_SOT23

3
10K_0402_5%

ACER LOGO BacKLight Conn

1
D
POWER SAVING Conn +5VS
(33) CY_I2C_INT 2
G
Q138
+3VALW
defult=H S 2N7002_SOT23

2
1

+3VALW R1837 10K_0402_5%

+5VALW L55 FBM-L11-160808-601LMT 0603

D72
For EMI solution 02/23

1
2

1 2 EC_I2C_INT (31)
4 R159 JP39 4
2

1 1 1SS355_SOD323-2
10K_0402_5% 2 2
3

2
0.1U_0402_16V4Z

JP38 1
1

6 GND 4 4
5 3 C463 3
GND 3 PWR_SAVING# (31) G1
2 2 R999 1 2 PWR_SAVE_LED# (31)
D19 4 G2
0_0402_5% 2
1
1 PJDLC05_SOT23~D ACES_88266-02001 Security Classification Compal Secret Data Compal Electronics, Inc.
1

ACES_87213-0400G 2007/09/29 2007/09/29 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 32 of 43
A B C D E
 5 4 3 2 1

SW1

1 3 CAP Sansor left(ENE) CAP Sansor right(Cypress)

Power Button/LED 2 4 ON/OFFBTN#
ON/OFFBTN# (32)
+5VS
+3VS
+MCVCC

JP2

6
5
SMT1-05_4P 1 1
2 2

1
3 3
EC_ESB_CK 1 R1437 2 0_0402_5% 4 R591 R596 +5VS
(31) EC_ESB_CK 4
EC_ESB_DA 1 2 0_0402_5% 5 JP6
(31) EC_ESB_DA 5
EC_ESB__RST# R1438 6 10K_0402_5% 10K_0402_5% 1
(31) EC_ESB__RST# 6 1
1 1 7 2

2
D C1128 C1129 7 2 D
8 8 3 3
300_0402_5% R587 LED3 9 EC_I2C_CK 4
GND (31) EC_I2C_CK 4

12P_0402_50V8J
+5VALW 2 1 2 1 ACIN_LED# 12P_0402_50V8J 10 EC_I2C_DA 5
2 2 GND (31) EC_I2C_DA 5
CY_I2C_INT 6
(32) CY_I2C_INT 6
S LED HT-150NB 1206 BLUE 2N7002_SOT23 ACES_85201-08051 EC_CYP__RST# 7
(31) EC_CYP__RST# 7

1
D
8 8
Q59 2 9
ACIN (18,21,31,35) GND
G 10
300_0402_5% R589 LED7 GND
S

3
2 1 2 1 ACES_85201-08051

S LED HT-150NB 1206 BLUE

LED5 CAP Sansor B COVER(ENE) +MCVCC

300_0402_5% R590 +3VLP
2 1 2 1 +3VS

99-113-BHC-AS1T1U-3T_BLUE JP7
+5VALW FBM-11-100505-301T 0402 1
EC_ESB_CK 1 R1433 2 2
1
2
R1439 20MIL
EC_ESB_DA 1 2 3 1 2
EC_ESB__RST# R1434 3 0_0603_5%
4 4 1
FBM-11-100505-301T
1 1 0402 5
C1127 5 C1135
6 GND1

33P_0402_50V8K
C1126 7 0.1U_0402_25V4K
33P_0402_50V8K GND2 2
LED12 R592 300_0402_5% 2 2 ACES_88266-05001
1 2 1 2

S LED HT-150NB 1206 BLUE

LED13 R593 300_0402_5%
C C
1 2 1 2
1

Q60 D
2 S LED HT-150NB 1206 BLUE
(31) PWR_LED
G LED14 R594 300_0402_5%
2N7002_SOT23 S 1 2 1 2
3

S LED HT-150NB 1206 BLUE

LED15 R595 300_0402_5%
1 2 1 2

S LED HT-150NB 1206 BLUE

T/P Lock Button/LED
+5VS

LED16
(31) T/P_LOCK_LED# R584 1 2 150_0402_1% 1 2
+3VS +5VS HT-191UY_Amber_0603
SW2
5

U38 1 3
LED11
2 B DATA ACCESS_LED#
P

(17) SATA_LED#
4 DATA ACCESS_LED# 1 2 1 2 (31) KSO0 2 4 KSI2 (31)
Y
(20) 5IN1_LED# 1 A
G

R582 300_0402_5%

6
5
NC7SZ08P5X_NL_SC70-5 HT-191NB_BLUE_0603 SMT1-05_4P
3

LED10
NUM_LED# 1 2 1 2
Num Lock
(31) NUM_LED#
B R583 300_0402_5% B
HT-191NB_BLUE_0603

LED9
CAPS_LED# 1 2 1 2
Cap Lock
(31) CAPS_LED#
R588 300_0402_5%
HT-191NB_BLUE_0603

(Hall Effect Switch)

PWR_LED# PWR_SUSP_LED#
+3VALW +3VALW
1

Q42 Q43
DTC114EKA_SC59-3 DTC114EKA_SC59-3

1
10K 10K
(31) PWR_LED 2 (31) PWR_SUSP_LED 2 R940

1
2 2 100K_0402_5%
10K 10K R941
47K_0402_5%
VDD

2
3

C865 1 D58

2
3 1 2 LID_SW#
OUTPUT LID_SW# (31)
0.1U_0402_16V4Z
CH751H-40PT_SOD323-2
GND

LED1 1
150_0402_1% R446 C866
+5VS 1 2 2 1 PWR_LED# U52
1

B
A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
150_0402_1% R447 2
+3VALW 1 2 4 A 3 PWR_SUSP_LED#
A A

HT-297UD/CB _BLUE/AMB_0603

LED6
150_0402_1% R464
1 2 2 1 BATT_BLUE_LED#
+5VALW
150_0402_1% R461
B BATT_BLUE_LED# (31) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
1 2 4 3 BATT_AMB_LED#
+3VALW A BATT_AMB_LED# (31)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HT-297UD/CB _BLUE/AMB_0603 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 33 of 43

5 4 3 2 1
 5 4 3 2 1

U31
+3VALW to +3VS Transfer UMA@
+5VALW to +5VS Transfer +3VALW to +3VMXM Transfer
+3VALW SB548000310 +3VALW
+3VS R1419 @ 40mil(1A)
+5VALW +5VS U21 0.1U_0402_16V4Z SI4800DY_SO8 0_0805_5% +3VMXM
8 D S 1 1 2
U20 0.1U_0402_16V4Z 1 7 2 U31 0.1U_0402_16V4Z
+VSB C637 D S
8 D S 1 6 D S 3 1 1 8 D S 1
C644 7 2 10U_0805_10V4Z 5 4 C648 C649 7
+VSB 10U_0805_10V4Z
1 D S D G +VSB C705
1 D S 2
6 D S 3 1 1 6 D S 3 1 1

1
2 SI4800DY_SO8 10U_0805_10V4Z 10U_0805_10V4Z C706 C707
5 D G 4 5 D G 4
C645 C646 R548 2 2
1

1
2 SI4800DY_SO8 10U_0805_10V4Z 330K_0402_5% 2 AO4430_SO8 10U_0805_10V4Z
D
R546 2 2 R556 VGA@ 2 2 D

200K_0402_5% 330K_0402_5%

2
+3VS_GATE R549 1 2 RUNON
@ 0_0402_5%
2

2
RUNON 1 +3VMXM_GATE

1
D C650
1 SUSP 2 Q28 0.1U_0603_25V7K 1
1

1
D C647 G D C679
SUSP Q27 0.1U_0603_25V7K 2N7002_SOT23 2 DGPU_PWR_EN# Q32 0.1U_0603_25V7K
2 S 2

3
G G
2N7002_SOT23 2 2N7002_SOT23 2
S S
3

3
VGA@

U32
UMA@ +5VALW to +5VMXM Transfer
SB548000310 +5VALW R1423 @ 100mil(2.5A)
0_0805_5% +5VMXM
+1.5V to +1.5VS Transfer SI4800DY_SO8 1 2
U32 0.1U_0402_16V4Z
+1.5V 8
+1.5VS D S 1
1 7 D S 2
U22 0.1U_0402_16V4Z +VSB C710 6
10U_0805_10V4Z D S 3 1
C709
1
C711
8 D S 1 5 D G 4
1 7 D S 2

1
+VSB C932 2 AO4430_SO8 10U_0805_10V4Z
6 D S 3 1 1
10U_0805_10V4Z C933 C934 R557 VGA@ 2 2
5 D G 4
330K_0402_5%
1

C
2 SI4800DY_SO8 10U_0805_10V4Z C
R984 2 2

2
510K_0402_5% +5VMXM_GATE

1
2

1
+1.5VS_GATE D C708
DGPU_PWR_EN# 2 Q37 0.1U_0603_25V7K
1 G
2N7002_SOT23
1

D Q29 C935 2
S

3
SUSP 0.1U_0603_25V7K VGA@
2
G 2N7002W-T/R7_SOT323-3
S 2
3

+5VALW
MXM Discharge circuit

1
+3VMXM_GATE 1 2
R550 R102 0_0402_5% +3VMXM +5VMXM
10K_0402_5% +5VMXM_GATE 1 2
+5VALW R103 0_0402_5%

1
2
+5VALW R504 R505
1

DGPU_PWR_EN# 1K_0402_5% 1K_0402_5%

R544 UMA@ UMA@
1

Q50

2
1

1
47K_0402_5% R545 D D
2 2 Q35
(18,21) DGPU_PWR_EN (30) SUSP
2

3
10K_0402_5% G G
2N7002_SOT23

1
(20,29,40) SYSON# SYSON# S S Q16A Q16B
2

3
B B
SUSP R539 R558
(30) SUSP
10K_0402_5% 2N7002_SOT23 10K_0402_5% DGPU_PWR_EN# 2 DGPU_PWR_EN# 5
1

D D VGA@ VGA@
2 2 Q26 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
(29,30,31,39) SYSON (21,27,29,31,40) SUSP#

4
G G
2N7002_SOT23
1

Q49 S S
3

R532 2N7002_SOT23 R547 R504 R505

100K_0402_5% VGA@ VGA@
10K_0402_5%
SD028200080 SD028200080
2

200 +-5% 0402 200 +-5% 0402

Discharge circuit +VCCP +3VS +3VS +3VS B+

1 1 1 1 1
C441 C442 C443 C444 C445
+5VS +3VS +1.5V +1.5VS +VCCP +0.75V
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 @ 2 @ 2 @ 2 @ 2 @
1

R498 R499 R500 R501 R502 R503

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% +5VS +5VS +5VS +5VS +5VS
2

A A
6

Q9A Q9B Q10A Q10B Q11A Q11B

SUSP 2 SUSP 5 SYSON# 2 SUSP 5 SUSP 2 SUSP 5

1

2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6 2N7002DW T/R7_SOT363-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401673 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 30, 2009 Sheet 34 of 43
5 4 3 2 1
 A B C D

PR1
1M_0402_1%
1 2

VIN VS VIN

1
@ PR2 PR3
10K_0402_5% 84.5K_0402_1%
PR6

8
PR5 22K_0402_5%

2
1 1

10K_0402_5% 3 1 2

P
PACIN +
(18,21,31,33) ACIN 1 2 1 2 1 0

20K_0402_1%
- 2

1
G
10K_0402_5%

PR8
PCN1 PL1 PR4 PU1A

1
PC1
0.1U_0603_25V7K
SMB3025500YA_2P 0_0402_5% LM358DT_SO8 PC2

4
DC_IN_S1 1 2 DC_IN_S2 PD1 1000P_0402_50V7K
1 VIN

2
GLZ4.3B_LL34-2

2
PR7

2
G 2

2
G
3

1
SINGA_2DC-G756I200 PC3 PC4 PC5 PC6
1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 RTCVREF

2
PR9
DC231000N00 (DIS) 10K_0402_5%

DC231000P00 (UMA)

Vin Dectector
Min. Typ Max.
H-->L 17.208V 17.212V 17.217V
L-->H 17.879V 17.894V 17.909V
2
RTC Battery 2

- BATT1 +
2 1 +RTCBATT +RTCBATT

ML1220T13RE
45@

PJ1 @ PJ2 @
VIN 2 1 2 1
+3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V
JUMP_43X118 JUMP_43X118
2

PD2 PJ3 @
LL4148_LL34-2 2 1
PD3 2 1
LL4148_LL34-2 PJ4 @ JUMP_43X118
1

BATT+ 2 1 +5VALWP 2 2 1 1 +5VALW

1

3 3

JUMP_43X118
PR10 PR11
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR12
PJ5
2

200_0603_5% @ PJ6 @
CHGRTCP 1 2 N1 3 1 VS +VSBP 2 1 +VSB +0.75VP 2 1 +0.75V
2 1 2 1
JUMP_43X39 JUMP_43X118
1

PC8
PR13 PC7 0.1U_0603_25V7K
100K_0402_1%
2

0.22U_0603_25V7K PJ7 @ PJ8 @

2

+1.05VSP 2 1 +VCCP +1.8VP 2 1 +1.8V

2 1 2 1
(32) 51ON# 1 2
PR14 JUMP_43X118 JUMP_43X118
22K_0402_1%
PJ9 @
2 2 1 1
RTCVREF JUMP_43X118
1

PR15
200_0603_5%
PR16 PR17 PU2 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN
1

GND
4
PC9 PC10 4

10U_0805_10V4Z 1 1U_0805_25V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 35 of 43
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
VL ENTRIP1 (38)
VL
VMB

2
DC040006300
PJP1 PL2 PR18

1
1 1

SMB3025500YA_2P 47K_0402_1% D

1
VMB 1 2 BATT+ PH1 PC11 2 PQ2
0.1U_0603_25V7K PR19 G SSM3K7002FU_SC70-3

1
2 100K_0603_1%_ERTJ1VS104FA 47K_0402_1% S

3
3

1
EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR20
5

8
1000P_0402_50V7K 0.01U_0402_25V7K 13.7K_0402_1% PU3A

2
6 PD4
1 2 3

P
7 +
O 1 2 1
TM_REF1 2 ENTRIP2 (38)
-

G
LL4148_LL34-2
LM393DG_SO8

4
改 DC040006G00

0.22U_0603_16V7K
2nd DC040006F00

1
D

15.4K_0402_1%
2

1
2 PQ3
Footprint

1000P_0402_50V7K
PC14

PR23
PR21 PR22 G SSM3K7002FU_SC70-3
100_0402_1% 100_0402_1% 2 1 S
VL

3
1
SUYIN_200275MR007G12MZR_7P PR25

PC15
6.49K_0402_1% PR24
1

2
2 1 100K_0402_1%
+3VALWP

2
PJP1 battery connector

1
1

SMART Battery: PR27

PR26
100K_0402_1%
1.VMB 1K_0402_1%

2
2.VMB
3.TSA
2

4.SMC
2 2

BATT_TEMP (31)

5.SMD
6.GND SMB_EC_CK1 (21,31)

7.GND PH2 near main Battery CONN :

SMB_EC_DA1 (21,31)
BAT. thermal protection at 76 degree C
Recovery at 72 degree C
VL
solve battery thermal issue 03/03

2
PR28
VL 47K_0402_1%
PR29
47K_0402_1%

1
1 2

1
PQ4
TP0610K-T1-E3_SOT23-3 PH2

100K_0603_1%_ERTJ1VS104FA VL
B+ 3 1 +VSBP

2
0.22U_1206_25V7K
100K_0402_1%

0.1U_0603_25V7K

PR31
1

8
3.32K_0402_1% PU3B
1

1
PR30

PC16

PC17

1 2 5 PD5

P
+

0.22U_0603_16V7K
O 7 2 1
TM_REF1 6
2

G
3 3

PR32 @ @ LL4148_LL34-2
2

1
22K_0402_1% LM393DG_SO8

4
VL

PC18
1 2 PR33
17.8K_0402_1%

2
2

PR34
100K_0402_1%

PR35
1

0_0402_5% D
1 2 2 PQ5
(38) POK
G SSM3K7002FU_SC70-3
0.1U_0402_16V7K

S
3
1

PC19
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Friday, May 15, 2009 Sheet 36 of 43
A B C D
 A B C D

B+
PQ6 PQ7
AO4407_SO8 AO4407_SO8 PR36
VIN 8 1 1 8 0.015_2512_1%
7 2 2 7 PJ10 @
6 3 3 6 1 4 1 2 CHG_B+
1 2

1
5 5 PR38

2
2200P_0402_25V7K
CHGEN#

4.7U_1206_25V6K

4.7U_1206_25V6K
2 3 JUMP_43X118 100K_0402_1%
PR37 PC20

2
0.01U_0402_25V7K
3.3_1210_5% 0.01U_0402_25V7K

1
2

100K_0402_1%

PC22

PC23

PC24

2
1
PC21 PC26 PC27

1
2

5
6
7
8

3
2
1
1 1

PC25

PR39
0.01U_0603_50V7K 0.1U_0402_16V7K PU4 0.1U_0603_25V7K

1
1 2 1 28 PVCC 1 2 PQ9
CHGEN PVCC

1
AO4407_SO8

1
PR40 PC28 PR42 /BATDRV 4

2
3.3_1210_5% PC29 0.1U_0603_25V7K 2.2_0603_1% PQ8

2
0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR41 @PD7
@ PD7
340K_0402_1% 1 2 ACN 2 26 DH_CHG
ACN HIDRV
1

ACP 3

3
2
1

5
6
7
8
PC30 GLZ4.3B_LL34-2 ACP PR43

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL3 0.02_2512_1%
2

ACDET ACDRV PH 10UH_PCMB104T-100MS_6A_20%

5 ACDET BATT+
2 1 1 2 1 2 1 4

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PD6 PC31 2 3

2
LL4148_LL34-2 0.1U_0603_25V7K

REGN
CELLS

5
6
7
8

1
PC123

PC33
24751_VREF PR44 PR45

PC32
GND 3 Cell 54.9K_0402_1% ACSET 6 4.7_1206_5%
ACSET
24

2
REGN @
VREF 4 Cell
1
1

1
PC34 PQ10
1U_0603_10V6K 4 AO4466_SO8 PC35

1
PR46 @ PR47
@PR47 680P_0402_50V7K

2
2

47K_0402_1% 0_0402_5%
1 2 1 2 7
2

2
PR48 PC36 ACOP DL_CHG
23

3
2
1
340K_0402_1% 0.47U_0603_16V7K LODRV
CELLS
1

PGND 22
OVPSET 8 PC37
OVPSET
1

2 D 0.1U_0402_16V7K 2

2 1 2
G 3S/4S# (31) 9 21 ACOFF (31)
AGND LEARN
2

S PQ11
3

1
SSM3K7002FU_SC70-3 PR49 PC38 PC39
54.9K_0402_1% 0.1U_0603_25V7K 0.1U_0603_25V7K
24751_VREF CELLS
20

2
PQ12 CELLS
1

SI2301BDS-T1-E3_SOT23-3 24751_VREF
Cells selector 10 VREF
2

PC40
1U_0603_10V6K
PR50
100K_0402_1% 19 SE_CHG+

2
SRP
CP Point Setting PQ15_GATE 2 11 18 SE_CHG-
1

1 VDAC SRN
CP point=Iadapter*85% PR51 17
BAT
1

100K_0402_1%

1
90W adapter PC42 VADJ 12
0.1U_0603_25V7K VADJ PC41
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

ACSET 0.1U_0603_25V7K

2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A TP 29 Icharge Setting
ACGOOD# 13 ACGOOD ICHG setting For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
65W adapter R=(100K*100K)/(100K+100K)=50K PR52 For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
24751_VREF 24751_VREF 16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V /BATDRV 14
SRSET IREF (31) IREF*(100k/(100K+17.4K)/3.3)*(0.1/0.02)=Icharge
BATDRV 17.4K_0402_1%

1
200K_0402_1%

PR54
IREF=0.77484*Icharge
1

1
100K_0402_1%

CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR55

1

PR53

PQ15_GATE 15 1 2 100K_0402_1% PC43 @

IADAPT
PR56

0.01U_0402_25V7K

2
Input OVP : 22.3V VMB BQ24751ARHDR_QFN28_5X5

2
1

3 3
D
2

1
Input UVP : 17.26V 2 PQ13
2

0.1U_0402_16V7K G SSM3K7002FU_SC70-3 PC44

1

PC45 D 100P_0402_50V8J
Fsw : 300KHz S
3

2
ACOFF 1 2 2 PQ14
G SSM3K7002FU_SC70-3 VS PR57
S 340K_0402_1%
3
1
340K_0402_1%

2
PR58

0.01U_0402_25V7K

(31) ADP_I @PR59

@ PR59
0_0402_5% 24751_VREF
1 2
1

PC46
2

1
PR60 PR61 @
2

499K_0402_1% 887K_0402_1%
PQ15 @ 24751_VREF
SI2301BDS-T1-E3_SOT23-3 PR63 @
LI-4S :18.0V----BATT-OVP=2.677V
2

2
8

PR62 PU1B 0_0402_5%

S
10K_0402_1% REGN VADJ

D
5 BATT-OVP=0.1487*VMB 3 1 1 2
P

2
1 2 7 0
(31) BATT_OVP 6 LI-3S :13.5V----BATT-OVP=2.007V PR64
-

1
G

105K_0402_1%

0.01U_0402_25V7K

Use 0.1% level

G
100K_0402_1%

2
1

PR66 LM358DT_SO8 PR65 @

BATT-OVP=0.1487*VMB
4

1
PR67

PC47

64.9K_0402_1% 100K_0402_1%

1
24751_VREF 1 ACSET PR68 PR69 CHGEN#
2 Per cell=3.5V 210K_0402_0.1% 499K_0402_0.1%
2

2
2
1

1
D

2
2 PQ16
(31) FSTCHG

1
PR70 D G SSM3K7002FU_SC70-3
100K_0402_1% 2 PQ17 @ S

3
(31) Calibrate#
1

4
G SSM3K7002FU_SC70-3 4
2

PR71 Charger ADJ Calibrate# S

3
100K_0402_1%
1

D
(31) 65W90W#
2 4.0V L=0V
2

G
S PQ18
3

SSM3K7002FU_SC70-3 4.2V 1.8755V Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title
4.3V 2.8132V SCHEMATIC,MB A5011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.35V H=3.3V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 37 of 43
A B C D
 5 4 3 2 1

Frequency different
RT8205C TPS51125
2VREF_51125 300KHZ/375KHZ 245KHZ/305KHZ
OCP calculation method different

0.22U_0603_10V7K
RT8205C TPS51125
D D
Rtrip*Itrip/10 (Rtrip*Itrip/9)-24mV

1
PC48
GND pad need add via to ground

2
Add pull high resistor to +3VLP on pin13

PR72 PR73
13K_0402_1% 30K_0402_1%
1 2 1 2

PR74 PR75
B++
20K_0402_1% 19.1K_0402_1%
B++
1 2 1 2

PJ11 @
B+ 2 2 1 1 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

JUMP_43X118 PR76 PR77

10U_1206_25V6M

10U_1206_25V6M
196K_0402_1% 226K_0402_1%
1

2200P_0402_50V7K
PC49

4.7U_0805_10V6K
1 2 1 2

1
PC50

PC51
PC53
2

2
6

5
6
7
8
PC52
PU5

8
7
6
5

1
C C

VREF
ENTRIP2

VFB2

VFB1

ENTRIP1
TONSEL
25 PQ20
PQ19 P PAD AO4466_SO8

2
AO4466_SO8
7 VO2 VO1 24 POK (36) 4
4
8 23 PR79 PC55
PR78 VREG3 PGOOD 2.2_0603_1% 0.1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_1% VBST2 VBST1
1
2
3

PL4 PC54 UG_3V 10 21 UG_5V PL5

4.7UH_SIL1045R-4R7PF_6.3A_30% 0.1U_0402_16V7K DRVH2 DRVH1 4.7UH_SIL1045R-4R7PF_6.3A_30%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

680P_0603_50V7K 4.7_1206_5%
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1
PR80

PR81
SKIPSEL

330U_6.3V_M
PQ21 PQ22

VREG5
330U_6.3V_M

VCLK
1 AO4712_SO8 AO4712_SO8

GND
1

EN0

VIN
2

2
+ +
PC56

PC57
4 4
TPS51125RGER_QFN24_4X4

13

14

15

16

17

18
1

1
680P_0603_50V7K

PC59
PR82
2 2
PC58

499K_0402_1%
B+ 1 2
2

1
2
3

3
2
1

2
1
100K_0402_1%
1 2 VL

1
PR83

PC60
4.7U_0805_10V6K
PR84
B @ 0_0402_5% B

2
B++

1
ENTRIP1 (36) ENTRIP2 (36)

0.1U_0603_25V7K
2
PC61
2VREF_51125
+5VALWP Ipeak=8.644A ; Imax=6.0508A
1

D D
PQ23
SSM3K7002FU_SC70-3 G
2 2
G
PQ24
SSM3K7002FU_SC70-3
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
S S Vtrip=(10E-06 * 226K)/9-24=227mV
3

+3.3VALWP Ipeak=8.444A ; Imax=5.9108A Ilimit=227mV/18m ~ 227mV/15m

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) =12.617A ~ 15.141A
2 1 Vtrip=(10E-06 * 196K)/9-24=194mV Iocp=Ilimit+Delta I/2
VL
PR85 Ilimit=194mV/18m ~ 194mV/15m =13.2395A ~ 15.7635A
100K_0402_1%
=10.778A ~ 12.933A Delta I=1.245A (Freq=300KHz)
1

D
1 2 2 PQ25
Iocp=Ilimit+Delta I/2
VS
A
G SSM3K7002FU_SC70-3 =11.148A ~ 13.303A A
49.9K_0402_1%

0.01U_0402_16V7K

PR86 S
3
1

100K_0402_1% Delta I=0.74A (Freq=375KHz)

1
PR87

@ PC62
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2007/11/12 Deciphered Date 2008/11/12 Title

SCHEMATIC,MB A5011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 38 of 43
5 4 3 2 1
 A B C D

PL11
FBMA-L18-453215-900LMA90T_1812

51117_1.5V_B+ 2 1 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC63

PC64
5
6
7
8

2
PQ26
1 AO4466_SO8 1

PR88 4
280K_0402_1%
1 2
PR89
0_0402_5%

3
2
1
1 2 1.5V_EN BST_1.5V
(29,30,31,34) SYSON

1
@ PR91 @ PC66 PR90 PL6

15

14
PC65

1
47K_0402_5% 0.1U_0402_16V7K PU6 2.2_0603_1% 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1 2BST_1.5V-1 1 2 1 2

EN_PSV

TP

VBST
+1.5VP

2
2

2 13 UG_1.5V 0.1U_0603_25V7K
TON DRVH

1
+1.5V 3 12 LX_1.5V
VOUT LL

5
6
7
8

330U_6.3V_M
PR92 1
4 11 +5VALW 4.7_1206_5%

D
D
D
D
V5FILT TRIP

PC67
+

2
5 10 PQ27
VFB V5DRV FDS6670AS_NL_SO8

1
LG_1.5V 2
6 PGOOD DRVL 9 4 G

PGND
PC68 VFB=0.75V

GND
@ PR163 680P_0603_50V8J
Vo=VFB*(1+PR95/PR96)=1.5V

2
1

S
S
S
100K_0402_5%

18K_0402_1%
@ PR164

1
0_0402_5% TPS51117RGYR_QFN14_3.5x3.5 PC69 Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=4.68E-7
2

3
2
1
PR94
2 1 4.7U_0805_10V6K
(7,30) DDR3_SM_PWROK Freq=356KHz

2
1
@ PC124 Cesr=15m ohm

2
PR93 @ PC71 0.1U_0402_16V4Z
Ipeak=13.67A Imax=9.569A
2
2
300_0603_5% 47P_0402_50V8J 2

+5VALW 1 2 Delta I=((19.5-1.5)*(1.5/19.5))/(L*Freq)=2.429A

Vtrip=Rtrip*10uA=0.180V
Layout Note: Iocp-min=Vtrip/Rdsonmax*1.1+2.429=15.161A
1

Place near V5FILT Pin Iocp-max=Vtrip/Rdsontyp*1.1+2.429=23.436A

PC70 PR95
1U_0603_10V6K 59K_0402_1% VFB=0.75V Iocp=15.161~23.436A
2

1 2
1

PR96
59K_0402_1%
PL12
2

FBMA-L18-453215-900LMA90T_1812

51117_1.05V_B+ 2 1 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC72

PC73
5
6
7
8

2
PQ28
AO4466_SO8

PR97 4
3
280K_0402_1% 3

1 2

3
2
1
1.05V_EN BST_1.05V

PR98 PR99 PL7

15

14

PC74
1

0_0402_5% PU7 2.2_0603_1% 2.2U_FDV0630-2R2M-P3_7.2A_20%

1 2 1 2BST_1.05V-1 1 2 1 2
EN_PSV

TP

VBST

(30) VS_ON +1.05VSP

1

@ PR100 2 13 UG_1.05V 0.1U_0603_25V7K

TON DRVH

1
47K_0402_5% @ PC75
0.1U_0402_16V7K 3 12 LX_1.05V
2

VOUT LL
5
6
7
8
PR101 1
2

4 11 +5VALW 4.7_1206_5%
D
D
D
V5FILT TRIP D + PC76

2
5 10 PQ29 330U_D2E_2.5VM
PR102 VFB V5DRV FDS6670AS_NL_SO8

1
300_0603_5% LG_1.05V 2
6 PGOOD DRVL 9 4 G
PGND

PC77 VFB=0.75V
GND

+5VALW
680P_0603_50V8J
Vo=VFB*(1+PR105/PR106)=1.05V
2
1

S
S
S
18K_0402_1%
1

Layout Note: @ PC80 PC78 Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=3.54E-07

7

3
2
1
1

PR103

47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

Freq=330KHz
2

Place near V5FILT Pin 1 2

2

PC79 Cesr=15m ohm

2

1U_0603_10V6K
Ipeak=17.47A Imax=12.229A
@ PR104 PR105 Delta I=((19.5-1.05)*(1.05/19.5))/(L*Freq)=1.597A
30K_0402_1% 23.7K_0402_1% VFB=0.75V Vtrip=Rtrip*10uA=0.180V
+VCCP 2 1 1 2
4 Iocp-min=Vtrip/Rdsonmax*1.1+1.597=14.745A 4

Iocp-max=Vtrip/Rdsontyp*1.1+1.597=23.019A
1

Iocp=14.745~23.019A
PR106
59K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/08/10 Deciphered Date 2009/08/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 39 of 43
A B C D
 5 4 3 2 1

D D

+1.5V

1
PJ14 @

1
JUMP_43X118

2
PU8

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
1
PC81 3 7 PC82
4.7U_0603_6.3V6M PR107 REFEN NC 1U_0402_6.3V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
GND
RT9173DPSP_SO8

0.1U_0402_16V7K
PR108 PQ30
+0.75VP

1
0_0402_5% SSM3K7002FU_SC70-3 D PR109

PC83
1 2 2 1K_0402_1%
(20,29,34) SYSON#

1
G

2
1
S PC85

2
PC84 10U_0805_6.3V6M

2
C 0.1U_0402_16V7K C

+5VALW
1

+3VALWP PC86
1U_0402_6.3V6K
2

B B
1
1

PJ15 @
JUMP_43X79 PU9
2

6 VCNTL
5 3 +1.8VP
2

VIN VOUT
9 VIN VOUT 4
1

22U_0805_6.3V6M
8 PR110
EN
1

PC89
PC88 7 2 1.54K_0402_1% PC87
GND

4.7U_0603_6.3V6M POK FB 2
0.01U_0402_25V7K

2
2

APL5913-KAC-TRL_SO8
1

PR111
1.2K_0402_1%
PR112
2

10K_0402_1%
(21,27,29,31,34) SUSP# 1 2
1
1

PC90 PR113
1U_0402_6.3V6K 47K_0402_5%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 40 of 43

5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_B+

2
PL8

(5)

(5)

(5)

(5)

(5)

(5)

(5)
CPU_VID6

CPU_VID5
CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR114 FBMA-L18-453215-900LMA90T_1812

(30,31)
VR_ON
1_0603_5%
2 1

2200P_0402_50V7K

1000P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M
1

1
PC93

PC94
D
PR115 499_0402_1% D

PC95

PC97
(7,18) DPRSLPVR 1 2 PC92 + PC96
PC91 2.2U_0603_6.3V6K 220U_25V_M

2
5
PR116 0_0402_5% 0.022U_0402_16V7K

2
2
(5,7,17) H_DPRSTP# 1 2

PR117 0_0402_5%
1 2 PQ31

1
1

PR123 0_0402_5%

PR124 0_0402_5%

PR125 0_0402_5%

PR126 0_0402_5%
CLK_ENABLE#

PR119 0_0402_5%

PR120 0_0402_5%

PR121 0_0402_5%

PR122 0_0402_5%
4
PR118 0_0402_5%
+3VS 1 2 SI7686DP-T1-E3_SO8
+3VS

3
2
1
1

2
1.91K_0402_1%

1U_0402_6.3V6K
PC99 UGATE_CPU1-2 PL9

PC98
0.22U_0603_10V7K 0.36UH_FDU1040D-R36M_26A_20%

1
BOOT_CPU1 1 2 1 2 1 4 +VCC_CORE

2
2

PR129
PR128 PR127

5
6
7
8

1
4.7_1206_5%

3.65K_0805_1%
2.2_0603_1% 2 3

5
6
7
8

1
10K_0402_1%
PR132
499_0402_1% PQ33

49

48

47

46

45

44

43

42

41

40

39

38

37

1
PR131

PR133
1 2 AO4456_SO8
2

PR134

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

PR130 0_0603_1% PQ32 1_0402_5%

1 2

2
680P_0402_50V7K
1 36 AO4456_SO8 4 PR135 @

2
(7,18) VGATE PGOOD BOOT1 0_0603_5%
4

2
(5) H_PSI# 1 2 2 35 UGATE_CPU1-1 VSUM 1 2
PSI# UGATE1

PC100
PR136 0_0402_5% PC101

2
1 2 3 34 PHASE_CPU1 1 2

3
2
1
(31) PGD_IN @PR137
@ PR137 PMON PHASE1
VCC_PRM

3
2
1
0_0402_5% 1 2 4 33 ISEN1
PR138 147K_0402_1% RBIAS PGND1 0.22U_0603_10V7K
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

2200P_0402_50V7K
5
C C
6 NTC PVCC 31

10U_1206_25V6M

10U_1206_25V6M
ISL6266ACRZ-T_QFN48_7X7

1
7 30 LGATE_CPU2
SOFT LGATE2

PC102

PC103

PC104
PU10 PQ34
PC105 8 29

2
0.022U_0603_25V7K OCSET PGND2
4
1 2 9 28 PHASE_CPU2 SI7686DP-T1-E3_SO8
VW PHASE2 PR139
PR140 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2 PL10
COMP UGATE2 0_0603_1% 0.36UH_FDU1040D-R36M_26A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR141
1 2

1
4.7_1206_5%
PC107 1000P_0402_50V7K 2.2_0603_1% PC106
DROOP

12 FB2 NC 25 2 3
VDIFF

ISEN2

ISEN1
VSUM
VSEN

3.65K_0805_1%
PR143 11.3K_0402_1% 0.22U_0603_10V7K
GND

VDD
RTN

DFB

5
6
7
8

5
6
7
8

1
VIN

10K_0402_1%
VO

1 2

1
PR142

PR145

PR146
PQ35 PQ36 PR144

680P_0402_50V7K
1 2 AO4456_SO8 AO4456_SO8
13

14

15

16

17

18

19

20

21

22

23

24

1 2
PC108 1000P_0402_50V7K 1_0402_5%

2
PC109
ISEN1 4 4 PR147 @

2
ISEN2 0_0603_5%

2
PR150 2

@ 0_0402_5%

PR149 97.6K_0402_1% PC110 1 2 +5VS 1 2

2 PR151 1
1K_0402_1%

1 2 2 1 VSUM
1

PR148 1_0603_5% PC112

3
2
1

3
2
1
270P_0402_50V7K PC111 1 2
1 2 1U_0402_6.3V4Z
1

0.22U_0603_10V7K
PC113 100P_0402_50V8J
PR153 VCC_PRM
PR152 PC114 2200P_0402_50V7K 10_0603_5% ISEN2
1 2 1 2 1 2 CPU_B+
B 100_0402_1% B
1

1 2 PC115
0.1U_0603_25V7K
PR154 1K_0402_1%
2

PC116 330P_0402_50V7K
(5) VCCSENSE 1 2 1 2
VSUM
1

PR156 PR155
1

2.61K_0402_1%

20_0402_5% 0_0402_5% PC118 PC117

PR157

+VCC_CORE 1 2 330P_0402_50V7K 0.01U_0603_50V7K

2

(5) VSSSENSE 1 2
2
1

11K_0402_1%

PC119 180P_0402_50V8J
2

PR160

PR158 1 2
2

PR159 0_0402_5%
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR161 1K_0402_1% PR162 3.74K_0402_1%

1

VCC_PRM

PC120 0.1U_0402_16V7K
1 2

2 1

PC121 0.22U_0402_6.3V6K

A A
1

PC122
0.22U_0603_10V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/29 Deciphered Date 2007/09/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5011
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401673
Date: Thursday, April 30, 2009 Sheet 41 of 43
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D
Unite parts PQ5,PQ11,PQ13,PQ14,PQ16,PQ17,PQ18,PQ30 2008
1 Change from SB000006800、SB000009080 to SB000009610 12/19
EVT
Add PR80,PR81,PR131,PR142 SD001470B80 2008
2 EMI request
(S RES 1/4W 4.7 +-5% 1206) 12/19
EVT
Change PR78,PR79,PR127,PR141 from 0 to 2.2 2008
3 EMI request
(SD014220B80) 12/19
EVT
2008
4 Reduse 1.5V, 1.05V frequency to about 300KHz Change PR88,PR97 from 180K to 280K(SD034280380)
12/19
EVT
2008
5 Output voltage error Set 1.8V voltage Change PR111 from 1.71K to 1.2K(SD034120180)
12/19
EVT
2008
6 Down size Change PC88 from 0805 to 0603(SE093475K80)
12/19
EVT
2008
7 Heavy load efficiency fail Raise heavy load efficiency 38 Change PL4,PL5 from 10uF to 4.7uF(SH000006J80)
12/19
EVT
Add PC58,PC59 S CER CAP 680P 50V K X7R 0603 2008
8
C C
EMI request EVT
(SE025681K80) 12/19
Add PC100,PC109 S CER CAP 680P 50V K X7R 0402 2008
9 EMI request
(SE074681K80) 12/19
EVT
2008
10 41 Change PR143 from 8.25K to 11.3K(SD034113280)
12/19
EVT
2008
11 Improve load line 41 Change PR162 from 4.42K to 3.74K(SD034374180)
12/22
EVT
2008
12 New charge voltage setting 37 Delete PQ15,PQ17,PR61,PR63,PR65
12/23
EVT
2008
13 New charge voltage setting 37 Add PR68 210K_0402_1%(SD034210380)
12/23
EVT
2008
14 New charge voltage setting 37 Change PR69 from 221K to 49.9K(SD034499280)
12/23
EVT
2009
B 15 Battery can't charge to 100% 37 Change PR69 from 49.9K to 499K(SD034499380)
01/12
DVT B

HDMI 5V voltage test 2009

16 fail(should 4.8~5.3V)
Raise 5V voltage 38 Change PR75 from 20K to 19.1K(SD034191280)
01/17
DVT
2009
17 Prevent spike 37 Add PD7
01/21
DVT
2009 2009
18 Improve charge voltage 37 Change PR68, PR69 from 1% to 0.1%
01/22
DVT 02/09
刪除
Change PR90, PR99 from 0 to 2.2(SD014220B80) 2009
19 EMI request 39
Enable PR92, PR101, PC68, PC77 02/04
DVT
Change PJ12 to PL11(SM010020720) 2009
20 EMI request 39
Change PJ13 to PL12(SM010020720) 02/04
DVT
Change PR42 from 0 to 2.2(SD014220B80) 2009
21 EMI request 37
Enable PR45, PC35 02/04
DVT
2009
22 Protect logic low Set trigger point at 76℃ 36 Enable PD5, PH2, PR28, PR29, PR31, PR33, PC18
02/25
PVT
A A

23

Compal Electronics, Inc.

Title

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL SCHEMATIC,MB A5011
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Size Document Number Rev
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
401673 B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Date: Thursday, April 30, 2009 Sheet 42 of 43
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Version change list (P.I.R. List) Page 2 of 2

for PWR
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D D

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30

C 31 C

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B B

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A A

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Compal Electronics, Inc.

Title
SCHEMATIC,MB A5011
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Size Document Number Rev
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
401673 B
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Thursday, April 30, 2009 Sheet 43 of 43

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