Lecture 6

Steady-state analysis of Cuk converter

 Cuk converter

• Voltage (current) step-up AND step-down capability,

controlled by the duty ratio, D

• Combines good characteristics of buck and boost converters

(in terms of filtering on the input and output sides)

• Negative output voltage

(similar to basic buck-boost converter)

• Coupling capacitor

• Complex controller

Raja Ayyanar, ASU

 Cuk converter: schematic
iL1 iCC iL2
Cc
vL1 _ _ _ vL2 + _
iin + + vCC
S1
+ qA Co
D1
D + Vo
Vin
_ iCo Io +

o Power transfer through the coupling capacitor, Cc

o Cc is assumed large enough to approximate its
voltage to be constant DC in steady-state
o however, it is not as large as the output capacitor,
and the ripple in the voltage is higher
o Its voltage polarity in steady-state is as shown in schematic
o Inductors on both input and output sides ensure the currents
are non-pulsating

Raja Ayyanar, ASU

 Cuk converter: basic operation
iL1 iCC iL2
Cc
iin + vL1 _ + vCC
_ _ vL2 + _
S1 Co
+ qA D1
D + Vo
Vin
_ iCo Io +

iL1 iL2 iL1 iL2

+ vCc − + vCc −
_ _

Vo Vo

+ +
Switch ON interval Switch OFF interval

Raja Ayyanar, ASU

 Similarity to cascaded boost and buck converters

+
q +
+
q D Vo
Vin + vCC
D −
_

Boost stage Buck stage

• Cuk converter is similar to the cascaded connection of a boost converter
and a buck converter with the switch of both converters controlled by the
same switching function (hence, same duty ratio)
• Cuk converter realizes the same functionality and performance with a
single switch and a diode – but results in negative output
For the cascaded boost/buck (in CCM)
Vin Vo D
vCC  Vo  D VCC 
1 D Vin 1 D
Raja Ayyanar, ASU
 Similarity to cascaded boost and buck converters

+
iL1 D1 + iL2 +
S2
+ vCc
Vo
S1 D2
− −

ON interval Cascaded OFF interval

iL1 iL2 iL1 iL2
+ + + +

Vin Vin vCc

vCc Vo
Vo
− − − −

iL1 iL2 iL1 iL2

+ vCc − Cuk + vCc −
_ _

Vin Vo Vo
Vin
+ +
Raja Ayyanar, ASU https://youtu.be/AwOaOsi8cDw
 Similarity to cascaded boost and buck converters

+
+ +
Vin S1
D +
vCc D1 Vo
− −

_ _
+ vCc −
Vo Vo

+ +

_ _
+ vCC
S1
+ D1 Vo
Vin D

+
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 Switch ON interval
o Diode reverse biased by VCc
o Current and stored energy in L1 rise
with power drawn from input source

o Current and stored energy in L2 rise

with power drawn from Cc

iL1 iL2 o Cc discharges (voltage change is

+ vCc −
_ small due to large value of Cc)

Vo o iCo  iL2  I o , a ramp current which is

iCo negative for half the ON interval and
Io + positive for the remaining half
Switch ON interval

Raja Ayyanar, ASU

 Switch OFF interval
o Current and stored energy in L1
decrease with energy released to Cc

o Current and stored energy in L2

decrease with energy released to
Co and load

o Cc charges (voltage change is

iL1 iL2 small due to large value of Cc)
+ vCc −
_
o iCo  iL2  I o , a ramp current which
Vo is positive for half the OFF interval
iCo
and negative for the remaining half
Io
+
Switch OFF interval

Raja Ayyanar, ASU

 Voltage across CC
iL1 iCC iL2
Cc

iin + vL1 _ + vCC _ - vL2 + _

S1
+ qA Co
D1
D + Vo
Vin
_ iCo Io +

KVL around the larger loop in average (CCA) quantities

Vin  vL1  vCC  vL 2  Vo  0

vCC  Vin  Vo

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 Input-output relationship

vCC  Vin  Vo

Applying volt-second balance across L1

Vin DTs  Vin  Vin  Vo 1 D Ts  0

By power balance
Vin D  Vo 1 D  Vo  D I in

D
Vin 1 D I o 1 D

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 Waveforms: voltages and currents of the two inductors

vL1
& vL2 Vin
(1-D)TS
0 t
DTS
-Vo
iL2 Io

iL1
Iin
0
t

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 Waveforms: coupling capacitor current
iCc
iL2 Io

iL1
Iin
0
iCc

Applying current-second balance for Cc

I o DTs  I in 1 D Ts  0

I in D
I in 1 D   I o D 
I o 1 D

Raja Ayyanar, ASU https://youtu.be/sW-lwkybHrw

 Inductor design
i  1or 2

Consider the TOFF interval

 I Li
Li  Vo
1 DTS
vL1
Vo 1 D TS
& vL2 Vin
Li 
0
(1-D)TS
 I Li
DTS t
-Vo
iL2 Io • L selected for current ripple
 I L2
to be about 10-20% of its
 I L1 max. avg. current (Iin or Io )
iL1
Iin
0 • Worst case D is Dmin for
t
constant Vo applications

Raja Ayyanar, ASU https://youtu.be/yTTF_fMUzPE

 Design parameters for inductor
Input side inductor, L1 Output side inductor, L2

Vo 1 Dmin TS Vo 1 Dmin TS

L1  L2 
 I L1  I L2

 I L1  I L2
I L1, peak  I in,max  I L 2, peak  I o,max 
2 2

DC bias : I in,max DC bias : I o,max

I L 2 
2
I L1 
2
I L1, RMS  I in2 ,max  I L 2, RMS  I o2,max 
12 12

The two inductors can be coupled, i.e, wound on the same core
Raja Ayyanar, ASU
 Output capacitor design

• Output capacitor design identical to that of a buck

(Refer buck converter design video)

Vo Vo
ESR  
Voltage rating = VO I Co I L 2
I L 2 Vo  allowed pk-pk ripple in Vo
RMS current rating = I L 2  maximum pk-pk ripple in iL 2
2 3
An advantage of Cuk topology is that the I L 2 1
RMS current in output capacitor is very low
C 
Vo 8 f s

Raja Ayyanar, ASU

 Coupling capacitor design

• Cc design based on limiting the peak-peak voltage ripple, VCc

• since VCc is an internal variable, large ripple can be allowed
• for example, 10% of nominal VCc at full load
• this allows use of low capacitance, and hence film capacitors

• RMS current can be large and is another critical requirement to be met

• Voltage rating is Vin  Vo with sufficient margin for the larger ripple
and transient conditions

Raja Ayyanar, ASU

 Coupling capacitor: C value
iL2 Io

iL1
Iin
0

Consider the ON interval

I DTS
VCc  o
C

I o DTS
C
iCc
Neglecting inductor current ripple
Iin
VCc
ESR for film capacitors may be neglected

-Io

Raja Ayyanar, ASU

 Coupling capacitor: current rating
iL2 Io

iL1
Iin
0

I C , RMS  I o2 D  I in 2 1 D 
Io D
substitute, I in 
Neglecting inductor current ripple 1 D
iCc Iin D
IC ,RMS  I o
1 D
-Io

Raja Ayyanar, ASU

 Switch selection

MOSFET
Voltage rating = Vin +Vo
Peak current rating = iL1  iL 2 max
I L1  I L 2
  I in  I o max 
Diode 2
Same as above
Average current rating = (Io+ Iin)(1-D) = Io

Raja Ayyanar, ASU