Analysis and Design of Analog Integrated Circuits

Lecture 8

Cascode Techniques

Michael H. Perrott
February 15, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Review of Large Signal Analysis of Current Mirrors

Vdd

ΔV2
I1 I2 1 μ C W2 2
n ox (VGS2-VTH) (1+λ2Vds2)
I2 2 L2
=
I1 1 μ C W1
n ox (VGS1-VTH)2(1+λ1Vds1)
M2 2 L1
M1 Vds2 > Vdsat2 ΔV1
Vss=0 VTH+ΔV1 VTH+ΔV2 But, VTH+ΔV1=VTH+ΔV2 ΔV1 = ΔV2

I2 W2 L1 (1+λ2Vds2)
I2 =
M2 in I1 W1 L2 (1+λ1Vds1)
Saturation Current Mismatch
setting due to Vds
M2 in based on difference
Triode geometry
Note: for accurate ratio, set L1 = L2
Vds2
Vdsat2

M.H. Perrott 2
 The Issue of Vds Mismatch in Current Mirrors

Vdd I2 W2 (1+λ2Vds2)
=
I1 W1 (1+λ1Vds1)
I1 I2
Current Mismatch
setting due to Vds
based on difference
geometry
Vds1 Vds2
M1 M2 Note: we are assuming L1 = L2

 Issue: Current I2 can vary significantly as a function

of the drain voltage of M2
- We often want a tightly controlled current set only by I 1
and transistor sizes
 How do we improve the current mirror matching
performance?

M.H. Perrott 3
 Cascoded Current Source

Iref Rthd3 Rthd3

Ibias Vbias Vbias
M3 M3

M2 ro1
M1

 Offers increased output resistance

- Reduces small signal dependence of output current on
the output voltage of the current source
- From Lecture 6, we derived:
 Output resistance boosted by intrinsic gain of M3, gm3ro3
 But how do we reduce the influence of large signal Vds
mismatch between M1 and M2?

M.H. Perrott 4
 Match Vds of Current Mirror Devices With Proper Bias
Vdd

I1
I2 I2 W1 L4 (1+λ1Vds1)
Recall: =
M3 M2 Vo I1 W4 L1 (1+λ4Vds4)
W/L W/L Vds2 > ΔV Current Mismatch
VTH+ΔV VTH+ΔV setting due to Vds
based on difference
M4 M1 geometry
W/L W/L Vds1 = VTH+ΔV
Vss=0 VTH+ΔV VTH+ΔV

 Key transistor for determining I2 is M1

- Why is M 2 less important?
 Above biasing approach provides a much closer
match between Vds1 and Vds4
W1 1 + λVds1 W1
I2 = I1 ≈ I1
W4 1 + λVds4 W4
M.H. Perrott 5
 The Drawback of Basic Cascode Bias Approach
Vdd
I2
I1 M1 and M2
M1 in saturation in saturation
I2
M2 in triode
M3 M2 Vo
W/L W/L Vds2 > ΔV M1 and M2
VTH+ΔV VTH+ΔV in triode

M4 M1 Vo
V1 VTH+2ΔV
W/L W/L Vds1 = VTH+ΔV
VTH+ΔV VTH+ΔV calculation of V1 is nontrivial
Vss=0

 Output voltage range is reduced

- Now V must be > V + 2V
o TH
- What will happen to the output impedance of the current
source if the output voltage is too low?
- Can we improve the voltage range?
M.H. Perrott 6
 Improved Swing Cascode
I2 M1 and M2
in saturation
Vdd
M1 and M2
in triode no wasted voltage region
I1

2VTH+3ΔV
Vo
I2 Vdsat1+Vdsat2
M3 M5
αW/L W/L Vo
VTH+2ΔV M2
VTH+2ΔV VTH+ΔV W/L Vds2 > ΔV
VTH+ΔV

M4 M6 M1
W/L W/L Vds1 = ΔV
W/L
Vss=0 VTH+ΔV VTH+ΔV VTH+ΔV

 Key idea: set size of M3 such that Vds1 = V

- Assuming strong inversion for M 1 and M3:

M.H. Perrott 7
 Alternative Implementation of Improved Swing Cascode
I2 M1 and M2
in saturation

Vdd
M5 M6 M7 M1 and M2
Wp/Lp in triode no wasted voltage region
Wp/Lp Wp/Lp
I1 I1
I2 Vo
2ΔV
Vo
M3 M2
αW/L W/L Vds2 > ΔV
I1
VTH+2ΔV VTH+ΔV

M4 M1
W/L W/L Vds1 = ΔV
Vss=0 VTH+ΔV VTH+ΔV

 Set  as on previous slide

 Note: both implementations share a common problem

M.H. Perrott 8
 The Issue of Current Mismatch

I1 I2

VTH+2ΔV M2
I2 W2 (1+λ2Vds2)
Recall: =
I1 W1 (1+λ1Vds1)
VTH+ΔV
Mismatch
M4 M1 due to Vds
Vds4 = VTH+ΔV Vds1 = ΔV difference
W/L W/L

 The improved swing approach causes a systematic

mismatch between I2 and I1
- Key issue: V ds1  Vds4

 Can we fix this problem?

M.H. Perrott 9
 Techniques to Reduce Current Mismatch
I1 I2

M3 VTH+2ΔV M2
W/L W/L
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Systematic mismatch between I1 and I2 is greatly

reduced by using the above circuit (now Vds1 ≈ Vds4)
- Note that gate bias on M and M3 may be provided by
2
previously discussed circuits
 Additional techniques for accurately matching I1 and I2
- Set L = L >> L
1 4 min
 Note: set L = L ≈ L for lower area and capacitance
2 3 min
- Set W /W = I /I so that V = V
M.H. Perrott
2 3 2 1 2 3 10
 Another Common Cascode Bias Topology
Vdd
M5 M6 M7
Wp/Lp
Wp/Lp Wp/Lp
I1 I1

M8
W/L
M9
VTH+2ΔV
W/L
M10
I2
W/L
M11 M3 M2
W/L W/L W/L
I1
M12 VTH+ΔV VTH+ΔV
W/L
M13 M4 M1
W/L Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Key issue: needs two bias current branches

M.H. Perrott 11
 Utilizing a Simple Resistor to Achieve One Bias Branch

M5 M7
Wp/Lp
Wp/Lp
I1

VTH+2ΔV

ΔV RB
I2

M3 M2
W/L W/L
I1
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Issue: poly resistor is large and won’t track NMOS

devices across temperature and process variations 12
M.H. Perrott
 Better Approach: Use PMOS Device In Triode Region

M5 M7
Wp/Lp
Wp/Lp
I1

VTH+2ΔV

M6
Wp/Lp ΔV
I2

M3 M2
W/L W/L
I1
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Much smaller, better tracking with NMOS devices than

resistor 13
M.H. Perrott
 Wilson Current Mirror

I2
I1 Rthd2

M2

M3 M1

 Relies on feedback in its operation

 Using Hybrid- analysis

- Output resistance comparable to cascode current source

 This circuit is rarely used these days

M.H. Perrott 14
 Enhanced Cascode Current Source

Ibias Ibias2 Iref

M4

M3

M2 M1

 Offers output resistance comparable to double

cascode current source
 As with Wilson mirror, analysis is tricky due to
source/gate coupling
- Using results shown in the following slide:
M.H. Perrott 15
 Thevenin Resistances for CMOS Transistor Feedback Pair

RA RC RA RC
Rthd
D Rthd M4 D

M4

M3 vgs4 gm4vgs4 -gmb4vs4 ro4

S Rths M3
RB

S
ro3 -gmb3vs3 gm3vgs3 vgs3 Rths
vs4 RB
vs3=0

M.H. Perrott 16
 Basic Cascode Amplifier

RD
Vout M2
M2
Rths2 is2 d2
RG
M1

Vin α 2is2 Rthd2 RD vout

RS

s2
M1
Common Gate
RG g1 Rths1 is1 d1

vin Rthg1 vg1 Av1vg1 α 1is1 Rthd1

s1

General Model RS

 Allows improved frequency response (discussed later)

 Reduction to two-port will be done in several steps
17
M.H. Perrott
 Eliminate Middle Sections

RD
Vout M2
M2
Rths2 is2 d2
RG
M1

Vin α 2is2 Rthd2 RD vout

RS

s2
M1

RG g1 d1

vin Rthg1 vg1 Gm1vg1 Rthd1

 Calculation of Gm1 same as for common source amp

 To reduce further, note that

M.H. Perrott 18
 Resulting Two-Port Similar to Common Source Amp

RD
Vout M2
M2
d2
RG
M1

Vin Gm1vg1 Rthd2 RD vout

RS

M1

RG g1

vin Rthg1 vg1

 Key difference: drain impedance much larger

M.H. Perrott 19
 Slight Twist to Cascode Amplifier

Vdd
RL
Vout
RL
Vout
Ibias
1 is1 ro1
gm1+gmb1
Vbias
Iin is1
M1

Vin iin ro4 ro2

M4 M2 M3 Vss=0

 What is the difference between this amplifier and

basic cascode amplifier?
 What are the constraints in setting Vbias?
 What is the maximum output voltage swing?

M.H. Perrott 20
 Constraints on Vbias and Output Range
Vdd

RL
Vout
Ibias
M1
>ΔV1 Vbias
Iin
VTH+ΔV1

Vin >ΔV4 >ΔV2

M4 M2 M3 Vss=0

 To keep M2 and M4 in saturation

 To keep M1 in saturation

M.H. Perrott 21
 Calculation of Maximum Output Range
Vdd

RL
Vout
Ibias
M1
>ΔV1 Vbias
Iin
VTH+ΔV1

Vin >ΔV4 >ΔV2

M4 M2 M3 Vss=0

 Minimum Vbias allows the maximum output range

 Resulting output range

M.H. Perrott 22
 Variation on a Theme: Enhanced Cascode Amplifiers

Ibias1 Ibias2 R1
Vout
M4
Input Source
M3

Iin Rs
M2 M1

 We can turn the enhanced cascode current source

into an amplifier
- Inject a current input at the source of M 4
 Key aspects of small signal analysis can be done
using Thevenin method
- Simply leverage Thevenin resistance formulas shown on
Slide 16
M.H. Perrott 23
 Small-Signal Analysis of Enhanced Cascode Amp

Ibias1 Ibias2 R1 R1 Rout

Vout Vout
M4 M4
Input Source Input Source
M3 M3

Iin Rs 1 Rthd1 Rin Iin Rs

M2 M1 gm2

 From Thevenin resistance calculations on Slide 16:

- Input impedance is quite low
- Output impedance is probably determined by R 1

 This amplifier is useful for extracting a current signal

while keeping the source voltage nearly constant
M.H. Perrott 24