Chapter 1  Charge of C from DC through R:

0 , 0  Average power delivered to resistance: ,

⁄
 Charge flows from positive polarity towards negative (absorbs energy) 

 Power, P= v*I (units: v*A, J/s, Watts)  DC Steady State: C are OC (i=0), L are SC (V=0)
 P= -v*I, if current reference enters the negative end.
 RL Circuits  ,
 KCL- net current entering node is 0 (Entering is neg.)
 KVL-sum of voltages = 0 for any loop in circuit (va+vb-vc=0)  Charge of L from DC through R: ⁄
,
 V=i*R (current enters positive end of polarity, otherwise –i*R)  ( , , ,
, ⁄
 Ohm’s Law for current:
⁄  , , ,

⁄

Chapter 2  Discharge of L from DC through R:
 0, 0 Thus all of the power delivered by the
 Series resistances: Req=R1+R2+R3
 Forced response(steady state)-sinusoidal source persists source is absorbed by the resistance.
 Parallel resistances:
indefinitely  Power-Factor Correction
 Voltage division (series combination of resistances):  Natural response-decays rapidly to zero  Placing capacitors in parallel w/an inductive load to
∗
increase PF.
 Current division (current flowing into a parallel combination of resistances): Chapter 5  Thevenin and Norton Circuits
 Sinusoidal currents and voltages
∗  ∶ :
 cos , ,
 Supernode: drawing a dash line around several nodes, including elements in-  Maximum Average Power Transfer
between
,
 2 , 
 Thevenin circuits: independent voltage source in series w/a resistance. No ∗
current flows through the thevenin resistance.  , 1⁄  = j
∶  sin cos 90°  2

 To zero independent sources, we replace voltage sources w/short circuits and 

replace current sources w/open circuits.
 Can NOT zero dependent sources. MUST: write current equation at node 1, 
write expression for controlling variable ix in terms of voc. Substitute back and
solve. Chapter 14
 Common-mode signal, (average of the input voltages)
Thevenin/Norton circuit Analysis Differential signal, (difference of input voltages)

1a. Determine open-circuit voltage vt=voc Ideal Op Amp:
1b. Determine short circuit current in=isc  * ∞ input impedances
√ * ∞ gain for
1c. zero independent sources and find thevenin resistance, Rt
2. Use vt = Rt*In to compute remaining value  360° * 0 gain for
3. Thevenin consists of vt in series w/Rt * 0 output impedances
4. Norton consists of In in parallel w/ Rt  * ∞ bandwidth
Superposition Principle: rT is sum of r’s to each independent source acting Equiv. circuit for ideal amp consists only of controlled source = ∗Open-loop gain,
individually rT=r1+r2+…+rn  Phasors
Resistivity, :  cos , ∠ INVERTING AMPLIFIERS
Neg. Feedback: return part of output to input in opposition to source signal.
Wheatstone bridge: circuit used to measure unknown resistances  cos , ∠ Pos. Feedback: signal returned aids orig. source signal
,
 Impedance for Inductor: ∠90° -if pos enters pos. op. amp. terminal
-very large pos. or neg. Vo results
 Impedance for Capacitor: ∠ 90° Summing-point constraint:
 , , 1. verify negative feedback present
2. Assume: (ideal-∞) – ( - 0) – ( - 0)
 : 0
Chapter 3 3. Solve quantities of interest (KVL/KCL/Ohm)
 Capacitor  Power in AC Circuits The Basic Inverter

 Stored Charge, q=Cv  | |

 I=  Resistors
 v  cos
 Power, p  cos
 cos
 Energy is stored in electric field between plates Closed-loop gain, (neg. means inverting)
 I
 Energy delivered,
 cos
( is 0!)
  sin
NON-INVERTING AMPLIFIERS
  sin 2

 C
∗
, d=dist between plates, A=area  Capacitors
 cos
 ∗ , 1 , 8.85 ∗ 10
 sin
 Inductor The basic non-inverting amplifier
 sin 2
 Neg. feedback, becomes pos. then is large pos. also b/c feedback signal
opposes original input.
  (if : negative=C, positive=L, 0=R)
0 0 0
 Average Power, cos ∶ , so

 Power Factor, cos ,
 Energy delivered, 1
 Capacitive load – Leading, Inductive load – lagging (non-inverting b/c Av is pos.)
  Ex) 90% lagging, current lags voltage *Non-inverting amplifier is an ideal voltage amplifier

  Peak instantaneous power, reactive power, Voltage follower: unity gain, 1, for non-inverting when 1 0
sin ∶
 Parasitic effects of C and L store energy
 Elements must withstand the current associated w/reactive
 Mutual Inductance: (-M if dots on power even if average power is zero.
opposite ends)  Apparent power = ∶

Chapter 4  A
 Transients-time varying currents and voltages  | |∠ , R=resistance of load,
 RC Circuits  ,
⁄
 Discharge of C from DC through R: ,
,
 Vout     H f   H1 f   H2 f   
H f  
Vin
LP filter  ⋅

        
1 R
fB  fB   
2RC 2 L

 
1        1  
H f   H f  
f
H f    arctan


1  j f fB  1  f fB 
2
 fB 

HP filter 

                  
 
1  
fB 
2RC

R  
fB 
2 L
Vout j f fB      f     
H f    H f  
f fB H f   90  arctan 
Vin 1  j f fB   fB
1  f fB  
2
Convert Hex to Octal ‐> Convert to Binary and regroup 
Decibells  Convert Binary to Hexadecimal, group by fours 
H f  dB  20 log H f         H f  dB  H1 f  dB  H2 f  dB   Convert Binary to Octal, group by threes 
 log  f 2 f1        f   Characteristics of Ideal Amplifiers
#octaves   # decades  log  2 
 log  2    f1 
  Input Output Gain
st Amplifier Type Sense Produces Impedance Impedance Parameter
Bode Plots: 1  Order LP 
Voltage V V ∞ 0 A(voc)
Current I I 0 ∞ A(isc)
Transductance V I ∞ ∞ G(msc)
Transresistance I V 0 0 R(moc)

 
Number of digits required to represent a decimal 
 
1st Order HP  number in binary: log2(x) 
 
 
 

 
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