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Indian Institute of Technology Kharagpur

POWER SYSTEM PROTECTION

Assignment -1

TYPE OF QUESTION:MCQ

Number ofquestions: 10 Total mark: 10 X 2 = 20

QUESTION 1:

A fault is detected in 2 cycles of a 50 Hz power system and the circuit breaker clears in 2.5 cycles. Calculate
the fault clearing time for the case.

(A) 60 ms (B) 90 ms (C) 120 ms (D) 150 ms

Correct answer:(B) 90 ms

Detailed Solution:
Each cycle in 50 Hz system=1/50 s =20 ms.
Fault clearing time = detection time + breaker opening time
= 4.5 cycles= 4.5x20ms
= 90ms
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QUESTION 2:

In an overcurrent protection scheme to improve the dependability,

(A) fuse setting should be changed from 5 A to 4 A

(B) fuse setting should be changed from 5 A to 6 A
(C) fuse characteristics should be changed without changing its rating of 5A
(D) load should be increased

Correct answer:(A) fuse setting should be changed from 5 A to 4 A

Detailed Solution:

For dependability improvement, lower level fault current should also be detected. Note in such case the
relay may compromise security, which is not to trip for fault in other elements or non-fault situations.
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QUESTION 3:

Calculate the negative sequence component (with phase-a as reference) for the given voltage phasors for a
system with abc as phase sequence

Va = 207.76∠-55.940kV, Vb = 164.25∠175.34 0kV, Vc = 212.18∠61.42 0kV

(A) 194.37∠ -59.350kV (B) 14.11∠-93.170kV

(C) 194.37∠-179.350kV (D) 14.11∠26.830kV.

Correct answer:(B) 14.11∠-93.170kV

Detailed Solution:𝑉𝑎2 = (𝑉𝑎 + 𝛼 2 𝑉𝑏 + 𝛼𝑉𝑐 )⁄3, 𝛼 = 1∠1200

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QUESTION 4:

Calculate the phase-b current phasor for the given sequence data sets with abc as phase sequence

Ic1 = 2.51∠23.870kA, Ic2 = 0.71∠-118.17 0kA, Ia0 = 0.67∠121.980kA

(A) 1.91∠-87.610kA (B) 3.83∠136.120kA

(C) 1.88∠31.040kA (D) 2.23∠121.830kA.

Correct answer:(B) 3.83∠136.120kA

Detailed Solution:𝐼𝑏1 = 𝛼𝐼𝑐1 , 𝐼𝑏2 = 𝛼 2 𝐼𝑐2 , 𝐼𝑏0 = 𝐼𝑎0 , Ib = Ib1+Ib2+Ib0

𝛼 = 1∠1200
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QUESTION 5:

With abc as phase sequence, the positive sequence current calculated (with phase-a as reference) for the
phase-b-to-phase-c (bc) fault in a radial system, is 3∠440kA. The phase-B current is

(A) 5.2∠1340kA (B) 0 (C) 5.2∠-460kA (D) 3∠-1360kA

Correct answer:(C) 5.2∠-460kA

Detailed Solution:For bc fault, Ia1 = -Ia2, Ia0 = 0 Ib1 = α2 Ia1 , Ia2 = αIa2 , Ib0 = Ia0 .

Ib = Ib1 + Ib2 + Ib0

𝛼 = 1∠1200
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QUESTION 6:

For a 4 kHz sampling rate for 50 Hz power system, the sampling interval between two consecutive samples
is how much?

(A) 0.25ms (B) 0.025ms (C) 2.5 ms (D) 2ms

Correct answer:(A) 0.25ms

Detailed Solution:

∆t = 1/4000 s (Note For 50 Hz system, 1 cycle =20ms, 4000 kHzsampling rate implies 80 samples per
cycle.)
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QUESTION 7:

The relay recorded data of a phase current is plotted below. What is the fault detection and decision time for
the relay?

(A) 984 ms and 1 s (B) 4 ms and 20 ms (C) 984 ms and 20 ms (D) 4 ms and 1 s

Correct answer:(B) 4 ms and 20 ms

Detailed Solution:
Fault detection time for the relay = Fault detection instant – fault inception instant
= 0.984 s – 0.98 s = 4ms

Decision time for the relay = Decision instant – fault inception instant
= 1s – 0.98 s = 20 ms
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QUESTION 8:

The relay recorded data of a phase current is plotted below, with a fault incepted at 0.98s. If the fault
detection algorithm uses sample to sample comparison, what is the maximum value of |in – i(n-1)|?
(n is the current measurement sample)

(A) 3.5 kA (B) 2 kA (C) 2.5 kA (D) 1.5 kA

Correct answer:(C) 2.5 kA

Detailed Solution:

Note: The required threshold can be set accordingly and the maximum value for fault detection must be
less than 3 kA.
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QUESTION 9:

The relay recorded data of a phase current is plotted below, with a fault incepted at 0.98s. If the fault
detection algorithm uses cycle to cycle comparison, what is the maximum value of |in – i(n-N)|?
(n is the current measurement sample, N= number of samples per cycle)

(A) 0.8 kA (B) 1.2 kA (C) 0.3 kA (D) 1.8 kA

Correct answer:(B) 1.2 kA

Detailed Solution:

According to the figure, maximum value for fault detection must be less than 1.36 kA. Effect of noise
and measurement uncertainty, must be considered.
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QUESTION 10:

For an 8 bit ADCwith largest possible input V, the quantization error will be

(A) (1/16)V (B) (1/128)V (C) (1/256)V (D) (1/512)V

Correct answer:(C) (1/256)V

Detailed Solution:q = 2−8 V