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    The document discusses the connections and pins used for interfacing ROM memories with microcontrollers like the 8051. It explains that ROM memories have address pins to specify the memory location, data pins to output the stored data, and control pins like Output Enable and Chip Select. It also describes how the 8051 uses its ports and control pins like PSEN, ALE, and RD to latch the address from its ports into an external latch IC and then read the data from the ROM memory.

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    The document discusses the connections and pins used for interfacing ROM memories with microcontrollers like the 8051. It explains that ROM memories have address pins to specify the memory location, data pins to output the stored data, and control pins like Output Enable and Chip Select. It also describes how the 8051 uses its ports and control pins like PSEN, ALE, and RD to latch the address from its ports into an external latch IC and then read the data from the ROM memory.

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    © All Rights Reserved
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    15 views15 pages

    Pdf&rendition 1 3

    Uploaded by

    Anuj Nikam
    The document discusses the connections and pins used for interfacing ROM memories with microcontrollers like the 8051. It explains that ROM memories have address pins to specify the memory location, data pins to output the stored data, and control pins like Output Enable and Chip Select. It also describes how the 8051 uses its ports and control pins like PSEN, ALE, and RD to latch the address from its ports into an external latch IC and then read the data from the ROM memory.

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    of 15

    Mrs. Vaishali S.

    Salunke
    Asst. Prof. ,Department of Electronics ,
    P.E.S ., Modern College of Arts, Science and Commrce,
    Ganeshkhind ,Pune-16
    Connections/Pins available with ROM Memories

    Output Enable (Active low) OE

    Chip Select (Active low) CS

    ROM
    . A0
    n-Bit (lines) of Address Bus . to
    An-1

    D0
    8-Bit Data Bus to
    D7
    Connections/Pins available with 64ROM Memories

    Size /capacity of memory=2n


    Where n = Number of address lines OE
    If n=16 then CS
    216 =64K ; Size/capacity of memory
    64K
    . A0
    ROM
    n-Bit (lines) of Address Bus . to
    An-1

    D0
    8-Bit Data Bus to
    D7
    Connections/Pins available with ROM Memories

     n=16
    Let the 16 address lines beA0 -A15
    OE

    CS

    64K
    A0
    .
    to ROM
    16-Bit (lines) of Address .
    A15
    Bus

    D0
    8-Bit Data Bus to
    D7
    Pins with 8051
    WR
    RD Write /Read control for RAM
    PSEN Program Store Enable
    ALE Address Latch Enable
    P0.0 . Lower Byte(8-bit) of Address (A0-A7)
    . &
    P0.7 8-Bit Data (D0-D7)

    P2.0
    EA . Upper Byte(8-bit) of Address
    . A8-A15
    P2.7

    8051
    Port 0 to A0-A7Address of ROM
    WR
    RD
    PSEN OE
    ALE CS
    P0.0 A0 64K
    A7
    P0.7 ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    8051
    Latch IC 74LS373
    PSEN OE

    ALE 74LS373 CS
    G
    P0.0 A0
    D
    64K
    P0.7 A7
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    ROM
    Use of ALE pin to use P0 for both
    Address and Data
    PSEN OE

    ALE 74LS373 CS
    G
    P0.0 A0
    D 64K
    P0.7 A7
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    ROM
    ALE Pin for using Port 0 for both
    Address and Data connection
    WR
    RD
    PSEN OE
    ALE 74LS373 CS
    G
    P0.0 A0
    D
    P0.7 A7 64K
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    8051
    Upper byte of Address from Port 2
    WR
    RD
    PSEN OE
    ALE 74LS373 CS
    G
    P0.0 A0
    D
    P0.7 A7 64K
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    8051
    External ROM Interface
    WR
    RD
    PSEN OE
    ALE 74LS373 CS
    G
    P0.0 A0
    D
    P0.7 A7

    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    8051
    Reading Data from ROM memory
    Send and Latch the Address
    PSEN 1. Send address to 3. 74373 latches the OE
    RAM address and send
    2. Send ALE signal to RAM
    ALE 74LS373 CS
    G
    P0.0 A0
    D 64K
    P0.7 A7
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.7 A15

    ROM
    Read data from ROM
    WR WR
    1. Send RD Signal
    PSEN OE

    ALE 74LS373 CS
    G
    P0.0 A0
    D 64K
    P0.7 A7
    2. ROM sends data to 8051
    ROM
    D0
    D7
    EA
    P2.0 A8
    P2.1 A9

    ROM
    Thank You

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