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  • EXPERIMENT NO 8 Mux and Demux in Verilog

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    Ajay Kumar
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    This document describes an experiment to develop Verilog modules for a 4x1 multiplexer and 1x4 demultiplexer. It includes the logic diagrams and Verilog code for the multiplexer and demultiplexer, as well as test benches and output waveforms to verify their functionality. The purpose is to model these devices in Verilog HDL and confirm their truth tables match what is expected.

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    This document describes an experiment to develop Verilog modules for a 4x1 multiplexer and 1x4 demultiplexer. It includes the logic diagrams and Verilog code for the multiplexer and demultiplexer, as well as test benches and output waveforms to verify their functionality. The purpose is to model these devices in Verilog HDL and confirm their truth tables match what is expected.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    40 views4 pages

    EXPERIMENT NO 8 Mux and Demux in Verilog

    Uploaded by

    Ajay Kumar
    This document describes an experiment to develop Verilog modules for a 4x1 multiplexer and 1x4 demultiplexer. It includes the logic diagrams and Verilog code for the multiplexer and demultiplexer, as well as test benches and output waveforms to verify their functionality. The purpose is to model these devices in Verilog HDL and confirm their truth tables match what is expected.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 4

    EXPERIMENT NO.

    MUX AND DEMUX IN VERILOG

    AIM OF THE EXPERIMENT:

    a. Development of verilog modules for a 4x1 MUX.


    b. Development of verilog modules for a 1x4 DEMUX.

    BRIEF DESCRIPTION

    4X1 MULTIPLEXER

    Logic Diagram of 4X1 multiplexer


    1X4 DEMULTIPLEXER

    Logic Diagram of 1X4 de-multiplexer

    VERILOG CODE FOR 4X1 MULTIPLEXER

    Verilog code Test Bench

    VERILOG CODE FOR 1X4 DEMULTIPLEXER

    Verilog code Test Bench

    OUTPUT WAVEFORMS
    4X1 MULTIPLEXER

    1x4 DEMULTIPLEXER

    INFERENCE

    Modelled multiplexer and demultiplexer in verilogHDL and their truth-tables were verified

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