TABLE 4.

1
BJT Bias Configurations

Type Configuration Pertinent Equations

Fixed-bias VCC

VCC - VBE
RC IB =
RB RB
IC = bIB, IE = (b + 1)IB
␤ VCE = VCC - IC RC

Emitter-bias VCC

RC VCC - VBE
RB IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
␤ Ri = (b + 1)RE
VCE = VCC - IC (RC + RE)
RE

Voltage-divider VCC
bias

R1
RC R2VCC APPROXIMATE: bRE Ú 10R2
EXACT: RTh = R1||R2, ETh =
R1 + R2 R2VCC
VB = , V = VB - VBE
ETh - VBE R1 + R2 E
IB =
␤ RTh + (b + 1)RE VE IE
IE = ,I =
IC = bIB, IE = (b + 1)IB RE B b + 1
R2
RE VCE = VCC - IC (RC + RE) VCE = VCC - IC (RC + RE)

Collector-feedback VCC

RC
RF
VCC - VBE
IB =
RF + b(RC + RE)
␤ IC = bIB, IE = (b + 1)IB
VCE = VCC - IC (RC + RE)
RE

Emitter-follower

VEE - VBE
IB =
RB + (b + 1)RE
IC = bIB, IE = (b + 1)IB
RB
RE VCE = VEE - IE RE

–VEE
Common-base VEE - VBE
IE =
RE
RE RC IE
IB = , I = bIB
– + b + 1 C
VEE VCC VCE = VEE + VCC - IE (RC + RE)
+ –
VCB = VCC - ICRC
193
 TABLE 5.1
Unloaded BJT Transistor Amplifiers

Configuration Zi Zo Av Ai
Fixed-bias: Medium (1 k⍀) Medium (2 k⍀) High (- 200) High (100)

RB 7 bre RC 7 r o (RC 7 ro)

VCC
Io = = bRBro
RC = - =
RB re (ro + RC)(RB + bre)
Ii
+ ⬵ bre ⬵ RC
Vo RC ⬵ b
+ Zo
– (RB Ú 10bre) (ro Ú 10RC) ⬵ -
Vi re
Zi (ro Ú 10RC,
–
(ro Ú 10RC) RB Ú 10bre)

Voltage-divider Medium (1 k⍀) Medium (2 k⍀) High (- 200) High (50)

R1 7 R2 7 bre RC 7 r o RC 7 r o b(R1 7 R2)ro

bias: VCC
Io
(ro + RC)(R1 7 R2 + bre)
RC = =
R1 = - =
Ii
re
⬵
b(R1 7 R2)
+ RC

R1 7 R2 + bre
+ Zo RC
Vo (ro Ú 10RC) ⬵ - ⬵
Vi Zi R2 re
RE CE
– – (ro Ú 10RC) (ro Ú 10RC)

Unbypassed High (100 k⍀) Medium (2 k⍀) Low (- 5) High (50)

RB 7 Zb
emitter bias: VCC
= = RC RC bRB
Io RC = - ⬵ -
RB r e + RE RB + Zb
Ii Zb ⬵ b(re + RE) (any level of ro)

RB 7 bRE
+
⬵ RC
+ Zo ⬵ -
Vo RE
Vi
Zi RE (RE W re)
(RE W re)
– –

Emitter- High (100 k⍀) Low (20 ⍀) Low ( ⬵1) High (- 50)

RB 7 Zb = RE 7 r e
follower: VCC
= RE bRB
Ii RB = ⬵ -
RE + r e RB + Zb
Zb ⬵ b(re + RE)

RB 7 bRE
+ ⬵ re
⬵ ⬵ 1
Vi Io RE + (RE W re)
Zi Vo
– Zo (RE W re)
–
Common-base: Low (20 ⍀) Medium (2 k⍀) High (200) Low (- 1)

RE 7 r e
Ii
= = RC RC ⬵ -1
⬵
+ Io RC + re
RE ⬵ re
Vi Zi Zo Vo
VEE VCC
– – (RE W re)

Collector Medium (1 k⍀) Medium (2 k⍀) High (- 200) High (50)

⬵ RC 7 RF
feedback: VCC
Io re RC bRF
RC
RF = ⬵ - =
1 RC re RF + bRC
+ (ro Ú 10RC)
Ii + b RF
(ro Ú 10RC) RF
+ Zo Vo (ro Ú 10RC) ⬵
(RF W RC) RC
Vi Z
o
– –

293
 TABLE 5.2
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

- (RL 储 RC) RB 7 bre RC

re

Including ro:

(RL 7 RC 7 ro)
- RB 7 bre RC 7 r o
re

- (RL 7 RC) R1 7 R2 7 bre RC

re

Including ro:

- (RL 7 RC 7 ro)
R1 7 R2 7 bre RC 7 r o
re

R⬘E = RL 7 RE R⬘s = Rs 7 R1 7 R2

R1 7 R2 7 b(re + R⬘E) RE 储 a + re b
R⬘s
⬵ 1
b

R1 7 R2 7 b(re + R⬘E)
Including ro:
RE 储 a + re b
R⬘s
⬵ 1
b

- (RL 7 RC) RE 7 r e RC
⬵
re

Including ro:

- (RL 7 RC 7 ro)
⬵ RE 7 r e RC 7 r o
re

VCC

- (RL 7 RC)
R1 7 R2 7 b(re + RE) RC
RC RE
R1
Vo
Rs Vi Including ro:

- (RL 7 RC)
R1 7 R2 7 b(re + Re)
Zo
+ RL ⬵ RC
Vs Zi R2 RE
RE
–

294
 TABLE 5.2 (Continued)
BJT Transistor Amplifiers Including the Effect of Rs and RL

Configuration AvL ⴝ Vo >Vi Zi Zo

VCC

- (RL 7 RC)
RC RB 7 b(re + RE1) RC
RB RE1
Vo
Rs Vi

Zo Including ro:

- (RL 7 RC)
RB 7 b(re + RE)
+ RE1 RL
Zi
Vs ⬵ RC
– REt
RE2 CE

VCC

- (RL 7 RC) RF
RC bre 储 RC
re 兩 Av 兩
RF
Vo

Rs Vi Including ro:

- (RL 7 RC 7 ro)
Zo

RC 7 RF 7 r o
+ RL

0 Av 0
RF
Vs
Zi
bre 储
– re

VCC

- (RL 7 RC)
⬵ RC 7 RF
0 Av 0
RF
RC bRE 储
RE
RF
Vo

Rs Vi
Zo Including ro:

- (RL 7 RC)
⬵ RC 7 RF
0 Av 0
+ RL RF
Vs ⬵ ⬵ bRE 储
RE RE
Zi L
–

packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is
called a two-port system because there are two sets of terminals—one at the input and the
other at the output. At this point it is particularly important to realize that
the data surrounding a packaged system is the no-load data.
This should be fairly obvious because the load has not been applied, nor does it come with
the load attached to the package.

Ii Io

+ +
Zi Zo
Vi AvNL Vo

– –

Thévenin

FIG. 5.61
Two-port system.
295
 TABLE 6.3
Field Effect Transistors

Symbol and Input Resistance

Type Basic Relationships Transfer Curve and Capacitance
JFET
(n-channel)

Ri 7 100 M⍀
Ci: (1 - 10) pF

MOSFET
depletion type
(n-channel)

Ri 7 1010 ⍀
Ci: (1 - 10) pF

MOSFET
enhancement type
(n-channel)

Ri 7 1010 ⍀
Ci: (1 - 10) pF

MESFET
depletion type
(n-channel)

Ri 7 1012 ⍀
Ci: (1 - 5) pF

MESFET
enhancement type
(n-channel)

Ri 7 1012 ⍀
Ci: (1 - 5) pF
 TABLE 7.1
FET Bias Configurations

Type Configuration Pertinent Equations Graphical Solution

VDD ID
RD IDSS
JFET VGSQ = - VGG
Fixed-bias RG VDS = VDD - IDRS Q-point
VGG –
+ VP VGG 0 VGS

ID
VDD
IDSS
RD
JFET VGS = - IDRS
I'D
Self-bias VDS = VDD - ID(RD + RS) Q-point
RG RS
VP V' 0 VGS
GS

VDD ID
RD R2VDD IDSS
JFET R1 VG =
R1 + R2 VG
Voltage-divider
VGS = VG - IDRS Q-point RS
bias R2 RS
VDS = VDD - ID(RD + RS)
VP 0 VG VGS

VDD ID
RD IDSS
JFET VGS = VSS - IDRS VSS
Q-point
Common-gate VDS = VDD + VSS - ID(RD + RS) RS
RS
–VSS VP 0 VSS VGS

ID
VDD VGS = - IDRS IDSS
RD
JFET VD = VDD
(RD = 0 ⍀) VS = IDRS I'D
Q-point
VDS = VDD - ISRS
VP V'GS 0 VGS

VDD ID
RD Q-point IDSS
JFET
VGSQ = 0 V
Special case VGS = 0 V
IDQ = IDSS Q
(VGSQ = 0 V) RG
VGG
VP 0 VGS

ID
VDD
Depletion-type Q-point
MOSFET VGSQ = + VGG IDSS
Fixed-bias RG VDS = VDD - IDRS
RS
(and MESFETs)
VP 0 VGG VGS

ID
Depletion-type VDD R2VDD
VG
MOSFET R1 RD VG = RS Q-point
R1 + R2 IDSS
Voltage-divider
VGS = VG - ISRS
bias R2 RS
VDS = VDD - ID(RD + RS)
(and MESFETs) VP 0 VG VGS

VDD ID
Enhancement VDD
RD
type MOSFET RG RD ID(on)
VGS = VDS
Feedback Q-point
VGS = VDD - IDRD
configuration
(and MESFETs) 0 VGS(Th)
VGS(on)
VDD VGS

Enhancement VDD VG ID
RS
type MOSFET R1
RD R2VDD
VG =
Voltage-divider R1 + R2 Q-point
bias R2 RS VGS = VG - IDRS
(and MESFETs) 0 VGS(Th) VG VGS

450
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k⍀) Medium (- 10)
RD
C2 High (10 M⍀)
C1
Vo = RD 储 r d = - gm(rd 储 RD)
Vi = RG
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k⍀) Medium (- 10)
[JFET or D-MOSFET] RD
C2
High (10 M⍀)
Vo = RD 储 r d = - gm(rd 储 RD)
C1 = RG
Vi
Zo ⬵ RD ⬵ - gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (- 2)
c 1 + gmRS + dR
Self-bias +VDD RS
unbypassed RS rd D gmRD
[JFET or D-MOSFET] High (10 M⍀)
c 1 + gmRS + d
RD = =
C2 RS RD RD + RS
Vo + 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd = ⬁ ⍀ ⬵ -
RG 1 + gmRS 3 rd Ú 10 (RD + RS)4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k⍀) Medium (- 10)
RD
C2 High (10 M⍀)
R1
Vo = RD 储 r d = - gm(rd 储 RD)
C1
Vi = R1 储 R2
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+ 10)
Common-gate +VDD Low (1 k⍀)
[JFET or D-MOSFET] Medium (2 k⍀) RD
RD r d + RD gmRD +
RS 储 c d rd
C1 Q1 C2
Vi
=
1 + gmrd = RD 储 r d =
Vo RD
1 +
⬵ RD rd
1
Zi RS Zo ⬵ RS 储 (Rd Ú 10 RD)

RG CS gm ⬵ gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k⍀)
[JFET or D-MOSFET] +VDD
High (10 M⍀) gm(rd 储 RS)
C1 rd 储 RS 储 1>gm =
Vi
= 1 + gm(rd 储 RS)
C2 = RG
Zi RG
Vo ⬵ RS 储 1>gm gmRS
(rd Ú 10 RS)
RS ⬵
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M⍀)
E-MOSFET Medium (2 k⍀) Medium (- 10)
RD RF + r d 储 RD
C2
RF =
1 + gm(rd 储 RD) = RF 储 r d 储 RD = - gm(RF 储 rd 储 RD)
Vo
C1
Vi RF ⬵ RD ⬵ - gmRD
(RF, rd Ú 10RD)
Zo ⬵ (RF, rd Ú 10RD)
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k⍀) Medium (−10)
RD
C2 Medium (1 M⍀)
R1 D Vo
= RD 储 r d = - gm(rd 储 RD)
C1
G = R1 储 R2
Vi
Zo ⬵ RD ⬵ - gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515