Chapter 2

Basic semiconductor physics (II)

Semester: Fall 2019

Professor: Sung-Jin Choi
School of EE, Kookmin University

Class Notes, IC fabrication

1
Prof. S.-J. Choi (All rights reserved)
 Crystallographic planes

Si atom

No atoms on the same plane

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 Crystallographic notation

면방향

벡터방향

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 Electrical contacts to Si
rectifying
High WF metal

Majority carriers cannot move easily from the metal into the n-Si, due to a large potential
barrier. For the same metal, this barrier is smaller for contacts to p-type Si

High WF metal non-rectifying

Depending on the metal, doping types, the Schottky diode

characteristics are determined. 4
 Electrical contacts to Si
E0

Metal WF
Ec EF n-type

EF EF p-type
Ev

High WF metal Si

Energy band diagram for electrical contact

Class Notes, IC fabrication, Prof. S.-J. Choi
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 Electrical contacts to Si

ohmic

The depth of the depletion region (Xd) decreases with increasing dopant
concentration. For very high doping, Xd is small enough (<10 nm) to allow
quantum tunneling of carriers.
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 Electrical contacts to Si

Inverter configuration
Ohmic contacts

Class Notes, IC fabrication, Prof. S.-J. Choi

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 Device isolation

GND VOUT VDD

VIN

Class Notes, IC fabrication, Prof. S.-J. Choi

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 Device isolation
Isolation을 위한 SiO2,
gate poly 아래 Si이 inversion이 되지 않는 것이 핵심
Inversion을 막기위한
Field oxide

N-ch. P-ch.

Inversion region Inversion region

Class Notes, IC fabrication, Prof. S.-J. Choi

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 LOCOS
• LOCOS: local oxidation of silicon

Buffer oxide

LOCOS regions
Active region
(field oxide, FOX)
I. Preparation of silicon substrate
II. CVD deposition of SiO2 (or growth of SiO2) for buffer oxide
III. CVD deposition of Si3N4 (nitride)
IV. Etching of nitride layer and SiO2 layer (active region define)
V. Thermal growth of SiO2 (field oxide, FOX)
VI. Removal of nitride mask
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 LOCOS
LOCOS region Pros.: simple process
Cons.: Bird beak
 Gate oxide is thicker than near the
edges of the device
 Reduced active area & integratability
A A’

B
B B’
Bird beak Gate Bird beak
A A’
S D

LOCOS (SiO2)
Reduced active area B’

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 STI process
STI
• Shallow trench isolation (STI)
Trench

HDP oxide
1. Cover the wafer with buffer oxide and nitride
2. Etch nitride/oxide/silicon  Anisotropic etch (0.4-0.5 μm)
3. Grow a thin thermal oxide layer
4. A CVD dielectric film (using HDP) is used to fill the trench
*HDP: high density plasma
5. Chemical mechanical polishing (CMP) to polish
back of the dielectric layer
6. Densify the dielectric material at 900 °C STI
/strip the nitride and oxide
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 LOCOS vs STI
Pros.: Bird beak free / Cons.: Complex process, stress, etc.
STI

LOCOS LOCOS STI STI

Comparison btw. LOCOS and STI

Bird beak free

High electric field
Gate
 Early inversion S D
 Error for target VT
STI (SiO2)

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 Process flow example
For electrical contact
For device isolation

n-channel MOSFET

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 Process flow example
• Simple n-channel MOSFET process flow

Si3N4

Channel stop
Implantation (VT를 증가)

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 Process flow example
Called field oxide (FOX)

Isolation by LOCOS

Polysilicon
gate

S D

바깥쪽은 SiO2
Called “Self-align process”

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 Process flow example

via
via via
via

Aluminum

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