Digital CK Ts

Digital Circuits: Part 1
M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
Department of Electrical Engineering

Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay

Digital circuits
1
high
low
0
t t
analog signal digital signal

Digital circuits
1
high
low
0
t t
* An analog signal x(t) is represented by a real number at a given time point.

Digital circuits
1
high
low
0
t t

* A digital signal is “binary” in nature, i.e., it takes on only two values: low (0) or high (1).

Digital circuits
1
high
low
0
t t

* Although we have shown 0 and 1 as constant levels, in reality, that is not required. Any value in the low
(high) band will be interpreted as 0 (1) by digital circuits.

Digital circuits
1
high
low
0
t t

* Although we have shown 0 and 1 as constant levels, in reality, that is not required. Any value in the low
(high) band will be interpreted as 0 (1) by digital circuits.
* The definition of low and high bands depends on the technology used, e.g.,
TTL (Transistor-Transistor Logic)
CMOS (Complementary MOS)
ECL (Emitter-Coupled Logic)

A simple digital circuit
5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)
* If Vi is low (“0”), Vo is high (“1”).

If Vi is high (“1”), Vo is low (“0”).

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* The circuit is called an “inverter” because it inverts the logic level of the input. If the input is 0, it makes
the output 1, and vice versa.

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* Digital circuits are made using a variety of devices. The simple BJT inverter is only an illustration.

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* Digital circuits are made using a variety of devices. The simple BJT inverter is only an illustration.
* Most of the VLSI circuits today employ the MOS technology because of the high packing density, high
speed, and low power consumption it offers.
Digital circuits
V1
t
original data
Digital circuits
V1
t
original data
V2
t
corrupted data
Digital circuits
V1
t
original data
V2
V2
Vref V3
Vref
t
corrupted data comparator
Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
corrupted data comparator recovered data

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
* A major advantage of digital systems is that, even if the original data gets distorted (e.g., in transmitting
through optical fibre or storing on a CD) due to noise, attenuation, etc., it can be retrieved easily.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
* There are several other benefits of using digital representation:

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can use computers to process the data.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can store in a variety of storage media.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can store in a variety of storage media.
- can program the functionality. For example, the behaviour of a digital filter can be changed simply
by changing its coefficients.
Logical operations
Operation NOT AND OR
Gate
Truth table
Notation
Logical operations
Gate A Y
A Y
Truth table 0 1
1 0
Notation Y=A
Logical operations
A
Gate A Y Y
B
A B Y
A Y 0 0 0
Truth table 0 1 0 1 0
1 0 1 0 0
1 1 1
Notation Y=A Y= A·B

= AB
Logical operations
A A
Gate A Y Y Y
B B
A B Y A B Y
A Y 0 0 0 0 0 0
Truth table 0 1 0 1 0 0 1 1
1 0 1 0 0 1 0 1
1 1 1 1 1 1
Notation Y=A Y= A·B Y=A+B

= AB

Logical operations
Operation NAND NOR XOR
Gate
Truth table
Notation
Logical operations
A
Gate Y
B
A B Y
0 0 1
Truth table 0 1 1
1 0 1
1 1 0
Notation Y= A·B
= AB
Logical operations
A A
Gate Y Y
B B
A B Y A B Y
0 0 1 0 0 1
Truth table 0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Notation Y= A·B Y= A+B

= AB
Logical operations
A A A
Gate Y Y Y
B B B
A B Y A B Y A B Y
0 0 1 0 0 1 0 0 0
Truth table 0 1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0
Notation Y= A·B Y= A+B Y=A⊕B

= AB = AB + AB

Logical operations
* The AND operation is commutative.

→ A · B = B · A.

Logical operations

→ A · B = B · A.
* The AND operation is associative.
→ (A · B) · C = A · (B · C ).

Logical operations

→ A · B = B · A.
→ (A · B) · C = A · (B · C ).
* The OR operation is commutative.
→ A + B = B + A.

Logical operations

→ A · B = B · A.
→ (A · B) · C = A · (B · C ).
* The OR operation is commutative.
→ A + B = B + A.
* The OR operation is associative.
→ (A + B) + C = A + (B + C ).

Boolean algebra (George Boole, 1815-1864)
* Theorem: A = A.

* Theorem: A = A.
The theorem can be proved by constructing a truth table:
A A A
0 1 0
1 0 1

* Theorem: A = A.
A A A
0 1 0
1 0 1
Therefore, for all possible values that A can take (i.e., 0 and 1), A is the same as A.
⇒ A = A.

* Theorem: A = A.
A A A
0 1 0
1 0 1
⇒ A = A.
* Similarly, the following theorems can be proved:
A+0=A A·1=A
A+1=1 A·0=0
A+A=A A·A=A
A+A=1 A·A=0

* Theorem: A = A.
A A A
0 1 0
1 0 1
⇒ A = A.
* Similarly, the following theorems can be proved:
A+0=A A·1=A
A+1=1 A·0=0
A+A=A A·A=A
A+A=1 A·A=0
Note the duality: (+ ←→ ·) and (1 ←→ 0).

De Morgan’s theorems
A B A+B A+B A B A·B A·B A·B A+B

0 0
0 1
1 0
1 1


0 0 0
0 1 1
1 0 1
1 1 1


0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0


0 0 0 1 1
0 1 1 0 1
1 0 1 0 0
1 1 1 0 0


0 0 0 1 1 1
0 1 1 0 1 0
1 0 1 0 0 1
1 1 1 0 0 0


0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0


0 0 0 1 1 1 1 0
0 1 1 0 1 0 0 0
1 0 1 0 0 1 0 0
1 1 1 0 0 0 0 1


0 0 0 1 1 1 1 0 1
0 1 1 0 1 0 0 0 1
1 0 1 0 0 1 0 0 1
1 1 1 0 0 0 0 1 0


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0
* Comparing the truth tables for A + B and A B, we conclude that A + B = A B.


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

* Similarly, A · B = A + B.


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

* Similar relations hold for more than two variables, e.g.,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,
A + B + C + D = A · B · C · D,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,
A + B + C + D = A · B · C · D,
(A + B) · C = (A + B) + C = A · B + C .

Distributive laws
1. A · (B + C ) = A B + A C .

Distributive laws
1. A · (B + C ) = A B + A C .
A B C B +C A · (B + C ) AB AC AB + AC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 1 0 0 0
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 1 1 1 0 1
1 1 0 1 1 1 0
1 1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

Distributive laws
2. A + B · C = (A + B) · (A + C ).
A B C BC A+BC A+B A+C (A + B) (A + C )

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 1 1 1
1 0 0 0 1 1
1 0 1 0 1 1
1 1 0 0 1 1
1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 0 1 1 1
1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

Useful theorems
* A + A B = A.
To prove this theorem, we can follow two approaches:

Useful theorems
* A + A B = A.
(a) Construct truth tables for LHS and RHS for all possible input combinations, and show that they are
the same.

Useful theorems
* A + A B = A.
the same.
(b) Use identities and theorems stated earlier to show that LHS=RHS.

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A
* A · (A + B) = A.

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A
* A · (A + B) = A.
Proof: A · (A + B) = A · A + A · B
= A + AB
=A

Duality
A + AB = A ←→ A · (A + B) = A.
Note the duality between OR and AND.

Duality
A + AB = A ←→ A · (A + B) = A.
Dual of A + (A B) (LHS): A B → A + B
A + A B → A · (A + B).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
Dual of A (RHS) = A (since there are no operations involved).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.
Similarly, consider A + A = 1, with (+ ←→ .) and (1 ←→ 0).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of LHS = A · A.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of RHS = 0.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of RHS = 0.
⇒ A · A = 0.

Useful theorems
* A + A B = A + B.

Useful theorems
* A + A B = A + B.
Proof: A + A B = (A + A) · (A + B) (by distributive law)

= 1 · (A + B)
=A+B
Dual theorem: A · (A + B) = A B.

Useful theorems
* A + A B = A + B.

= 1 · (A + B)
=A+B
* A B + A B = A.

Useful theorems
* A + A B = A + B.

= 1 · (A + B)
=A+B
* A B + A B = A.
Proof: A B + A B = A · (B + B) (by distributive law)

=A·1
=A
Dual theorem: (A + B) · (A + B) = A.

A game of words
In an India-Australia match, India will win if one or more of the following conditions are met:

A game of words
(a) Tendulkar scores a century.

A game of words
(b) Tendulkar does not score a century AND Warne fails (to get wickets).

A game of words
(c) Tendulkar does not score a century AND Sehwag scores a century.

A game of words
Let T ≡ Tendulkar scores a century.
S ≡ Sehwag scores a century.
W ≡ Warne fails.
I ≡ India wins.

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)
=T +W +T +S
=T +W +S

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)
=T +W +T +S
=T +W +S
i.e., India will win if one or more of the following hold:

(a) Tendulkar strikes, (b) Warne fails, (c) Sehwag strikes.

Logical functions in standard forms
Consider a function X of three variables A, B, C :

X = AB C + AB C + AB C + AB C
≡ X1 + X2 + X3 + X4


≡ X1 + X2 + X3 + X4
This form is called the “sum of products” form (“sum” corresponding to OR

and “product” corresponding to AND).


≡ X1 + X2 + X3 + X4

We can construct the truth table for X in a systematic manner:


≡ X1 + X2 + X3 + X4

(1) Enumerate all possible combinations of A, B, C .
Since each of A, B, C can take two values (0 or 1), we have 23 possibilities.


≡ X1 + X2 + X3 + X4

(2) Tabulate X1 = A B C , etc. Note that X1 is 1 only if A = B = C = 1 (i.e., A = 0, B = 1, C = 0),
and 0 otherwise.


≡ X1 + X2 + X3 + X4

(2) Tabulate X1 = A B C , etc. Note that X1 is 1 only if A = B = C = 1 (i.e., A = 0, B = 1, C = 0),
and 0 otherwise.
(3) Since X = X1 + X2 + X3 + X4 ,
X is 1 if any of X1 , X2 , X3 , X4 is 1; else X is 0.
→ tabulate X .

“Sum of products” form
X = X1 + X2 + X3 + X4 = A B C + A B C + A B C + A B C
A B C X1 X2 X3 X4 X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C X1 X2 X3 X4 X
0 0 0
0 0 1
0 1 0 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C X1 X2 X3 X4 X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A B C X1 X2 X3 X4 X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A B C X1 X2 X3 X4 X
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 0 0 0
1 1 0 0 0 0 1
1 1 1 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 1 0
1 0 1 0 0 0 0
1 1 0 0 0 0 1
1 1 1 0 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 1 0 0 1
1 0 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 1 1
1 1 1 0 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 1 0 0 1
1 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0
1 1 0 0 0 0 1 1
1 1 1 0 0 0 0 0

Consider a function Y of three variables A, B, C :

Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
This form is called the “product of sums” form (“sum” corresponding to OR,


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
We can construct the truth table for Y in a systematic manner:


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
(2) Tabulate Y1 = A + B + C , etc. Note that Y1 is 0 only if A = B = C = 0;
Y1 is 1 otherwise.


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
(2) Tabulate Y1 = A + B + C , etc. Note that Y1 is 0 only if A = B = C = 0;
Y1 is 1 otherwise.
(3) Since Y = Y1 Y2 Y3 Y4 ,
Y is 0 if any of Y1 , Y2 , Y3 , Y4 is 0; else Y is 1.
→ tabulate Y .

“Product of sums” form
Y = Y1 Y2 Y3 Y4 = (A + B + C) (A + B + C) (A + B + C) (A + B + C)
A B C Y1 Y2 Y3 Y4 Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1 0
1 1 0 1 1
1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 1
1 1 1 1 1 1 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1
1 1 1 1 1 1 0 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1 1
1 1 1 1 1 1 0 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1 1
1 1 1 1 1 1 0 0
Note that Y is identical to X (seen two slides back). This is an example of how the same function can be written in two
seemingly different forms (in this case, the sum-of-products form and the product-of-sums form).
Standard sum-of-products form

X = AB C + AB C + AB C


This form is called the standard sum-of-products form, and each individual term (consisting of all three
variables) is called a “minterm.”


In the truth table for X , the numbers of 1s is the same as the number of minterms, as we have seen in an
example.


example.
X can be rewritten as,
X = A B C + A B (C + C )
= A B C + A B.


example.
X = A B C + A B (C + C )
= A B C + A B.
This is also a sum-of-products form, but not the standard one.

Standard product-of-sums form

X = (A + B + C ) (A + B + C ) (A + B + C )


X = (A + B + C ) (A + B + C ) (A + B + C )
This form is called the standard product-of-sums form, and each individual term (consisting of all three
variables) is called a “maxterm.”


X = (A + B + C ) (A + B + C ) (A + B + C )
In the truth table for X , the numbers of 0s is the same as the number of maxterms, as we have seen in an
example.


X = (A + B + C ) (A + B + C ) (A + B + C )
example.
X = (A + B + C ) (A + B + C ) (A + B + C )
= (A + B + C ) (A + C + B) (A + C + B)
= (A + B + C ) (A + C + B B)
= (A + B + C ) (A + C ).


X = (A + B + C ) (A + B + C ) (A + B + C )
example.
X = (A + B + C ) (A + B + C ) (A + B + C )
= (A + B + C ) (A + C + B) (A + C + B)
= (A + B + C ) (A + C + B B)
= (A + B + C ) (A + C ).
This is also a product-of-sums form, but not the standard one.

The “don’t care” condition
I want to design a box (with inputs A, B, C , and output S) which will help in scheduling my appointments.
A ≡ I am in town, and the time slot being suggested for the appointment is free.
B ≡ My favourite player is scheduled to play a match (which I can watch on TV).
C ≡ The appointment is crucial for my business.
S ≡ Schedule the appointment.

The following truth table summarizes the expected functioning of the box.
A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1
Note that we have a new entity called X in the truth table.

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

X can be 0 or 1 (it does not matter) and is therefore called the “don’t care” condition.

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

X can be 0 or 1 (it does not matter) and is therefore called the “don’t care” condition.
Don’t care conditions can often be used to get a more efficient implementation of a logical function.

M. B. Patil


Karnaugh maps
* A Karnaugh map (“K-map”) is a representation of the truth table of a logical

function.

Karnaugh maps

function.
* A K-map can be used to obtain a “minimal” expression of a function in the
sum-of-products form or in the product-of-sums form.

Karnaugh maps

function.
* A “minimal” expression has a minimum number of terms, each with a minimum
number of variables. (For some functions, it is possible to have more than one
minimal expressions, i.e., more than one expressions with the same complexity.)

Karnaugh maps

function.
* A “minimal” expression has a minimum number of terms, each with a minimum
number of variables. (For some functions, it is possible to have more than one
minimal expressions, i.e., more than one expressions with the same complexity.)
* A minimal expression can be implemented with fewer gates.

K-maps
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 X
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0
1 0 0 X 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1 X
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1 X
1 0 0 X 1 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
* A K-map is the same as the truth table of a function except for the way the entries are arranged.
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
* A K-map is the same as the truth table of a function except for the way the entries are arranged.
* In a K-map, the adjacent rows or columns differ only in one variable. For example, in going from the
column A B = 01 to A B = 11, there is only one change, viz., A = 0 → A = 1.

K-maps: example with four variables
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 AB
CD 00 01 11 10
0 1 0 1 1 00 0 0 0 0
0 1 1 0 0 01 1 1 0 X
0 1 1 1 0 11 1 0 1 1
1 0 0 0 0 10 1 0 0 0
1 0 0 1 X
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 0 0 0
11 0 0 0 0
10 0 0 0 0
X1 = A B C D
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0
X1 = A B C D X2 = A C D
K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
*
No. of variables No. of 1’s
4 20
3 21
2 22

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
*
No. of variables No. of 1’s
4 20
3 21
2 22
* The 1’s can be enclosed by a rectangle in each case.

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3
* We are interested in identifying a minimal expression from the given K-map.

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3
* We are interested in identifying a minimal expression from the given K-map.

* Minimal: smallest number of terms, smallest number of variables in each term
→ smallest number of rectangles containing 2k 1’s, each as large as possible
K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0
What is the logical function (Y ) represented by this K-map?

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0
* There are 21 1’s forming a rectangle → we can combine them.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term is 1 if B = 1, and C = 0.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term does not depend on A.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term does not depend on A.
→ Y =B C

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1
Can the 1s shown in the K-map be combined?

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1

Although the number of 1’s is a power of 2 (21 ), they cannot be combined because they are not adjacent
(i.e., they do not form a rectangle).

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1

Although the number of 1’s is a power of 2 (21 ), they cannot be combined because they are not adjacent
(i.e., they do not form a rectangle).
→ the function (A B C + A B C ) cannot be minimized.

K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0
K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0
Can the 1’s shown in the K-map be combined?

K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0

Let us redraw the K-map by changing the order of the columns cyclically.
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

The two 1’s are, in fact, adjacent and can be combined to give B C .
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

→ Columns A B = 00 and A B = 10 in the K-map on the left are indeed “logically adjacent” (although they are
not geometrically adjacent) since they differ only in one variable (A).
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

→ Columns A B = 00 and A B = 10 in the K-map on the left are indeed “logically adjacent” (although they are
not geometrically adjacent) since they differ only in one variable (A).
We could have therefore combined the 1’s without actually redrawing the K-map.

K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 0 0 0 0
10 0 0 0 0
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 0 0 0 0
10 0 0 0 0
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
X2 = B C
11 0 0 0 0
10 0 0 0 0

K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0
Standard sum-of-products form:

X1 = A B C D + A B C D + A B C D
Since the number of minterms is not a power of 2, they cannot be combined

into a single term; however, they can be combined into two terms:
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


X1 = A B C D + A B C D + A B C D + A B C D (using Y=Y+Y)
= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1 X1 = A C + B C + A B C D + A B D
11 0 0 1 0
10 0 0 0 1

K-maps
AB
CD 00 01 11 10
00 0 0 X 0
Z: 01 1 1 0 0
11 0 0 0 0
10 1 X 1 1
K-maps
AB
CD 00 01 11 10
00 0 0 X 0
Z: 01 1 1 0 0
11 0 0 0 0
10 1 X 1 1
Since X represents a “don’t care” condition, we can assign 0 or 1 to the corresponding minterm to arrive at a
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0 Z = CD + ACD
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.

M. B. Patil


Binary numbers
Decimal (base 10) system
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100
102 101 100

Binary numbers
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100
102 101 100
* Digits: 0,1,2,..,9
* example: 4 1 5 3
most significant least significant

digit digit
Binary numbers
Decimal (base 10) system Binary (base 2) system
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
0
10 2
101 10 2 0
24 23 21
22
* Digits: 0,1,2,..,9
* example: 4 1 5 3
most significant least significant

digit digit
Binary numbers
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
0
10 2
101 10 2 0
24 23 21
22
* Digits: 0,1,2,..,9
* Bits: 0,1
* example: 4 1 5 3
* example: 1 0 0 1 1 0
most significant least significant most significant least significant

digit digit
bit (MSB) bit (LSB)

Addition of binary numbers
104 103 102 101 100 weight

3 1 7 9 first number
8 0 1 5 second number
1 1 carry
1 1 1 9 4 sum
104 103 102 101 100 weight 24 23 22 21 20 weight
3 1 7 9 first number 1 0 1 1 first number (dec. 11)
8 0 1 5 second number 1 1 1 0 second number (dec. 14)
1 1 carry 1 1 1 carry
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
* 1 + 1 + 1 = 11 (dec. 3) → S = 1, C = 1

example
24 23 22 21 20 weight
1 0 1 1 first number
1 1 1 0 second number
1 1 1 0 − carry
1 1 0 0 1 sum
example general procedure
24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number
1 1 1 0 second number BN ··· B2 B1 B0 second number
1 1 1 0 − carry CN CN−1 · · · C1 C0 carry
1 1 0 0 1 sum SN S2 S1 S0 sum
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
AN BN A2 B2 A1 B1 A 0 B0
A A A A
FA B FA B FA B HA B
CN Co S Cin Co S Cin Co S Cin Co S

CN−1 C1 C0
SN S2 S1 S0
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
A A A A
FA B FA B FA B HA B

CN−1 C1 C0
SN S2 S1 S0
* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input carry.
This block is called a “half adder.”
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
A A A A
FA B FA B FA B HA B

CN−1 C1 C0
SN S2 S1 S0
* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input carry.
This block is called a “half adder.”
* Each of the subsequent blocks adds three bits (Ai , Bi , Ci−1 ) and is called a “full adder.”
Half adder implementation
A B Co S
A A0
HA B
0 0 0 0
B0
Co S 0 1 0 1
C0 1 0 0 1
1 1 1 0
S0
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
Implementation 1
A AB
B
S
AB
A
Co
B
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
Implementation 1 Implementation 2
A AB
B A A+B
S B
S
AB Co
AB
A
Co
B

Full adder implementation
A
FA B
Co S Cin
A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
FA B AB
Cin 00 01 11 10
Co S Cin 0 0 1 0 1
S:
1 1 0 1 0
S = A B Cin + A B Cin + A B Cin + A B Cin

A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
FA B AB
Cin 00 01 11 10
Co S Cin 0 0 1 0 1
S:
1 1 0 1 0
S = A B Cin + A B Cin + A B Cin + A B Cin

A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
AB
0 1 1 1 0 Cin 00 01 11 10
0 0 0 1 0
1 0 0 0 1 Co :
1 0 1 1 1
1 0 1 1 0
1 1 0 1 0 Co = A B + B Cin + A Cin
1 1 1 1 1
Implementation of functions with only NAND gates
The NOT, AND, OR operations can be realised by using only NAND gates:
NOT
A= A·A
A A
NOT AND
A= A·A A·B= A·B
A
A A AB
B
NOT AND OR
A= A·A A·B= A·B A+B =A·B
A
A
A A AB A+B
B
B

Implement Y = A B + B C D + A D using only NAND gates.

A= A·A
A·B =A·B
A+B= A·B
Y = AB ·BCD · AD
A= A·A
A·B =A·B
A+B= A·B
Y = AB ·BCD · AD
AB A= A·A
A·B =A·B
A+B= A·B
Y
BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
A+B= A·B
Y
BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD
A
D AD

A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D

Implement Y = A + B + C using only 2-input NAND gates.

A=A·A
A·B =A·B
A+B =A·B
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B =A·B
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B
A+B =A·B
C
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A·B =A·B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A·B =A·B
A+B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A A A·B =A·B
A+B
A+B
A+B =A·B
B B
Y
C C

Implementation of functions with only NOR gates
The NOT, AND, OR operations can be realised by using only NOR gates:
NOT
A= A+A
A A
NOT AND
A= A+A A·B= A+B
A
A A AB
B
NOT AND OR
A= A+A A·B= A+B A+B =A+B
A
A
A A AB A+B
B
B
NOT AND OR
A= A+A A·B= A+B A+B =A+B
A
A
A A AB A+B
B
B
Implementation of functions with only NOR (or only NAND) gates is more than a theoretical curiosity. There
are chips which provide a “sea of gates” (say, NOR gates) which can be configured by the user (through
programming) to implement functions.

Implement Y = A B + B C D + A D using only NOR gates.
A= A+A
A+B= A+B
A·B =A+B
Y = AB + BCD + AD
A= A+A
A+B= A+B
A·B =A+B
Y = AB + BCD + AD
A= A+A
AB
A+B= A+B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A= A+A
AB
A+B= A+B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D
A
AD
D
D

Multiplexers
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3
Multiplexers
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3
* A multiplexer or data selector (MUX in short) has N Select lines, 2N input lines, and it routes one of the
input lines to the output.
Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
* Conceptually, a MUX may be thought of as 2N switches. For a given combination of the select inputs,
only one of the switches closes (makes contact), and the others are open.

Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
* Conceptually, a MUX may be thought of as 2N switches. For a given combination of the select inputs,
only one of the switches closes (makes contact), and the others are open.
* SEQUEL file: mux test 1.sqproj

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0
* A 4-to-1 MUX can be implemented as,

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
For a given combination of S1 and S0 , only one of the terms survives (the others being 0). For example, with S1 = 0,
S0 = 1, we have Z = I1 .

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.
* ICs with arrays of multiplexers (and other digital blocks) are also available. These blocks can be configured (“wired”) by
the user in a programmable manner to realise the functionality of interest.
Active high and active low inputs/outputs
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.
Active high and active low inputs/outputs
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.
S1 S0 Z
I0
1 1 I0
I1
Z 1 0 I1
I2
I3 0 1 I2
0 0 I3
S1 S0
Select inputs are active low.

Enable (E) pin
inputs outputs inputs outputs
E E
Active high enable pin Active low enable pin

Enable (E) pin
E E
* Many digital ICs have an “Enable” (E) pin. If the Enable pin is active, the IC functions as desired; else, it
is “disabled,” i.e., the outputs are set to some default values.

Enable (E) pin
E E
* The Enable pin can be active high or active low.

Enable (E) pin
E E
* The Enable pin can be active high or active low.
* If the Enable pin is active low, it is denoted by Enable or E. When E = 0, the IC functions normally; else,
it is disabled.

Using two 8-to-1 MUXs to make a 16-to-1 MUX
D0 I0 S3 S2 S1 S0 X
D1 I1
D2 I2 0 0 0 0 D0
D3 I3
0 0 0 1 D1
D4 I4 74151 Z X1
D5 I5 0 0 1 0 D2
D6 I6
D7 I7 0 0 1 1 D3
D8 S2 S1 S0
0 1 0 0 D4
D9
D10 E 0 1 0 1 D5
D11
D12 X 0 1 1 0 D6
D13 0 1 1 1 D7
D14
D15 I0 1 0 0 0 D8
I1
1 0 0 1 D9
I2
I3 1 0 1 0 D10
I4 74151 Z X2
I5 1 0 1 1 D11
I6
1 1 0 0 D12
I7
S2 S1 S0 1 1 0 1 D13
E 1 1 1 0 D14
1 1 1 1 D15
S3 S2 S1 S0 M. B. Patil, IIT Bombay

Implement X = A B C D + A B C D using a 16-to-1 MUX.
A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
D = 1, i.e., the input line corresponding to
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1 * Similarly, when A B C D = 1, we want
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
I5 * In all other cases, X should be 0.
0 1 1 0 0 I6 → connect all other pins to 0.
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
0 I0
0 0 1 1 0 0 I1 * Similarly, when A B C D = 1, we want
0 I2 X = 1.
0 1 0 0 1 0 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
0 I5 * In all other cases, X should be 0.
0 1 1 0 0 0 I6 → connect all other pins to 0.
0 I7 MUX Z X
0 1 1 1 0 0 I8
1 I9
1 0 0 0 0
0 I10
1 0 0 1 1 0 I11
0 I12
1 0 1 0 0 0 I13
0 I14
1 0 1 1 0
0 I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
0 I0
0 0 1 1 0 0 I1 * Similarly, when A B C D = 1, we want
0 I2 X = 1.
0 1 0 0 1 0 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
0 I5 * In all other cases, X should be 0.
0 1 1 0 0 0 I6 → connect all other pins to 0.
0 I7 MUX Z X
0 1 1 1 0 0 I8 * In this example, since the truth table is
1 I9 organized in terms of ABCD, with A as
1 0 0 0 0
0 I10
I11
the MSB and D as the LSB (the same
1 0 0 1 1 0
0 I12 order in which A, B, C , D are connected
1 0 1 0 0 0 I13 to the select pins), the design is simple:
0 I14 connect
1 0 1 1 0
0 I15 I0 to X(0 0 0 0),
1 1 0 0 0 S3 S2 S1 S0
I1 to X(0 0 0 1),
1 1 0 1 0
A B C D
I2 to X(0 0 1 0), etc.
1 1 1 0 0
1 1 1 1 0
Implement X = A B C D + A B C D using an 8-to-1 MUX.
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C
* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* In all other cases, X should be 0.
→ connect all other pins to 0.
A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* Home work: Implement the same function (X ) with S2 = B, S1 = C , S0 = D.
A B C D X
Implement the function X using an 8-to-1 MUX.
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 * Home work: repeat with S2 = B, S1 = C ,

D I0
S0 = D.
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* A demultiplexer takes a single input (I) and routes it to one of the output lines (O0, O1,· · · ).

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .
* SEQUEL file: demux test 1.sqproj

Demultiplexer: gate-level diagram
I
O0
O1
O2
O0
O1
O2 O3
O3
I DEMUX
O4 O4
O5
O6 O5
S2 S1 S0 O7
O6
O7
S2 S1 S0 M. B. Patil, IIT Bombay

Decoders
A0 O0
A1 O1
N inputs Decoder M outputs
AN−1 OM−1

Decoders
A0 O0
A1 O1
N inputs Decoder M outputs
AN−1 OM−1
* For each input combination, an associated bit pattern appears at the output.

3-to-8 decoder (1-of-8 decoder)
A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
O0
O1 0 0 1 0 1 0 0 0 0 0 0
O2 0 1 0 0 0 1 0 0 0 0 0
A0
O3
A1 Decoder 0 1 1 0 0 0 1 0 0 0 0
O4
A2 1 0 0 0 0 0 0 1 0 0 0
O5
O6 1 0 1 0 0 0 0 0 1 0 0
O7 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Binary-Coded-Decimal (BCD) encoding
* Example:
Decimal 75

* Example:
Decimal 75
Binary 1001011

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
* BCD coding is commonly used to display numbers in electronic systems.

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
BCD 0111 0101
input
BCD−to−7−seg
decoder
7−segment
display

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
BCD 0111 0101
input
BCD−to−7−seg
decoder
7−segment
display
* In some electronic systems (e.g., calculators), all computations are performed in BCD.

7-segment display
VCC
a
common
a anode
b
f b
c
e g
f e c
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
BCD-to-7 segment decoder
VCC
a
a common
anode
MSB b
D c f b
C d
7446
B e g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VCC
a
a common
* The resistors serve to limit the diode
anode
b current. For VCC = 5 V , VD = 2 V , and
MSB
ID = 10 mA, R = 300 Ω.
D c f b
C d
7446
B e g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VCC
a
a common
* The resistors serve to limit the diode
anode
b current. For VCC = 5 V , VD = 2 V , and
MSB
ID = 10 mA, R = 300 Ω.
D c f b * Home work: Write the truth table for
C d c (in terms of D, C , B, A). Obtain a
7446 minimized expression for c using a K
B e map.
g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
BCD-to-decimal decoder
A3 A2 A1 A0 Active output
0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2
O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2
A0 0 1 0 1 O5
O3
A1 0 1 1 0 O6
7442 O4
A2
O5 0 1 1 1 O7
A3
O6 1 0 0 0 O8
O7
1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none
BCD-to-decimal decoder
A3 A2 A1 A0 Active output
0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2
O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2
A0 0 1 0 1 O5
O3
A1 0 1 1 0 O6
7442 O4
A2
O5 0 1 1 1 O7
A3
O6 1 0 0 0 O8
O7
1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none
Encoders
A0 O0
A1 O1
M inputs Encoder N outputs
AM−1 ON−1

Encoders
A0 O0
A1 O1
AM−1 ON−1
* Only one input line is assumed to be active. The binary number corresponding to the active input line
appears at the output pins.

Encoders
A0 O0
A1 O1
AM−1 ON−1
* The N output lines can represent 2N binary numbers, each corresponding to one of the M input lines, i.e.,
we can have M = 2N . Some encoders have M < 2N .

Encoders
A0 O0
A1 O1
AM−1 ON−1
* The N output lines can represent 2N binary numbers, each corresponding to one of the M input lines, i.e.,
we can have M = 2N . Some encoders have M < 2N .
* As an example, for N = 3, we can have a maximum of 23 = 8 input lines.

Encoders
8−to−3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O2 O1 O0

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Encoders

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
* Note that only one of the input lines is assumed to be active.

Encoders

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
* Note that only one of the input lines is assumed to be active.

* What if two input lines become simultaneously active?
→ There are “priority encoders” which assign a priority to each of the input lines.

74147 decimal-to-BCD priority encoder
A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binary output is 1000
(i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binary output is 1000
(i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .
* The lower input lines are therefore shown as “don’t care” (X) conditions.
M. B. Patil


Sequential circuits

Sequential circuits
* The digital circuits we have seen so far (gates, multiplexer, demultiplexer, encoders,
decoders) are combinatorial in nature, i.e., the output(s) depends only on the
present values of the inputs and not on their past values.

Sequential circuits
* In sequential circuits, the “state” of the circuit is crucial in determining the output
values. For a given input combination, a sequential circuit may produce different
output values, depending on its previous state.

Sequential circuits
* In other words, a sequential circuit has a memory (of its past state) whereas a
combinatorial circuit has no memory.

Sequential circuits
* In other words, a sequential circuit has a memory (of its past state) whereas a
combinatorial circuit has no memory.
* Sequential circuits (together with combinatorial circuits) make it possible to build
several useful applications, such as counters, registers, arithmetic/logic unit (ALU),
all the way to microprocessors.

NAND latch (RS latch)
A A B X1 X2
X1
1 0
0 1
1 1
X2
B
0 0
* A, B: inputs, X1 , X2 : outputs
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B
0 0
* Consider A = 1, B = 0.
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B
0 0
B = 0 ⇒ X2 = 1
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1
1
A A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
1
A 0 A B X1 X2
X1
1 0
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
1
A 0 A B X1 X2
X1
1 0 0 1
0 1
1 1
0 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
Overall, we have X1 = 0, X2 = 1.
01
A 0 A B X1 X2
X1
1 0 0 1
0 1
1 1
10 X2
B 1 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
01
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
10
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
* Consider A = B = 1.
10
A 10 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1
10 X2
B 01 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
If X1 = 1, X2 = 0 previously, the circuit continues to “hold” that state.
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
Similarly, if X1 = 0, X2 = 1 previously, the circuit continues to “hold” that state.
10
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
The circuit has “latched in” the previous state.
01
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will
become clear later.
01
A X102 A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
10 X2
B X011 0 0 1 1
B = 0 ⇒ X2 = 1 ⇒ X1 = A X2 = 1 · 1 = 0.
→ X1 = 1, X2 = 0.
X1 = A X2 = X2 , X2 = B X1 = X1 ⇒ X1 = X2
* For A = B = 0, X1 and X2 are both 1. This combination of A and B is not allowed for reasons that will
become clear later.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* The combination A = 1, B = 0 serves to reset X1 to 0 (irrespective of the previous state of the latch).
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* The combination A = 0, B = 1 serves to set X1 to 1 (irrespective of the previous state of the latch).
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
A = 1, B = 0 → latch gets reset to 0.
A = 0, B = 1 → latch gets set to 1.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
* The A input is therefore called the RESET (R) input, and B is called the SET (S) input of the latch.
A A B X1 X2
X1
1 0 0 1
0 1 1 0
1 1 previous
X2
B invalid
0 0
* In other words,
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q.
A A B X1 X2 R R S Q Q
X1 Q
1 0 0 1 1 0 0 1
0 1 1 0 0 1 1 0
1 1 previous 1 1 previous
X2 Q
B invalid S invalid
0 0 0 0
* In other words,
* X1 is denoted by Q, and X2 (which is X1 in all cases except for A = B = 0) is denoted by Q.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t1 , R goes high → R = S = 1, and the latch holds its previous state
→ no change at the output.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
* Up to t = t1 , R = 0, S = 1 → Q = 1.
* At t = t2 , S goes low → R = 1, S = 0 → Q = 0.
* At t = t3 , S goes high → R = S = 1, and the latch holds its previous state

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3
Why not allow R = S = 0?

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

- It makes Q = Q = 1, i.e., Q and Q are not inverse of each other any more.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3

- More importantly, when R and S both become 1 simultaneously (starting from R = S = 0), the final
outputs Q and Q cannot be uniquely determined. We could have Q = 0, Q = 1 or Q = 1, Q = 0,
depending on the delays associated with the two NAND gates.
R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q
Q t
S invalid
0 0 Q
t
t1 t2 t3 t4 t5

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q ?
Q t
S invalid
0 0 Q ?
t
t1 t2 t3 t4 t5

R
R R S Q Q t
Q
1 0 0 1 S
t
0 1 1 0
1 1 previous Q ?
Q t
S invalid
0 0 Q ?
t
t1 t2 t3 t4 t5


NOR latch (RS latch)
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1
* The NOR latch is similar to the NAND latch:

When R = 1, S = 0, the latch gets reset to Q = 0.
When R = 0, S = 1, the latch gets set to Q = 1.

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).

R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

* For R = S = 0, the latch retains its previous state (i.e., the previous values of Q and Q).
* R = S = 1 is not allowed for reasons similar to those discussed in the context of the NAND latch.

Comparison of NAND and NOR latches
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
R R S Q Q
Q
1 0 0 1
0 1 1 0
0 0 previous
Q
S invalid
1 1

NAND latch: alternative node names
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
NAND latch: alternative node names
R R S Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
S invalid
0 0
Active low input nodes:
S S R Q Q
Q
1 0 0 1
0 1 1 0
1 1 previous
Q
R invalid
0 0

Chatter (bouncing) due to a mechanical switch
A
Vs R Vo
A
Vs R Vo
* When the switch is thrown from A to B, Vo is expected to go from 0 V to Vs (say, 5 V ).

B
Vo
A
Vs
Vs R Vo
t
expected

B
Vo
A
Vs
Vs R Vo
t
expected

* However, mechanical switches suffer from “chatter” or “bouncing,” i.e., the transition from A to B is not a
single, clean one. As a result, Vo oscillates between 0 V and 5 V before settling to its final value (5 V ).
B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual

B
Vo Vo
A
Vs Vs
Vs R Vo
t t
expected actual

* In some applications, this chatter can cause malfunction → need a way to remove the chatter.

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from
A to B.

5V
S
R S Q Q
t
R Q 1 0 0 1
B R
0 1 1 0
A t
1 1 previous
S
0 0 invalid Q
t
5V
* Because of the chatter, the S and R inputs may have multiple transitions when the switch is thrown from
A to B.
* However, for S = R = 1, the previous value of Q is retained, causing a single transition in Q, as desired.

The “clock”
* Complex digital circuits are generally designed for synchronous operation, i.e., transitions in the various
signals are synchronised with the clock.

The “clock”
* Synchronous circuits are easier to design and troubleshoot because the voltages at the nodes (both output
nodes and internal nodes) can change only at specific times.

The “clock”
* A clock is a periodic signal, with a positive-going transition and a negative-going transition.
positive edge negative edge
0
t
T

The “clock”
0
t
T
* The clock frequency determines the overall speed of the circuit. For example, a processor that operates
with a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.

The “clock”
0
t
T
* The clock frequency determines the overall speed of the circuit. For example, a processor that operates
with a 1 GHz clock is 10 times faster than one that operates with a 100 MHz clock.
Intel 80286 (IBM PC-AT): 6 MHz
Modern CPU chips: 2 to 3 GHz.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
Clocked RS latch NAND RS latch

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is inactive (0), A = B = 1, and the latch holds the previous state.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS latch (right), we can
construct the truth table for the clocked RS latch.

Clocked RS latch
CLK R S Q Q
S A A B Q Q
previous A
Q 0 X X Q 1 0 0 1
1 1 0 0 1
CLK 0 1 1 0
1 0 1 1 0
1 1 previous
Q 1 0 0 previous Q
B 0 0 invalid
R B invalid
1 1 1
* When clock is active (1), A = S, B = R. Using the truth table for the NAND RS latch (right), we can
construct the truth table for the clocked RS latch.
* Note that the above table is sensitive to the level of the clock (i.e., whether CLK is 0 or 1).

Clocked RS latch
CLK R S Q Q
S A
Q 0 X X previous
1 1 0 0 1
CLK
1 0 1 1 0
Q 1 0 0 previous
R B invalid
1 1 1
CLK
0 0.2 0.4 0.6 0.8

time (msec) M. B. Patil, IIT Bombay
Edge-triggered flip-flops
* The clocked RS latch seen previously is level-sensitive, i.e., if the clock is active (CLK = 1), the flip-flop
output is allowed to change, depending on the R and S inputs.

* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transition
from 0 to 1 or from 1 to 0).

* In an edge-sensitive flip-flop, the output can change only at the active clock edge (i.e., CLK transition
from 0 to 1 or from 1 to 0).
* Edge-sensitive flip-flops are denoted by the following symbols:
R Q R Q
CLK CLK
S Q S Q
positive edge−triggered flip−flop negative edge−triggered flip−flop

JK flip-flop: introduction
R S Q Q R
J
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
R S Q Q R
J
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch
* When CLK = 0, we have R = S = 1, and the RS latch holds the previous Q. In other words, nothing
happens as long as CLK = 0.
CLK J K Q (Qn+1 )
R S Q Q R
J 0 X X previous (Qn )
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
Truth table for RS latch Truth table for JK flip−flop
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = K = 0 → R = S = 1, RS latch holds previous Q, i.e., Qn+1 = Qn , where n denotes the nth clock
pulse (This notation will become clear shortly).
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
1 0 0 previous (Qn )
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
Case (i): Qn = 0 → S = 1 (i.e., R = S = 1) → Qn+1 = Qn = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
Case (ii): Qn = 1 → S = 0 (i.e., R = 1, S = 0) → Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- J = 0, K = 1 → R = 1, S = Qn .
In either case, Qn+1 = 0 → For J = 0, K = 1, Qn+1 = 0.
CLK J K Q (Qn+1 )
R S Q Q R previous (Qn )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
- Consider J = 1, K = 0 → S = 1, R = Qn = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1 (i.e., R = 1, S = 1) → Qn+1 = Qn = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
- Consider J = 1, K = 1 → R = Qn , S = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
CLK J K Q (Qn+1 )
J 0 X X
1 0 0 1
Q
0 1 1 0 CLK 1 0 1 0
1 1 previous
1 1 0 1
Q
0 0 invalid K
S 1 1 1 toggles (Qn )
RS latch
* When CLK = 1:
Case (i): Qn = 0 → R = 0 (i.e., R = 0, S = 1) → Qn+1 = 1.
→ For J = 1, K = 0, Qn+1 = 1.
Case (i): Qn = 0 → R = 0, S = 1 → Qn+1 = 1.
Case (ii): Qn = 1 → R = 1, S = 0 → Qn+1 = 0.
→ For J = 1, K = 1, Qn+1 = Qn .
CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch
Truth table for JK flip−flop
Consider J = K = 1 and CLK = 1.

CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch

As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).

CLK J K Q (Qn+1 )
R previous (Qn )
J 0 X X
Q
CLK 1 0 1 0
1 1 0 1
Q
K
RS latch

As long as CLK = 1, Q will keep toggling! (The frequency will depend on the delay values of the various gates).
→ Use the “Master-slave” configuration.

JK flip-flop (Master-Slave)
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
RS latch 1 RS latch 2
CLK CLK
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
* When CLK goes high, only the first latch is affected; the second latch retains its previous value (because
CLK = 0 → R2 = S2 = 1).
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
* When CLK goes low, the output of the first latch (Q1 ) is retained (since R1 = S1 = 1), and Q1 can now
affect Q.
Master Slave
J
R1 R2 Q
Q1
Q
K
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
* In other words, the effect of any changes in J and K appears at the output Q only when CLK makes a
transition from 1 to 0.
This is therefore a negative edge-triggered flip-flop.
Master Slave
CLK J K Qn+1
J
R1 R2 Q 0 0 Qn
Q1
0 1 0
1 0 1
Q
K 1 1 Qn
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
Master Slave
CLK J K Qn+1
J
R1 R2 Q 0 0 Qn
Q1
0 1 0
1 0 1
Q
K 1 1 Qn
S1 S2
CLK CLK
CLK = 0 → R2 = S2 = 1).
affect Q.
* Note that the JK flip-flop allows all four input combinations.
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
RS latch 1 RS latch 2 S1
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn
Master Slave
CLK
t
J
J
R1 R2 Q
Q1 t
K
t
R1
Q
K
S1 S2 t
t
CLK CLK Q1
t
R2
CLK J K Qn+1 t
0 0 Qn S2
0 1 0 t
Q
1 0 1
t
1 1 Qn

JK flip-flop
CLK J K Qn+1 CLK J K Qn+1

J Q Qn J Q Qn
0 0 0 0
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 K Q 1 0 1
1 1 Qn 1 1 Qn
positive edge−triggered JK flip−flop negative edge−triggered JK flip−flop

JK flip-flop

J Q Qn J Q Qn
0 0 0 0
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 K Q 1 0 1
1 1 Qn 1 1 Qn
* Both negative (e.g., 74ALS112A, CD54ACT112) and positive (e.g., 74ALS109A, CD4027) edge-triggered
JK flip-flops are available as ICs.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK
Consider a negative edge-triggered JK flip-flop.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

* As seen earlier, when CLK is high (i.e., t1A < t < t1B , etc.), the input J and K determine the Master
latch output Q1 .
During this time, no change is visible at the flip-flop output Q.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* When the clock goes low, the Slave flip-flop becomes active, making it possible for Q to change.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Q
value is determined by J and K values just before the active edge.

JK flip-flop
J Q
Q1 CLK
Master Slave
K Q
Q1 t1A t1B t2A t2B
CLK CLK

latch output Q1 .
* In short, although the flip-flop output Q can only change after the active edge, (t1B , t2B , etc.), the new Q
value is determined by J and K values just before the active edge.
This is a very important point!

JK flip-flop
CLK J K Qn+1
J Q Qn
0 0
CLK 0 1 0
K Q 1 0 1
1 1 Qn
positive edge−triggered JK flip−flop
CLK
0 0.1 0.2 0.3 0.4 0.5 0.6

time (msec)
JK flip-flop

J Q Qn Q
0 0 J
0 0 Qn
CLK 0 1 0 CLK 0 1 0
K Q 1 0 1 1 0 1
K Q
1 1 Qn 1 1 Qn
CLK CLK
J J
K K
Q Q
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
time (msec) time (msec)
JK flip-flop
J1 = K1 = 1. Assume Q1 = Q2 = 0 initially.
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn
JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn
* Since J1 = K1 = 1, Q1 toggles after every active clock edge.

JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

* J2 = Q1 , K2 = Q1 . We need to look at J2 and K2 values just before the active edge, to determine the next value of Q2 .
JK flip-flop
J1 Q1 J2 CLK
1 J Q J Q Q2
t
Q1
K Q K Q
K1 K2
t
CLK Q2
CLK J K Qn+1
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

* It is convenient to construct a table listing J2 and K2 to figure out the next Q2 value.
JK flip-flop
J1 Q1 J2
1 J Q J Q Q2 CLK t J2 (t = t− −
k ) K2 (t = tk ) Q2 (t = t+
k)
t1 0 1 0
t
Q1 t2 1 0 1
K Q K Q
K1 K2 t3 0 1 0
t
CLK Q2 t4 1 0 1
CLK J K Qn+1 t5 0 1 0
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn

JK flip-flop
J1 Q1 J2
1 J Q J Q Q2 CLK t J2 (t = t− −
k ) K2 (t = tk ) Q2 (t = t+
k)
t1 0 1 0
t
Q1 t2 1 0 1
K Q K Q
K1 K2 t3 0 1 0
t
CLK Q2 t4 1 0 1
CLK J K Qn+1 t5 0 1 0
t
0 0 Qn t1 t2 t3 t4 t5
0 1 0
1 0 1
1 1 Qn


CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
t
Q0
t
Q1
t
Q2
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1
t2 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0 0 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1 1 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 1
0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 0
1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 1
0 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 0
1
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
1
0 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
0
1 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
1
0 0
1 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
0
1 1
0 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1 0 0 0
t
t1 t2 t3 t4 t5
CLK J K Qn+1
Q0 Q1 Q2
1 J Q J Q J Q Qn
0
1 1
0 0
1 0 0
0 1 0
K Q K Q K Q 1 0 1
1
0 0
1 1
0
1 1 Qn
CLK
CLK
tk − tk +
t Q0 Q1 Q2 J0 K0 J1 K1 J2 K2 Q0 Q1 Q2 t
Q0
t1 0 0 0 1 0 1 1 0 1 1 1 0
t2 1 1 0 1 0 0 0 1 0 1 1 1 t
Q1
t3 1 1 1 1 1 0 0 1 0 0 1 1
t4 0 1 1 1 1 1 1 0 0 1 0 1 t
Q2
t5 1 0 1 1 1 0 0 1 1 0 0 0
t
t1 t2 t3 t4 t5

M. B. Patil


JK flip-flop: asynchronous inputs
Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
K Sd Q 0 0 0 1 0 normal
0 0 1 0 1 operation
0 0 1 1 Qn

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* Clocked flip-flops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (also
called Preset and Clear, respectively) which override all other inputs (J, K, CLK).

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .

Sd Rd CLK J K Qn+1
0 1 X X X 0
Rd Q 1 0 X X X 1
J
1 1 X X X invalid
CLK
0 0 0 0 Qn
0 0 1 0 1 operation
0 0 1 1 Qn
* The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
* The asynchronous inputs are convenient for starting up a circuit in a known state.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q
positive edge−triggered D flip−flop

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q
negative edge−triggered D flip−flop

t
t1 t2 t3 t4 t5

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* The D flip-flop can be used to delay the Data (D) signal by one clock period.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.

D flip-flop
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
CLK
D Q D J Q t
CLK D Qn+1
D
CLK 0 0 CLK
1 1 t
Q K Q Q

t
t1 t2 t3 t4 t5
* With J = D, K = D, we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the first case, 1 in the second case.
* Instead of a JK flip-flop, an RS flip-flop can also be used to make a D flip-flop, with S = D, R = D.
Shift register
Q1 Q2 Q3
D D Q D Q D Q D Q Q4 CLK D Qn+1
0 0 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
Shift register
Q1 Q2 Q3
0
1 0
1 0
1 0
1 0 0
Q Q Q Q 1 1
CLK
CLK
Q1
Q2
Q3
Q4
SEQUEL file: ee101 shift reg 1.sqproj

Parallel transfer between shift registers
A3 A2 A1 A0
D Q D Q D Q D Q
Q Q Q Q
Register A A3 A2 A1 A0
B3 B2 B1 B0 Register B B3 B2 B1 B0
D Q D Q D Q D Q
Q Q Q Q
CLK

Parallel transfer between shift registers
A3 A2 A1 A0
D Q D Q D Q D Q
Q Q Q Q
Register A A3 A2 A1 A0
B3 B2 B1 B0 Register B B3 B2 B1 B0
D Q D Q D Q D Q
Q Q Q Q
CLK
* After the active clock edge, the contents of the A register (A3 A2 A1 A0 ) are copied to the B register.

Bidirectional shift register
D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK
* When the mode input (M) is 1, we have

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .
D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .

D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q
DR
Q Q Q Q
DL
M
CLK

D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .
D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .
* M = 1 → shift right operation.
M = 0 → shift left operation.

Shift left operation
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
after
shift left 0 0 0 1 1 0 1 0 dec. 26
27 26 25 24 23 22 21 20
original dec. 13
0 0 0 0 1 1 0 1 0
number
after
shift left 0 0 0 1 1 0 1 0 dec. 26
Shift left → × 2

Multiplication using shift and add
1 0 1 1 A3 A2 A1 A0 (decimal 11)
1 1 0 1 B3 B2 B1 B0 (decimal 13)
1 0 1 1 since B0 = 1
0 0 0 0 Z since B1 = 0
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 1 0 1 1 1 addition
1 0 1 1 Z Z Z since B3 = 1
1 0 0 0 1 1 1 1 addition (decimal 143)
Note that Z = 0. We use Z to denote 0s which are

independent of the numbers being multiplied.
1 0 1 1 A3 A2 A1 A0 (decimal 11) Register 2 Register 1
1 1 0 1 B3 B2 B1 B0 (decimal 13) Z Z Z Z Z Z Z Z initialize
1 0 1 1 since B0 = 1
0 0 0 0 Z since B1 = 0
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 0 1 1 Z Z since B2 = 1 Z 1 0 1 1 Z Z Z shift
1 0 1 1 Z Z Z since B3 = 1

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
1 1 0 1 1 1 addition load 0000
0 0 0 0
1 0 1 1 Z Z Z since B3 = 1 since B1 = 0

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
1 0 0 0 1 1 1 1 addition (decimal 143) 0 1 0 1 1 Z Z Z add

1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
independent of the numbers being multiplied. 1 0 1 1 load 1011
since B2 = 1
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 0 0 1 1 1 1 Z add
1 0 1 1 since B0 = 1 1 0 1 1 load 1011

0 0 0 0 Z since B1 = 0 since B0 = 1
1 0 1 1 Z Z Z Z add
0 1 0 1 1 addition
0 0 0 0
Z 0 1 0 1 1 Z Z shift
since B2 = 1
1 1 0 1 1 1 Z Z add
Z 1 1 0 1 1 1 Z shift
1 0 1 1 load 1011
since B3 = 1
1 0 0 0 1 1 1 1 Z add
Z 1 0 0 0 1 1 1 1 shift
Load
A3 A2 A1 A0
0 J
S d Q Q3 J S d Q Q2 J S d Q Q1 J Sd Q Q0
1 K Rd Q K Rd Q K Rd Q K Rd Q
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* All flip-flops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* When Load = 1, Sd = Ai , Rd = 0 → Ai gets loaded into the i th flip-flop.
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
* Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0 .
→ parallel in-serial out data movement
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Load
A3 A2 A1 A0
0 J
Clear
CLK
Clear 0 0 0 0 0
t
Load
t
CLK
t
Q0 = A 0 Q0 = A1 Q0 = A 2 Q0 = A3
Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
State transition diagram General configuration

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
* A counter with k states is called a modulo-k (mod-k) counter.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* A counter can be made with flip-flops, each flip-flop serving as a memory element with two states (0 or 1).

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 or
Q = 1). It is possible to exclude some of these states.
→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic

* If there are N flip-flops in a counter, there are 2N possible states (since each flip-flop can have Q = 0 or
Q = 1). It is possible to exclude some of these states.
→ N flip-flops can be used to make a mod-k counter with k ≤ 2N .
* Typically, a reset facility is also provided, which can be used to force a certain state to initialize the
counter.
Counters: example
Q0 Q1 Q2
1 J Q J Q J Q
0 0 0
1
K Q K Q K Q
1 1 1
k 2
CLK
3 CLK
state Q0 Q1 Q2
t 1 0 0 0
Q0
4 0 1 1 0 1 0 2 1 1 0
t 3 1 1 1
Q1
0 1 1 1 0 0 4 0 1 1
State transition diagram
t 5 1 0 1
Q2
0 0 1 1 1 0 1 0 0 0
t
t1 t2 t3 t4 t5

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
X is 1 for state 3; else, it is 0.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
* The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using appropriate logic.

Counters
Q0
1
Q1
k 2 Q2
Clock Counter
3 QN−1
Reset
Decoding
4
logic
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1
CLK
t
X
t
8T
* The counter outputs (i.e., the flip-flop outputs, Q0 , Q1 , · · · QN−1 ) can be decoded using appropriate logic.
* In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i, and 0 otherwise.
→ For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k. For this reason, a
mod-k counter is also called a divide-by-k counter.
A binary ripple counter
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* J = K = 1 for all flip-flops. Let Q0 = Q1 = Q2 = 0 initially.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* Since J = K = 1, each flip-flop will toggle when an active (in this case, negative) clock edge arrives.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
* For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
CLK
t
Q0
t
Q1
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2 Q2 Q1 Q0
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all flip-flops, allowing normal
flip-flip operation. M. B. Patil, IIT Bombay
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111.
→ it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter,
therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
0 0 1
0 1 0
CLK
0 1 1
1 0 0
t
Q0 1 0 1
1 1 0
t 1 1 1
Q1
0 0 0 repeats
t
Q2
t
* If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter,
therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requiring decoding logic.
* This type of counter is called a “ripple” counter since the clock transitions ripple through the flip-flops. M. B. Patil, IIT Bombay
1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
1 1 1
1 1 0
CLK
1 0 1
1 0 0
t
Q0 0 1 1
0 1 0
t 0 0 1
Q1
0 0 0 repeats
t
Q2

1
Q0 Q1 Q2
J Q J Q J Q
K Q K Q K Q 0 0 0
1 1 1
1 1 0
CLK
1 0 1
1 0 0
t
Q0 0 1 1
0 1 0
t 0 0 1
Q1
0 0 0 repeats
t
Q2
* If positive edge-triggered flip-flops are used, we get a binary down counter (counting down from 111 to 000).

Binary ripple counters
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
1
Q0 Q1 Q2
J Q J Q J Q
CLK FF0 FF1 FF2
K Q K Q K Q
* Home work: Sketch the waveforms (CLK, Q0 , Q1 , Q2 ), and tabulate the counter states in each case.

Up-down binary ripple counters
1
M
J Q J Q J Q
Q0 Q1 Q2
CLK FF0 FF1 FF2
K Q K Q K Q
M
M=1 M=0
CLK CLK
t t
Q0 Q0
t t
Q1 Q1
t t
Q2 Q2
t t

Up-down binary ripple counters
1
M
J Q J Q J Q
Q0 Q1 Q2
CLK FF0 FF1 FF2
K Q K Q K Q
M
M=1 M=0
CLK CLK
t t
Q0 Q0
t t
Q1 Q1
t t
Q2 Q2
t t
* When Mode (M) = 1, the counter counts up; else, it counts down. (SEQUEL file: ee101 counter 3.sqproj)
0
1 Decade counter using direct inputs
Sd Q0 Sd Q1 Sd Q2 Sd Q3
J Q J Q J Q J Q
CLK FF0 FF1 FF2 FF3
K Rd Q K Rd Q K Rd Q K Rd Q
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 SEQUEL file: ee101 counter 5.sqproj
0
J Q J Q J Q J Q * When the counter reaches
Q3 Q2 Q1 Q0 = 1010 (i.e., decimal 10),
CLK FF0 FF1 FF2 FF3 Q3 Q1 = 1, and the flip-flops are
cleared to Q3 Q2 Q1 Q0 = 0000.
K Rd Q K Rd Q K Rd Q K Rd Q
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
0
J Q J Q J Q J Q * When the counter reaches
Q3 Q2 Q1 Q0 = 1010 (i.e., decimal 10),
CLK FF0 FF1 FF2 FF3 Q3 Q1 = 1, and the flip-flops are
cleared to Q3 Q2 Q1 Q0 = 0000.
K Rd Q K Rd Q K Rd Q K Rd Q * The counter counts from 0000
(decimal 0) to 1001 (decimal 9)
→ “decade counter.”
Q3 Q2 Q1 Q0
0 0 0 0
Q0 0 0 0 1
0 0 1 0
0 0 1 1
Q1 0 1 0 0
0 1 0 1
0 1 1 0
Q2
0 1 1 1
1 0 0 0
Q3 1 0 0 1
0 0 0 0 repeats
A synchronous counter
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all flip-flops are driven by the same clock, the counter is called a “synchronous” counter.
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
* FF0 toggles after every active edge.
FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. (Similarly, for FF2 and FF3)
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .

J Q J Q J Q J Q
Q0 Q1 Q2 Q3
FF0 FF1 FF2 FF3
K Q K Q K Q K Q
CLK
CLK
t
Q0
t
Q1
t
Q2
t
Q3
t
* J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
* From the waveforms, we see that it is a binary up counter.
Design of synchronous counters
CLK J K Qn+1
J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
CLK J K Qn+1 CLK Qn Qn+1 J K

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to
make that happen?

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
* Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn by making J = 0, K = 0.

J Q
0 0 Qn
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).
* Similarly, work out the other entries in the table.

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).

J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1 X 0
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).


J Q
0 0 Qn 0 0 0 X
CLK 0 1 0 0 1 1 X
K Q 1 0 1 1 0 X 1
1 1 Qn 1 1 X 0
make that happen?
→ J = 0, K = X (i.e., K can be 0 or 1).
* The table for a negative edge-triggered flip-flop would be identical except for the active edge.

state Q2 Q1 Q0 CLK Qn Qn+1 J K

J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Design a synchronous mod-5 counter with the given state transition table.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
* State 1 → State 2 means
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* Refer to the right table. For Q2 : 0 → 0, we must have J2 = 0, K2 = X , and so on.


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .


J2 Q2 J1 Q1 J0 Q0
1 0 0 0 J Q J Q J Q 0 0 0 X
2 0 0 1
0 1 1 X
3 0 1 0
1 0 X 1
4 0 1 1 K Q K Q K Q
K2 K1 K0
5 1 0 0 1 1 X 0
CLK
1 0 0 0 repeats
Outline of method:
Q2 : 0 → 0,
Q1 : 0 → 0,
Q0 : 0 → 1.
* When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 .
* The last step is to come up with suitable functions for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . This can be done
with K-maps. (If the number of flip-flops is more than 4, other techniques can be employed.)

state Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
CLK Qn Qn+1 J K
1 0 0 0
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to find
logical functions for each of them.
CLK Qn Qn+1 J K
1 0 0 0 0 X 0 X 1 X
0 0 0 X
2 0 0 1 0 X 1 X X 1
3 0 1 0 0 X X 0 1 X 0 1 1 X
4 0 1 1 1 X X 1 X 1 1 0 X 1
5 1 0 0 X 1 0 X 0 X
1 1 X 0
1 0 0 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to find
logical functions for each of them.
* Note that we have not tabulated the J and K values for those combinations of Q0 , Q1 , Q2 which do not
occur in the state transition table (such as Q2 Q1 Q0 = 110). We treat these as don’t care conditions.

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) don’t care conditions. Since these are different
from the don’t care conditions arising from the state transition table, we mark them with a different colour.

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the five
allowed states (say, Q2 Q1 Q0 = 000).

Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 0 0 X X 0 X X X 1
J2 K2
1 0 1 X X 1 X X X X
1 0 0 0 0 X 0 X 1 X Q2 Q1 Q2 Q1
2 0 0 1 0 X 1 X X 1 Q0 00 01 11 10 Q0 00 01 11 10
3 0 1 0 0 X X 0 1 X 0 0 X X 0 0 X 0 X X
J1 K1
4 0 1 1 1 X X 1 X 1
1 1 X X X 1 X 1 X X
5 1 0 0 X 1 0 X 0 X
1 0 0 0 Q2 Q1 Q2 Q1
Q0 00 01 11 10 Q0 00 01 11 10
0 1 1 X 0 0 X X X X
J0 K0
1 X X X X 1 1 1 X X
* We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the five
allowed states (say, Q2 Q1 Q0 = 000).
* From the K-maps, J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.
Design of synchronous counters: verification
J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q
K Q K Q K Q
K2 K1 K0
CLK
1
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
SEQUEL file: ee101 counter 6.sqproj
* J2 = Q1 Q0 ,
J2 Q2 J1 Q1 J0 Q0 K2 = 1,
J Q J Q J Q
J1 = Q0 ,
K1 = Q0 ,
J0 = Q2 ,
K Q K Q K Q
K2 K1 K0 K0 = 1.
CLK
1
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
* J2 = Q1 Q0 ,
J2 Q2 J1 Q1 J0 Q0 K2 = 1,
J Q J Q J Q
J1 = Q0 ,
K1 = Q0 ,
J0 = Q2 ,
K Q K Q K Q
K2 K1 K0 K0 = 1.
CLK * Note that the design is independent
1 of whether positive or negative
edge-triggered flip-flops are used.
CLK
Q0
Q1
Q2
0.04 0.14 0.24 0.34

time (msec)
Combination of counters: Approach 1
A1
A2
Counter 1
Clock 1 mod-k1
k1 = 4 AN1
B1
B2
Counter 2
Clock 2 mod-k2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1
Clock 1 mod-k1 Clock 1 mod-k1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
Clock 2 mod-k2 Counter 1 state 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
k2 = 3 BN2
A1
A2
Counter 1 Counter 1 Decoding Counter 2
Clock 1 mod-k1 Clock 1 mod-k1 Logic mod-k2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 1 2 3 1
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
3 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
A1
A2
Clock 2
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
3 1 1 1 1 2 2 2 2 3 3 3 3 1 1 1 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
→ the combined counter is a mod-k1 k2 counter.

Combination of counters: example
J0 Q0 J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
K0 K2 K1 K0
CLK
1
CLK CLK
t t
Q0 Q0
t t
Q1
t
Q2
mod−2 counter mod−5 counter

JA QA J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
KA K2 K1 K0
CLK
t
QA
t
Q0
t
Q1
t
Q2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 t

A1
A2
Counter 1
Clock 1 mod-k1
k1 = 4 AN1
B1
B2
Counter 2
Clock 2 mod-k2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1
Clock 1 mod-k1 mod-k1
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2
A1
A2
Counter 1 Counter 1 Clock 2 Counter 2
Clock 1 mod-k1 mod-k1 mod-k2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
A1
A2
Clock 1
k1 = 4 AN1
B1 Clock 1
B2
Counter 2
k2 = 3 BN2 Clock 2
Counter 2 state 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2
Combined state
4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1
→ the combined counter is a mod-k1 k2 counter.

Combination of counters: example (same as before)
J0 Q0 J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
CLK
1 K Q K Q K Q K Q
K0 K2 K1 K0
CLK
1
CLK CLK
t t
Q0 Q0
t t
Q1
t
Q2
mod−2 counter mod−5 counter

JA QA J2 Q2 J1 Q1 J0 Q0
J Q J Q J Q J Q
K Q K Q K Q K Q
1 KA K2 K1 K0
CLK
1
CLK
t
QA
t
Q0
t
Q1
t
Q2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 t

555 timer IC
The 555 timer is useful in timer, pulse generation, and oscillator applications. We will look at two common
applications.

555 timer IC
applications.
* Monostable multivibrator
Vtrigger
t
Vout
t
T

555 timer IC
applications.
* Monostable multivibrator
Vtrigger
t
Vout
t
T
* Astable multivibrator
Vout
t
T

555 timer
VCC
Threshold R Q
Out
R buffer
S Q Discharge
Trigger
R
R S Q Q
1 0 0 1
0 1 1 0
0 0 previous
555 timer
VCC
R
2 VCC
3
Threshold R Q Threshold R Q
Out Out
R buffer
S Q VCC S Q
Discharge 3
Discharge
Trigger Trigger
R
R S Q Q
1 0 0 1
0 1 1 0
0 0 previous
555 timer
VCC
R
2 VCC
3
Threshold R Q Threshold R Q
Out Out
R buffer
S Q VCC S Q
Discharge 3
Discharge
Trigger Trigger
R
R S Q Q
1 0 0 1
0 1 1 0 STOP
0 0 previous
555 monostable multivibrator
VCC
2 VCC
R
3
Threshold R Q
Out
VC C
VCC S Q Discharge
3
Trigger
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
t
to VCC
VC
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
t
T to VCC
2 VCC
VC 3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
VC 3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
1
→ e −T /τ = → T = τ log 3 ≈ 1.1 τ
3
t
VCC Trigger
2 VCC
R
3
t
Threshold R Q S
Out
VC C
VCC S Q Discharge t
3
Trigger R
t
Q
VC (t) = VCC 1 − e −t/τ

t
T to VCC
2 VCC
2 VCC
VC 3
→ = VCC 1 − e −T /τ
3
1
→ e −T /τ = → T = τ log 3 ≈ 1.1 τ
3
SEQUEL file: ic555 mono 1.sqproj
t
555 astable multivibrator
2 VCC
VCC
3
Threshold
Ra R Q
Out
VCC S Q
Rb Discharge
3
Trigger
VC C
2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
Let VC (t) = A e −t/τ1 + B
VCC
2 VCC
→ B = VCC , A = − 3
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
2 VCC
→ B = VCC , A = − 3
3
2 VCC 2 VCC −TH /τ1
=− e + VCC
3 3 0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
Charging:
VCC 2 VCC
VC (0) = , VC (∞) = VCC . 3
3
VC
VCC
2 VCC
→ B = VCC , A = − 3
3
2 VCC 2 VCC −TH /τ1
=− e + VCC
3 3 0
t
→ TH = τ1 log 2, with τ1 = (Ra + Rb ) C . TH TL

2 VCC
VCC
3
Threshold
Ra R Q
Out
VCC S Q
Rb Discharge
3
Trigger
VC C
2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3
VC
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
Discharging: VC (0) = , VC (∞) = 0. 2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
VCC
3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
VCC 2 VCC −TL /τ2 VCC
= e
3 3 3
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
= e
3 3 3
→ TL = τ2 log 2, with τ2 = Rb C .
0
t
TH TL

2 VCC S
VCC
3
Threshold
Ra R Q
Out t
R
VCC S Q
Rb Discharge
3
t
Q
Trigger
VC C
t
VCC
2 VCC
3 3
2 VCC −t/τ2
→ VC (t) = e VC
3
= e
3 3 3
→ TL = τ2 log 2, with τ2 = Rb C .
0
t
SEQUEL file: ic555 astable 1.sqproj TH TL

Digital CK Ts

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Digital Circuits: Part 1

Department of Electrical Engineering

M. B. Patil, IIT Bombay

analog signal digital signal

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Operation NOT AND OR

Operation NOT AND OR

Operation NOT AND OR

Notation Y=A Y= A·B

Operation NOT AND OR

Notation Y=A Y= A·B Y=A+B

M. B. Patil, IIT Bombay

Operation NAND NOR XOR

Operation NAND NOR XOR

Operation NAND NOR XOR

Notation Y= A·B Y= A+B

Operation NAND NOR XOR

Notation Y= A·B Y= A+B Y=A⊕B

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay