Week 10 Slides

Digital circuits
1
high
low
0
t t
analog signal digital signal
M. B. Patil, IIT Bombay

Digital circuits
1
high
low
0
t t
* An analog signal x(t) is represented by a real number at a given time point.

Digital circuits
1
high
low
0
t t

* A digital signal is “binary” in nature, i.e., it takes on only two values: low (0) or high (1).

Digital circuits
1
high
low
0
t t

* Although we have shown 0 and 1 as constant levels, in reality, that is not required. Any value in the low
(high) band will be interpreted as 0 (1) by digital circuits.

Digital circuits
1
high
low
0
t t

* Although we have shown 0 and 1 as constant levels, in reality, that is not required. Any value in the low
(high) band will be interpreted as 0 (1) by digital circuits.
* The definition of low and high bands depends on the technology used, e.g.,
TTL (Transitor-Transitor Logic)
CMOS (Complementary MOS)
ECL (Emitter-Coupled Logic)

A simple digital circuit
5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)
* If Vi is low (“0”), Vo is high (“1”).

If Vi is high (“1”), Vo is low (“0”).

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* The circuit is called an “inverter” because it inverts the logic level of the input. If the input is 0, it makes
the output 1, and vice versa.

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* Digital circuits are made using a variety of devices. The simple BJT inverter is only an illustration.

5 V VCC 4
Vo (Volts)
RC 3
Vo 2
Vi RB 1
0
0 1 2 3 4 5
Vi (Volts)

* Digital circuits are made using a variety of devices. The simple BJT inverter is only an illustration.
* Most of the VLSI circuits today employ the MOS technology because of the high packing density, high
speed, and low power consumption it offers.
Digital circuits
V1
t
original data
Digital circuits
V1
t
original data
V2
t
corrupted data
Digital circuits
V1
t
original data
V2
V2
Vref V3
Vref
t
corrupted data comparator
Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
corrupted data comparator recovered data

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
* A major advantage of digital systems is that, even if the original data gets distorted (e.g., in transmitting
through optical fibre or storing on a CD) due to noise, attenuation, etc., it can be retrieved easily.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
* There are several other benefits of using digital representation:

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can use computers to process the data.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can store in a variety of storage media.

Digital circuits
V1
t
original data
V3
V2
V2
Vref V3
Vref
t
t
- can store in a variety of storage media.
- can program the functionality. For example, the behaviour of a digital filter can be changed simply
by changing its coefficients.
Logical operations
Operation NOT AND OR
Gate
Truth table
Notation
Logical operations
Gate A Y
A Y
Truth table 0 1
1 0
Notation Y=A
Logical operations
A
Gate A Y Y
B
A B Y
A Y 0 0 0
Truth table 0 1 0 1 0
1 0 1 0 0
1 1 1
Notation Y=A Y= A·B

= AB
Logical operations
A A
Gate A Y Y Y
B B
A B Y A B Y
A Y 0 0 0 0 0 0
Truth table 0 1 0 1 0 0 1 1
1 0 1 0 0 1 0 1
1 1 1 1 1 1
Notation Y=A Y= A·B Y=A+B

= AB

Logical operations
Operation NAND NOR XOR
Gate
Truth table
Notation
Logical operations
A
Gate Y
B
A B Y
0 0 1
Truth table 0 1 1
1 0 1
1 1 0
Notation Y= A·B
= AB
Logical operations
A A
Gate Y Y
B B
A B Y A B Y
0 0 1 0 0 1
Truth table 0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Notation Y= A·B Y= A+B

= AB
Logical operations
A A A
Gate Y Y Y
B B B
A B Y A B Y A B Y
0 0 1 0 0 1 0 0 0
Truth table 0 1 1 0 1 0 0 1 1
1 0 1 1 0 0 1 0 1
1 1 0 1 1 0 1 1 0
Notation Y= A·B Y= A+B Y=A⊕B

= AB = AB + AB

Logical operations
* The AND operation is commutative.

→ A · B = B · A.

Logical operations

→ A · B = B · A.
* The AND operation is associative.
→ (A · B) · C = A · (B · C ).

Logical operations

→ A · B = B · A.
→ (A · B) · C = A · (B · C ).
* The OR operation is commutative.
→ A + B = B + A.

Logical operations

→ A · B = B · A.
→ (A · B) · C = A · (B · C ).
* The OR operation is commutative.
→ A + B = B + A.
* The OR operation is associative.
→ (A + B) + C = A + (B + C ).

Boolean algebra (George Boole, 1815-1864)
* Theorem: A = A.

* Theorem: A = A.
The theorem can be proved by constructing a truth table:
A A A
0 1 0
1 0 1

* Theorem: A = A.
A A A
0 1 0
1 0 1
Therefore, for all possible values that A can take (i.e., 0 and 1), A is the same as A.
⇒ A = A.

* Theorem: A = A.
A A A
0 1 0
1 0 1
⇒ A = A.
* Similarly, the following theorems can be proved:
A+0=A A·1=A
A+1=1 A·0=0
A+A=A A·A=A
A+A=1 A·A=0

* Theorem: A = A.
A A A
0 1 0
1 0 1
⇒ A = A.
* Similarly, the following theorems can be proved:
A+0=A A·1=A
A+1=1 A·0=0
A+A=A A·A=A
A+A=1 A·A=0
Note the duality: (+ ←→ ·) and (1 ←→ 0).

De Morgan’s theorems
A B A+B A+B A B A·B A·B A·B A+B

0 0
0 1
1 0
1 1


0 0 0
0 1 1
1 0 1
1 1 1


0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0


0 0 0 1 1
0 1 1 0 1
1 0 1 0 0
1 1 1 0 0


0 0 0 1 1 1
0 1 1 0 1 0
1 0 1 0 0 1
1 1 1 0 0 0


0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0


0 0 0 1 1 1 1 0
0 1 1 0 1 0 0 0
1 0 1 0 0 1 0 0
1 1 1 0 0 0 0 1


0 0 0 1 1 1 1 0 1
0 1 1 0 1 0 0 0 1
1 0 1 0 0 1 0 0 1
1 1 1 0 0 0 0 1 0


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0
* Comparing the truth tables for A + B and A B, we conclude that A + B = A B.


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

* Similiarly, A · B = A + B.


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

* Similar relations hold for more than two variables, e.g.,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,
A + B + C + D = A · B · C · D,


0 0 0 1 1 1 1 0 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 0 0 0 0 1 0 0

A · B · C = A + B + C,
A + B + C + D = A · B · C · D,
(A + B) · C = (A + B) + C = A · B + C .

Distributive laws
1. A · (B + C ) = A B + A C .

Distributive laws
1. A · (B + C ) = A B + A C .
A B C B +C A · (B + C ) AB AC AB + AC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 1 0 0 0
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 1 1 1 0 1
1 1 0 1 1 1 0
1 1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

Distributive laws
1. A · (B + C ) = A B + A C .
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

Distributive laws
2. A + B · C = (A + B) · (A + C ).
A B C BC A+BC A+B A+C (A + B) (A + C )

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 1 1 1
1 0 0 0 1 1
1 0 1 0 1 1
1 1 0 0 1 1
1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 0 1 1 1
1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

Distributive laws
2. A + B · C = (A + B) · (A + C ).

0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

Useful theorems
* A + A B = A.
To prove this theorem, we can follow two approaches:

Useful theorems
* A + A B = A.
(a) Construct truth tables for LHS and RHS for all possible input combinations, and show that they are
the same.

Useful theorems
* A + A B = A.
the same.
(b) Use identities and theorems stated earlier to show that LHS=RHS.

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A
* A · (A + B) = A.

Useful theorems
* A + A B = A.
the same.
A + AB = A · 1 + A · B
= A · (1 + B)
= A · (1)
=A
* A · (A + B) = A.
Proof: A · (A + B) = A · A + A · B
= A + AB
=A

Duality
A + AB = A ←→ A · (A + B) = A.
Note the duality between OR and AND.

Duality
A + AB = A ←→ A · (A + B) = A.
Dual of A + (A B) (LHS): A B → A + B
A + A B → A · (A + B).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
Dual of A (RHS) = A (since there are no operations ivolved).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.
Similarly, consider A + A = 1, with (+ ←→ .) and (1 ←→ 0).

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of LHS = A · A.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of RHS = 0.

Duality
A + AB = A ←→ A · (A + B) = A.
A + A B → A · (A + B).
⇒ A · (A + B) = A.

Dual of RHS = 0.
⇒ A · A = 0.

Useful theorems
* A + A B = A + B.

Useful theorems
* A + A B = A + B.
Proof: A + A B = (A + A) · (A + B) (by distributive law)

= 1 · (A + B)
=A+B
Dual theorem: A · (A + B) = A B.

Useful theorems
* A + A B = A + B.

= 1 · (A + B)
=A+B
* A B + A B = A.

Useful theorems
* A + A B = A + B.

= 1 · (A + B)
=A+B
* A B + A B = A.
Proof: A B + A B = A · (B + B) (by distributive law)

=A·1
=A
Dual theorem: (A + B) · (A + B) = A.

A game of words
In an India-Australia match, India will win if one or more of the following conditions are met:

A game of words
(a) Tendulkar scores a century.

A game of words
(b) Tedulkar does not score a century AND Warne fails (to get wickets).

A game of words
(c) Tedulkar does not score a century AND Sehwag scores a century.

A game of words
Let T ≡ Tendulkar scores a century.
S ≡ Sehwag scores a century.
W ≡ Warne fails.
I ≡ India wins.

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)
=T +W +T +S
=T +W +S

A game of words
W ≡ Warne fails.
I ≡ India wins.
I =T +TW +TS
=T +T +TW +TS
= (T + T W ) + (T + T S)
= (T + T ) · (T + W ) + (T + T ) · (T + S)
=T +W +T +S
=T +W +S
i.e., India will win if one or more of the following hold:

(a) Tendulkar strikes, (b) Warne fails, (c) Sehwag strikes.

Logical functions in standard forms
Consider a function X of three variables A, B, C :

X = AB C + AB C + AB C + AB C
≡ X1 + X2 + X3 + X4


≡ X1 + X2 + X3 + X4
This form is called the “sum of products” form (“sum” corresponding to OR

and “product” corresponding to AND).


≡ X1 + X2 + X3 + X4

We can construct the truth table for X in a systematic manner:


≡ X1 + X2 + X3 + X4

(1) Enumerate all possible combinations of A, B, C .
Since each of A, B, C can take two values (0 or 1), we have 23 possibilities.


≡ X1 + X2 + X3 + X4

(2) Tabulate X1 = A B C , etc. Note that X1 is 1 only if A = B = C = 1 (i.e., A = 0, B = 1, C = 0),
and 0 otherwise.


≡ X1 + X2 + X3 + X4

(2) Tabulate X1 = A B C , etc. Note that X1 is 1 only if A = B = C = 1 (i.e., A = 0, B = 1, C = 0),
and 0 otherwise.
(3) Since X = X1 + X2 + X3 + X4 ,
X is 1 if any of X1 , X2 , X3 , X4 is 1; else X is 0.
→ tabulate X .

“Sum of products” form
X = X1 + X2 + X3 + X4 = A B C + A B C + A B C + A B C
A B C X1 X2 X3 X4 X
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C X1 X2 X3 X4 X
0 0 0
0 0 1
0 1 0 1
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C X1 X2 X3 X4 X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A B C X1 X2 X3 X4 X
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
A B C X1 X2 X3 X4 X
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0
0 0 1 0 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 0 0 0
1 1 0 0 0 0
1 1 1 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 0 0 1
1 0 1 0 0 0
1 1 0 0 0 0 1
1 1 1 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 1 0
1 0 1 0 0 0 0
1 1 0 0 0 0 1
1 1 1 0 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 1 0 0 1
1 0 0 0 0 1 0 1
1 0 1 0 0 0 0
1 1 0 0 0 0 1 1
1 1 1 0 0 0 0
A B C X1 X2 X3 X4 X
0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 1 0 0 1
1 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0
1 1 0 0 0 0 1 1
1 1 1 0 0 0 0 0

Consider a function Y of three variables A, B, C :

Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
This form is called the “product of sums” form (“sum” corresponding to OR,


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
We can construct the truth table for Y in a systematic manner:


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
(2) Tabulate Y1 = A + B + C , etc. Note that Y1 is 0 only if A = B = C = 0;
Y1 is 1 otherwise.


Y = (A + B + C ) · (A + B + C ) · (A + B + C ) · (A + B + C )
≡ Y1 · Y2 · Y3 · Y4
(2) Tabulate Y1 = A + B + C , etc. Note that Y1 is 0 only if A = B = C = 0;
Y1 is 1 otherwise.
(3) Since Y = Y1 Y2 Y3 Y4 ,
Y is 0 if any of Y1 , Y2 , Y3 , Y4 is 0; else Y is 1.
→ tabulate Y .

“Product of sums” form
Y = Y1 Y2 Y3 Y4 = (A + B + C) (A + B + C) (A + B + C) (A + B + C)
A B C Y1 Y2 Y3 Y4 Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0
0 0 1 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1 0
1 1 0 1 1
1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 1 1 1 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 0 1
1 1 0 1 1 1 1
1 1 1 1 1 1 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1
1 1 1 1 1 1 0 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1 1
1 1 1 1 1 1 0 0
A B C Y1 Y2 Y3 Y4 Y
0 0 0 0 1 1 1 0
0 0 1 1 0 1 1 0
0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 1 1 0 1 0
1 1 0 1 1 1 1 1
1 1 1 1 1 1 0 0
Note that Y is identical to X (seen two slides back). This is an example of how the same function can be written in two
seemingly different forms (in this case, the sum-of-products form and the product-of-sums form).
Standard sum-of-products form

X = AB C + AB C + AB C


This form is called the standard sum-of-products form, and each individual term (consisting of all three
variables) is called a “minterm.”


In the truth table for X , the numbers of 1s is the same as the number of minterms, as we have seen in an
example.


example.
X can be rewritten as,
X = A B C + A B (C + C )
= A B C + A B.


example.
X = A B C + A B (C + C )
= A B C + A B.
This is also a sum-of-products form, but not the standard one.

Standard product-of-sums form

X = (A + B + C ) (A + B + C ) (A + B + C )


X = (A + B + C ) (A + B + C ) (A + B + C )
This form is called the standard product-of-sums form, and each individual term (consisting of all three
variables) is called a “maxterm.”


X = (A + B + C ) (A + B + C ) (A + B + C )
In the truth table for X , the numbers of 0s is the same as the number of maxterms, as we have seen in an
example.


X = (A + B + C ) (A + B + C ) (A + B + C )
example.
X = (A + B + C ) (A + B + C ) (A + B + C )
= (A + B + C ) (A + C + B) (A + C + B)
= (A + B + C ) (A + C + B B)
= (A + B + C ) (A + C ).


X = (A + B + C ) (A + B + C ) (A + B + C )
example.
X = (A + B + C ) (A + B + C ) (A + B + C )
= (A + B + C ) (A + C + B) (A + C + B)
= (A + B + C ) (A + C + B B)
= (A + B + C ) (A + C ).
This is also a product-of-sums form, but not the standard one.

The “don’t care” condition
I want to design a box (with inputs A, B, C , and output S) which will help in scheduling my appointments.
A ≡ I am in town, and the time slot being suggested for the appointment is free.
B ≡ My favourite player is scheduled to play a match (which I can watch on TV).
C ≡ The appointment is crucial for my business.
S ≡ Schedule the appointment.

The following truth table summarizes the expected functioning of the box.
A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1
Note that we have a new entity called X in the truth table.

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

X can be 0 or 1 (it does not matter) and is therefore called the “don’t care” condition.

A B C S
0 X X 0
1 0 X 1
1 1 0 0
1 1 1 1

X can be 0 or 1 (it does not matter) and is therefore called the “don’t care” condition.
Don’t care conditions can often be used to get a more efficient implementation of a logical function.

Karnaugh maps
* A Karnaugh map (“K-map”) is a representation of the truth table of a logical

function.

Karnaugh maps

function.
* A K-map can be used to obtain a “minimal” expression of a function in the
sum-of-products form or in the product-of-sums form.

Karnaugh maps

function.
* A “minimal” expression has a minimum number of terms, each with a minimum
number of variables. (For some functions, it is possible to have more than one
minimal expressions, i.e., more than one expressions with the same complexity.)

Karnaugh maps

function.
* A “minimal” expression has a minimum number of terms, each with a minimum
number of variables. (For some functions, it is possible to have more than one
minimal expressions, i.e., more than one expressions with the same complexity.)
* A minimal expression can be implemented with fewer gates.

K-maps
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 X
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0
1 0 0 X 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1 X
1 0 0 X 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB
0 1 0 1 00 01 11 10
C
0 1 1 0 0 1 X
1 0 0 X 1 1 1
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
* A K-map is the same as the truth table of a function except for the way the entries are arranged.
K-maps
A B C Y
0 0 0 0
0 0 1 1
AB AB
0 1 0 1 00 01 11 10 00 01 11 10
C C
0 1 1 0 0 1 X 0 0 1 0 X
1 0 0 X 1 1 1 1 1 0 1 0
1 0 1 0
1 1 0 0
1 1 1 1
* A K-map is the same as the truth table of a function except for the way the entries are arranged.
* In a K-map, the adjacent rows or columns differ only in one variable. For example, in going from the
column A B = 01 to A B = 11, there is only one change, viz., A = 0 → A = 1.

K-maps: example with four variables
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 AB
CD 00 01 11 10
0 1 0 1 1 00 0 0 0 0
0 1 1 0 0 01 1 1 0 X
0 1 1 1 0 11 1 0 1 1
1 0 0 0 0 10 1 0 0 0
1 0 0 1 X
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 0 0 0
11 0 0 0 0
10 0 0 0 0
X1 = A B C D
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0
X1 = A B C D X2 = A C D
K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
*
No. of variables No. of 1’s
4 20
3 21
2 22

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
*
No. of variables No. of 1’s
4 20
3 21
2 22
* The 1’s can be enclosed by a rectangle in each case.

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3
* We are interested in identifying a minimal expression from the given K-map.

K-maps
AB AB AB
CD 00 01 11 10 CD 00 01 11 10 CD 00 01 11 10
00 0 0 1 0 00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 0 0 01 0 0 0 0
11 0 0 0 0 11 0 0 0 0 11 0 0 1 1
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1
X1 = A B C D X2 = A C D X3 = A C
AB
CD 00 01 11 10
00 0 0 1 0
01 1 1 0 0
11 0 0 1 1
10 0 0 1 1
Y = X1 + X2 + X3
* We are interested in identifying a minimal expression from the given K-map.

* Minimal: smallest number of terms, smallest number of variables in each term
→ smallest number of rectangles containing 2k 1’s, each as large as possible
K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0
What is the logical function (Y ) represented by this K-map?

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0
* There are 21 1’s forming a rectangle → we can combine them.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term is 1 if B = 1, and C = 0.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term does not depend on A.

K-maps
AB
C 00 01 11 10
0 0 1 1 0
1 0 0 0 0

* The product term does not depend on A.
→ Y =B C

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1
Can the 1s shown in the K-map be combined?

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1

Although the number of 1’s is a power of 2 (21 ), they cannot be combined because they are not adjacent
(i.e., they do not form a rectangle).

K-maps
AB
C 00 01 11 10
0 0 0 1 0
1 0 0 0 1

Although the number of 1’s is a power of 2 (21 ), they cannot be combined because they are not adjacent
(i.e., they do not form a rectangle).
→ the function (A B C + A B C ) cannot be minimized.

K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0
K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0
Can the 1’s shown in the K-map be combined?

K-maps
AB
C 00 01 11 10
0 1 0 0 1
1 0 0 0 0

Let us redraw the K-map by changing the order of the columns cyclically.
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

The two 1’s are, in fact, adjacent and can be combined to give B C .
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

→ Columns A B = 00 and A B = 10 in the K-map on the left are indeed “logically adjacent” (although they are
not geometrically adjacent) since they differ only in one variable (A).
K-maps
AB AB
C 00 01 11 10 C 10 00 01 11
0 1 0 0 1 0 1 1 0 0
1 0 0 0 0 1 0 0 0 0

→ Columns A B = 00 and A B = 10 in the K-map on the left are indeed “logically adjacent” (although they are
not geometrically adjacent) since they differ only in one variable (A).
We could have therefore combined the 1’s without actually redrawing the K-map.

K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 0 0 0 0
10 0 0 0 0
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
11 0 0 0 0
10 0 0 0 0
K-maps
AB
CD 00 01 11 10
00 1 0 0 1
01 0 0 0 0
X1 = B D
11 0 0 0 0
10 1 0 0 1
AB
CD 00 01 11 10
00 1 0 0 1
01 1 0 0 1
X2 = B C
11 0 0 0 0
10 0 0 0 0

K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0
Standard sum-of-products form:

X1 = A B C D + A B C D + A B C D
Since the number of minterms is not a power of 2, they cannot be combined

into a single term; however, they can be combined into two terms:
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


X1 = A B C D + A B C D + A B C D + A B C D (using Y=Y+Y)
= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 0 0 1 0
01 0 1 1 0
11 0 0 0 0
10 0 0 0 0


= A B C (D + D) + B C D (A + A)
= ABC + BCD
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1
11 0 0 1 0
10 0 0 0 1
K-maps
AB
CD 00 01 11 10
00 1 1 0 1
X1 : 01 1 1 0 1 X1 = A C + B C + A B C D + A B D
11 0 0 1 0
10 0 0 0 1

K-maps
AB
CD 00 01 11 10
00 0 0 X 0
Z: 01 1 1 0 0
11 0 0 0 0
10 1 X 1 1
K-maps
AB
CD 00 01 11 10
00 0 0 X 0
Z: 01 1 1 0 0
11 0 0 0 0
10 1 X 1 1
Since X represents a “don’t care” condition, we can assign 0 or 1 to the corresponding minterm to arrive at a
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.
K-maps
AB AB
CD 00 01 11 10 CD 00 01 11 10
00 0 0 X 0 00 0 0 0 0
Z: 01 1 1 0 0 01 1 1 0 0 Z = CD + ACD
11 0 0 0 0 11 0 0 0 0
10 1 X 1 1 10 1 1 1 1
minimal expression.

Binary numbers
Decimal (base 10) system
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100
102 101 100

Binary numbers
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100
102 101 100
* Digits: 0,1,2,..,9
* example: 4 1 5 3
most significant least significant

digit digit
Binary numbers
Decimal (base 10) system Binary (base 2) system
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
0
10 2
101 10 2 0
24 23 21
22
* Digits: 0,1,2,..,9
* example: 4 1 5 3
most significant least significant

digit digit
Binary numbers
3 1 7 = 3 × 102 + 1 × 101 + 7 × 100 1 0 1 1 1 = 1 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20

= 23 (in decimal)
0
10 2
101 10 2 0
24 23 21
22
* Digits: 0,1,2,..,9
* Bits: 0,1
* example: 4 1 5 3
* example: 1 0 0 1 1 0
most significant least significant most significant least significant

digit digit
bit (MSB) bit (LSB)

Addition of binary numbers
104 103 102 101 100 weight

3 1 7 9 first number
8 0 1 5 second number
1 1 carry
1 1 1 9 4 sum
104 103 102 101 100 weight 24 23 22 21 20 weight
3 1 7 9 first number 1 0 1 1 first number (dec. 11)
8 0 1 5 second number 1 1 1 0 second number (dec. 14)
1 1 carry 1 1 1 carry
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)

104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
104 103 102 101 100 weight 24 23 22 21 20 weight
1 1 1 9 4 sum 1 1 0 0 1 sum (dec. 25)
* 0 + 1 = 1 + 0 = 1 → S = 1, C = 0
* 1 + 1 = 10 (dec. 2) → S = 0, C = 1
* 1 + 1 + 1 = 11 (dec. 3) → S = 1, C = 1

example
24 23 22 21 20 weight
1 0 1 1 first number
1 1 1 0 second number
1 1 1 0 − carry
1 1 0 0 1 sum
example general procedure
24 23 22 21 20 weight 2N 22 21 20 weight
1 0 1 1 first number AN ··· A2 A1 A0 first number
1 1 1 0 second number BN ··· B2 B1 B0 second number
1 1 1 0 − carry CN CN−1 · · · C1 C0 carry
1 1 0 0 1 sum SN S2 S1 S0 sum
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
AN BN A2 B2 A1 B1 A 0 B0
A A A A
FA B FA B FA B HA B
CN Co S Cin Co S Cin Co S Cin Co S

CN−1 C1 C0
SN S2 S1 S0
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
A A A A
FA B FA B FA B HA B

CN−1 C1 C0
SN S2 S1 S0
* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input carry.
This block is called a “half adder.”
24 23 22 21 20 weight 2N 22 21 20 weight
1 1 0 0 1 sum SN S2 S1 S0 sum
A A A A
FA B FA B FA B HA B

CN−1 C1 C0
SN S2 S1 S0
* The rightmost block (corresponding to the LSB) adds two bits A0 and B0 ; there is no input carry.
This block is called a “half adder.”
* Each of the subsequent blocks adds three bits (Ai , Bi , Ci−1 ) and is called a “full adder.”
Half adder implementation
A B Co S
A A0
HA B
0 0 0 0
B0
Co S 0 1 0 1
C0 1 0 0 1
1 1 1 0
S0
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
Implementation 1
A AB
B
S
AB
A
Co
B
A B Co S
A A0
HA B
0 0 0 0
B0 S = AB + AB = A ⊕ B
Co S 0 1 0 1
C0 Co = A B
1 0 0 1
1 1 1 0
S0
Implementation 1 Implementation 2
A AB
B A A+B
S B
S
AB Co
AB
A
Co
B

Full adder implementation
A
FA B
Co S Cin
A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
FA B AB
Cin 00 01 11 10
Co S Cin 0 0 1 0 1
S:
1 1 0 1 0
S = A B Cin + A B Cin + A B Cin + A B Cin

A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
FA B AB
Cin 00 01 11 10
Co S Cin 0 0 1 0 1
S:
1 1 0 1 0
S = A B Cin + A B Cin + A B Cin + A B Cin

A B Cin Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
AB
0 1 1 1 0 Cin 00 01 11 10
0 0 0 1 0
1 0 0 0 1 Co :
1 0 1 1 1
1 0 1 1 0
1 1 0 1 0 Co = A B + B Cin + A Cin
1 1 1 1 1
Implementation of functions with only NAND gates
The NOT, AND, OR operations can be realised by using only NAND gates:
NOT
A= A·A
A A
NOT AND
A= A·A A·B= A·B
A
A A AB
B
NOT AND OR
A= A·A A·B= A·B A+B =A·B
A
A
A A AB A+B
B
B

Implement Y = A B + B C D + A D using only NAND gates.

A= A·A
A·B =A·B
A+B= A·B
Y = AB ·BCD · AD
A= A·A
A·B =A·B
A+B= A·B
Y = AB ·BCD · AD
AB A= A·A
A·B =A·B
A+B= A·B
Y
BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
A+B= A·B
Y
BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD
AD
Y = AB ·BCD · AD
A AB A= A·A
B A·B =A·B
B
C A+B= A·B
Y
D BCD
A
D AD

A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D
A
A A= A·A
B A·B= A·B
B
A+B= A·B
C Y
D
D

Implement Y = A + B + C using only 2-input NAND gates.

A=A·A
A·B =A·B
A+B =A·B
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B =A·B
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B
A+B =A·B
C
Y = (A + B) + C
= (A + B) · C
A=A·A
A·B =A·B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A·B =A·B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A·B =A·B
A+B
A+B
A+B =A·B
C C
Y = (A + B) + C
= (A + B) · C
= A·B·C
A=A·A
A A A·B =A·B
A+B
A+B
A+B =A·B
B B
Y
C C

Implementation of functions with only NOR gates
The NOT, AND, OR operations can be realised by using only NOR gates:
NOT
A= A+A
A A
NOT AND
A= A+A A·B= A+B
A
A A AB
B
NOT AND OR
A= A+A A·B= A+B A+B =A+B
A
A
A A AB A+B
B
B
NOT AND OR
A= A+A A·B= A+B A+B =A+B
A
A
A A AB A+B
B
B
Implementation of functions with only NOR (or only NAND) gates is more than a theoretical curiosity. There
are chips which provide a “sea of gates” (say, NOR gates) which can be configured by the user (through
programming) to implement functions.

Implement Y = A B + B C D + A D using only NOR gates.
A= A+A
A+B= A+B
A·B =A+B
Y = AB + BCD + AD
A= A+A
A+B= A+B
A·B =A+B
Y = AB + BCD + AD
A= A+A
AB
A+B= A+B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A= A+A
AB
A+B= A+B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
Y
BCD
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D
AD
Y = AB + BCD + AD
= (A + B) + (B + C + D) + (A + D)
A
A A= A+A
AB
B A+B= A+B
B
A·B =A+B
C
C Y
BCD
D
A
AD
D
D

Multiplexers
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3
Multiplexers
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
S1 S0
1 1 I3
* A multiplexer or data selector (MUX in short) has N Select lines, 2N input lines, and it routes one of the
input lines to the output.
Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
* Conceptually, a MUX may be thought of as 2N switches. For a given combination of the select inputs,
only one of the switches closes (makes contact), and the others are open.

Multiplexers
S1 S0 Z
I0
I0 SW0
0 0 I0 I1 SW1
I1
Z 0 1 I1 I2 SW2
I2 Z
I3 1 0 I2 I3 SW3
S1 S0 S1 S0
1 1 I3
* Conceptually, a MUX may be thought of as 2N switches. For a given combination of the select inputs,
only one of the switches closes (makes contact), and the others are open.
* SEQUEL file: mux test 1.sqproj

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0
* A 4-to-1 MUX can be implemented as,

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
For a given combination of S1 and S0 , only one of the terms survives (the others being 0). For example, with S1 = 0,
S0 = 1, we have Z = I1 .

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.

Multiplexers
I0
S1 S0 Z
I0 I1
0 0 I0
I1
Z 0 1 I1 Z
I2 I2
I3 1 0 I2
S1 S0
1 1 I3
I3
S1 S0

Z = I0 S1 S0 + I1 S1 S0 + I2 S1 S0 + I3 S1 S0 .
S0 = 1, we have Z = I1 .
* Multiplexers are available as ICs, e.g., 74151 is an 8-to-1 MUX.
* ICs with arrays of multiplexers (and other digital blocks) are also available. These blocks can be configured (“wired”) by
the user in a programmable manner to realise the functionality of interest.
Active high and active low inputs/outputs
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.
Active high and active low inputs/outputs
S1 S0 Z
I0
0 0 I0
I1
Z 0 1 I1
I2
I3 1 0 I2
1 1 I3
S1 S0
Select inputs are active high.
S1 S0 Z
I0
1 1 I0
I1
Z 1 0 I1
I2
I3 0 1 I2
0 0 I3
S1 S0
Select inputs are active low.

Enable (E) pin
inputs outputs inputs outputs
E E
Active high enable pin Active low enable pin

Enable (E) pin
E E
* Many digital ICs have an “Enable” (E) pin. If the Enable pin is active, the IC functions as desired; else, it
is “disabled,” i.e., the outputs are set to some default values.

Enable (E) pin
E E
* The Enable pin can be active high or active low.

Enable (E) pin
E E
* The Enable pin can be active high or active low.
* If the Enable pin is active low, it is denoted by Enable or E. When E = 0, the IC functions normally; else,
it is disabled.

Using two 8-to-1 MUXs to make a 16-to-1 MUX
D0 I0 S3 S2 S1 S0 X
D1 I1
D2 I2 0 0 0 0 D0
D3 I3
0 0 0 1 D1
D4 I4 74151 Z X1
D5 I5 0 0 1 0 D2
D6 I6
D7 I7 0 0 1 1 D3
D8 S2 S1 S0
0 1 0 0 D4
D9
D10 E 0 1 0 1 D5
D11
D12 X 0 1 1 0 D6
D13 0 1 1 1 D7
D14
D15 I0 1 0 0 0 D8
I1
1 0 0 1 D9
I2
I3 1 0 1 0 D10
I4 74151 Z X2
I5 1 0 1 1 D11
I6
1 1 0 0 D12
I7
S2 S1 S0 1 1 0 1 D13
E 1 1 1 0 D14
1 1 1 1 D15
S3 S2 S1 S0 M. B. Patil, IIT Bombay

Implement X = A B C D + A B C D using a 16-to-1 MUX.
A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
A B C D X * When A B C D = 1, we want X = 1.
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
D = 1, i.e., the input line corresponding to
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1
I2
0 1 0 0 1 I3
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
0 0 1 1 0 I1 * Similarly, when A B C D = 1, we want
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
I5
0 1 1 0 0 I6
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
I0
I2 X = 1.
0 1 0 0 1 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
I5 * In all other cases, X should be 0.
0 1 1 0 0 I6 → connect all other pins to 0.
I7 MUX Z X
0 1 1 1 0 I8
1 I9
1 0 0 0 0
I10
1 0 0 1 1 I11
I12
1 0 1 0 0 I13
I14
1 0 1 1 0
I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
0 I0
0 0 1 1 0 0 I1 * Similarly, when A B C D = 1, we want
0 I2 X = 1.
0 1 0 0 1 0 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
0 I5 * In all other cases, X should be 0.
0 1 1 0 0 0 I6 → connect all other pins to 0.
0 I7 MUX Z X
0 1 1 1 0 0 I8
1 I9
1 0 0 0 0
0 I10
1 0 0 1 1 0 I11
0 I12
1 0 1 0 0 0 I13
0 I14
1 0 1 1 0
0 I15
1 1 0 0 0 S3 S2 S1 S0
1 1 0 1 0
A B C D
1 1 1 0 0
1 1 1 1 0
0 0 0 0 0 A B C D = 1 → A = 1, B = 0, C = 0,
0 0 0 1 0 1001 (I9) gets selected.
0 0 1 0 0 → Make I9 = 1.
0 I0
0 0 1 1 0 0 I1 * Similarly, when A B C D = 1, we want
0 I2 X = 1.
0 1 0 0 1 0 I3
→ Make I4 = 1.
1 I4
0 1 0 1 0
0 I5 * In all other cases, X should be 0.
0 1 1 0 0 0 I6 → connect all other pins to 0.
0 I7 MUX Z X
0 1 1 1 0 0 I8 * In this example, since the truth table is
1 I9 organized in terms of ABCD, with A as
1 0 0 0 0
0 I10
I11
the MSB and D as the LSB (the same
1 0 0 1 1 0
0 I12 order in which A, B, C , D are connected
1 0 1 0 0 0 I13 to the select pins), the design is simple:
0 I14 connect
1 0 1 1 0
0 I15 I0 to X(0 0 0 0),
1 1 0 0 0 S3 S2 S1 S0
I1 to X(0 0 0 1),
1 1 0 1 0
A B C D
I2 to X(0 0 1 0), etc.
1 1 1 0 0
1 1 1 1 0
Implement X = A B C D + A B C D using an 8-to-1 MUX.
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C
* When A B C = 1, i.e., A = 1, B = 0, C = 0, we have X = D.

→ connect the input line corresponding to 100 (I4) to D.
A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 I0
I1
0 0 1 0
D I2
0 1 0 D
I3
MUX Z X
0 1 1 0 D I4
1 0 0 D I5
I6
1 0 1 0
I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* In all other cases, X should be 0.
→ connect all other pins to 0.
A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

A B C X
0 0 0 0 0 I0
0 I1
0 0 1 0
D I2
0 1 0 D
0 I3
MUX Z X
0 1 1 0 D I4
1 0 0 D 0 I5
0 I6
1 0 1 0
0 I7 S2 S1 S0
1 1 0 0
1 1 1 0 A B C

* Home work: Implement the same function (X ) with S2 = B, S1 = C , S0 = D.
A B C D X
Implement the function X using an 8-to-1 MUX.
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
I2
0 1 1 0 0
I3
0 1 1 1 1 MUX Z X
I4
1 0 0 0 1 I5
1 0 0 1 0 I6
I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 D I0
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
A B C D X
0 0 0 0 1
0 0 0 1 0 * When ABC = 000, X = D → I0 = D.
0 0 1 0 1 * When ABC = 001, X = 1 → I1 = 1,
0 0 1 1 1 and so on.
0 1 0 0 0 * Home work: repeat with S2 = B, S1 = C ,

D I0
S0 = D.
0 1 0 1 0 1 I1
0 I2
0 1 1 0 0
D I3
0 1 1 1 1 MUX Z X
D I4
1 0 0 0 1 1 I5
1 0 0 1 0 0 I6
0 I7 S2 S1 S0
1 0 1 0 1
1 0 1 1 1
A B C
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* A demultiplexer takes a single input (I) and routes it to one of the output lines (O0, O1,· · · ).

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .

Demultiplexers
S2 S1 S0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 I 0 0 0 0 0 0 0 O0
0 0 1 0 I 0 0 0 0 0 0 O1
0 1 0 0 0 I 0 0 0 0 0 O2
O3
0 1 1 0 0 0 I 0 0 0 0 I DEMUX
O4
1 0 0 0 0 0 0 I 0 0 0 O5
1 0 1 0 0 0 0 0 I 0 0 O6
1 1 0 0 0 0 0 0 0 I 0 S2 S1 S0 O7
1 1 1 0 0 0 0 0 0 0 I
* For N Select inputs (S0, S1,· · · ), the number of output lines is 2N .
* SEQUEL file: demux test 1.sqproj

Demultiplexer: gate-level diagram
I
O0
O1
O2
O0
O1
O2 O3
O3
I DEMUX
O4 O4
O5
O6 O5
S2 S1 S0 O7
O6
O7
S2 S1 S0 M. B. Patil, IIT Bombay

Decoders
A0 O0
A1 O1
N inputs Decoder M outputs
AN−1 OM−1

Decoders
A0 O0
A1 O1
N inputs Decoder M outputs
AN−1 OM−1
* For each input combination, an associated bit pattern appears at the output.

3-to-8 decoder (1-of-8 decoder)
A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
O0
O1 0 0 1 0 1 0 0 0 0 0 0
O2 0 1 0 0 0 1 0 0 0 0 0
A0
O3
A1 Decoder 0 1 1 0 0 0 1 0 0 0 0
O4
A2 1 0 0 0 0 0 0 1 0 0 0
O5
O6 1 0 1 0 0 0 0 0 1 0 0
O7 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Binary-Coded-Decimal (BCD) encoding
* Example:
Decimal 75

* Example:
Decimal 75
Binary 1001011

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
* BCD coding is commonly used to display numbers in electronic systems.

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
BCD 0111 0101
input
BCD−to−7−seg
decoder
7−segment
display

* Example:
Decimal 75
Binary 1001011
BCD 0111 0101
BCD 0111 0101
input
BCD−to−7−seg
decoder
7−segment
display
* In some electronic systems (e.g., calculators), all computations are performed in BCD.

7-segment display
VCC
a
common
a anode
b
f b
c
e g
f e c
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
BCD-to-7 segment decoder
VCC
a
a common
anode
MSB b
D c f b
C d
7446
B e g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VCC
a
a common
* The resistors serve to limit the diode
anode
b current. For VCC = 5 V , VD = 2 V , and
MSB
ID = 10 mA, R = 300 Ω.
D c f b
C d
7446
B e g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VCC
a
a common
* The resistors serve to limit the diode
anode
b current. For VCC = 5 V , VD = 2 V , and
MSB
ID = 10 mA, R = 300 Ω.
D c f b * Home work: Write the truth table for
C d c (in terms of D, C , B, A). Obtain a
7446 minimized expression for c using a K
B e map.
g
A f
LSB e c
g
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
BCD-to-decimal decoder
A3 A2 A1 A0 Active output
0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2
O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2
A0 0 1 0 1 O5
O3
A1 0 1 1 0 O6
7442 O4
A2
O5 0 1 1 1 O7
A3
O6 1 0 0 0 O8
O7
1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none
BCD-to-decimal decoder
A3 A2 A1 A0 Active output
0 0 0 0 O0
0 0 0 1 O1
0 0 1 0 O2
O0 0 0 1 1 O3
O1 0 1 0 0 O4
O2
A0 0 1 0 1 O5
O3
A1 0 1 1 0 O6
7442 O4
A2
O5 0 1 1 1 O7
A3
O6 1 0 0 0 O8
O7
1 0 0 1 O9
O8
1 0 1 0 none
O9
1 0 1 1 none
1 1 0 0 none
1 1 0 1 none
1 1 1 0 none
1 1 1 1 none
Encoders
A0 O0
A1 O1
M inputs Encoder N outputs
AM−1 ON−1

Encoders
A0 O0
A1 O1
AM−1 ON−1
* Only one input line is assumed to be active. The binary number corresponding to the active input line
appears at the output pins.

Encoders
A0 O0
A1 O1
AM−1 ON−1
* The N output lines can represent 2N binary numbers, each corresponding to one of the M input lines, i.e.,
we can have M = 2N . Some encoders have M < 2N .

Encoders
A0 O0
A1 O1
AM−1 ON−1
* The N output lines can represent 2N binary numbers, each corresponding to one of the M input lines, i.e.,
we can have M = 2N . Some encoders have M < 2N .
* As an example, for N = 3, we can have a maximum of 23 = 8 input lines.

Encoders
8−to−3 encoder example A0 A1 A2 A3 A4 A5 A6 A7 O2 O1 O0

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Encoders

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
* Note that only one of the input lines is assumed to be active.

Encoders

1 0 0 0 0 0 0 0 0 0 0
A0
0 1 0 0 0 0 0 0 0 0 1
A1
A2 0 0 1 0 0 0 0 0 0 1 0
O0
A3 0 0 0 1 0 0 0 0 0 1 1
Encoder O1
A4
O2 0 0 0 0 1 0 0 0 1 0 0
A5
0 0 0 0 0 1 0 0 1 0 1
A6
A7 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
* Note that only one of the input lines is assumed to be active.

* What if two input lines become simultaneously active?
→ There are “priority encoders” which assign a priority to each of the input lines.

74147 decimal-to-BCD priority encoder
A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binary output is 1000
(i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .

A1 A2 A3 A4 A5 A6 A7 A8 A9 O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
A1 X X X X X X X X 0 0 1 1 0
A2
X X X X X X X 0 1 0 1 1 1
A3
O0 X X X X X X 0 1 1 1 0 0 0
A4
O1 X X X X X 0 1 1 1 1 0 0 1
A5 74147
O2
A6 X X X X 0 1 1 1 1 1 0 1 0
O3
A7
X X X 0 1 1 1 1 1 1 0 1 1
A8
X X 0 1 1 1 1 1 1 1 1 0 0
A9
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
* Note that the higher input lines get priority over the lower ones.
For example, A7 gets priority over A1 , A2 , A3 , A4 , A5 , A6 . If A7 is active (low), the binary output is 1000
(i.e., 0111 inverted bit-by-bit) which corresponds to decimal 7, irrespective of
A1 , A2 , A3 , A4 , A5 , A6 .
* The lower input lines are therefore shown as “don’t care” (X) conditions.

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Digital circuits

analog signal digital signal

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

analog signal digital signal

* An analog signal x(t) is represented by a real number at a given time point.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

* If Vi is low (“0”), Vo is high (“1”).

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Operation NOT AND OR

Operation NOT AND OR

Operation NOT AND OR

Notation Y=A Y= A·B

Operation NOT AND OR

Notation Y=A Y= A·B Y=A+B

M. B. Patil, IIT Bombay

Operation NAND NOR XOR

Operation NAND NOR XOR

Operation NAND NOR XOR

Notation Y= A·B Y= A+B

Operation NAND NOR XOR

Notation Y= A·B Y= A+B Y=A⊕B

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

* The AND operation is commutative.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B

M. B. Patil, IIT Bombay

A B A+B A+B A B A·B A·B A·B A+B