Toshiba N500 N520 (Compal LA-6858P)

A B C D E
1 1
Compal Confidential
2 2
Cougar 2.0
Schematics Document
Intel Cedar Trail Processor/ Tiger point
3 2011-11-07 3
LA-6858P REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QBU00
Date: Monday, November 07, 2011 Sheet 1 of 38
A B C D E
A B C D E
Compal Confidential
Model Name : Cougar 2.0
Project Code : QBU00
1
Fan Control Low Power Clock Generator 1
page 26
RTM890N-397
page 9
CRT Conn. RGB

page 15
Intel Cedarview 2 Core 204pin DDRIII-SO-DIMM
HDMI Conn. HDMI Memory BUS(DDRIII)
page 16 1.86GHz (6.5W) page 10
1.5V DDRIII 1066MHz

LED Conn. LVDS (22x22mm) page 6,7,8
page 17 ONE CHANNEL
2
DMI x 2 2
PCIeMini Card
WWAN PCIe port 3 USB Conn X3 Int. Camera
(FULL)
USB port 5 USB USB USB port 0,1,4 USB port 7
page 18
5V 480MHz 5V 480MHz page 19 page 17
PCIeMini Card
PCIe 1x [2]
WLAN +BT COMBO (HALF) 1.5V 2.5GHz(250MB/s)
Tiger Pointer
PCIe port 2 USB port 6 USB Card Reader Card Reader Conn.
page 18
5V 480MHz RTL5137 page 24
USB port 3 page 24
PCIe 1x
(17x17mm)
RJ45 RTL8105E 1.5V 2.5GHz(250MB/s) SATA port 0 SATA HDD
page 23
10/100 LAN 5V 1.5GHz(150MB/s)
page 20
PCIe port 1 page 23
page 11,12,13,14
3 3
RTC CKT.
page 13 SPI ROM 3.3V 24.576MHz/48Mhz
HD Audio
2MB page 26
3.3V 33 MHz
LPC BUS
DC/DC Interface CKT. HDA Codec
ALC269
page 28 page 21
ENE KB930 E0
page 25
Power Circuit DC/DC
Int.
page 29~35 MIC CONN MIC CONN HP CONN SPK CONN
page 21 page 22 page 22 page 22
Touch Pad Int.KBD SPI ROM 128KB (10A 1X) (10B 2X)
page 27 page 27 page 26
4
Power/B 4
page 27

Block Diagrams
0.3
QBU00
Date: W ednesday, June 29, 2011 Sheet 2 of 38
A B C D E
A B C D E
Voltage Rails
1 SIGNAL 1
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 G3
Full ON HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) ON ON ON OFF
B+ AC or battery power rail for power circuit. ON ON ON ON S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
+GFX_CORE GFX support voltage ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
+1.05VS VCCP switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON OFF OFF OFF BTO Option Table
2 2
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF Function Mini PCI-E SLOT Display Clock gen
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF
description
+RTCVCC RTC power ON ON ON ON explain Wi-Fi WWAN 3G CRT HDMI Tpye
+3VS_PRIME 3.3V power rail for CPU and PCH ON OFF OFF OFF
BTO WLAN@ WWAN@ 3G@ CRT@ HDMI@ low@ normal@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3 3
EC SM Bus1 address EC SM Bus2 address

Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 010X b
NM10 SM Bus address

Device Address
Clock Generator 1101 001Xb

(SLG8SP556VTR)
DDR DIMMA 1010 000Xb
WWAN/WLAN
4 4

Notes List
Custom 0.3
QBU00
Date: W ednesday, June 29, 2011 Sheet 3 of 38
A B C D E
5 4 3 2 1
D D
C C
B B
A
Security Classification Compal Secret Data Compal Electronics, Inc. A
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
0.3
QBU00
Date: Wednesday, June 29, 2011 Sheet 4 of 38
5 4 3 2 1
5 4 3 2 1
B+ DESIGN CURRENT 250mA Cougar Power Map

Ipeak=6.97A, Imax=4.88A
DESIGN CURRENT 522mA
+3VALWP +-5%
** The SW just is reserved.
The power passes by jump or
TPS51125ARGER 0-ohm resistor. WOL_EN#
** P-CHANNEL +3V_LAN
AO3413 DESIGN CURRENT 300mA
D D
Ipeak=3.98A, Imax=2.8A +5VALWP +-5%

SUSP
N-CHANNEL +5VS
SI7326DN
VGATE
APL5930KA DESIGN CURRENT 151mA

+1.8VS
C C
SUSP
N-CHANNEL DESIGN CURRENT 5586mA
+3VS
SI7326DN ENVDD
P-CHANNEL +LCD_VDD
AO3413 DESIGN CURRENT 2000mA
VGATE#
N-CHANNEL DESIGN CURRENT 294mA

+3VS_PRIME
SUSP# SI7326DN
SY8033BDBC Ipeak=1.308A, Imax=4A +1.05VSP +-5%

VR_ON
B Imax=3.5A DESIGN CURRENT 4500mA +CPU_COREP B
RT8165BGQW DESIGN CURRENT 2000mA +GFX_COREP
SYSON
Ipeak=19.6A, Imax=13.72A +1.5VP +-5%
G5603RU1U
SUSP#
DESIGN CURRENT 2112mA +1.5VSP
SI7326DN
SUSP

+0.75VSP
G2992F1U
A A

Power tree
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
N2800@
<10> DDR_A_MA[0..15] U1
QB0Y B2 1.86G
<10> DDR_A_DQS#[0..7]
<10> DDR_A_DM[0..7]
<10> DDR_A_DQS[0..7] N2600@

U1B
U1A N2600@ ?
CEDARVIEW
<10> DDR_A_D[0..63] DDR_A_MA0 AK14 DDR_A_D0
CEDARVIEW
DDR3_MA0 DDR3_DQ0 Y30
DDR_A_MA1 AK16 Y29 DDR_A_D1
REV = 1.10 DDR_A_MA2 AJ14 DDR3_MA1 REV = 1.10 DDR3_DQ1 DDR_A_D2
DDR3_MA2 DDR3_DQ2 AC30
DMI_RXP0_C L3 K6 DMI_TXP0 <12> DDR_A_MA3 AJ16 AC31 DDR_A_D3
DMI_RXN0_C DMI_RXP0 DMI_TXP0 DDR_A_MA4 AK18 DDR3_MA3 DDR3_DQ3 DDR_A_D4
L2 DMI_RXN0 DMI_TXN0 K5 DMI_TXN0 <12> DDR3_MA4 DDR3_DQ4 W31
D DMI_RXP1_C DDR_A_MA5 AH18 DDR_A_D5 D
M3 DMI_RXP1 DMI_TXP1 L5 DMI_TXP1 <12> DDR3_MA5 DDR3_DQ5 W28
DMI_RXN1_C M2 L6 DDR_A_MA6 AJ18 AB28 DDR_A_D6
DMI_RXN1 DMI_TXN1 DMI_TXN1 <12> DDR3_MA6 DDR3_DQ6
N2 L9 DDR_A_MA7 AK20 AB30 DDR_A_D7
DMI_RXP2 DMI_TXP2 DDR_A_MA8 AJ20 DDR3_MA7 DDR3_DQ7 DDR_A_D8
N1 L8 AA24
DMI_RXN2 DMI_TXN2 DDR_A_MA9 AH20 DDR3_MA8 DDR3_DQ8 DDR_A_D9
P2 N5 AA22
DMI
DMI_RXP3 DMI_TXP3 DDR_A_MA10 AJ12 DDR3_MA9 DDR3_DQ9 DDR_A_D10
P3 DMI_RXN3 DMI_TXN3 N6 DDR3_MA10 DDR3_DQ10 AE27
+1.5VS DDR_A_MA11 AK21 AE26 DDR_A_D11
DDR_A_MA12 AJ21 DDR3_MA11 DDR3_DQ11 DDR_A_D12
<9> CLK_CPU_EXP N9 DMI_REFCLKP RSVD_TP_R8 R8 T1 R493 DDR3_MA12 DDR3_DQ12 AB27
N8 R7 DDR_A_MA13 AJ8 AA25 DDR_A_D13
<9> CLK_CPU_EXP# DMI_REFCLKN RSVD_TP_R7 T2 DDR3_MA13 DDR3_DQ13
2 1 DMI_REF1P5 T2 T1 DMI_IRCOMP1 2 DMI_REF1P5 DDR_A_MA14 AH22 AD25 DDR_A_D14
DMI_REF1P5 DMI_RCOMP DDR3_MA14 DDR3_DQ14
1U_0402_6.3V6K
R973 0_0402_5% DDR_A_MA15 AJ22 AD27 DDR_A_D15
7.5K_0402_5% DDR3_MA15 DDR3_DQ15 DDR_A_D16
1 AD29
DDR3_DQ16
C1088
+1.5V pull up must be placed DDR_A_WE# AH10 AE29 DDR_A_D17

<10> DDR_A_WE# DDR3_WE# DDR3_DQ17
1 OF 6 DDR_A_CAS# AJ10 AJ30 DDR_A_D18
within 500 mils from Cedarview <10> DDR_A_CAS# DDR_A_RAS# AJ11
DDR3_CAS# DDR3_DQ18
AK29 DDR_A_D19
2 QB0Z B2 1.6G <10> DDR_A_RAS# DDR3_RAS# DDR3_DQ19
? AD28 DDR_A_D20
DDR_A_BS0 DDR3_DQ20 DDR_A_D21
<10> DDR_A_BS0 AK12 DDR3_BS0 DDR3_DQ21 AD30
DDR_A_BS1 AH13 AG30 DDR_A_D22
<10> DDR_A_BS1 DDR3_BS1 DDR3_DQ22
+1.5V pull up must be placed DDR_A_BS2 AK22 AJ29 DDR_A_D23
<10> DDR_A_BS2 DDR3_BS2 DDR3_DQ23 DDR_A_D24
AE24
within 500 mils from Cedarview AH12
DDR3_DQ24
AG24 DDR_A_D25
DDR3_CS#0 DDR3_DQ25 DDR_A_D26
AH8 AD22
DDR_CS2# DDR3_CS#1 DDR3_DQ26 DDR_A_D27
<10> DDR_CS2# AK11 DDR3_CS#2 DDR3_DQ27 AC21
DDR_CS3# AK8 AG27 DDR_A_D28
<10> DDR_CS3# DDR3_CS#3 DDR3_DQ28 DDR_A_D29
AG25
C948 1 DMI_RXP0_C DDR3_DQ29 DDR_A_D30
<12> DMI_RXP0 2 AH23 DDR3_CKE0 DDR3_DQ30 AG21
0.1U_0402_10V6K AJ24 AE21 DDR_A_D31
DDR_CKE2 DDR3_CKE1 DDR3_DQ31 DDR_A_D32
<10> DDR_CKE2 AK24 AD13
C949 1 DMI_RXN0_C DDR_CKE3 DDR3_CKE2 DDR3_DQ32 DDR_A_D33
<12> DMI_RXN0 2 <10> DDR_CKE3 AH24 DDR3_CKE3 DDR3_DQ33 AD11
0.1U_0402_10V6K SMPWROK AG8 DDR_A_D34
DDR3_DQ34
0.1U_0402_16V4Z
AK10 AG7 DDR_A_D35
C950 1 DMI_RXP1_C DDR3_ODT0 DDR3_DQ35 DDR_A_D36
<12> DMI_RXP1 2 AK7 AG13
DDR3_ODT1 DDR3_DQ36
10K_0402_5%
C 0.1U_0402_10V6K M_ODT2 DDR_A_D37 C
<10> M_ODT2 AL9 DDR3_ODT2 DDR3_DQ37 AE13
M_ODT3 AJ7 AD10 DDR_A_D38
<10> M_ODT3 DDR3_ODT3 DDR3_DQ38
2
C951 1 2 DMI_RXN1_C 1 AF8 DDR_A_D39
<12> DMI_RXN1 DDR3_DQ39
1
0.1U_0402_10V6K D DDR_A_D40
AG15 DDR3_CK0 DDR3_DQ40 AH2
<28> SYSON# SYSON# 2 Q37 AF15 AG3 DDR_A_D41
G DDR3_CK#0 DDR3_DQ41 DDR_A_D42
AF17 AD2
2 DDR3_CK1 DDR3_DQ42 DDR_A_D43
S 2N7002_SOT23 AG17 AD3
1
DDR3_CK#1 DDR3_DQ43
R880
C1063
M_CLK_DDR2 AD17 AH4 DDR_A_D44
<10> M_CLK_DDR2 M_CLK_DDR#2 AC17 DDR3_CK2 DDR3_DQ44 DDR_A_D45
<10> M_CLK_DDR#2 DDR3_CK#2 DDR3_DQ45 AK3
@ M_CLK_DDR3 AC15 AE2 DDR_A_D46
<10> M_CLK_DDR3 M_CLK_DDR#3 AD15 DDR3_CK3 DDR3_DQ46 DDR_A_D47
@ AD4
<10> M_CLK_DDR#3 DDR3_CK#3 DDR3_DQ47
AD7 DDR_A_D48
<10> DRAMRST# DDR3_DQ48
@ R878 AD6 DDR_A_D49
DDR3_DQ49 DDR_A_D50
+1.5V 1 2 AK25 AA6
DDR3_DRAMRST# DDR3_DQ50 DDR_A_D51
AB5
10K_0402_5% DDR_VREF DDR3_DQ51 DDR_A_D52
AJ27 AE8
DDR3_VREF DDR3_DQ52 DDR_A_D53
AL28 AE5
R883 0_0402_5% DDR3_VREF_NCTF DDR3_DQ53 DDR_A_D54
AB9
DDR3_DQ54
<9> CLK_CPU_MPLL_C 1 2 CLK_CPU_MPLL AC19 AA8 DDR_A_D55
DDR3_REFP DDR3_DQ55
<9> CLK_CPU_MPLL#_C 1 2 CLK_CPU_MPLL# AB19 DDR3_REFN DDR3_DQ56 AB2 DDR_A_D56
R892 0_0402_5% AB4 DDR_A_D57
0_0402_5% DDR3_DQ57 DDR_A_D58
W4
R881 1 SMPWROK DDR3_DQ58 DDR_A_D59
<33> SM_PWROK 2 AA5 V3
DRAM_VR_PWRGD DDR3_DRAM_PWROK DDR3_DQ59 DDR_A_D60
W7 AC2
DDR3_VCCA_PWROK DDR3_DQ60 DDR_A_D61
AB3
DDR_ODTPU DDR3_DQ61 DDR_A_D62
AJ26 Y2
+1.5V DDR_CMDPU DDR3_ODTPU DDR3_DQ62 DDR_A_D63
AJ25 DDR3_CMDPU DDR3_DQ63 W1
DDR_DQPU AK27
DDR3_DQPU DDR_A_DQS0
AA30
DDR3_DQS0
1
AB11 AB24 DDR_A_DQS1
R500 RSVD_TP_AB11 DDR3_DQS1 DDR_A_DQS2
AB13 AF30
RSVD_TP_AB13 DDR3_DQS2 DDR_A_DQS3
AF19 AE22
B 1K_0402_1% RSVD_TP_AF19 DDR3_DQS3 DDR_A_DQS4 B
AG19 RSVD_TP_AG19 DDR3_DQS4 AG10
AF4 DDR_A_DQS5
2
DDR_VREF DDR3_DQS5 DDR_A_DQS6
DDR3 AB6
DDR3_DQS6 DDR_A_DQS7
DDR3_DQS7 Y3
1
1
R504 C953 DDR_A_DM0 Y28 AA31 DDR_A_DQS#0
DDR_A_DM1 DDR3_DM0 DDR3_DQS#0 DDR_A_DQS#1
AB26 AB25
1K_0402_1% 0.1U_0402_16V4Z DDR_A_DM2 DDR3_DM1 DDR3_DQS#1 DDR_A_DQS#2
AE30 AF29
2 DDR_A_DM3 DDR3_DM2 DDR3_DQS#2 DDR_A_DQS#3
AB21 AF22
2
AG11 DDR3_DM4 DDR3_DQS#4 AF10
DDR_A_DM5 AG2 AF3 DDR_A_DQS#5
AB8 AB7
AA3 DDR3_DM7 DDR3_DQS#7 AA2
QB0Z B2 1.6G
DDR_DQPU 2 OF 6 ?
R966 @ 0_0402_5%
<7> XDP_DBREST# 1 2
1
33.2_0402_1%
1
R967 0_0402_5% @
R893
1 2 C952 0.01U_0402_16V7K
<13> PCH_POK
+5VALW +1.5V 2 R553 DDR_CMDPU
2
DRAM_VR_PWRGD 1 2 PCH_POK_R 22.6_0402_1%

R968 12.1K_0402_1%
2
R503
R969 1 2 DDR_ODTPU
10K_0402_5%
270_0402_1%
1
A A
1 1 1 1
C1050 C1065
C203 C204
68P_0402_50V8J 0.1U_0402_16V4Z 68P_0402_50V8J 0.1U_0402_16V4Z
2 2 2 2

Cedarview(1/3)
2010.07.12 RF request Custom 0.3
QBU00
Date: Wednesday, November 02, 2011 Sheet 6 of 38
5 4 3 2 1
5 4 3 2 1
R894 1 2 1M_0402_5%
HDMI@ Y3 H_FERR#_CPU 1 2 H_FERR#

H_FERR# <11>
0_0402_5% R1006 27MHZ_18PF_X3S027000FI1H-X R895 0_0402_5%
GMCH_CRT_DATA 2 1 U1D N2600@ ?
GMCH_CRT_CLK 2 1 CPU_DREFCLK_C 1 3 CPU_DREFCLK#_C H_A20M#_C 1 2 H_A20M#
CEDARVIEW H_A20M# <11>
0_0402_5% R1007 2 4 R896 0_0402_5%
HDMI@ 1 1
REV = 1.10
C1076 C1077
U1C N2600@ ? 18P_0402_50V8J 18P_0402_50V8J
2 2 L26 B18 H_SMI#
<16> HDMICLK_C RSVD_L26 SMI# H_SMI# <11>
CEDARVIEW L27 C22 H_NMI
<16> HDMIDAT_C STRAP_L27 NMI/LINT10 H_NMI <11>
D14 K28 C18 H_A20M#_C
CRT_HSYNC GMCH_CRT_HSYNC <15> STRAP_K28 RSVD_C18
REV = 1.10 C14 K25 D22 H_STPCLK#
CRT_VSYNC GMCH_CRT_VSYNC <15> RSVD_K25 STPCLK# H_STPCLK# <11>
CRT@ R1002 0_0402_5% J28
D HDMICLK_C H_RSVD_K26 RSVD_J28 D
1 2 H25 K26
HDMIDAT_C DDI0_DDC_SCL RSVD_K26
1 2 J22 B12 GMCH_CRT_R K27
ICH
DDI0_DDC_SDA CRT_RED GMCH_CRT_R <15> RSVD_K27
CRT@ R1003 0_0402_5%
CRT_GREEN B11 GMCH_CRT_G GMCH_CRT_G <15> H27 RSVD_H27
C8 DDI0_AUXP CRT_BLUE C11 GMCH_CRT_B GMCH_CRT_B <15> K30 RSVD_K30
<16> HPD_C B8 DDI0_AUXN L29 RSVD_L29
D12 CRT_IRTN CRT@ R1008 2 1 0_0402_5% L30 C21 H_DPRSTP#
DDI
CRT_IRTN RSVD_L30 DPRSTP# H_DPRSTP# <13>
VGA
1 2 HPD_C H22 A13 DAC_IREF CRT@ R510 681_0402_1% K29 B21 H_DPSLP#
DDI0_HPD CRT_IREF RSVD_K29 DPLSLP# H_DPSLP# <13>
CRT@ R1005 0_0402_5% J31 RSVD_J31 CPUSLP# B22 H_CPUSLP# H_CPUSLP# <11>
HDMI_TXD2+ G2 E29 +3VS H30
<16> HDMI_TXD2+ DDI0_TXP0 CRT_DDC_DATA GMCH_CRT_DATA <15> RSVD_H30
HDMI_TXD2- G3 E27 A23 H_INIT#
<16> HDMI_TXD2- DDI0_TXN0 CRT_DDC_CLK GMCH_CRT_CLK <15> INIT# H_INIT# <11>
HDMI_TXD1+ F3 D20 H_INTR
<16> HDMI_TXD1+ DDI0_TXP1 INTR/LINT00 H_INTR <11>
HDMI_TXD1- F2 F17 CPU_SSCDREFCLK
<16> HDMI_TXD1- DDI0_TXN1 DPL_REFSSCCLKP CPU_SSCDREFCLK <9>
HDMI_TXD0+ D4 E17 CPU_SSCDREFCLK# K24 B20 H_THERMTRIP# H_THERMTRIP# <11>
<16> HDMI_TXD0+ DDI0_TXP2 DPL_REFSSCCLKN CPU_SSCDREFCLK# <9> HV_GPIO_RCOMP THERMTRIP#
HDMI_TXD0- @ R897
2.2K_0402_5%
2.2K_0402_5%
<16> HDMI_TXD0- C3 DDI0_TXN2 K23 MV_GPIO_RCOMP RSVD_L11 L11
HDMI_CLK0+ B7 B9 CPU_DREFCLK_C 1 2
<16> HDMI_CLK0+ DDI0_TXP3 DPL_REFCLKP CPU_DREFCLK <9>
R900
HDMI_CLK0- A7 A9 CPU_DREFCLK#_C1 20_0402_5% Close to CPU
<16> HDMI_CLK0- DDI0_TXN3 DPL_REFCLKN CPU_DREFCLK# <9>
1
@ R898 0_0402_5%
49.9_0402_1%
49.9_0402_1%
R899
R902
H15 C20 H_FERR#_CPU
RSVD_TP_H15 PBE#
R901
J15 R958 0_0402_5%
RSVD_TP_J15
R1009 0_0402_5% F28 LVDS_VTRL_CLK A19 H_PROCHOT# 1 2 VR_HOT VR_HOT <35>
1
LVDS_CTRL_CLK PROCHOT#
1 2 F25 E24 LVDS_VTRL_DATA D23 H_PWRGD H_PWRGD <13>
2
DDI1_DDC_SCL LVDS_CTRL_DATA PWRGOOD
1 2 G27 G30 PLTRST# PLTRST# <13,18,23>
DDI1_DDC_SDA RESET#
R1010 0_0402_5%
LVDS_DDC_CLK G24 LCD_EDID_CLK <17> DBR# E30 XDP_DBREST# XDP_DBREST# <6>
D10 DDI1_AUXP LVDS_DDC_DATA H24 LCD_EDID_DATA <17>
+1.5VS C10
BREF_1.5V DDI1_AUXN
E10 L_IBG R509 H29 XDP_PRDY# 2011.05.06 Add 0 ohm for XDP signal.
LVDS_IBG 2.37K_0402_1% PRDY# XDP_PREQ#
D26 DDI1_HPD LVDS_VBG F10 PREQ# G29
1U_0402_6.3V6K
1
1 HDMI@ E11 H2 R509 be placed U1.R22 J19 CLK_CPU_HPLCLK CLK_CPU_HPLCLK <9>

DDI1_TXP0 LVDS_VREFH HPLL_REFCLK_P
HDMI@ C1120
CRT@ R903 R975 F11 DDI1_TXN0 LVDS_VREFL H3 HPLL_REFCLK K19 CLK_CPU_HPLCLK# CLK_CPU_HPLCLK# <9>
0_0402_5% 0_0402_5% J11 DDI1_TXP1
CPU
H11 G10 LCD_TXOUT0+ <17> E19
LVDS
2 DDI1_TXN1 LVDS_TXP0 RSVD_E19
F13 H10 LCD_TXOUT0- <17> F19
2
DDI1_TXP2 LVDS_TXN0 RSVD_F19

C E13 DDI1_TXN2 LVDS_TXP1 F8 LCD_TXOUT1+ <17> C
J13 E8 LCD_TXOUT1- <17>
DDI1_TXP3 LVDS_TXN1
K13 DDI1_TXN3 LVDS_TXP2 H7 LCD_TXOUT2+ <17>
1
H8 LCD_TXOUT2- <17>
HDMI@ R974 LVDS_TXN2 XDP_TCK_R C25 SVID_ALERT#
J17 RSVD_TP_J17 LVDS_TXP3 G5 TCLK SVID_ALERT# B16 SVID_ALERT# <35>
7.5K_0402_1% H17 G6 XDP_TDI_R C24 D18 SVID_CLK
RSVD_TP_H17 LVDS_TXN3 TDI SVID_CLK SVID_CLK <35>
XDP_TDO_R B25 C16 SVID_DATA
TDO SVID_DATA SVID_DATA <35>
BREF_1.5V E15 H4 XDP_TMS_R D24
LCD_TXCLK+ <17>
2
CRT@ 1 BREFREXT BREF1P5V LVDS_CLKP XDP_TRST#_R B24 TMS

2 F15 BREFREXT LVDS_CLKN J4 LCD_TXCLK- <17> TRST#
R904 0_0402_5%
HDA_BITCLK_CPU H21 R5
IHDA
<13> HDA_BITCLK_CPU AZIL_BCLK RSVD_R5

HDA_SYNC_CPU F22 G22 R6
<13> HDA_SYNC_CPU AZIL_SYNC PANEL_BKLTCTL GMCH_INVT_PWM <17> RSVD_R6
HDMI@ E25 ENBKL W25
PANEL_BKLTEN ENBKL <25> RSVD_W25
33_0402_5%
1 R905 2 HDA_SDIN1_CPU E22 F29 ENBKL R517 W26 K21
<13> HDA_SDIN1 AZIL_SDI PANEL_VDDEN GMCH_ENVDD <17> RSVD_W26 RSVD_K21
HDA_SDOUT_CPU F21 100K_0402_5% N24 L22
<13> HDA_SDOUT_CPU AZIL_SDO RSVD_N24 RSVD_L22
To be placed <250 mils to U1 ball N25
RSVD_N25 RSVD_L24
L24
HDA_RST#_CPU E21
<13> HDA_RST#_CPU AZIL_RST# 3 OF 6
To be placed <500 mils to U1 ball
CRT@ RV155 150_0402_1%
QB0Z B2 1.6G
GMCH_CRT_R 1 2
CRT@ RV156 150_0402_1%
? GMCH_CRT_G 1 2
CRT@ RV157 150_0402_1%
4 OF 6
GMCH_CRT_B 1 2 QB0Z B2 1.6G
+1.05VS
XDP_TDI_R R495 1 2
B 51_0402_5% B
XDP_TMS_R R496 1 2
51_0402_5%
XDP_TDO_R R499 1 2
51_0402_5%
XDP_TRST#_R R502 1 2
51_0402_5%
XDP_TCK_R R505 1 2
51_0402_5%
+1.8VS
+3VS CPU THERMAL SENSOR
XDP_PREQ# R501 1 2
REMOTE Thermal sensor
0.1U_0402_16V4Z
1
51_0402_5%
XDP_PRDY# R906 1 2 C968
1
51_0402_5% U2 C
+1.05VS 2 H_THERMDA 2 Q8
B MMBT3904WH_SOT323-3
1 8 EC_SMB_CK2 E
EC_SMB_CK2 <25>
3
SVID_ALERT# R907 2 VDD SMCLK
1 2
75_0402_5% H_THERMDA 2 7 EC_SMB_DA2 C190@
DP SMDATA EC_SMB_DA2 <25>
SVID_DATA R908 2 1 C969 2200P_0402_50V7K
110_0402_1% 1 2 H_THERMDC 3 6 2 1 +3VS
H_PROCHOT# R511 2 2200P_0402_50V7K DN ALERT# R523 10K_0402_5% 1
1
100_0402_5% CPU_THERM# 4 5 H_THERMDC
+3VS THERM# GND
+3VS 1 2 place near the hottest spot area for

R524 10K_0402_5%
XDP_DBREST# R971 2 1 EMC1402-1-ACZL-TR_MSOP8
NB & top SODIMM.
1K_0402_1% Address:0100_1100 EMC1402-1
A Address:0100_1101 EMC1402-2 A
Layout Note:

Cedarview(2/3)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
+1.05VS
?
723mA ?
U1F N2600@
U1E N2600@
R525 R909
1 2 +VCCA_VCCD 1 2 +VCCDMPL CEDARVIEW A11 CEDARVIEW H19
+CPU_CORE VSS VSS
2.2U_0402_6.3V6M
0_0805_5% 0_0603_5% A16 H26
VSS VSS
4234mA1U_0402_6.3V6K 4.7U_0603_6.3V6K
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1U_0402_6.3V6K A21 VSS VSS H28
+VCCA_VCCD AA14 REV = 1.10 P18 4.7U_0603_6.3V6K A25 REV = 1.10 H6
VCCADDR_1 VCC_CPU_01 VSS VSS
C1078
1 1 1 1 AA16 P19 AA1 J10
VCCADDR_2 VCC_CPU_02 VSS VSS
C971
C970
C972
C973
W16 P21 1 1 1 1 1 1 1 AA10 J2
1 VCCADDR_3 VCC_CPU_03 C974 C976 C977 C988 C996 VSS VSS
W18 P28 C975 C987 AA13 J21
@ VCCADDR_4 VCC_CPU_04 @ @ @ VSS VSS
P29 AA19 J30
@ 2 @ 2 2 2 +1.05VS_EAST VCC_CPU_05 VSS VSS
N30 P30 AA21 K11
VCCRAMXXX_1 VCC_CPU_06 2 2 2 2 2 2 2 VSS VSS
N31 R22 AA23 K15
+VCCA_VCCD VCCRAMXXX_2 VCC_CPU_07 VSS VSS
V4 R23 AA26 K3
VCCRAMXXX_3 VCC_CPU_08 4.7U_0603_6.3V6K VSS VSS
R24 1U_0402_6.3V6K 1U_0402_6.3V6K AA27 K7
+VCCA_VDDR VCC_CPU_09 VSS VSS
W8 R25 AA29 K8
C973 1UF for VCCACKDDR_1 VCC_CPU_10 VSS VSS
W9 R26 AA7 K9
CPU pin V4 VCCACKDDR_2 VCC_CPU_11 VSS VSS
DDR
D R27 AA9 L1 D
VCC_CPU_12 VSS VSS
CPU
W11 VCCADLLDDR_1 VCC_CPU_13 T19 Please closed U1 ball AB15 VSS VSS L10
R526 W13 VCCADLLDDR_2 VCC_CPU_14 T21 AB17 VSS VSS L13
1 2 +1.05VS_EAST +1.05VS T29 AB23 L23
+VCCCK_DDR VCC_CPU_15 VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
0_0603_5% AJ6 T30 AB29 L25
VCCCKDDR_1 VCC_CPU_16 VSS VSS
1 1 AK6 T31 AC1 L31
VCCCKDDR_2 VCC_CPU_17 +CPU_CORE VSS VSS
C1079
C1080
VCC_CPU_18 U22 AC10 VSS VSS L7

+VCC_SM AH14 U23 2 x 330uF(9mohm/2) AC11 M29
V_SM_1 VCC_CPU_19 VSS VSS
GND
AH19 U24 AC13 M4
330U_D2_2.5VY_R9M
@ 2 2 V_SM_2 VCC_CPU_20 VSS VSS
1 AK23 V_SM_3 VCC_CPU_21 U25 1 1 AC22 VSS VSS N10
AK5 U26 AC28 N14
+ V_SM_4 VCC_CPU_22 + + VSS VSS
C1081
C1079 1UF for C1080 1UF for AL11 U27 C984 C985 AC4 N19
CPU pin N30,N31 CPU pin L19 V_SM_5 VCC_CPU_23 VSS VSS
AL16 V18 AD19 N21
V_SM_6 VCC_CPU_24 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M VSS VSS
AL21 V19 AD21 N22
2 V_SM_7 VCC_CPU_25 +CPU_CORE 2 2 VSS VSS
R956 AG31 V21 AD24 N23
+VCCA_VDDR V_SM_8 VCC_CPU_26 VSS VSS
1 2 VCC_CPU_27 V28 AD26 VSS VSS N26
+VCCADP_1.05
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0_0603_5% B5 VCCADP_1 VCC_CPU_28 V29 AD5 VSS VSS N27

1 1 1 C6 VCCADP_2 VCC_CPU_29 V30 AD8 VSS VSS N28
C1082
C1083
C1084
D6 VCCADP_3 AE1 VSS VSS N4

+GFX_CORE
Close Chipset pin
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
AE10 VSS VSS N7
+VCCADP0_SFR K17 1938mA 1 1 1 1 AE11 P14
2 2 2 VCCADP0_SFR VSS VSS
POWER
C989
C990
C991
C1085
@ +VCCADP1_SFR L18 N11 AE15 P16
VCCADP1_SFR VCC_GFX_01 VSS VSS
N13 AE17 P4
+1.05VS_EAST VCC_GFX_02 VSS VSS
L19 P11 AE19 T14
+VCCAGPIO1.5V VCCAGPIO_LV VCC_GFX_03 2 2 2 2 VSS VSS
R910 L16 P13 AE3 T18
+VCCADP_1.05 +VCCAGPIO1.8V VCCAGPIO_REF VCC_GFX_04 VSS VSS
1 2 N18 R10 AE31 T3
VCCAGPIO_DIO VCC_GFX_05 VSS VSS
1U_0402_6.3V6K
0_0603_5% R9 AF11 U5
+VCCAGPIO3.3V VCC_GFX_06 VSS VSS
1 D30 T11 AF13 U6
VCCAGPIO_1 VCC_GFX_07 VSS VSS
C1086
D31 VCCAGPIO_2 VCC_GFX_08 T13 AF21 VSS VSS U9

U10 AF24 V2
+VCC_CRT_DAC VCC_GFX_09 VSS VSS
B13 VCCADAC VCC_GFX_10 V11 AF28 VSS VSS W10
2 V13 AF7 W14
+VCCALVDS VCC_GFX_11 VSS VSS
H5 VCCALVDS AG22 VSS VSS W19
+VCCDLVDS J1 B4 +VCC_DMI AG5 W2
DMI
+VCC_DMI VCCDLVDS VCCADMI_1 +CPU_CORE VSS VSS
1 R531 2 C5 AH26 W21
VCCADMI_2 VSS VSS
1U_0402_6.3V6K
A4 AH28 W22
0_0603_5% +VCCDIO VCCADMI_3 +VCCADMI_1.5VS VSS VSS
1 L21 K4 AH6 W23
VCCDIO VCCADMI_PLLSFR VSS VSS
1
C994
C AH9 W24 C
+VCCAZILAON +VCCA_VCCD R532 VSS VSS
2011.04.25 Add for RGB I/F B29
VCCAZILAON_1 VCCFHV_1
V16 AJ2
VSS VSS
W27
A30 T16 AJ3 W30
CRT@ 2 VCCAZILAON_2 VCCFHV_2 100_0402_5% VSS VSS
AK13 VSS VSS W5
+VCCSFRMPL AA18 V14 AK19 W6
R1004
2
+VCCDIO +VCCDMPL VCCSFRMPL VCCFHV_3 VSS VSS
PLL
1 2 AA11 VCCDMPL AK28 VSS VSS Y4
M28 VCCSENSE
1U_0402_6.3V6K
0_0603_5% VCC_CPUSENSE VCCSENSE <35> AK9 VSS

1 +VCCPLLCPU0 B27 M30 VSSSENSE AL13
VCCPLLCPU0 VSS_CPUSENSE VSSSENSE <35> VSS
CRT@
C166
HDMI@ +VCCPLLCPU1 C29 AL19 A27

C166 VCCPLLCPU1_1 VCC_GFXSENSE VSS VSS
B30 U8 AL23 A29
VCCPLLCPU1_2 VCC_GFXSENSE VSS VSS
1
0_0402_5% U7 VSS_GFXSENSE +1.8VS AL25 A3
2 +VCCAHPLL VSS_GFXSENSE R911 R533 VSS VSS
B26 VCCAHPLL AL7 VSS VSS AH1
N16 +VCCATHRM 1 2 B10 AJ1
VCCTHRM_1 100_0402_5% VSS VSS
K2 B14 AJ31
+1.5V VCCTHRM_2 VSS VSS
10U_0805_10V4Z
0_0603_5%
1U_0402_6.3V6K
B19 AK1
2
VSS VSS
1 1 B23 AK2
VSS VSS
C1090
C1089
1 2 +VCCCK_DDR C12 AK30
VSS VSS
C26 AK31
R530 @ VSS VSS
22U_0805_6.3V6M
1U_0402_6.3V6K
C30 AL2
0_0603_5% 2 +GFX_CORE 2 VSS VSS
1 1 C7 AL29
VSS VSS
C992
C993
D19 AL3
VSS VSS
D28 AL30
VSS VSS
1
D8 AL5
2 2 +3VS_PRIME R912 VSS VSS
D9 VSS VSS B2
E2 VSS VSS B3
Please closed U1 ball R913
100_0402_5% E5 VSS VSS B31
2 1 +VCCAGPIO3.3V E7 C1
2
VSS VSS
0_0603_5% F24 C2
VSS VSS
R914 F4 C31
+1.5V +VCCAZILAON VCC_GFXSENSE VSS VSS
R527 1 2 VCC_GFXSENSE <35> G1 E1
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M HDMI@ VSS_GFXSENSE VSS VSS
0_0603_5% VSS_GFXSENSE <35> G11
+VCC_SM VSS
1 2 2 2 G13
VSS
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CRT@ G15 L14

VSS VSS_CDVDET
1
C1092
C1093 HDMI@
0_1206_5% 2 2 2 2 C1093 G17 D13

0_0402_5% R915 VSS VSSA_CRTDAC
G19
C979 C980 C981 C982 1 1 VSS
G21
100_0402_5% VSS
5 OF 6 G31 VSS
1 1 1 1 G8
B QB0Z B2 1.6G B
2
VSS
H13
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M VSS
+1.8VS ?
+1.05VS 6 OF 6
QB0Z B2 1.6G
?
R916 R917 +GFX_CORE
1 2 +VCCDLVDS 1 2 +VCCPLLCPU0
+1.5VS
0_0603_5% 0_0603_5%
1U_0402_6.3V6K
10U_0805_10V4Z
1 1 2 +VCCALVDS +VCCA_VCCD 1 2
C983 R918 0_0402_5% C159 22P_0402_50V8J
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
R919 1 1
1 2 +VCCADMI_1.5VS
4.7U_0603_6.3V6K
RF@
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C1094
C1095
1U_0402_6.3V6K
22U_0805_6.3V6M
1U_0402_6.3V6K
0_0603_5% 2 1 1 1
C1006
C1007
C1008
C1009
1 C986 1 1 1 1 1 +VCCCK_DDR 1 2
2 2 + +
C1097
C1005
C1004
C1096
C150 22P_0402_50V8J
0.1uH use 2 R920 +GFX_CORE RF@
1 2 +VCCPLLCPU1
2 0 ohm replace 2 2 2 2 2 2 2
10U_0805_10V4Z
1U_0402_6.3V6K
0_0603_5%
R921 1 1 1 2
+VCCAGPIO1.8V C153 22P_0402_50V8J
1U_0402_6.3V6K
R922 1 2
+CPU_CORE
C1098
C1099
1 2 +VCCAGPIO1.5V 1
0_0603_5%
C1100
0_0603_5% 2 2
Close Chipset pin
2 1 2
C1101 C156 22P_0402_50V8J
@ CRT@ 2
R923 2011.06.14 Stuff C1007,C1008,C1009 for EDS issue
0.1U_0402_10V6K 1 R535 2 +VCC_CRT_DAC 1 2 +VCCAHPLL
1
10U_0603_6.3V
0_0603_5% 0_0603_5%
1U_0402_6.3V6K
10U_0805_10V4Z
1
CRT@
C1125
HDMI@
C1125
1 1 2010.07.12 RF request
C1102
C1103
0_0603_5%
2
2011.04.25 Add for RGB I/F 2 2
+1.5VS +1.5VS +1.5VS
A A
2
R924 R925 R926

0_0603_5% 0_0603_5% 0_0603_5%
1
@ @ @
R927 R928 R929
+1.05VS 1 2 +VCCADP0_SFR +1.05VS 1 2 +VCCADP1_SFR +1.05VS 1 2 +VCCSFRMPL
0_0603_5% 0_0603_5%
4.7U_0603_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
10U_0805_10V4Z
1U_0402_6.3V6K
0_0603_5% 1 1 1 1 1 1
C1104
C1126
C1106
C1127
C1109

C1108
@ 2010/06/27 2011/6/27 Title

@ 2 2 @ 2 2 2 2 Issued Date Deciphered Date
Cedarview(3/3)
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
+3VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB R81 250 mA
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1 2
1 1 1 1
0_0603_5% C126 C127 C128 C129 C133
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
+1.05VM_CK505 +3VS
R82
0 1 0 200 100 33.3 14.318 96.0 48.0 80 mA
+1.05VS 1 2
FBMH1608HM601-T_0603 1 1 1 1 1 1 R83 R84
0 1 1 166 100 33.3 14.318 96.0 48.0 C134 C135 C136 C137 C138 C139 C141
D 2.2K_0402_5% 2.2K_0402_5% D
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J
2 2 2 2 2 2 Q1A
1 0 0 333 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6
<13> PCH_SMBDATA 6 1 CLK_SMBDATA
1 0 1 100 100 33.3 14.318 96.0 48.0 +1.5VM_CK505
R477
2
1 1 0 400 100 33.3 14.318 96.0 48.0 +1.5VS 1 2 +3VS
10U_0805_10V4Z
SA00003H730 (Realtek :RTM890N-397-VC-GRT)
5
0_0603_5% 1
C942
1 1 1 LOW@
Reserved CLK_SMBCLK
Low power CLK Gen. <13> PCH_SMBCLK 3 4
2 Q1B 2N7002DW-T/R7_SOT363-6
Normal Power Low Power

+3VM_CK505 +3VM_CK505
2011.04.29 Reserve R305,C392 for RF
LOW@U4
LOW@ U4
R477 @ Stuff NORMAL@ R478 9 CLK_SMBDATA
+3VM_1.5VM_R SDA CLK_SMBDATA <10,18> @ @
R478 Stuff @ +1.5VM_CK505
1 2 55
VDD_SRC
10 CLK_SMBCLK
R305 C392
SCL CLK_SMBCLK <10,18>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0_0603_5% CLK_SMBCLK 1
R479 Stuff @ LOW@R483
LOW@R483
6
VDD_REF
2 1 2
1 1 1
C943
C944
C945
CLK_CPU_HPLCLK 10_0402_5% 22P_0402_50V8J
R480 @ Stuff 1
0_0603_5%
2 12 VDD_PCI CPU_0 71 CLK_CPU_HPLCLK <7>
CLK_CPU_HPLCLK#
R483 @ Stuff NORMAL@ R479 2 2 2
72
VDD_CPU CPU_0#
70 CLK_CPU_HPLCLK# <7>
SRC PORT LIST
+1.05VM_CK505 1 2 19 68 CLK_CPU_MPLL_C
VDD_48 CPU_1 CLK_CPU_MPLL_C <6>
0_0603_5% 27 VDD_PLL3 CPU_1# 67 CLK_CPU_MPLL#_C
CLK_CPU_MPLL#_C <6> PORT DEVICE
LOW@R480
LOW@R480 +1.05VM_CK505
+1.05VS
C +1.5VM_CK505 1 2 +1.05VM_1.5VM_R 66
VDD_CPU_IO SRC_0/DOT_96
24 CPU_DREFCLK
CPU_DREFCLK <7> SRC0 CPU_DREFCLK C
47P_0402_50V8J
0.1U_0402_16V4Z
0_0603_5% CPU_DREFCLK#
1 31 VDD_PLL3_IO SRC_0#/DOT_96# 25 CPU_DREFCLK# <7> SRC2
1
C946
C947
@
R481
470_0402_5%
62 VDD_SRC_IO
28 CPU_SSCDREFCLK
CPU_SSCDREFCLK <7>
SRC3 CPU_EXP
R482 2 LCDCLK/27M
2.2K_0402_5%
52
VDD_SRC_IO
29 CPU_SSCDREFCLK#
CPU_SSCDREFCLK# <7>
SRC4 PCIE_SATA
2
FSA 2 LCDCLK#/27M_SS
1 23
VDD_IO SRC6 PCIE_WLAN
38
VDD_SRC_IO SRC_2
32 2011.06.29 Swap CLK Gen output for SRC7
10_0402_5% 1 2 R92 CPU_SCDREFFCLK and CPU_DREFCLK
SRC_2# 33
SRC8
1
<24> CLK_48M_CR
@ R484 10_0402_5% 1 2 R91 FSA
<12> CLK_PCH_48M
20
USB_0/FS_A
35 CLK_CPU_EXP
CLK_CPU_EXP <6>
SRC9 PCIE_LAN
1K_0402_5% FSB SRC_3
1
C143
2
22P_0402_50V8J
2
FS_B/TEST_MODE
36 CLK_CPU_EXP#
CLK_CPU_EXP# <6>
SRC10 PCIE_PCH
2
33_0402_5% 1 SRC_3#
2 R93 FSC 2011.03.30 CLK_CPU_EXP change to SRC3
<13> CLK_PCH_14M
7
REF_0/FS_C/TEST_ SRC11 PCIE_WWAN
1 2 8 39 CLK_PCIE_SATA
REF_1 SRC_4 CLK_PCIE_SATA <11> +3VS
+3VS R65 1 2 H_STP_CPU#_R C868 22P_0402_50V8J
10K_0402_5% 40 CLK_PCIE_SATA#
SRC_4# CLK_PCIE_SATA# <11>
VGATE 1
+1.05VS <13,25,28,34,35> VGATE CKPWRGD/PD#
11 57 CLK_PCIE_WLAN WLAN_CLKREQ# R99 2 1 10K_0402_5%
NC SRC_6 CLK_PCIE_WLAN <18>
WWAN_CLKREQ# R100 2 1 10K_0402_5%
1
56 CLK_PCIE_WLAN# LAN_CLKREQ# R101 2 1 10K_0402_5%

SRC_6# CLK_PCIE_WLAN# <18>
R485@
470_0402_5% @R432
@ R432 1 2 0_0402_5% H_STP_CPU#_R 53
R486 <13> H_STP_CPU# CPU_STOP#
61
1K_0402_5% @R427
@ R427 1 0_0402_5% H_STP_PCI#_R SRC_7
2 54
2
FSB <13> H_STP_PCI# PCI_STOP#

2 1 60
SRC_7#
CLK_XTAL_IN 5 XTAL_IN CPU_ITP 0_0402_5% R980@
B 64 T77 B
CLK_XTAL_OUT SRC_8/CPU_ITP
4
XTAL_OUT
1
+3VS R608 1 2 H_STP_PCI#_R 1 2 63 CPU_ITP# 0_0402_5% R983@

SRC_8#/CPU_ITP# T78
R488 10K_0402_5% C144 22P_0402_50V8J
0_0402_5% 33_0402_5% 1 2 R103 CLK_PCI_DDR_R CLK_PCIE_LAN

<18> CLK_PCI_DDR 13
PCI_1 SRC_9
44 CLK_PCIE_LAN <23>
REQ PORT LIST
2
PCI2_TME 14 45 CLK_PCIE_LAN#
PCI_2 SRC_9# CLK_PCIE_LAN# <23>
1 2
C145 22P_0402_50V8J 15 PCI_3
50 CLK_PCIE_PCH
CLK_PCIE_PCH <12>
PORT DEVICE
+1.05VS 33_0402_5% 1 SRC_10
<25> CLK_PCI_LPC 2 R107 PCI4_SEL 16
PCI_4/SEL_LCDCL
33_0402_5% 1 2 R108 ITP_EN 17
SRC_10#
51 CLK_PCIE_PCH#
CLK_PCIE_PCH# <12> REQ_3#
<11> CLK_PCI_PCH PCIF_5/ITP_EN
1
R489 1 2 48 CLK_PCIE_WWAN
CLK_PCIE_WWAN <18>
REQ_4#
470_0402_5% C146 22P_0402_50V8J SRC_11
R490 18 47 CLK_PCIE_WWAN#
CLK_PCIE_WWAN# <18>
REQ_6# PEIC_WLAN
10K_0402_5% VSS_PCI SRC_11#
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# REQ_7#
2
FSC 2 1 3
VSS_REF
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# REQ_9# PCIE_LAN
22 37
Pin28/29 : LCDCLK / LCDCLK# VSS_48 CLKREQ_3#
1 = Pin24/25 : SRC_0 / SRC_0# 26 41
REQ_10#
VSS_IO CLKREQ_4#
1
@ R491 Pin28/29 : 27M/27M_SS 69 58 WLAN_CLKREQ#

WLAN_CLKREQ# <18>
REQ_11# PEIC_WWAN
VSS_CPU CLKREQ_6#
For PCI2_TME:0=Overclocking of CPU and SRC allowed REQ_A#
0_0402_5% 30 65
(ICS only) 1=Overclocking of CPU and SRC NOT allowed VSS_PLL3 CLKREQ_7#
2
34 43 LAN_CLKREQ#
VSS_SRC CLKREQ_9# LAN_CLKREQ# <23>
+3VS +3VS +3VS 59 49
VSS_SRC SLKREQ_10#
42 46 WWAN_CLKREQ#
VSS_SRC CLKREQ_11# WWAN_CLKREQ# <18>
2
@
A A
R119 R118 R112 73 21
CLK_XTAL_IN VSS USB_1/CLKREQ_A#
C147 22P_0402_50V8J 10K_0402_5% 10K_0402_5% 10K_0402_5%
1
RTM890N-397-VC-GRT QFN
1
Y1
14.31818MHZ 20PF 7A14300003 ITP_EN PCI4_SEL PCI2_TME
2
CLK_XTAL_OUT
2
C148 22P_0402_50V8J @
R113@ R114 R115 Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
10K_0402_5% 10K_0402_5% 10K_0402_5%
Clock Generator CK505
1
0.3
QBU00
5 4 3 2 1
5 4 3 2 1
+DIMM_VREF +1.5V +1.5V

3A@1.5V
<6> DDR_A_DQS#[0..7]
<6> DDR_A_D[0..63] JDDR1

+1.5V +DIMM_VREF 1 2
VREF_DQ VSS1 DDR_A_D2
<6> DDR_A_DM[0..7] 3 4
DDR_A_D4 VSS2 DQ4 DDR_A_D7
5 6
DQ0 DQ5
<6> DDR_A_DQS[0..7] Layout Note: DDR_A_D5 7
DQ1 VSS3
8
0.1U_0402_16V4Z
9 10 DDR_A_DQS#0
Place near JDDR1 1 DDR_A_DM0 11
VSS4 DQS#0
12 DDR_A_DQS0
<6> DDR_A_MA[0..15]
1
DM0 DQS0
C117
1K_0402_1%
13 14
DDR_A_D1 VSS5 VSS6 DDR_A_D3
15 16
DQ2 DQ6
R74
DDR_A_D0 17 18 DDR_A_D6
2 DQ3 DQ7
D R879 19 20 D
21 22
2
DDR_A_D9 DQ8 DQ12 DDR_A_D13
1 2 +DIMM_VREF 23 24
0_0402_5% DQ9 DQ13
25 26
VSS9 VSS10
1
1K_0402_1%
DDR_A_DQS#1 27 28 DDR_A_DM1
+1.5V DDR_A_DQS1 DQS#1 DM1 DRAMRST#
29 30 DRAMRST# <6>
DQS1 RESET#
R75
31 32
33 34
35 36
2
DQ11 DQ15
37 38
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
22U_0805_6.3V6M
22U_0805_6.3V6M
2 2 2 2 39 40
DQ16 DQ20
C101
C102
DQ17 DQ21
C99
C100
2011.06.14 Add C119 for ESD issue 43
VSS15 VSS16
44
1 1 1 1 DDR_A_DQS2 DQS#2 DM2
47 48
+DIMM_VREF DQS2 VSS17 DDR_A_D19
49 50
+1.5V DDR_A_D18 VSS18 DQ22 DDR_A_D23
0.1U_0402_16V4Z
20mils DDR_A_D22
51
DQ18 DQ23
52
53 54
DQ19 VSS19 DDR_A_D28
55 56
1 1 1 57 58
C115 C104 C105 DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_A_DQS#3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 61 62
330U_D2_2.5VY_R9M
2.2U_0603_6.3V6K DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3

1 1 1 1 1 1 1 63 64
+ 2 2 2 DM3 DQS3
65 66
VSS23 VSS24
C106
C119
C107
C108
C109
C110
CZ03
CZ04
69 70
2 2 2 2 2 2 2 @ 2 0.1U_0402_16V4Z DQ27 DQ31
71 72
VSS25 VSS26
+1.5V
<6> DDR_CKE2 DDR_CKE2 73 74 DDR_CKE3
CKE0 CKE1 DDR_CKE3 <6>
75 76
VDD1 VDD2 DDR_A_MA15
77 78
DDR_A_BS2 NC1 A15 DDR_A_MA14
<6> DDR_A_BS2 79 80
C BA2 A14 C
0.1U_0402_16V4Z
81 82
1
VDD3 VDD4
1K_0402_1%
1 DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
C118
R77
DDR_A_MA9 85 86 DDR_A_MA7
+V_DDR_CPU_REF A9 A7
87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 90
2 A8 A6
Layout Note: DDR_A_MA5 91 92 DDR_A_MA4
2
A5 A4
93 94
Place one cap close to every 2 pullup DDR_A_MA3 95
VDD7 VDD8
96 DDR_A_MA2
1
A3 A2
1K_0402_1%
resistors terminated to +0.75VS DDR_A_MA1 97
A1 A0
98 DDR_A_MA0
99 100
VDD9 VDD10
R76
<6> M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 <6>
<6> M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 <6>
105 106
2
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <6>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<6> DDR_A_BS0 109 110 DDR_A_RAS# <6>
BA0 RAS#
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS2#
<6> DDR_A_WE# 113 114 DDR_CS2# <6>
+0.75VS DDR_A_CAS# WE# S0# M_ODT2
<6> DDR_A_CAS# 115 116 M_ODT2 <6>
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT3 +V_DDR_CPU_REF
119 120 M_ODT3 <6>+VREF_CA
DDR_CS3# A13 ODT1
<6> DDR_CS3# 121 122
S1# NC2
123 124
VDD17 VDD18 +VREF_CA
125 126 1 2
NCTEST VREF_CA R877 0_0402_5%
127 128
2.2U_0402_6.3V6M
129 130
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DQ32 DQ36 1 1 1
DDR_A_D32 DDR_A_D33
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1 131 132
DQ33 DQ37
C213
C215
C214
133 134
VSS29 VSS30
C111
C112
C113
C114
C116

DDR_A_DQS4 DQS#4 DM4 2 @ 2 2
137 138
2 2 2 2 2 DQS4 VSS31 DDR_A_D38
139 140
141 142
DDR_A_D35 DQ34 DQ39
143 144
145 146
B DDR_A_D41 VSS34 DQ44 DDR_A_D45 B
147 148
DDR_A_D44 DQ40 DQ45
149 150
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
2011.06.14 Add C116 for ESD issue 153
DM5 DQS5
154
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 166
DQ49 DQ53
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 170
DDR_A_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_A_D50
173 174
175 176
DDR_A_D55 DQ50 DQ55
177 178
179 180
DDR_A_D60 VSS46 DQ60 DDR_A_D61 +3VS
181 182
DDR_A_D57 DQ56 DQ61
183 184
185 186
1
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7 R513
189 190
VSS49 VSS50
DVT# SA0 change to DDR_A_D58 191
DQ58 DQ62
192 DDR_A_D59 10K_0402_5%
DDR_A_D62 193 194 DDR_A_D63
pull high +3VS 1 R207 2 195
DQ59 DQ63
196
+3VS
2
10K_0402_5% VSS51 VSS52 PM_EXTTS#0
197 198
SA0 EVENT# CLK_SMBDATA
+3VS 199 200 CLK_SMBDATA <9,18>
VDDSPD SDA CLK_SMBCLK
0.1U_0402_16V4Z
0.1U_0402_16V4Z
201 202 CLK_SMBCLK <9,18>

SA1 SCL
1 1 203 204 +0.75VS
1 VTT1 VTT2
10K_0402_5%
C219
C220
R208 205 206 0.65A@0.75V

G1 G2
2 2 FOX_AS0A621-U4SG-7H
A +0.75VS A
2

DDRII-SODIMMA
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
+3VS
U15A TGP
R539 1 2 8.2K_0402_5% RSVD01
A5 PAR AD0 B22
R540 1 2 8.2K_0402_5% RSVD02 PCI_DEVSEL# B15 D18
CLK_PCI_PCH DEVSEL# AD1
<9> CLK_PCI_PCH J12 PCICLK AD2 C17
PCI_RST# A23 C18
<25> PCI_RST# PCIRST# AD3
PCI_IRDY# B7 B17
+3VS IRDY# AD4
C22 PME# AD5 C19
1
RP7 PCI_SERR# PCI_RST#
100K_0402_5%
B11 SERR# AD6 B18
D 1 8 PCI_PIRQB# R541 PCI_STOP# F14 B19 D
PCI_PIRQF# PCI_PLOCK# STOP# AD7
2 7 A8 PLOCK# AD8 D16
3 6 PCI_PIRQC# PCI_TRDY# A10 D15 CLK_PCI_PCH
PCI_PIRQA# PCI_PERR# TRDY# AD9
4 5 D10 A13
0.1U_0402_16V4Z
2
PERR# AD10
1
PCI_FRAME# A16 E14 1
8.2K_0804_8P4R_5% FRAME# AD11 R542 @
AD12 H14
For EC request. @ 10_0402_5%
C1015
AD13 L14
+3VS J14
RP8 AD14 2
A18 E10 1
2
PCI_PIRQE# GNT1# AD15 @
1 8 E16 GNT2# AD16 C11
2 7 PCI_PLOCK# E12 C1016
PCI_PIRQG# REQ1# AD17 8.2P_0402_50V8D
3
4
6
5 PCI_IRDY# REQ2#
G16
A20
REQ1# PCI AD18 B9
B13
2
REQ2# AD19
2011.04.20 Stuff R544 for SPI mode AD20 L12
8.2K_0804_8P4R_5% B8
AD21
+3VS
G14 GPIO48/STRAP1# AD22 A3 For EMI, close to TigerPoint
A2 GPIO17/STRAP2# AD23 B5
RP16 GPIO22 C15 A6
PCI_SERR# GPIO1 GPIO22 AD24
1 8 C9 GPIO1 AD25 G12
2 7 PCI_PERR# H12
PCI_TRDY# @ R543 R544 AD26
3 6 AD27 C8
4 5 GPIO1 10K_0402_5% 10K_0402_5% D9
PCI_PIRQA# AD28
B2 PIRQA# AD29 C7
8.2K_0804_8P4R_5% PCI_PIRQB# D7 C1
+3VS PCI_PIRQC# PIRQB# AD30
B3 PIRQC# AD31 B1
RP10 PCI_PIRQD# H10
GPIO22 PCI_PIRQE# PIRQD# +1.05VS
1 8 E8 PIRQE#/GPIO2
2 7 PCI_DEVSEL# PCI_PIRQF# D6
PCI_PIRQD# PCI_PIRQG# PIRQF#/GPIO3
3 6 H8 PIRQG#/GPIO4 C/BE0# H16
C 4 5 PCI_PIRQH# PCI_PIRQH# F8 M15 C
PIRQH#/GPIO5 C/BE1#
1
C/BE2# C13
8.2K_0804_8P4R_5% D11 L16 R546
RSVD01 STRAP0# C/BE3# 60.4_0402_1%
K9 RSVD01
RSVD02 M13 RSVD02
+3VS 2
2
1
RP11 R545 H_FERR#
1 8 REQ2# @ 1K_0402_5% TIGERPOINT_ES1_BGA360 R546 closed TigerPoint within 1"
2 7 REQ1#
PCI_STOP# U15C TGP
3 6
1
4 5 PCI_FRAME#
R12 RSVD03 SATA0RXN AE6 SATA_IRX_C_DTX_N0 <20>
8.2K_0804_8P4R_5% AE20 AD6 +1.05VS
RSVD04 SATA0RXP SATA_IRX_C_DTX_P0 <20>
AD17 RSVD05 SATA0TXN AC7 SATA_ITX_DRX_N0 <20>
AC15 RSVD06 SATA0TXP AD7 SATA_ITX_DRX_P0 <20>
Signals have weak internal pull-ups AD18 RSVD07 SATA1RXN AE8 T63 PAD
Y12 RSVD08 SATA1RXP AD8 T64 PAD
AA10 AD9 T65 PAD R930
RSVD09 SATA1TXN H_IGNNE#
GPIO17 GPIO48 AA12
Y10
RSVD10 SATA1TXP AC9 T66 PAD 1 2
1K_0402_5%
RSVD11
AD15 RSVD12
SATA
W10 RSVD13
SPI 0 1 V12
AE21
RSVD14
RSVD15
AE18 RSVD16
AD19 RSVD17
PCI 1 0 U12 RSVD18
AD4 Please closed Tiger point
SATA_CLKN CLK_PCIE_SATA# <9>
AC17 AC4 CLK_PCIE_SATA <9>
B
AB13
RSVD19 SATA_CLKP PIN within 500 mils +3VS B
RSVD20
LPC 1 1 AC13 RSVD21 SATARBIAS# AD11 SATARBIAS R547 24.9_0402_1%
AB15 RSVD22 SATARBIAS AC11 R548
Y14 RSVD23 SATALED# AD25 SATALED# <27>
SATALED#
AB16 RSVD24 10K_0402_5%
AE24 RSVD25
AE23 R549
RSVD26 GATEA20
10K_0402_5%
AA14 U16 GATEA20 GATEA20 <25> R550
RSVD27 A20GATE H_A20M# SERIRQ
V14 RSVD28 A20M# Y20 H_A20M# <7> 1 2
Y21 H_CPUSLP# H_CPUSLP# <7>
CPUSLP# H_IGNNE# 8.2K_0402_5%
IGNNE# Y18
AD16 AD21 +1.05VS
RSVD29 INIT3_3V# H_INIT#
AB11 RSVD30 INIT# AC25 H_INIT# <7>
+3VS AB10 AB24 H_INTR
RSVD31 INTR H_INTR <7>
HOST
1
R551 Y22 H_FERR#
FERR# H_FERR# <7>
1 2 AD23 T17 H_NMI R552
GPIO36 NMI H_NMI <7>
AC21 EC_KBRST# EC_KBRST# <25> 60.4_0402_1%
8.2K_0402_5% RCIN# SERIRQ
SERIRQ AA16 SERIRQ <25>
AA21 H_SMI#
H_SMI# <7>
2
SMI# H_STPCLK#
STPCLK# V18 H_STPCLK# <7>
THRMTRIP# AA20 H_THERMTRIP# <7>
3
A A
TIGERPOINT_ES1_BGA360

Tigerpoint(1/4)
0.3
QBU00
Date: W ednesday, November 02, 2011 Sheet 11 of 38
5 4 3 2 1
5 4 3 2 1
D D
USB PORT LIST
PORT #EVT DEVICE

TGP
U15B
USB0 USB1(Left)
<6> DMI_TXN0 R23
R24
DMI0RXN USBP0N
H7
H6
USB20_N0
USB20_P0 USB20_N0 <19> USB1(Right) USB1 USB2(Left)
<6> DMI_TXP0 DMI0RXP USBP0P USB20_P0 <19>
<6> DMI_RXN0 P21
P20
DMI0TXN USBP1N
H3
H2
USB20_N1
USB20_P1 USB20_N1 <19> USB2(Right) USB2 NC
<6> DMI_RXP0 DMI0TXP USBP1P USB20_P1 <19>
<6> DMI_TXN1 T21
T20
DMI1RXN USBP2N
J2
J3
T49 PAD USB3 Card-reader
<6> DMI_TXP1 DMI1RXP USBP2P T50 PAD
<6> DMI_RXN1 T24
T25
DMI1TXN USBP3N
K6
K5
USB20_N3 <24> Card-reader USB4 USB3(Right)
<6> DMI_RXP1 DMI1TXP USBP3P USB20_P3 <24>
DMI
T19
DMI2RXN USBP4N
K1 USB20_N4
USB20_P4
USB20_N4 <19> USB5 WWAN
T18 DMI2RXP USBP4P K2
USB20_N5_L USB20_P4 <19> USB3(Left) USB6
U23
DMI2TXN USBP5N
L2
USB20_P5_L WLAN + BT
U24
V21
DMI2TXP USBP5P
L3
M6 USB20_N6 WWAN USB7
DMI3RXN USBP6N USB20_P6 USB20_N6 <18> CMOS
V20
V24
DMI3RXP USBP6P M5
N1 USB20_N7 USB20_P6 <18> WLAN + BT (Combo) #6/27 EVT
DMI3TXN USBP7N USB20_P7 USB20_N7 <17>
V23
DMI3TXP USBP7P
N2 USB20_P7 <17> CMOS
D4 USB_OC#0_1_PCH
OC0# USB_OC#0_1_PCH <19>
PCIE_PTX_C_IRX_N1 USB_OC#0_1_PCH
USB
<23> PCIE_PTX_C_IRX_N1 K21 PERN1 OC1# C5
PCIE_PTX_C_IRX_P1 K22 D3 USB_OC#2
<23> PCIE_PTX_C_IRX_P1 PCIE_ITX_PRX_N1 PERP1 OC2# USB_OC#3
LAN <23> PCIE_ITX_C_PRX_N1 C1019 2 1 0.1U_0402_10V6K J23 D2
C1020 2 PCIE_ITX_PRX_P1 PETN1 OC3# USB_OC#4_PCH
<23> PCIE_ITX_C_PRX_P1 1 0.1U_0402_10V6K J24 E5 USB_OC#4_PCH <19>
C PCIE_PTX_C_IRX_N2 PETP1 OC4# SLP_CHG_M3_PCH C
<18> PCIE_PTX_C_IRX_N2 M18 PERN2 OC5#/GPIO29 E6 SLP_CHG_M3_PCH <19>
PCIE_PTX_C_IRX_P2 SLP_CHG_M4_PCH +3VALW
WLAN+BT Combo <18> PCIE_PTX_C_IRX_P2 PCIE_ITX_PRX_N2
M19
PERP2 OC6#/GPIO30
C2
USB_OC#7 SLP_CHG_M4_PCH <19>
<18> PCIE_ITX_C_PRX_N2 WLAN@ C1017 2 1 0.1U_0402_10V6K K24 C3 RP12
WLAN@ C1018 2 PCIE_ITX_PRX_P2 PETN2 OC7#/GPIO31 USB_OC#0_1_PCH 4
<18> PCIE_ITX_C_PRX_P2 1 0.1U_0402_10V6K K25 PETP2 5
PCIE_PTX_C_IRX_N3 L23 SLP_CHG_M4_PCH 3 6
<18> PCIE_PTX_C_IRX_N3 PERN3
PCI-E
WWLAN PCIE_PTX_C_IRX_P3 L24 USB_OC#7 2 7
<18> PCIE_PTX_C_IRX_P3 PERP3
<18> PCIE_ITX_C_PRX_N3 WWAN@C1021 2
WWAN@C1021 1 0.1U_0402_10V6K PCIE_ITX_PRX_N3 L22 G2 1 8
WWAN@C1022
WWAN@ C1022 2 PCIE_ITX_PRX_P3 PETN3 USBRBIAS
<18> PCIE_ITX_C_PRX_P3 1 0.1U_0402_10V6K M21 G3 R957 10K_0804_8P4R_5%
PETP3 USBRBIAS#
PAD T51 P17 PERN4
22.6_0402_1% Please closed Tiger point
PAD T52 P18 RP13
N25
PERP4 PIN within 200 mils USB_OC#3 4 5
PAD T53 PETN4
N24 USB_OC#2 3 6
PAD T54 PETP4
F4 CLK_PCH_48M USB_OC#4_PCH 2 7
CLK48 CLK_PCH_48M <9> SLP_CHG_M3_PCH 1 8
10K_0804_8P4R_5%
1
Please closed Tiger point 33_0402_5%
PIN within 500 mils @
R554
+1.5VS
2
R555 24.9_0402_1% 1
1 2 H24 @ 1 2
DMI_ZCOMP C1023 @R3
@ R3 0_0402_5%
J22
DMI_IRCOMP 22P_0402_50V8J
W23 2 WCM2012F2S-900T04_0805
<9> CLK_PCIE_PCH# DMI_CLKN For EMI, Close to TigerPoint USB20_N5_L USB20_N5
W24 4 4
<9> CLK_PCIE_PCH DMI_CLKP 3 3 USB20_N5 <18>
2
USB20_P5_L 1 USB20_P5
TIGERPOINT_ES1_BGA360 1 2 2 USB20_P5 <18>
L2 WWAN@
1 2
B @R4
@ R4 0_0402_5% B
2010.07.12 RF request
A A

Tigerpoint(2/4)
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
HDMI@
+3VALW 90.9_0402_1%
1 2 R931 BITCLK_PCH
<7> HDA_BITCLK_CPU
33_0402_5%1 2 R582
<21> HDA_BITCLK_CODEC
2011.04.26 Reserve GPIO12 for clean password
HDMI@
2.2K_0402_5% 1 R560 2 PCH_SMBCLK 90.9_0402_1%
1 2 R932 RST#_PCH Layout note: Put J2 close to J1
<7> HDA_RST#_CPU
33_0402_5%1 2 R609
<21> HDA_RST#_CODEC
2.2K_0402_5% 1 R561 2 PCH_SMBDATA 2011.06.10 Change J2 to JPW
HDMI@ BITCLK_PCH
90.9_0402_1%
1 2 R933 SDOUT_PCH
<7> HDA_SDOUT_CPU GPIO12 +3VALW
33_0402_5%1 2 R568
<21> HDA_SDOUT_CODEC PM_CLKRUN# 1
2 2
+3VALW HDMI@ R598 10K_0402_5%
1
D 90.9_0402_1% SYNC_PCH D
<7> HDA_SYNC_CPU 1 2 R934 C1024 @
1
<21> HDA_SYNC_CODEC
33_0402_5%1 2 R569
1
10P_0402_50V8J EVT# For EC request 7/5 R610
JPW 1 10K_0402_5%
1
10K_0402_5% 2 R562 1 SYS_RST# JUMP_43X39
@ C1087
2
2
0.1U_0402_16V4Z BOARD_ID
2
1
8.2K_0402_5% R563 ICH_RI# @
R611
10K_0402_5% 2 R564 1 EC_SWI# U15D TGP
10K_0402_5%
10K_0402_5% 2 R565 1 SLP_CHG# AA5 T15 GPIO0
2
LDRQ1#/GPIO23 BMBUSY#/GPIO0 GPIO6
<25> LPC_AD0 V6 LAD0/FWH0 GPIO6 W16
LPC
AA6 W14 SLPIOVR
<25> LPC_AD1 LAD1/FWH1 GPIO7 EC_SMI#
<25> LPC_AD2 Y5 K18 EC_SMI# <25>
LAD2/FWH2 GPIO8 EC_SCI#
<25> LPC_AD3 W8 H19 EC_SCI# <25>
LAD3/FWH3 GPIO9 PCH_ACIN
Y8 LDRQ0# GPIO10 M17
+3VALW Y4 A24 GPIO12
<25> LPC_FRAME# LFRAME#/FWH4 GPIO12
C23 EC_LID_OUT#
BITCLK_PCH GPIO13 SLP_CHG# EC_LID_OUT# <25>
P6 P5
RST#_PCH HDA_BIT_CLK GPIO14 GPIO15
U2
HDA_RST# GPIO15
E24 2011.04.20 SLP_CHG# pull high only
AUDIO
W2 AB20 T43
<21> HDA_SDIN0 HDA_SDIN0 DPRSLPVR
<7> HDA_SDIN1 V2 HDA_SDIN1 STP_PCI# Y16 H_STP_PCI# <9>
P8 HDA_SDIN2 STP_CPU# AB19 H_STP_CPU# <9>
SDOUT_PCH AA1 R3
RP14 SYNC_PCH Y1 HDA_SDOUT GPIO24 R570 1
HDA_SYNC GPIO25 C24 2 1K_0402_5%
5 4 LINKALERT# <9> CLK_PCH_14M AA3 D19 BOARD_ID
CLK14 GPIO26
1
6 3 GPIO11 D20 12/31 Add HW Board ID function
GPIO27
7 2 SMLINK0 R571 U3 EE_CS GPIO28 F22
8 1 SMLINK1 # MP C1026 4.7P change to AE2 EE_DIN CLKRUN# AC19 PM_CLKRUN# PLTRST#
10_0402_5%
10K_0804_8P4R_5%
10p for RF request RF@
T6
V3
EE_DOUT EPROM GPIO33
U14
AC1
2
C C1025 EE_SHCLK GPIO34 C
GPIO38 AC23
2
18P_0402_50V8J 1 T4 AC24 1
RTCX1 LAN_CLK GPIO39 BT_PWR# <18>
2 1 RF@ P7 R573
C1026 LANR_RSTSYNC H_PWRGD C1064 100K_0402_5%
B23 LAN_RST# CPUPWRGD/GPIO49 AB22 H_PWRGD <7>
10M_0402_5%
+3VALW Y2 AA2 0.1U_0402_16V4Z
LAN
MISC
LAN_RXD0
1
RP15 32.768KHZ_12.5PF_Q13MC14610002 2 10P_0402_50V8J AD1 AB17 EC_THERM# 2
EC_THERM# <25>
1
R572 LAN_RXD1 THRM#
1 8 GPIO15 2 NC OSC 1 AC2 LAN_RXD2 VRMPWRGD V16 VGATE
2 7 PCH_LOW_BAT# W3 AC18 MCH_SYNC#
LAN_TXD0 MCH_SYNC#
3 6 GPIO12 3 NC OSC 4 T7 LAN_TXD1 PWRBTN# E21 PBTN_OUT#
PBTN_OUT# <25>
4 5 EC_LID_OUT# U4 H23 ICH_RI#
2
LAN_TXD2 RI#
C1027
SUS_STAT#/LPCPD# G22 T42 7/20 Add test point
EC_CLK
EC_CLK <25> 01/11 Reserve EC_CLK for KBC
8.2K_0804_8P4R_5% 18P_0402_50V8J W4 D22
RTC
RTCX2 RTCX1 SUSCLK SYS_RST#
2 1 V5 RTCX2 SYS_RESET# G18
RTCRST# T5 G23 PLTRST#
RTCRST# PLTRST# EC_SWI# PLTRST# <7,18,23>
2011.06.10 Change J1 to JCMOS WAKE#
C25 EC_SWI# <18,23,25>
GPIO11 E20 T8 INTRUDER#
PCH_SMBCLK SMBALERT#/GPIO11 INTRUDER# PCH_POK
<9> PCH_SMBCLK H18 U10
SMBCLK PWROK
SMB
R574 1 2 PCH_SMBDATA E23 AC3 PCH_RSMRST#
+RTCVCC <9> PCH_SMBDATA SMBDATA RSMRST#
20K_0402_5% LINKALERT# H21 AD3 INTVRMEN
SMLINK0 LINKALERT# INTVRMEN PCH_SPKR +3VALW
JCMOS F25 SMLINK0 SPKR J16 PCH_SPKR <21>
+RTCVCC @ SMLINK1 F24
SMLINK1
1 1 2 H20 PM_SLP_S3# <25>
2 SLP_S3#
2
1M_0402_5% 1 R575 2 INTRUDER# PCH_SI_SPI_SO R2 E25
<26> PCH_SI_SPI_SO SPI_MISO SLP_S4# PM_SLP_S4# <25>
<26> PCH_SO_SPI_SI PCH_SO_SPI_SI R616 PCH_SO_SPI_SI_RT1 F21 R578
JUMP_43X39 SPI_MOSI SLP_S5# PM_SLP_S5# <25>
1 R576
SPI
332K_0402_1% 2 INTVRMEN PCH_SPI_CS# 47_0402_5% M8 330K_0402_5%
<26> PCH_SPI_CS# SPI_CS#
C1028 R617 PCH_SPICLK_R P9 B25 PCH_LOW_BAT#
<26> PCH_SPICLK SPI_CLK BATLOW#
1U_0402_6.3V4Z 47_0402_5% R4 AB23 H_DPRSTP#
H_DPRSTP# <7>
1
SPI_ARB DPRSTP# H_DPSLP# D44
1 2 AA18 H_DPSLP# <7>
DPSLP#
12P_0402_50V8J
2 F20 PCH_ACIN 2 1
+3VS RSVD31 ACIN <25,31>
for RF request
C1158
CH751H-40PT_SOD323-2
B 8.2K_0402_5% R577 SLPIOVR 1 B
8.2K_0402_5% @R579 PM_CLKRUN#

D45
8.2K_0402_5% R580 GPIO0 +3VS PCH_POK 2 1 PCH_RSMRST#
8.2K_0402_5% R581 GPIO6

10K_0402_5% 2 R566 1 PCH_SI_SPI_SO PCH_POK 1 2 D46
+3VS R583 10K_0402_5% 1 2
10K_0402_5% 2 PCH_SO_SPI_SI <30,32> POK
R567 1
EC_PWROK 1 2
10K_0402_5% 2 R618 1 PCH_SPI_CS# R584 10K_0402_5% CH751H-40PT_SOD323-2
1K_0402_5% 1 R585 2 MCH_SYNC#

1 2
2011.06.15 Change Pull high to +3VS R586
+3VS
0_0402_5%
R587 2 1 0_0402_5%
PCH_RSMRST# 1 3
C
EC_RSMRST# <25>
1 1 2 @ Q36
E
@ R588 MMBT3906_SOT23-3
C1030 10K_0402_5%
B
2
0.1U_0402_16V4Z 1 2 +3VALW
2 @ R589
1
4.7K_0402_5%
5
+RTCBATT @U5
@ U5 @ D7B
@D7B @ D7A
1 BAV99DW-7_SOT363 BAV99DW-7_SOT363
P
<25> EC_PWROK B
4 PCH_POK <6>
+RTCVCC +RTCBATT_R Y
<9,25,28,34,35> VGATE 2
A
G
JRTC
6
TC7SH08FUF_SSOP5
1 3 2 1
RSMRST# circuit
3
A 1 GND D6 R126 @ R590 A

2 4
2 GND 2.2K_0402_5%
2 1 2 +RTCBATT
ACES_85205-0200N 1 1K_0402_5%
CONN@ 3 +3VL
1
C1029 BAV70W_SOT323-3
1U_0402_6.3V6K
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Tigerpoint(3/4)
Custom 0.3
QBU00
5 4 3 2 1
5 4 3 2 1
D U15F TGP D
TGP
+5VS +3VS U15E A1
VSS01
A25
+V5REF_RUN VSS02
VCC5REF F12 VSS03 B6
1
VSS04 B10
R591 D8 B16
VSS05
B20
100_0402_5% RB751V-40TE17_SOD323-2 +V5REF_SUS VSS06
VCC5REF_SUS F5 VSS07 B24
E18
2
+SATAPLL VSS08
VCCSATAPLL Y6 VSS09 F16
+V5REF_RUN 2mA G4
VSS10
1 6mA VCCRTC
AE3 +RTCVCC VSS11
G8
C1031
0.01U_0402_16V7K
H1
0.1U_0402_10V6K
1U_0402_6.3V6K +DMIPLL VSS12
Y25 1 1 H4
VCCDMIPLL VSS13
C1033
H5
2 VSS14
C1032
VCCUSBPLL F6 VSS15 K4
1432mA R592 K8
+VCC1_5 1 2 2 VSS16
2 +1.5VS K11
VSS17
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_10V4Z
VSS18 K19
W18 0_0603_5% K20
V_CPU_IO VSS19
14mA 2 2 1 1 1 L4
C1034
C1035
+5VALW +3VALW VSS20
C1036
C1037
C1038
VSS21 M7
M11
VSS22
AA8 N3
VCC1_5_1 VSS23
1
D47 M9 1 1 2 2 2 N12
R593 VCC1_5_2 VSS24
M20 N13
VCC1_5_3 VSS25
POWER
N22 N14
10_0402_5% RB751V-40TE17_SOD323-2 VCC1_5_4 VSS26
N23
R594 VSS27
P11
2
C +V5REF_SUS +VCC1_05 1 VSS28 C

2 +1.05VS VSS29 P13
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_10V4Z
P19
10mA 955mA 0_0603_5% VSS30
R14
C1039 1 1 1 1 VSS31
C1040
C1041
C1042
VCC1_05_1 J10 VSS32 R22
VCC1_05_2 K17 VSS33 T2
0.1U_0402_10V6K P15 T22
2 VCC1_05_3 2 2 2 VSS34
V10 V1
VCC1_05_4 VSS35
V7
VSS36
V8
VSS37
V19
R596 VSS38
216mA VSS39
V22
H25 +VCC33 1 2 +3VS_PRIME V25
VCC3_3_1 VSS40
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AD13 W12
VCC3_3_2 0_0603_5% VSS41
F10 1 1 1 1 1 1 1 W22
C1043
C1044
VCC3_3_3 VSS42
C1045
C1046
C1047
C1048
C1049
G10 @ @ Y2
VCC3_3_4 VSS43
R10 Y24
VCC3_3_5 VSS44
T9 AB4
VCC3_3_6 2 2 2 2 2 2 2 VSS45
AB6
VSS46
AB7
VSS47
VCCSUS3_3_1 F18 VSS48 AB8
VCCSUS3_3_2 N4 VSS49 AC8
K7 R599 AD2
VCCSUS3_3_3 +VCCSUS33 VSS50
F1 1 2 AD10
VCCSUS3_3_4 +3VALW VSS51
0.1U_0402_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0805_6.3V4Z
VSS52 AD20
92mA 0_0603_5% AD24
VSS53
1 1 1 1 VSS54 AE1
C1051
C1052
C1053
C1054
@ AE10
VSS55
AE25
VSS56
2 2 2 2
5
B B
VSS57 G24
Place closely pin Y25 within 100mlis. VSS58
AE13
F2
+1.5VS VSS59
+1.5VS
R601
1 2 AE16
+DMIPLL RF@C1068
RF@C1068 2200P_0402_50V7K RSVD32
1 2
+3VS
0.01U_0402_16V7K
24mA
4.7U_0603_6.3V6K
1 2
0_0603_5% 1 1 RF@C207
RF@ C207 68P_0402_50V8J
1 2
C1055
C1056
@ RF@C1069
RF@ C1069 2200P_0402_50V7K TIGERPOINT_ES1_BGA360
+3VALW 1 2
2 2 RF@C208
RF@ C208 68P_0402_50V8J
1 2
RF@C1070
RF@ C1070 2200P_0402_50V7K
+1.05VS 1 2
RF@C209
RF@ C209 68P_0402_50V8J
Place closely pin Y6 within 100mlis. RF@C1071
RF@ C1071
1 2
2200P_0402_50V7K
1 2
+1.5VS RF@ C210 68P_0402_50V8J
R602
1 2
1 2 +SATAPLL RF@C1072
RF@ C1072 0.1U_0402_10V6K
10U_0805_10V4Z
0.1U_0402_10V6K
45mA
0_0603_5% 1 2
C1057
C1058
A 2010.07.12 RF request A
2 1

Tigerpoint(4/4)
Custom 0.3
QBU00
5 4 3 2 1
A B C D E
CRT CONNECTOR
1 1
Place closed to conn.

CRT@ LV6
GMCH_CRT_R 1 2 CRT_R_L
<7> GMCH_CRT_R
NBQ100505T-800Y_0402
CRT@ LV7
GMCH_CRT_G 1 2 CRT_G_L
<7> GMCH_CRT_G
NBQ100505T-800Y_0402
CRT@ LV8
GMCH_CRT_B 1 2 CRT_B_L
<7> GMCH_CRT_B
NBQ100505T-800Y_0402
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1
1
CRT@ CRT@ CRT@ CRT@ 1 CRT@ 1 CRT@ 1 CRT@ 1 CRT@ 1 CRT@ 1
150_0402_1%
150_0402_1%
150_0402_1%
RV145 RV146 RV147 CV190 CV191 CV192 CV193 CV194 CV195
2 2 2 2 2 2
2
HDMI@ HDMI@ HDMI@
CV193 CV194 CV195
0_0402_5% 0_0402_5% 0_0402_5%
2 2
+CRT_VCC
CRT@ 1 2 1 2
CV196 0.1U_0402_16V4Z RV148 10K_0402_5%
5 CRT@ CRT@
1
UV13
OE#
P
2 4 CRT_HSYNC_1 CRT@ RV149 1 2 39_0402_5% HSYNC

<7> GMCH_CRT_HSYNC A Y
G
SN74AHCT1G125DCKR_SC70-5 CRT_VSYNC_1 CRT@ RV150 1 2 39_0402_5% VSYNC

3
33P_0402_50V8K
33P_0402_50V8K
+CRT_VCC
CRT@ 1 CRT@ 1
CRT@ 1 2 CV198 CV199 HDMI@ HDMI@
CV197 0.1U_0402_16V4Z CRT@ CV198 CV199
5
UV14 0_0402_5% 0_0402_5%

2 2
OE#
P
<7> GMCH_CRT_VSYNC 2 A Y 4
G
SN74AHCT1G125DCKR_SC70-5
3
R990
HDMI@ 1 2 +HDMI_5V_OUT
If=1A 0_0603_5%
+5VS
+CRT_VCC_R +CRT_VCC
DV5 FV1 30mil
3 3
2 1 1 2
1.1A_6V_MINISMDC110F-2 1
+3VS +CRT_VCC RB161M-20_SOD123-2
CV200
0.1U_0402_16V4Z
2
+3VS
1
+CRT_VCC
1
CRT@ RV151 RV152 CRT@ JCRT 2011.05.10 Co-lay with HDMI port
2.2K_0402_5% 2.2K_0402_5% CRT@ RV153 RV154 CRT@ 6
2.2K_0402_5% 2.2K_0402_5% RGND
11 ID0
CRT_R_L 1
2
Red
7
2
GGND
5
CRT@ CRT_DDC_DAT 12
QV3B CRT_G_L SDA
2 Green
4 3 CRT_DDC_DAT 8
<7> GMCH_CRT_DATA HSYNC BGND
13 Hsync
2N7002DW -T/R7_SOT363-6 CRT_B_L 3 Blue
2
9 +5V
VSYNC 14
CRT_DDC_CLK Vsync
<7> GMCH_CRT_CLK 1 6 4 res
CRT@ QV3A 10
2N7002DW -T/R7_SOT363-6 CRT_DDC_CLK SGND
1 1 15 SCL
5 GND
CRT@ CV201 CV202 CRT@
470P_0402_50V8J 470P_0402_50V8J 16
2 2 GND
17 GND
4
HDMI@ HDMI@ SUYIN_070546FR015S263ZR 4
CV201 CV202 CONN@
0_0402_5% 0_0402_5%

CRT PORT
0.3
QBU00
Date: Friday, November 04, 2011 Sheet 15 of 38
A B C D E
A B C D E
HDMI CONNECTOR
HDMI_CLK- @ 1 2 HDMI_R_CK-
R935 0_0402_5%
L14 HDMI@
1 2
1 2
4 4 3 3
WCM2012F2S-900T04_0805
1 HDMI_CLK+ @ HDMI_R_CK+ 1
1 2
R936 0_0402_5%
HDMI_TX0- @ 1 2 HDMI_R_D0-
R937 0_0402_5%
L15 HDMI@
1 2
1 2
4 3
4 3
<7> HDMI_TXD0+
HDMI@C1111 1
HDMI@C1112 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
HDMI_TX0+
HDMI_TX0- HDMI_TX0+ @
WCM2012F2S-900T04_0805
1 2 HDMI_R_D0+
< HDMI Connector >
<7> HDMI_TXD0-
HDMI@C1113 1 2 0.1U_0402_16V7K HDMI_TX1+ R938 0_0402_5%
<7> HDMI_TXD1+ HDMI_TX1- HDMI_TX1- HDMI_R_D1-
HDMI@C1114 1 2 0.1U_0402_16V7K @ 1 2
<7> HDMI_TXD1-
R939 0_0402_5%
HDMI@C1115 1 2 0.1U_0402_16V7K HDMI_TX2+ L16 HDMI@

<7> HDMI_TXD2+
HDMI@C1116 1 2 0.1U_0402_16V7K HDMI_TX2- 1 2 HPD
<7> HDMI_TXD2- HDMI_CLK+ 1 2
HDMI@C1117 1 2 0.1U_0402_16V7K +HDMI_5V_OUT
<7> HDMI_CLK0+
HDMI@C1118 1 2 0.1U_0402_16V7K HDMI_CLK-
<7> HDMI_CLK0- HDMIDAT
4 3
4 3 HDMICLK
WCM2012F2S-900T04_0805
HDMI_TX1+ @ 1 2 HDMI_R_D1+
R940 0_0402_5% HDMI_R_CK-
HDMI_TX2- @ 1 2 HDMI_R_D2-
R941 0_0402_5% HDMI_R_CK+
HDMI_R_D0-
L17 HDMI@
1 2 HDMI_R_D0+
1 2 HDMI_R_D1-
2 2
4 3 HDMI_R_D1+
4 3 HDMI_R_D2-
WCM2012F2S-900T04_0805
HDMI_TX2+ @ 1 2 HDMI_R_D2+ HDMI_R_D2+
C1119 0_0402_5%
+3VS
+HDMI_5V_OUT
+3VS
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2
HDMI@
HDMI@
2
R944
R945
HDMI@
HDMI@
R942
R943
1
5
HDMI@
1
Q3B
4 3 HDMIDAT
<7> HDMIDAT_C HDMI_CLK+ 1 2
2N7002DW-T/R7_SOT363-6 HDMI@R946 619_0402_1%
2
HDMI_CLK- 1 2
1 6 HDMICLK HDMI@R947 619_0402_1%
<7> HDMICLK_C Q3A
3 HDMI@2N7002DW-T/R7_SOT363-6 HDMI_TX0- 3
1 2
HDMI@R948 619_0402_1%
HDMI_TX0+ 1 2
HDMI@R949 619_0402_1%
+3VS HDMI_TX1- 1 2
HDMI@R950 619_0402_1%
1
HDMI_TX1+ 1 2
R952 HDMI@ HDMI@R951 619_0402_1%
10K_0402_5%
HDMI_TX2+ 1 2
HDMI@R953 619_0402_1%
2
<7> HPD_C HDMI_TX2- 1 2

3
HDMI@R954 619_0402_1%
Q46B
6
2N7002DW-T/R7_SOT363-6
5 HPD Q46A
HDMI@
2N7002DW-T/R7_SOT363-6
+3VS 2 HDMI@
4
R955 HDMI@
1
1M_0402_5%
1
2011.05.04 Change Q42,Q43 to dual package.
4 4

HDMI PORT
0.3
QBU00
A B C D E
5 4 3 2 1
LCD POWER CIRCUIT
D D
+LCDVDD
+3VS W=40mils
1
R116 +3VS
150_0603_5%
1
1
C149
2
1 @
R117 C183 4.7U_0805_10V4Z
3
100K_0402_5% 2
Q2B 0.1U_0402_16V7K 2A
3
2 S
G
2N7002DW -T/R7_SOT363-6 5 2 1 2
R141 47K_0402_5%
D Q11
1
1 AO3413_SOT23
C498
+LCDVDD
6
2
0.01U_0402_25V7K W=40mils 2011.05.22 Remove EDID pull up resistors for Intel issue
Q2A
<7> GMCH_ENVDD 2 1 1
1
2N7002DW -T/R7_SOT363-6 C186 C187 +3VS
@
1
R142 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2
C 100K_0402_5% C
2.2K_0402_5%
2.2K_0402_5%
2
2
R143
R144
@ @
1
LCD_EDID_CLK LCD_EDID_CLK <7>
LCD_EDID_DATA
LED/PANEL BD. Conn. LCD_EDID_DATA <7>
JLVDS1
+LCDVDD R377 1 2 0_0805_5% (20 MIL) +LCDVDD_R 1 1

2 2
+3VS 3 3
1 LCD_EDID_CLK 4 4
C468 1 LCD_EDID_DATA 5 5 2011.05.20 LCD brightness will controlled by CPU(DPST)
@ C469 <7> LCD_TXOUT0- LCD_TXOUT0- 6
680P_0402_50V7K @ LCD_TXOUT0+ 6
<7> LCD_TXOUT0+ 7 7
2 680P_0402_50V7K 8 8
2 LCD_TXOUT1- CH751H-40PT_SOD323-2 D55 @
<7> LCD_TXOUT1- 9 9
<7> LCD_TXOUT1+ LCD_TXOUT1+ 10 2 1 INVT_PW M_R
B 10 <25> INVT_PW M B
<7> LCD_TXOUT2- LCD_TXOUT2- 11
LCD_TXOUT2+ 11
<7> LCD_TXOUT2+ 12 12
13 R420 1 2 0_0402_5%
13 <7> GMCH_INVT_PW M
LCD_TXCLK- 14
<7> LCD_TXCLK- 14
LCD_TXCLK+ 15
<7> LCD_TXCLK+ 15
16 16
17 17
18 18
680P_0402_50V7K 2 1 C188 CH751H-40PT_SOD323-2 D54 INVT_PW M_R 19
BKOFF# 19
<25> BKOFF#_L 2 1 20 20
21 21
68P_0402_50V8J 2 1 C189 1 2 +LCD_INV 22
C306 0.1U_0402_16V4Z 22
23 23
24 24
+3VS_LVDS_CAM 25 25 MGND4 34
250mA B+ R376 1 2 0_0805_5% +LCD_INV USB20_N7_R 26 33
USB20_P7_R 26 MGND3
27 27
28
<21> DMIC_CLK
DMIC_CLK
DMIC_DAT
29
30
28
29 MGND2 32
31
Int. Camera 1 @
R392
2
0_0402_5%
+3VS_LVDS_CAM <21> DMIC_DAT 30 MGND1
R105 L13
1 1 2 2
0_0603_5% W=20mils 0.1U_0402_16V4Z I-PEX_20143-030E-20F~D USB20_N7_R
USB20_N7 <12>
+3VS 1 2 1 2 @ USB20_P7_R
USB20_P7 <12>
C313 4 3
D9 4 3
3 DMIC_CLK W CM2012F2S-900T04_0805
1 1 2
A 2 DMIC_DAT R393 0_0402_5% A
@
PACDN042Y3R_SOT23-3

LCD_TXCLK+ C871 1 2 10P_0402_50V8J LCD_TXCLK- 2010/06/27 2011/6/27 Title
Issued Date Deciphered Date
LVDS /INVERTER
0.3
QBU00
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMax 2/25 PVT:Mount C479,C480 with 47pf

3/16 PVT:Add BOM Config of C481,C482 to WLAN@
+3V_WLAN +1.5V_WLAN
120 mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1
C258 C259 C260 C479 C261 C262 C263 C480
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J
1 0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 1
For WWAN request For WWAN request
+1.5V_WLAN
+1.5VS
WLAN@ +3V_WLAN +3VS
BT_CTRL 2 1 EC_RX_P80_CLK_R 1 2 PJ20
1K_0402_5% R888 0_0805_5% 2 1
R326 JWLAN WLAN@ 2 1
1 @ JUMP_43X79
1
# MP Add R326 1K for WB195 pin 51 3
3 2
2
BT_CTRL 5 4
WLAN_CLKREQ# 5 4
<9> WLAN_CLKREQ# 7 6
7 6 LPC_FRAME#_R
9 9 8 8 LPC_FRAME#_R <25>
11 10 LPC_AD3_R
<9> CLK_PCIE_WLAN# 11 10 LPC_AD2_R LPC_AD3_R <25>
<9> CLK_PCIE_WLAN 13
13 12
12 LPC_AD2_R <25> #EVT WLAN&BT Combo module circuits
15 14 LPC_AD1_R
15 14 LPC_AD0_R LPC_AD1_R <25>
16 16 LPC_AD0_R <25> BT BT
on module on module
PLTRST# 17 Enable Disable
CLK_PCI_DDR 17
<9> CLK_PCI_DDR 19 18
19 18 WL_OFF_R#
21 20
21 20 PLTRST#
<12> PCIE_PTX_C_IRX_N2 23 23 22 22 PLTRST# <7,13,23> BT_CRTL HI LO
<12> PCIE_PTX_C_IRX_P2 25 25 24 24
27 26
27 26 # MP Add R328
29 29 28 28
<12> PCIE_ITX_C_PRX_N2 31 30 CLK_SMBCLK <9,10> by pass for cost down
31 30
33 32 CLK_SMBDATA <9,10>
<12> PCIE_ITX_C_PRX_P2 33 32 +3VS BT_CTRL
35 35 34 34
37 37 36 36 USB20_N6 <12>
WLAN/ WiFi +3V_WLAN 39
39 38
38 USB20_P6 <12>
2
41 40
2 41 40 @ R259 R328 @ 2
43 43 42 42
45 44 LED_WIMAX#_R 1 2 LED_WIMAX# 100K_0402_5% 0_0402_5%
45 44 LED_WIMAX# <25,27>
DEBUG@ 47 46
R425 1 0_0402_5% 47 46 R428 R229@
<25> EC_TX_P80_DATA 2 49 48
1
49 48
1
R426 1 EC_RX_P80_CLK_R 0_0402_5% 100K_0402_5% D
<25> EC_RX_P80_CLK 2 51 51 50 50
DEBUG@ 0_0402_5% 52 1 2 +3VS 2 Q41
52 <13> BT_PWR#
Debug card using 53 GND
G
1
54 S 2N7002_SOT23
3
R429 DEBUG@ GND WLAN@
100K_0402_5% CONN@ ACES_88910-5204
#DVT WLAN,WWAN and BT LED
control by EC and HW reserve @ D49
2
WL_OFF_R# 2 1 WL_OFF# <25>

Mini-Express Card for 3G/GPS 1 2
3G current need to 2750mA 3/16 PVT:Add BOM Config of C481,C482 to 3GGPS@ R430
0_0402_5%
+3V_WWAN +1.5V_WWAN
120 mil
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1
C265 C266 C267 C482 C268 C269 C270 C481
WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ WWAN@ D14
2 2 2 47P_0402_50V8J 2 2 2 47P_0402_50V8J 1 6
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z V I/O V I/O
For WWAN request For WWAN request 2
Ground V BUS
5 +UIM_PWR
2/25 PVT:Mount C482,C481 with 47pf +UIM_PWR
3 +3V_WWAN +3VS 3 4 3
+1.5VS +1.5V_WWAN V I/O V I/O
IP4223CZ6_SO6-6
1
1 2 R231
2011.04.28 Reserve for new 3G/LTE module 1 2 R889 0_0805_5% @ J3GSIM CONN@
4.7K_0402_5%
R890 0_0805_5% WWAN@ 3G@
JGPS +UIM_PWR
WWAN@ +UIM_PWR 1 4
MC77XX@ R4351 UIM_RST VCC GND UIM_VPP
<13,23,25> EC_SWI# 2 0_0402_5% 1 120 mil 2 5
2
1 RST VPP
1
Reserve MC77XX@ R4331 2 0_0402_5% 3 2 1 UIM_CLK 3 6 UIM_DATA

PAD T71 3 2 CLK I/O
PAD T72 MC77XX@ R4341 2 0_0402_5% 5 4 D13
WWAN_CLKREQ# 5 4 C296
<9> WWAN_CLKREQ# 7 7 6 6 +1.5V_WWAN GLZ20A LL-34 7 GND GND 8
9 8 +UIM_PWR 0.1U_0402_16V4Z
9 8 +UIM_PWR 2 3G@
11 10 UIM_DATA 3G@ SUYIN_254020MA006S522ZL~D
<9> CLK_PCIE_WWAN#
2
11 10 UIM_CLK
<9> CLK_PCIE_WWAN 13 12
13 12 UIM_RST
15 15 14 14
16 UIM_VPP
16
17
17
19 18
19 18 UWB_OFF#_R
21 20
21 20 PLTRST#
<12> PCIE_PTX_C_IRX_N3 23 23 22 22
<12> PCIE_PTX_C_IRX_P3 25 24
25 24
27 27 26 26
29 28
29 28 CLK_SMBCLK
<12> PCIE_ITX_C_PRX_N3 31 30
31 30 CLK_SMBDATA D52 @
<12> PCIE_ITX_C_PRX_P3 33 33 32 32
35 34 UWB_OFF#_R 2 1
35 34 UWB_OFF# <25>
37 36 USB20_N5 <12>
37 36 CH751H-40PT_SOD323-2
+3V_WWAN 39 38 USB20_P5 <12>
39 38
41 40
41 40 LED_WIMAX#_R
43 43 42 42
4 0_0402_5% 2 4
45 44 1R437 MC77XX@ T74 PAD 1 2
45 44 0_0402_5% 2
47 47 46 46 1R436 MC77XX@ T73 PAD
@ D57 49 48 WWAN@R431
WWAN@ R431
49 48
<25> GPS_OFF# 1 2 GPS_OFF#_R 51 50 0_0402_5%
51 50
52 52
CH751H-40PT_SOD323-2 53
GND 2011.04.28 Reserve for new 3G/LTE module
54 GND
1 2
P-TWO_A54402-A0G16-N
MC77XX@ R438
CONN@ Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title
0_0402_5%
WLAN/WiMAX Express Slot
2011.04.28 Reserve for new 3G/LTE module AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
QBU00
Date: Monday, November 07, 2011 Sheet 18 of 38
A B C D E
5 4 3 2 1
W=30mils
USB Sleep & Charge +5VALW +USB_VCCB
Auto-Mode 1
US4
GND VOUT
8
2 7
Mode3 <25> USB_CHG_EN# 1 2
3
4
VIN VOUT
VIN VOUT
EN FLG
6
5 USB_OC#4
R88
0_0402_5% G547E2P11U_SO8
<25> USB_EN# 1 2 1
@ R87 C288
0_0402_5% @
MAX14566B 4.7U_0805_10V4Z
D
2 D
CB0 CB1 (CEN#) #PVT R88 CHG@ change to
SLP_CHG_M4 STATUS always stuff for OC protect
SLP_CHG_M3
+USB_VCCB actioc same
0 0 AUTO MODE W=30mils
Force Dedicated charger mode +USB_VCCB 0.1U_0402_16V4Z
0 1 (MODE3) 1
1 1 1
Pass-Through (USB) Mode: C1 + C2 C3 C4
1 X Connect DP/DM to TDP/TDM 150U_B2_6.3VM_R45M
2 2 2 2
470P_0402_50V8J 1000P_0402_50V7K JUSB1

1 VCC
1 2 nonCHG@ USB20_N4_RL 2
R221 0_0402_5% USB20_P4_RL D-
3 D+
1 2 nonCHG@ 4
R222 0_0402_5% GND
5 GND1
6
GND2
SA00004GV00 7
GND3
8 GND4
US1 CHG@ C5
SLP_CHG_M3 1 8 SLP_CHG_M4 1 2 SUYIN_020133GB004M25MZL 0.1U_0402_16V4Z
USB20_N4_R CEN CB USB20_N4 @ R1 0_0402_5% CONN@ D1
2 DM TDM 7 USB20_N4 <12>
USB20_P4_R 3 6 USB20_P4 L1 1 6 1 2
DP TDP USB20_P4 <12> I/O1 I/O4
4 5 +5VALW USB20_N4_R 1 1 2 USB20_N4_RL
GND VCC 2
9 1 2 5 +5VALW
GND C892 REF1 REF2
MAX14566BEETA+_TDFN-EP8_2X2~D 0.1U_0402_16V7K USB20_P4_R 4 3 USB20_P4_RL USB20_P4_RL 3 4 USB20_N4_RL
CHG@ 4 3 I/O2 I/O3
2 WCM2012F2S-900T04_0805 CM1293A-04SO_SOT23-6
1 2
@ R2 0_0402_5%
For EMI request
C C
CHG@
R211 0_0402_5%
2 1 SLP_CHG_M3
<12> SLP_CHG_M3_PCH
CHG@ <12> USB_OC#0_1_PCH 1 2 USB_OC#0_1 1 2 USB_OC#0_1_EC <25>
R213 0_0402_5% @ R7 0_0402_5% R9 0_0402_5%
2 1 SLP_CHG_M4 <12> USB_OC#4_PCH 1 2 USB_OC#4 1 2 USB_OC#4_EC <25>
<12> SLP_CHG_M4_PCH
@ R8 0_0402_5% R10 0_0402_5%
#DVT USB_OC# control by EC

Use PCH 0120 reserve both EC and PCH.
For EMI request

For EMI request
2/3 DVT: Change D38,D37 from PRTR5V0U2X_SOT143-4 to CM1293A-04SO_SOT23-6
USB CONN
+5VALW 1.4A +USB_VCCA H2 H3 H4 H11 H12 H13 H14
W=60mils
U18
1 8 @ @ @ @ @ @ @
GND OUT
2 7 1
1
IN OUT H_2P3 H_2P3 H_2P3 H_3P3 H_3P3 H_2P0N H_2P0X2P6N
3 IN OUT 6 1
USB_EN# 4 5 C283
EN# OC#
APL3510BXI-TRG MSOP 8 4.7U_0805_10V4Z # PVT Add H14 and remove H1
2 H6 H7 H8 H9 H10
B B
@ @ @ @ @
1
1
H_2P3 H_2P3 H_1P2 H_1P2 H_1P2
USB_OC#0_1
+USB_VCCA
JP1
Add 0.1u Caps for each screw hole for ESD rule
1
1 +3VS +5VALW
2
2
3
3
4
USB20_P0 4
<12> USB20_P0 5
USB20_N0 5
6
0.1U_0402_16V4Z
<12> USB20_N0 6
7 1 1 1 1 1 1
7
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
USB20_P1 8
<12> USB20_P1 8
USB20_N1 9 C531 C528 @ C535 C534 C526 C527
<12> USB20_N1 9
10 0.1U_0402_16V4Z
10 2 2 2 2 2 2
11
GND
12
GND
ACES_85201-1005N_10P
CONN@ Close to H7 Close to H2 Close to H9,H6
FIDUCIAL_C40M80
FM1 FM2
@ @
1
A A
FM3 FM4
@ @
1
Close to H5

USB Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
QBU00
5 4 3 2 1
A B C D E F G H
SATA Conn.
For 1.8" SSD
+5VS +3VS SSD HDD need 400mA for 3V(PHISON)
Place closely JHDD SATA CONN.
1.2A
1 1 1 1 1 1 1 1
1 C275 C276 C277 C278 C279 C280 C281 C282 1
@ @ @
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2
JSATA
2011.06.16 Add for ESD
GND 1
2 SATA_ITX_C_DRX_P0 C284 1 2 0.01U_0402_25V7K
A+ SATA_ITX_DRX_P0 <11>
3 SATA_ITX_C_DRX_N0 C285 1 2 0.01U_0402_25V7K
A- SATA_ITX_DRX_N0 <11>
GND 4
5 SATA_IRX_DTX_N0 C286 1 2 0.01U_0402_25V7K
B- SATA_IRX_C_DTX_N0 <11>
6 SATA_IRX_DTX_P0 C287 1 2 0.01U_0402_25V7K
B+ SATA_IRX_C_DTX_P0 <11>
GND 7
V33 8 +3VS
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14 +5VS
V5 15
V5 16
GND 17
Reserved 18
2 19 2
GND
V12 20
V12 21
V12 22
GND 23
GND 24
SUYIN_127043FR022G226ZL_NR
CONN@
3 3
4 4

SATA / CRT
Custom 0.3
QBU00
A B C D E F G H
A B C D E
Speaker Connector
RA2
+PVDD1 600 mA 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5V_CODEC placement near Audio Codec
1 1 0_0603_5% 1 1
CA57 CA44 RA13
place close to chip CA56 CA43 SPKL+ 2 1 SPK_L1
SPK_L1 <22>
2
0_0603_5% 1
JA1 2 2 2 2
2
0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z CA19
470P_0402_50V8J 2
2
1
1 1 @ place close to chip @ CA24
CA2 CA1 1 1U_0402_6.3V4Z
1
1 +3VS_DVDD @ 1
+3VS_DVDD 1
10U_0805_10V4Z
2 2
# DVT For RF RA11 470P_0402_50V8J CA20
+PVDD2 2 1 RA14
+5V_CODEC 2
1 1 1 0_0603_5% SPKL- 2 1 @ SPK_L2
SPK_L2 <22>
0.1U_0402_16V4Z 0.1U_0402_16V4Z CA60 @ 0_0603_5%
1 2 35 mA CA61 C224 RF@ @ RA15
+3VS +AVDD
RA1 FBMH1608HM601-T 1 1 68P_0402_50V8J SPKR+ 2 1 SPK_R1
2 2 2 10U_0805_10V4Z SPK_R1 <22>
0_0603_5% 1
CA8 CA7
10U_0805_10V4Z RA3 CA25
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 470P_0402_50V8J
1 +5V_CODEC 2
0_0603_5% @ 2 CA27
ALC259@ 1 1U_0402_6.3V4Z
UA1 ALC269@ @
39
46
25
38
1 1 1 1
9
ALC259-VB5-GR_QFN48_7X7 UA1 CA3 CA4 CA5 CA6 470P_0402_50V8J CA26 1
Change CA9 and CA10 RA16
DVDD_IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
SPKR- 1 @ 2 SPK_R2
Ext. Mic/LINE IN to 1U at pre-MP 2 2 2 2
2 SPK_R2 <22>
place close to chip 0_0603_5%
10U_0805_10V4Z 0.1U_0402_16V4Z
ALC269@CA9 1U_0402_6.3V4Z
MIC1_LINE1_R_L 2 1 LINE1_L 23 40 SPKL+
<22> MIC1_LINE1_R_L
ALC269@CA10 LINE1_R 24 LINE1_L SPK_OUT_L+
41 SPKL- Beep sound
<22> MIC1_LINE1_R_R
MIC1_LINE1_R_R 2 11U_0402_6.3V4Z
LINE1_R SPK_OUT_L- EC Beep RA7
14 45 SPKR+ 1 2
LINE2_L SPK_OUT_R+ SPKR- <25> EC_BEEP
15 44 47K_0402_5%
4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-
MIC1_LINE1_R_L 2 1 MIC_L 21 32
MIC_R 22 MIC1_L HP_OUT_L HP_L <22>
33
MIC1_LINE1_R_R 2 1
MIC1_R HP_OUT_R HP_R <22> PCI Beep RA8
CA13
16 1 2 1 2 MONO_IN
4.7U_0805_10V4Z CA22 MIC2_L <13> PCH_SPKR
17 47K_0402_5%
MIC2_R HDA_SYNC_CODEC 0.1U_0402_16V4Z
10 HDA_SYNC_CODEC <13>
2 SYNC 2
DMIC_DAT 2 6 HDA_BITCLK_CODEC
<17> DMIC_DAT GPIO0/DMIC_DATA BCLK HDA_BITCLK_CODEC <13>
DMIC_CLK_R 3 GPIO1/DMIC_CLK
1
5 HDA_SDOUT_CODEC 1
SDATA_OUT HDA_SDOUT_CODEC <13> 100P_0402_50V8J
RA12
EC_MUTE# 4 8 HDA_SDIN0_R 2 1 CA18
<25> EC_MUTE# PD# SDATA_IN HDA_SDIN0 <13>
RA6 33_0402_5% 4.7K_0402_5%
2
2
HDA_RST#_CODEC 11 47
<13> HDA_RST#_CODEC RESET# EAPD
1
48
MONO_IN SPDIFO
1 2 12 PCBEEP
RA40 CA11 CA12 100P_0402_50V8J 20
100K_0402_5% 0.01U_0402_25V7K MONO_OUT
@ @ SENSE_A 13
2
SENSE A
For EMI MIC2_VREFO
29
+5VALW +5VS
18
SENSE B +5V_CODEC
MIC1_VREFO_R
30 +MIC1_VREFO_R CA23 10U_0805_10V4Z
1 2 36 CBP LDO_CAP 28 1 2
CA15 ALC269@
2.2U_0603_6.3V4Z 35 27 AC_VREF 1 2
CBN VREF RA53 0_0805_5%
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% 1 2
MIC1_VREFO_L JDREF RA54 0_0805_5%
1 2
EC_MUTE# 43 34 CPVEE 1 2 ALC259@
PVSS2 CPVEE CA14 2.2U_0603_6.3V4Z CA17 CA16
42 PVSS1
49 26 2.2U_0603_6.3V4Z
DVSS2 AVSS1
1
2 1
7 37
RA45 DVSS1 AVSS2 0.1U_0402_16V4Z
4.7K_0402_5% Add RA45 and un-mount RA43 at PVT ALC269Q-VB2-GR_QFN48_7X7 MIC_SENSE
for audio noise issue place close to chip
1
3 3
DGND AGND
2
RA55 ALC259@
0_0402_5%
6
for EMI request
QA1A
2
HDA_BITCLK_CODEC 1 2 1 2 ALC269@ RA28 100K_0402_5%
CA47 1 2 0.1U_0603_50V7K RF@RA42
RF@RA42 10_0402_5% 2N7002DW-T/R7_SOT363-6 2
RF@CA62
RF@ CA62 12P_0402_50V8J ALC269@
CA48 1 2 0.1U_0603_50V7K
1
<17> DMIC_CLK 1 2 DMIC_CLK_R
RA47 39_0402_5% CA49 1 2 0.1U_0603_50V7K Add RA43 for S/M battery mode at PVT
RF@ 2
RF@ CA50 1 2 0.1U_0603_50V7K
C438 +3VL RA44 100K_0402_5%
100P_0402_50V8J 1 2
1 RA18 0_0603_5% for RF request
<25> SM_SENSE#
3
place close to chip For EMI
QA1B
Sense Pin Impedance Codec Signals Function ALC269@
MIC_SENSE 2 1 SENSE_A 5
+3VS B+ BACK_SENSE <22>
39.2K PORT-I (PIN 32, 33) Headphone out RA10 20K_0402_1% 2N7002DW-T/R7_SOT363-6
4
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A 1 2
<22> NBA_PLUG @ CA28 1U_0402_6.3V4Z
10K PORT-C (PIN 23, 24) RA21 39.2K_0402_1% 1 2
4 @ CA29 1U_0402_6.3V4Z 4
5.1K (PIN 48) #EVT EMI for DMIC_CLK solution

Audio_ALC269
Custom QBU00 0.3
A B C D E
A B C D E
VL
SPEAKER
4.7K_0402_5%
RA48
MIC
1
ALC269@
JMIC1
1 8 1
7
3
2
MIC1_L LA2 1 2 FBM-11-160808-601-T_0603 MIC1_L_1 1
4
MIC1_R LA1 1 2 FBM-11-160808-601-T_0603 MIC1_R_1 2
DA7 BACK_SENSE 5
<21> BACK_SENSE
2 6
1
0.1U_0402_16V4Z
CA63
3 JSPK1 1 1 1 SINGA_2SJ2285-001191
6 CONN@
PESD5V0U2BT_SOT23-3 GND2 CA68 CA69 @
5 GND1
33P_0402_50V8K
33P_0402_50V8K
SPK_R1 4 2 2 2
<21> SPK_R1 4 1 1
SPK_R2 3
<21> SPK_R2 3
1
0_0402_5%
SPK_L1 2 CA64 CA65
<21> SPK_L1 2
SPK_L2 1 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<21> SPK_L2 1 2 2
PESD5V0U2BT_SOT23-3 CONN@ RA56
2 E&T_3806-F04N-02R ALC259@
2
1
2 2
3
DA6
Head phone
Ext.MIC/LINE IN JACK JHP2
8
RA46 2 1 +MIC1_VREFO_R 7
1K_0402_5% RA36 2.2K_0402_5% 3
MIC1_LINE1_R_R 2 1 MIC1_R HP_L RA52 1 2 40.2_0402_1% HP_L_R LA4 1 2 FBM-11-160808-601-T_0603 PL 1
<21> MIC1_LINE1_R_R <21> HP_L
4
HP_R RA51 1 2 40.2_0402_1% HP_R_R LA3 1 2 FBM-11-160808-601-T_0603 PR 2
MIC1_LINE1_R_L MIC1_L <21> HP_R
<21> MIC1_LINE1_R_L 2 1
1K_0402_5% <21> NBA_PLUG NBA_PLUG <BOM Structure> 5
RA35 2 1 +MIC1_VREFO_L 6
RA31 2.2K_0402_5% <BOM Structure>
3
1 1 CA71 SINGA_2SJ2285-001191 3
@
0.1U_0402_16V4Z CA70
33P_0402_50V8K
CONN@
33P_0402_50V8K 1
2 2
2 1
CA66
CA67 0.1U_0402_16V4Z
2
4 4

Audio Jack MIC/HP
Custom QBU00 0.3
A B C D E
A B C D
2011.04.20 Change to port 1 3/10 Change CL13 0805-->0603

UL1
Close to Pin 27,39,12,47,48 +3V_LAN
<12> PCIE_PTX_C_IRX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP LED3/EEDO 31
37 +LAN_VDD10
LED1/EESK
<12> PCIE_PTX_C_IRX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 1 2
LL1 @ 0.1U_0402_16V4Z CL10
17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2 1 2
<12> PCIE_ITX_C_PRX_P1 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% 2.2UH +-5% NLC252018T 0.1U_0402_16V4Z CL4
<12> PCIE_ITX_C_PRX_N1 HSIN EEDI/SDA
1 2 1 2
Layout Note: LL1 must be 0.1U_0402_16V4Z CL5
+3VALW RL19 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36 CL13 CL9 1 2
<9> LAN_CLKREQ# CLKREQB MDIP0
2 LAN_MDI0- CL8,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL6
MDIN0 LAN_MDI1+ 200mil to LL1 2 1
1
<7,13,18> PLTRST# 25 PERSTB MDIP1 4 1 2 1
5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL7

MDIN1
1
<9> CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7

RL102 20 8
<9> CLK_PCIE_LAN# REFCLK_N NC/MDIN2
10K_0402_5% NC/MDIP3 10
NC/MDIN3 11
LAN_X1 43
2
CKXTAL1
LOM_W AKE# LAN_X2 44 13 +LAN_VDD10 Close to Pin 3,6,9,13,29,41,45
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_EVDD10
DVDD10 29
41 +LAN_VDD10
RL20 0_0402_5% LOM_W AKE# DVDD10
<13,18,25> EC_SW I# 28 LANWAKEB 2 1
0_0603_5% LL2 1 2 1 2
ISOLATEB 26 27 +3V_LAN 0.1U_0402_16V4Z CL19
ISOLATEB DVDD33 CL18 CL17
DVDD33 39 1 2
2011.04.26 Change control signal to EC_SWI# 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL20
2 1
14 NC/SMBCLK AVDD33 12 +3V_LAN 1 2
15 42 0.1U_0402_16V4Z CL21
NC/SMBDATA AVDD33
+3V_LAN 1 RL22 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 1 2
48 0.1U_0402_16V4Z CL22
AVDD33
ENSW REG 33 ENSWREG
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG
35 VDDREG AVDD10 3 +LAN_VDD10
AVDD10 6
9 +3V_LAN +LAN_VDDREG
AVDD10
1 2 46 RSET AVDD10 45
RL5 2.49K_0402_1% 2 1
+3VS 24 36 +LAN_REGOUT 0_0603_5% LL3
GND REGOUT 1 2
49 PGND @
CL28 CL29
1
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 2
RL6 RTL8105E-VL-CGT_QFN48_6X6 2 1
1K_0402_1%
2
ISOLATEB
+3V_LAN
RL7 +3VS
15K_0402_5%
+3VALW TO +3V_LAN
2 1 RL4 @
@ CL33 0.01U_0402_16V7K 0_0402_5% +3VALW
2 1 +3VALW
@ CL34 0.01U_0402_16V7K
2
2 1 ENSW REG Vgs=-4.5V,Id=3A,Rds<97mohm
@ CL35 0.01U_0402_16V7K RL25
RL23 100K_0402_5% 2
0_0402_5% CL12
YL1
0.1U_0402_16V7K QL1
3
S
LAN_X1 2 1LAN_X2
1 G
<25> W OL_EN# 1 2 2
RL16 47K_0402_5%
25MHZ_20PF_7A25000012
1 1 1
D
1
CL14 AO3413_SOT23
CL26 CL27 0.01U_0402_25V7K +3V_LAN
27P_0402_50V8J 27P_0402_50V8J
2 2 2
1 1
3 3
CL15 CL8 1U_0402_6.3V4Z

4.7U_0805_10V4Z
@ 2 2
UL2
LAN_MDI1+ 1 16 RJ45_MIDI1+
LAN_MDI1- TD+ TX+ RJ45_MIDI1- JLAN1
2 TD- TX- 15
2 1 3 14 RL26 RJ45_MIDI1- 1
CL30 0.01U_0402_16V7K CT CT CL31 1 RJ45_MIDI1+ 1
4 NC NC 13 2 1000P_0402_50V7K 1 2 75_0402_1% 2 2
5 12 1 2 1 2 RJ45_GND 1 2 1000P_1808_3KV7K LANGND 3
NC NC CL32 1000P_0402_50V7K 75_0402_1% CL3 RJ45_MIDI0- 3
6 CT CT 11 4 4
LAN_MDI0+ 7 10 RJ45_MIDI0+ RL27 RJ45_MIDI0+ 5
LAN_MDI0- RD+ RX+ RJ45_MIDI0- @ 5
8 RD- RX- 9 1 6 6
3
2
CL23 7
D56 7
8
3
NS681680 8
AZC199-02SPR7G_SOT23-3 4.7U_0603_6.3V6K 9 GND1
2
10 GND2
1
ACES_88231-08001
1
CONN@
4
2011/04/18 Add D56 for ESD request 4

LAN RTL8105E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
A B C D
A B C D E
XD_CD#
SP1 XD_RDY SD_WP MS_CLK
SP2 XD_RE# MS_INS#
SP3 XD_CE# SD_D1
SP4 XD_CLE SD_D0 MS_D7
SP5 XD_ALE SD_D7 MS_D3
SP6 XD_WE# SD_CD#
SP7 XD_WP SD_D6 MS_D6
SP8 XD_D0 SD_CLK MS_D2
SP9 XD_D1 SD_D5 MS_D0
1 SP10 XD_D2 SD_CMD 1
SP14 XD_D6 MS_BS
XD_D7
+3VS_CR CC4 2 1 100P_0402_50V8J

UC1
RC7 1 2 6.2K_0603_1% RREF 1
R891 REFE
17 CR_LED#
GPIO0 CR_LED# <27>
+3VS 2 1 <12> USB20_N3 2 DM
3 24 XTLI 2 1
<12> USB20_P3 DP CLK_IN CLK_48M_CR <9>
0_0402_5% RC19
0_0805_5%
4 3V3_IN XD_D7 23 R556 C1073
+VCC_3IN1 5 48Mhz1
4.7U_0805_10V4Z
0.1U_0402_16V4Z
VREG CARD_3V3
1 2 6 V18 SP14 22 2 1 2
need 12 mil trace SD_DATA2
CC5
CC13
1 21
1U_0402_6.3V6K
SP13 SD_DATA3
CC8
7 XD_CD# SP12 20 33_0402_5% 22P_0402_50V8J
SP11 19
2 1 SDW P# SDCMD @ @
8 SP1 SP10 18
2
9 SP2 SP9 16
SD_DATA1 10 15 SD_MS_CLK RC11 1 2 33_0402_5% SDCLK
SP3 SP8
EPAD
SD_MS_DATA0 11 14
2 SP4 SP7 SDCD# 2
12 SP5 SP6 13
RTS5137-GR QFN 24P_4X4
25
2 in 1 Card Reader
JREAD1
SD_DATA3 1 SD-DAT3
SDCMD 2 SD-CMD
+VCC_3IN1 3 SD-GND
4 SD-VCC
0.1U_0402_16V4Z
3 SDCLK 3
2 5 SD-CLK
CB29
6 SD-GND
1 SD_MS_DATA0 7 SD-DAT0
SD_DATA1 8 SD-DAT1
SD_DATA2 9 SD-DAT2
SDCD# 10 12
DETECT GND1
SDW P# 11 13
PROTECT GND2
TAITW _PSDATA009GLBS1ZZ4H
CONN@
10_0402_5% 10P_0402_50V8J
SDCLK 1 2
@ RC18 @ CC15
4 4

Card reader RTL5137
Custom 0.3
QBU00
A B C D E
LPC_FRAME#_R 1 2 LPC_FRAME# +3VL
<18> LPC_FRAME#_R
0_0402_5% DEBUG@ R310
LPC_AD3_R 1 2 LPC_AD3 R613
<18> LPC_AD3_R +3V_EC
0_0402_5% DEBUG@ R311 2 1
LPC_AD2_R 1 2 LPC_AD2 0_0603_5%
<18> LPC_AD2_R +3VALW C679
0_0402_5% DEBUG@ R315 L49
LPC_AD1_R 1 2 LPC_AD1 @ R612 FBMA-L11-160808-800LMT_0603 0.1U_0402_16V4Z +3VL
<18> LPC_AD1_R
0_0402_5% DEBUG@ R316 2 1 +3V_EC 1 2 +EC_VCCA 1 2 ECAGND
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
LPC_AD0_R 1 2 LPC_AD0 0_0603_5%
<18> LPC_AD0_R
0_0402_5% DEBUG@ R317 1 1 1 1 2 2 R985 R986
C673
C674
C675
C676
C677
C678
1 2 1 2
0_0402_5% 0_0402_5%
2 2 2 2 1 1 @
CLK_PCI_LPC
111
125
22
33
96
67
U29
9
R302
@ 10_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
2
1
GATEA20 1 21 SM_SENSE#
<11> GATEA20 GATEA20/GPIO00 PWM0/GPIO0F SM_SENSE# <21>
C385 EC_KBRST# 2 23 EC_BEEP
<11> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM1/GPIO10 EC_BEEP <21>
@ 22P_0402_50V8J SERIRQ 3 PWM Output 26 EC_PWM_FAN Place closely pin 109
2 <11> SERIRQ SERIRQ# FANPWM0/GPIO12 EC_PWM_FAN <26> R243
LPC_FRAME# 4 27 ACOFF @ R329
<13> LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF <31>
LPC_AD3 5 +3VALW 1 2 1 2 LID_SW#
<13> LPC_AD3 LPC_AD3/LAD3
LPC_AD2 7 C682 2 1 100P_0402_50V8J ECAGND 0_0402_5%
<13> LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA R330 1
<13> LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA <30> 47K_0402_5%
LPC_AD0 10 64 +3VL 1 2
<13> LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
2011.04.26 Reserve GPIO to control LED LPC & MISC 65 ADP_I 0_0402_5% @ C525
ADP_I/AD2/GPI3A ADP_I <31>
CLK_PCI_LPC 12 66 ADP_V 0.1U_0402_16V4Z
+3V_EC <9> CLK_PCI_LPC CLK_PCI_EC/PCICLK AD3/GPI3B ADP_V <31> 2
R303 PCI_RST# 13 AD Input 75 USB_OC#0_1_EC
<11> PCI_RST# PCIRST#/GPIO05 AD4/GPI42 USB_OC#0_1_EC <19>
47K_0402_5% ECRST# 37 76
ECRST# EC_SCI# EC_RST#/ECRST# AD5/GPI43
2 1 <13> EC_SCI# 20 EC_SCI#/GPIO0E
<18,27> LED_WIMAX# 1 2LED_WIMAX#_EC 38
R987 0_0402_5% CLKRUN#/GPIO1D USB_CHG_EN#
2 1 DAC_BRIG/DA0/GPO3C 68 USB_CHG_EN# <19>
C387 0.1U_0402_16V4Z 70
EN_DFAN1/DA1/GPO3D IREF
#DVT EC to contral WWAN, DA Output IREF/DA2/GPO3E
71 IREF <31>
KSI0 55 72 CHGVADJ
KSO[0..15] WLAN and BT LED KSI1 56
KSI0/GPIO30 DA3/GPO3F CHGVADJ <31>
<26> KSO[0..15] KSI2 KSI1/GPIO31
57
KSI[0..7] KSI3 KSI2/GPIO32 EC_MUTE#
58 83 EC_MUTE# <21>
<26> KSI[0..7] KSI4 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN#
59 84 USB_EN# <19>
KSI5 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B THERM# 1
60 85 2 EC_THERM# <13>
KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C
confirm battery team change +5VALW to +3VALW KSI6 61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 R988 0_0402_5%
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <27>
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <27>
KSO1 40
+3V_EC KSO2 KSO1/GPIO21
41
KSO3 KSO2/GPIO22 VGATE
42 97 VGATE <9,13,28,34,35>
KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 WOL_EN#
43 98 WOL_EN# <23>
EC_SMB_CK1 KSO5 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 GPS_OFF#
KSO5/GPIO25 Int. K/B
44 99 GPS_OFF# <18>
R323 2.2K_0402_5% KSO6 ME_EN/SDIMOSI/GPXIOA02
45 109
EC_SMB_DA1 KSO7 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00
46
KSO7/GPIO27 SPI Device I/F
R314 2.2K_0402_5% KSO8 47
KSO9 KSO8/GPIO28 EC_SI_SPI_SO
48 119 EC_SI_SPI_SO <26>
KSO10 KSO9/GPIO29 SPIDI/MISO EC_SO_SPI_SI
49 120 EC_SO_SPI_SI <26>
KSO11 KSO10/GPIO2A SPIDO/MOSI EC_SPICLK
+3VS
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 EC_SPICLK <26>
KSO12 51 128 SPI_CS#
KSO12/GPIO2C SPICS# SPI_CS# <26>
KSO13 52
EC_SMB_CK2 KSO14 KSO13/GPIO2D
53
R308 2.2K_0402_5% KSO15 KSO14/GPIO2E ENBKL
54 KSO15/GPIO2F GPIO40 73 ENBKL <7>
EC_SMB_DA2 81 74 USB_OC#4_EC
KSO16/GPIO48 H_PECI/GPIO41 USB_OC#4_EC <19>
R309 2.2K_0402_5% 82 GPIO 89 FSTCHG
KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG <31>
90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# <27> +3V_EC
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <26>
EC_SMB_CK1 77 92 BATT_CHG_LOW_LED#
<30> EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <27>
For EC recommend 10/17 <30> EC_SMB_DA1
EC_SMB_DA1 78
EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55
93 PWR_ON_LED#
PWR_ON_LED# <27> 1 2
EC_SMB_CK2 79 95 SYSON 330K_0402_5% R307
<7> EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON <28,33>
01/06 Add HW board ID in EC pin16 EC_SMB_DA2 80 121 D21
<7> EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <35>
127 PM_SLP_S4# ACIN_D 2 1
AC_IN/GPIO59 PM_SLP_S4# <13> ACIN <13,31>
+3V_EC
SM Bus
PM_SLP_S3# 6 100 EC_RSMRST# Add D21 for AC-IN leakage issue
<13> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <13>
PM_SLP_S5# 14 101 EC_LID_OUT#
<13> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <13>
1
EC_SMI# 15 102
<13> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05
@R318 2 1 PCI_RST# HW_BOARD_ID 16 103 EC_SWI#
GPIO0A EC_SWI#/GPXIOA06 EC_SWI# <13,18,23>
10K_0402_5% C389 0.1U_0402_16V4Z 17 104 EC_PWROK
GPIO0B ICH_PWROK/GPXIOA07 EC_PWROK <13> +3VALW
WP 18 GPIO 105 BKOFF#_L BKOFF#_L <17>
GPIO0C BKOFF#/GPXIOA08 PBTN_OUT#
19 GPO RF_OFF#/GPXIOA09 106 PBTN_OUT# <13>
2
HW_BOARD_ID INVT_PWM SUS_PWR_DN_ACK/GPIO0D UWB_OFF# R5

2010.07.15 EMI request <17> INVT_PWM 25
INVT_PWM/PWM2/GPIO11 GPXIOA10
107 UWB_OFF# <18>
FAN_SPEED1 28 108 WL_OFF# WL_OFF# <18> 10K_0402_5%
<26> FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11
1
29 USB_OC#0_1_EC 2 1
R319 EC_TX_P80_DATA FANFB1/GPIO15
<18> EC_TX_P80_DATA 30
EC_RX_P80_CLK EC_TX/GPIO16 ACIN_D R6
10K_0402_5% <18> EC_RX_P80_CLK 31 110
EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 EC_ON 10K_0402_5%
32 112 EC_ON <27>
PWR_SUSP_LED# ON_OFF/GPIO18 ENBKL/GPXIOD02 ON/OFFBTN# USB_OC#4_EC
<27> PWR_SUSP_LED# 34 114 ON/OFFBTN# <27> 2 1
2
SUSP_LED#/GPIO19 EAPD/GPXIOD03 LID_SW#

36 NUM_LED#/GPIO1A GPI EC_THERM#/GPXIOD04 115 LID_SW# <27>
116 SUSP#
SUSP#/GPXIOD05 SUSP# <28,34>
@ R320 117
WP_R WP PBTN_OUT#/GPXIOD06
<26> WP_R 1 2 118
EC_PME#/GPXIOD07
122
0_0402_5% XCLK1 +EC_V18R
<13> EC_CLK 1 2 123 124
0_0402_5% R322 XCLK0 V18R
20mil
AGND
GND
GND
GND
GND
GND
1 C391
1
4.7U_0603_6.3V6K
BATT_TEMPA 1 2 RZ01 KB930QF-A1_LQFP128_14X14
11
24
35
94
113
69
C388 100P_0402_50V8J 100K_0402_5% @ CZ01 20mil

2 20P_0402_50V8J L50 TP_CLK
+5VS 1 2
ACIN_D 1 2 ECAGND 2 1 R595 4.7K_0402_5%
2
C390 100P_0402_50V8J FBMA-L11-160808-800LMT_0603 1 2 TP_DATA

R597 4.7K_0402_5%
+3V_EC
KSO1 1 2
@ R312 47K_0402_5%
KSO2 1 2
@ R313 47K_0402_5% 2010/06/27 2011/6/27 Title
KB926 D3
2011.08.29 Un-stuff R312,R313, KB930 dosen't need pull high Custom 0.3
QBU00
SPI Flash (1Mb*1)
+3V_EC
SPI ROM on PCH => 2M Byte

U22 +3V_EC
1
RF@
2011.06.07 Change U36 Footprint330P_0402_50V7K
C221 1 1 1
68P_0402_50V8J C503 C502 C411
2
1
+3VS +3VS 16M W25Q16CVSSIG SOIC 8P 1 R741 2 SPI_CS#_R 0.1U_0402_16V4Z
<25> SPI_CS# 2 2 2
@ R335 @ C321 R321 33_0402_5% U36
PCH_SPICLK 1 2 1 2 0_0402_5% 1 8 470P_0402_50V8J
CS# VCC
<25> EC_SI_SPI_SO 1 R338 2EC_SI_SPI_SO_R 2 SO HOLD# 7
R334 1 2 SPI_W P# 1 0_0402_5% 3 6 EC_SPICLK_R 1 R740 2 33_0402_5% EC_SPICLK <25>
2
3.3K_0402_5% 10_0402_5% 6P_0402_50V WP# SCLK EC_SO_SPI_SI_R 1 R739
4 GND SI 5 2 33_0402_5% EC_SO_SPI_SI <25>
C320
<25> W P_R
R336 1 2SPI_HOLD# 0.1U_0402_16V4Z MX25L1005AMC-12G_SO8
3.3K_0402_5% 2
U22 CONN@ 1
8 4 C501
VCC VSS
SPI_W P# 3 330P_0402_50V7K
W 2
SPI_HOLD# 7
R337 HOLD
PCH_SPI_CS# 1 2 1
<13> PCH_SPI_CS# S
15_0402_5%
PCH_SPICLK 6 R412
<13> PCH_SPICLK C
1 2 1 2 EC_SPICLK
PCH_SO_SPI_SI 5 2 SPI_SO_L R615 PCH_SI_SPI_SO PCH_SI_SPI_SO <13> 33_0402_5%
<13> PCH_SO_SPI_SI D Q 47_0402_5% C508 12P_0402_50V8J
W IESON G6179 8P SPI RF@ RF@
2011/04/15 Add BIOS ROM for non-share
KSI0 C414 1 2 100P_0402_50V8J
KSI1 C419 1 2 100P_0402_50V8J
KSI2 C416 1 2 100P_0402_50V8J

+5VS +3VS
KSI3 C418 1 2 100P_0402_50V8J
FAN Control Circuit
1
1
RF@
KEYBOARD KSI4 C422 1 2 100P_0402_50V8J
1
RF@ C223 KSI5 C424 1 2 100P_0402_50V8J
2
C222
68P_0402_50V8J
R332
10K_0402_5%
R887
10K_0402_5%
2
68P_0402_50V8J
CONN. KSI6 C426 1 2 100P_0402_50V8J
JFAN KSI[0..7] KSI7 C428 1 2 100P_0402_50V8J

KSI[0..7] <25>
2
1 1
R600 2 KSO[0..15] KSO0 C430 1 2 100P_0402_50V8J
<25> FAN_SPEED1 2 KSO[0..15] <25>
<25> EC_PW M_FAN 1 2 EC_PW M_FAN_R 3 3 KSO1 C432 1 100P_0402_50V8J
+5VS 4 4 2
10_0603_5%
1 5 JKB KSO2 C434 1 2 100P_0402_50V8J
GND1
6 GND2 1
C218 KSO3 C436 1 2 100P_0402_50V8J
ACES_88231-04001 2
68P_0402_50V8J 3 CAPS_LED# <25>
2 CONN@ R382 1
4 2 300_0402_5% +3VS
KSI1
5 KSI6
6 KSI5
7 KSI0 KSO4 C415 1 100P_0402_50V8J
8 2
KSI4
9 KSI3 KSO5 C420 1 100P_0402_50V8J
10 2
KSI2
11 KSI7 KSO6 C417 1 100P_0402_50V8J
12 2
KSO15
13 KSO12 KSO7 C421 1 100P_0402_50V8J
14 2
KSO11
15 KSO10 KSO8 C423 1 100P_0402_50V8J
16 2
KSO9
17 KSO8 KSO9 C425 1 100P_0402_50V8J
18 2
KSO13
19 KSO7 KSO10 C427 1 100P_0402_50V8J
20 2
KSO6
21 KSO14 KSO11 C429 1 100P_0402_50V8J
22 2
KSO5
23 KSO3 KSO12 C431 1 100P_0402_50V8J
24 2
KSO4
25 KSO0 KSO13 C433 1 100P_0402_50V8J
26 2
KSO1
27 KSO2 KSO14 C435 1 100P_0402_50V8J
28 2
29 KSO15 C437 1 100P_0402_50V8J
30 2
31 CAPS_LED# C461 1 100P_0402_50V8J
32 2
33
34
CONN@ ACES_88170-3400
Security Classification Compal Secret Data

SPI ROM//KB//FAN/Debug Poart
0.3
QBU00
A B C D E
Power Button +3V_EC Touch/B Connector

1/22 DVT:JTOUCH pin define reversal
2
+5VS
R324
100K_0402_5%
1
D24 JTOUCH
1
2 R325 R223
1 2 0_0402_5% 1 8
ON/OFFBTN#_R 1 ON/OFFBTN# <25> <25> LID_SW# 1 G2
0_0603_5% 2 7
2 G1
3 51_ON# <29> <25> TP_DATA 3 3
<25> TP_CLK 4
2
BAV70W_SOT323-3 4
5 5
1 1
2 6 6
2
E-T_7182K-F06N-00R
1
D C405
1 1U_0402_6.3V4Z
D26 CONN@ 2011.06.14 Add C406 for ESD issue
2 Q15 PJDLC05_SOT23-3
<25> EC_ON G C406
2
S 2N7002_SOT23 2 1
3
R327
10K_0402_5% 1U_0402_6.3V4Z
1
1
JPOWER
1
1
2
2
ON/OFFBTN#_R R415 1 2
2 FBMA-10-100505-151T 3 R331
3
4 4
0.1U_0402_16V4Z
0_0402_5%
2
180P_0402_50V8J
1
GND
3
2
PJSOT24C_SOT23-3
2 D27 6 @ R333 C407

@ @ GND
1 2 1
C538
C505
JOINT_F1017WR-S-04P 0_0402_5%
CONN@ 1U_0402_6.3V4Z
1
1 @
2
2011.08.29 Add C407 for ESD issue
1
+3VALW
+3VL
2 2
LED Conn
+5VS 1
JLED
1
ISPD
+5VALW 2 2
3 CRT@ PCB1
<25> BATT_CHG_LOW_LED# 3
<25> BATT_FULL_LED# 4 4
<25> PWR_SUSP_LED# 5
5
<25> PWR_ON_LED#
<18,25> LED_WIMAX#
6
7
6
7
PCB
8
SATALED#_R 8 PCB LA-6858P_CRT
9
9
10
10
11 GND
12
GND
P-TWO_161021-10021 HDMI@ PCB2
CONN@
PCB
PCB LA-6859P_HDMI
D50
2 1 CR_LED# <24>
3 CH751H-40PT_SOD323-2 3
D51
SATALED#_R 2 1 SATALED# <11>
4 4

ON/OFF /TP Conn/LEDS
Custom 0.3
QBU00
Date: Friday, November 04, 2011 Sheet 27 of 38
A B C D E
A B C D E
+3VALW TO +3VS +5VALW TO +5VS

+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
SI7326DN-T1-E3_PAK1212-8 1 1 SI7326DN-T1-E3_PAK1212-8 1 1
Q18 Q19
C439 C440 C441 C442
470_0805_5%
470_0805_5%
1 1
2
2 1U_0402_6.3V4Z 4.7U_0805_10V4Z 2 1U_0402_6.3V4Z 4.7U_0805_10V4Z
2 2 2 2 R343
1 5 3 5 3 1
R342
0.1U_0402_16V4Z
1 R344 2 +VSB 1 R346 2 +VSB

4
3 1
3 1
@1 1 1 47K_0402_5% 1 1 47K_0402_5%
0.01U_0402_25V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
6
6
C447
0.022U_0402_16V7K
1
C529 C446 C448 C449 R349 Q7A
R348 Q6A Q6B 200K_0402_5% Q7B
2 2 2 SUSP 2 2 @ SUSP
2 5 2 5
330K_0402_5% 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
4
4/2 MP:For EMI ESD solution
+3VS TO +3VS_PRIME
+3VS +3VS_PRIME
@ +5VALW
R977 1 2 0_0805_5% +5VALW
SI7326DN-T1-E3_PAK1212-8
2
Q20
1 R362 R978
2 100K_0402_5% 100K_0402_5%
2
10U_0805_10V6K
1U_0402_6.3V4Z
5 3 1 1
1 R979
1
2 C1122 C1123 470_0603_5% SYSON# 2
<6> SYSON#
C1121 @ VGATE#
4
10U_0805_10V6K 2 2
1 1
6
2
D Q28B
2 SUSP Q45A
G SYSON 5 2N7002DW -T/R7_SOT363-6 2
<25,33> SYSON <9,13,25,34,35> VGATE
2
S Q44
3
+VSB 1 R186 2 2N7002_SOT23-3 2N7002DW -T/R7_SOT363-6
1
@ R402
47K_0402_1% 1 10K_0402_5%
3
C1124
1
Q45B
0.1U_0402_25V7K~D
VGATE# 2
5
2N7002DW -T/R7_SOT363-6
4
+5VALW
+1.5V TO +1.5VS
2
+GFX_CORE +1.5VS +1.8VS

R361 +1.5V +1.5VS
470_0603_5%
2
3 @ R603 R363@ R604@ 3

1
470_0603_5% 470_0603_5% 470_0603_5% SI7326DN-T1-E3_PAK1212-8 1 2

SUSP Q33 C1059
<33> SUSP
1 C1060
1
1
6
2 10U_0805_10V4Z
2 1
5 3
6
Q28A
2 @ Q25B @ Q31B 1U_0402_6.3V4Z
<25,34> SUSP#
@Q31A 1
4.7U_0805_10V4Z
4
2
2N7002DW -T/R7_SOT363-6 2 SUSP 5 SUSP 5 SUSP

1
C1061
R401 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
1
10K_0402_5% 2
1 R605 2 +VSB
47K_0402_5%
200K_0402_5%
1
1
+3VALW
1
R606 C1062
2
0.01U_0402_25V7K
2 R607
2
10K_0402_5%
3
2011.06.14 Add C1128 for ESD issue
1
+0.75VS +1.5V +1.05VS
5
Q35B
2
6
@ @ 2N7002DW -T/R7_SOT363-6
4
1 R366 R367 R365@
C1128 470_0603_5% 470_0603_5% 1 470_0603_5% 1
4
@ @ Q35A 2 SUSP# 4
0.1U_0402_25V7K~D C533 C532
6 1
2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2N7002DW -T/R7_SOT363-6
1
2 2
D
1
@Q25A
D
1
SUSP @ Q26 2SYSON#

2
G @ Q24 2 SUSP Security Classification Compal Secret Data Compal Electronics, Inc.
2N7002DW -T/R7_SOT363-6 2N7002_SOT23 S G 2009/04/07 2012/10/21 Title
1
2N7002_SOT23 S
DC INTERFACE
3
Custom 0.3
QBU00
A B C D E
A B C D
VIN
PL1
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
PJP1 5A_32V_S1206-H-5.0A
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1
+
PC4
PC1
PC2
PC3
1 1
2
-
@ SINGA_2DW -0005-B03
VIN
2
PD3
RLS4148_LL34-2
1
1
1
PQ4 PR8 PR9
68_1206_5% 68_1206_5%
BSS84_SOT23-3
2
PD4
2 1 N1 3 1
BATT+ VS
2 2
RLS4148_LL34-2
1
PR10 PC6
1
100K_0402_1% 0.22U_0603_25V7K PC5
2
0.1U_0603_25V7K
2
2
PR11
<27> 51_ON# 1 2
22K_0402_1%
PJ332 PJ152
+3VALW P 2 2 1 1 +3VALW +1.5VP 2 2 1 1 +1.5V
@ JUMP_43X118 @ JUMP_43X118
(6.11A,250mils ,Via NO.= 12) (4.65A,200mils ,Via NO.= 10)
PJ352 PJ402
+5VALW P 2 2 1 1 +5VALW +1.05VSP 2 2 1 1 +1.05VS
3 3
@ JUMP_43X118 @ JUMP_43X118
(5.3A,220mils ,Via NO.= 11) (1.8A,80mils ,Via NO.=4)
PJ182
PJ5 2 1
+1.8VSP 2 1 +1.8VS
+VSBP 2 1 +VSB
2 1
@ JUMP_43X118
@ JUMP_43X39
(0.15A,40mils ,Via NO.= 1)
(120mA,40mils ,Via NO.= 1)
PJ75
+0.75VSP 2 2 1 1 +0.75VS
@ JUMP_43X79
(0.5A,40mils ,Via NO.= 1)
4 PJ331 4
+3VLP 2 2 1 1 +3VL
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)

DCIN & DETECTOR
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cedar trail 0.3
A B C D
A B C D
1
VMB 1
PL2 PH1 under CPU botten side :

PJP2 PF2 SMB3025500YA_2P
9 9 BATT_S1 1 2 1 2 BATT+
CPU thermal protection at 95 degree C
8
8
7 7 7A_32V_TR/3216FF7-R Recovery at 56 degree C
6 BATT_P4
6 BATT_P5
5 5
EC_SMDA
1
10 GND 4 4
11 3 EC_SMCA PC7 PC8
1
GND 3 0.01U_0402_25V7K
2 1000P_0402_50V7K
2 PR14
2
1 1
1K_0402_1%
@ SUYIN_200045MR009G171ZR
2
PD6
VL
1
PJSOT24C_SOT23-3
1
PD5 2
PJSOT24C_SOT23-3 1
PR15
3
1
PR16 19.6K_0402_1%
6.49K_0402_1% PC9
3
2
2 1 0.1U_0402_25V6
2
+3VL
2
PR18
1
8.66K_0402_1%
PR19 PU1
1
2 2
1 8
1
1K_0402_1% VCC TMSNS1
PH1
2 7
2
GND RHYST1
2
100K_0402_1%_NCP15W F104F03RC
PR20 PR21 BATT_TEMPA <25> 3 6
2
OT1 TMSNS2
100_0402_1% 100_0402_1%
4 OT2 RHYST2 5
<32> VS_ON
1
G718TM1U_SOT23-8
EC_SMB_DA1 <25>
EC_SMB_CK1 <25>
PQ5
BSS84_SOT23-3
B+ 3 1 +VSBP
3 3
0.22U_0603_25V7K
100K_0402_1%
1
PC10
1
1
PR23
PC11 @
VL @ 0.1U_0603_25V7K
2
2
2
PR24
2
1 2
PR25 22K_0402_1%
100K_0402_1%
1
D
PR26
1 2 2 PQ6
<13,32> POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1
@ PC12
.1U_0402_16V7K
2
4 4

BATTERY CONN / OTP
A B C D
A B C D
10U_1206_25V6M
10U_1206_25V6M
PC228 47P_0402_50V8J
1
1
PC209
PC227
PR215
B+ CHG_B+
P2 PQ204 P3 0.05_1206_1% PQ207
PD203
2
AO4407A_SO8 PL201 AO4435_SO8
VIN 2 1 1 8 1 4 2 1 1 8
2 7 PC225 PC226 1.2UH_1231AS-H-1R2N=P3_2.9A_30% 2 7
3 6 2 3 CSIN 3 6
B340A_SMA2
5 0.1U_0402_25V6 5
10U_1206_25V6M
2200P_0402_50V7K
PC224 47P_0402_50V8J
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
CSIP
0.1U_0402_25V6
4
4
1
1
1 1
1
PC231
PC232
1
PC233
PC208
PC222
PC207
VIN
2
PC211 PR236
1 2
2
VIN
2
1
2
5600P_0402_25V7K
2
47K_0402_1%
1
1
2
0.1U_0603_25V7K
6251VDD
PR210
200K_0402_1% PR212 PR226 PR237
2
ACSETIN
PC210
200K_0402_1% 191K_0402_1% 10K_0402_1%
2
2.2U_0603_6.3V6K
PD201
1
RB751V-40_SOD323-2 ACSETIN
1000P_0402_25V8J
1
PC212
1 1
3
1
1
PC217
47K
2
PR228
PR227 14.3K_0402_1%
2 47K
2
PR216 10_1206_5%
2
PQ210 10K_0402_1%
2
<25> FSTCHG 2 1 PU200
1
1
PDTA144EU_SOT323-3 PC218
1 24 DCIN 2 1
1
VDD DCIN
1
1
0.1U_0603_25V7K
PR213 PR217 PQ215
BATT_ON 2 2 23 ACPRN 2
PQ211 150K_0402_1% 100K_0402_1% ACSET ACPRN DTC115EUA_SC70-3
DTC115EUA_SC70-3 PR229 20_0402_5%
2
2
6251_EN 3 22 1 2 CSON
6
D EN CSON
1
PC219 PQ201
3
3
5
2 0.047U_0402_16V7K
AON7408L_DFN8-5
G PR238
4 21 1 2 CSOP
1
CELLS CSOP 100K_0402_1%
PR230 20_0402_5%
S PQ212A PC213
1
2
2 DMN66D0LDW -7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5% 2
ICOMP CSIN
2
PC220 4
PQ212B PC214 PR218 6800P_0402_25V7K BATT_ON
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 19 1 2
1
VCOMP CSIP PL202
3
D
PR232 2_0402_5%
5 0.01U_0402_25V7K
10K_0402_1%
PR219 10UH_MPL73-100_3A_20% PR235 BATT+
3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG 1 4
<25> ADP_I ICM PHASE
47K_0402_1%
1
5
S PC215 PQ202 2 3
4
PR211 1 2 6251VREF 8 17 DH_CHG

47K_0402_1% PR220 VREF UGATE PR206
0.02_1206_1%
AON7408L_DFN8-5
PACIN 309K_0402_1% PC205 4.7_1206_5%
10U_1206_25V6M
10U_1206_25V6M
1 2 .1U_0402_16V7K PR205
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
2200P_0402_50V7K
<25> IREF
2
CHLIM BOOT
0.1U_0402_25V6
0_0603_5% 4
1
1
0.01U_0402_25V7K
1
0.1U_0603_25V7K
1
PC202
PC203
PC204
PR222
PC229
PD202
1
1
6251VREF
1 2 6251aclim 10 15 6251VDDP PC206
ACLIM VDDP
1
PQ213 RB751V-40_SOD323-2
PC216
2
24.9K_0402_1%
2
680P_0603_50V7K
2
DTC115EUA_SC70-3 PR221 1 2 6251VDD
2
3
2
1
ACOFF 2 100K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
<25> ACOFF
2
VADJ LGATE
1
2
2
PC221
PR223 12 13 4.7U_0603_6.3V6M
1
GND PGND
20K_0402_1%
3
ISL6251AHAZ-T_QSOP24
CP mode PR224
<25> CHGVADJ 1 2
3 Iada=0~1.579A(30W) CP= 92%*Iada; CP=1.45A 15.4K_0402_1% 3
2
Vaclim=1.08132V(30W) PR70=53.6k PR216=0.05

PR225
31.6K_0402_1%
VIN
1
6251VDD
CC=0.25A~2A CHGVADJ=(Vcell-4)*9.455
IREF=1.636*Icharge Vcell CHGVADJ
IREF=0.409V~3.272V 4V 0V
1
PR241
1
VCHLIM need over 95mV 4.2V 1.898V 10K_0402_1% PR246

PR240 1 2
- 4.35V 3.309V 47K_0402_1% PR242 ACIN <13,25> 309K_0402_1%
10K_0402_1% PR247
2
10K_0402_1%
2
Ki PACIN 1 2 ADP_V <25>

Vchlim=Iref*(PR221/(PR220+PR221))
1
=Iref*(100K/(309K+100K))
1
PQ214
Vin Detector
1
=Iref*0.2444 DTC115EUA_SC70-3 PR248 PC223
1
Ichanrge=(165mV/PR235)*(Vchlim/3.3V) 47K_0402_1% .1U_0402_16V7K

=(165m/20m)*(1/3.3V)*Iref*0.5537 ACPRN 2 PR243
2
=0.611*Iref 14.3K_0402_1% High 18.089V
2
Iref=1.636*Ichanrge =>Ki=1.636 Low 17.44V
2
3
Kv
4
Rinternal ic=514K Rec=3K R1=PR224=15.4K R2=PR225=31.6K 4
R=514K//31.6K//(15.4K+3k)=11.372K
r=514K//514K//31.6K=28.14K
Vcell=0.175*Vadj+3.99v
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K))
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 Security Classification Compal Secret Data Compal Electronics, Inc.
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv Issued Date 2010/01/25 Deciphered Date 2009/04/28 Title
A=Vref*(R/(R+514K))=0.052 CHARGER
Kv=9.455 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Cedar trail 0.3
A B C D
5 4 3 2 1
2VREF_6182
D D
1
PC363
1U_0402_6.3V6K
2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2
PR363 PR365
UP6182_B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 UP6182_B+
PL331
HCB2012KF-121T50_0805
ENTRIP1
ENTRIP2
B+ 1 2 +3VLP PR337 PR357
2200P_0402_50V7K
120K_0402_1% 120K_0402_1%
10U_1206_25V6M
1 2 1 2
PC374 0.1U_0402_25V6
47P_0402_50V8J
10U_1206_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
1
1
PC372
PC366
PC368
1
4.7U_0603_6.3V6K
5
5
PU330
2
1
PQ331 PQ351
PC361
2
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
AON7408L_DFN8-5
2
C C
25
2
P PAD
PC375
PC367
PC360
4 4
7 VO2 VO1 24 POK <13,30>
PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AON7408L_DFN8-5
1
2
3
3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 0_0603_5% 0_0603_5% PL352
UG_3V 10 21 UG_5V
4.7UH_FDVE0630-H-4R7M=P3_5.5A_20% UGATE2 UGATE1 4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 PHASE2 PHASE1 20 1 2
5
5
1
1
PQ332 LG_3V 12 19 LG_5V PQ352
LGATE2 LGATE1
S CER CAP 0.1U 25V K X5R 0402

SKIPSEL
PR336
2200P_0402_50V7K
PR356
VREG5
150U_B2_6.3VM_R35M
4.7_1206_5% 4.7_1206_5%
0.1U_0402_25V6
1 1
GND
VIN
RT8205EGQW _W QFN24_4X4
NC
1
EN
PC373
1
4 4
1
2
+ +
PC369
PC332
PC352
PC371
PR360
13
14
15
16
17
18
1
1
499K_0402_1%
2
150U_B2_6.3VM_R35M
2
2
2 PC336 PC356 2
AON7702L_DFN8-5 1 2 AON7702L_DFN8-5
B+
1
2
3
3
2
1
680P_0603_50V7K 680P_0603_50V7K
2
2
Ipeak=6.11A
1
100K_0402_5%
Imax=4.277A
1
VL
PR361
PC362
F=375KHz
1
1U_0402_6.3V6K
PC364
2
B Total Capacitor 150uF, 4.7U_0603_6.3V6K
B
2
ESR 35mohm ENTRIP1 ENTRIP2 UP6182_B+ Ipeak=5.3A
2
Imax=3.71A
D F=300KHz
6
D
3
PQ360A
2 5 Total Capacitor 150uF,
G G PQ360B
ESR 35mohm
1
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 PC365
S S
2VREF_6182
1
0.1U_0603_25V7K
2
PR370
VL 2 1
100K_0402_1%
1
<30> VS_ON PQ361

DTC115EUA_SC70-3
PR371
VS 1 2 2
100K_0402_1%
42.2K_0402_1%
1
1
PR372
@ PC370
0.1U_0402_16V4Z
2
2
A A

+3VALWP/+5VALWP
5 4 3 2 1
A B C D
1 1
PL151
HCB2012KF-121T50_0805
1.5_B+ 1 2 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V6
2200P_0402_50V7K
0.1U_0402_25V6
1
1
1
1
1
PC163
PC168
PC164
PC165
5
PC169
PQ151
2
2
2
2
PR164
255K_0402_1%
4
1 2
PR160
<25,28> SYSON 1 2 PR155
BST_1.5V 1 2 AON7408L_DFN8-5
0_0402_5%
3
2
1
0_0603_5%
1
PL152
15
14
PC160 @
1
PU150 PC155 S COIL 2.2UH +-20% PCMC063T-2R2MN 8A
.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP
EN/DEM
NC
BOOT
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON UGATE
2200P_0402_50V7K
3 12 LX_1.5V Ipeak=4.65A
VOUT PHASE
220U_B2_2.5VM_R25M
PR161 PR157
PQ152 PR156 Imax=3.255A
0.1U_0402_25V6
+5VALW 1 2 4 VDD CS 11 1 2 +5VALW 1
VFB=0.75V 4.7_1206_5%
1
1
100_0603_5% 7.87K_0402_1% F=313KHz
PC152
+
PC167
5 FB VDDP 10
2
Total Capacitor 220uF, 2
2
1
2
DL_1.5V
2
PC161 6 9 4
<6> SM_PW ROK PGOOD LGATE ESR 25mohm
PGND
2
GND
4.7U_0603_6.3V6K
PC170
AON7702L_DFN8-5
2
1
1 PC162 PC156
RT8209MGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K 680P_0603_50V7K
3
2
1
2
PR165
10K_0402_1%
2
+1.5VP
PR162
1 2
10K_0402_1%
1
PR163
10K_0402_1%
2
3
+1.5V 3
1
PJ76
1
JUMP_43X79
@
2
2
PU75
1 VIN VCNTL 6 +3VALW
PC260 2 5
GND NC
2
4.7U_0805_6.3V6K
1
3 7 PC261
PR261 VREF NC
1
1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
9
2
TP
G2992F1U_SO8
PR262
.1U_0402_16V7K
+0.75VSP
1
0_0402_5% D
SSM3K7002FU_SC70-3
PQ261
PC263
1K_0402_1%
1 2 2
<28> SUSP
1
G
2
S PR263 PC264
3
1
10U_0603_6.3V6M
2
PC262
.1U_0402_16V7K
2
4 4
For shortage changed

+1.5VP/+0.75VSP
A B C D
A B C D
1 1
+3VALW +5VALW
1
PJ181
@ JUMP_43X39
1
2
1U_0603_10V6K
PC181
2
2
2 2
1
PC182
2
4.7U_0805_25V6-K
PU180
6 VCNTL
5 VIN VOUT 3 +1.8VSP
PR184 9 4
VIN VOUT
1
0_0402_5%
0.01U_0402_25V7K
1
PC183
<9,13,25,28,35> VGATE 1 2 8 EN PR182
22U_0805_6.3V6M
7 2
GND
POK FB
1
3K_0402_1%
2
1
PC184
@ PC185
2
APL5930KAI-TRG_SO8
2
0.47U_0402_6.3V6K
1
PR183
2.4K_0402_1%
2
3 3
PU400
SY8033BDBC_DFN10_3X3 PL400
4
@ PJ400 1UH_PCMC063T-1R0MN_11A_20%
+5VALW 2 1 10 2 LX_1.05V 1 2 +1.05VSP Ipeak=1.8A
PG
2 1 PVIN LX
JUMP_43X39 ILIM = 1.26A
68P_0402_50V8J
9 PVIN LX 3
1
F=1MHz
1
1
4.7_1206_5%
PC402
PC405 8 SVIN
Total Capacitor330uF,9mohm
PR403
22U_0805_6.3V6M PR404
6 10K_0402_1%
22U_0805_6.3V6M
22U_0805_6.3V6M
2
2
FB
5
2
EN
1
NC
NC
TP
PC404
PC403
2
FB=0.6Volt FB_1.05V
11
2
PR402
1
680P_0603_50V7K
<25,28> SUSP# 1 2 EN_1.05V
1
PC406
0_0402_5% PR405
13.7K_0402_1%
1
2
1
@ PR401 PC401@
2
499K_0402_1% 0.1U_0402_10V7K
2
2
Pin 1 define same with Pin 2 & Pin 3 that just for SY8035 ,
4
SY8035 is for 5A loading , let LX shape can bigger!! 4

+1.8VSP/+1.05VSP
A B C D
A B C D E F G H
+CPU_CORE
1
@ PR528 PR526 @
100_0402_5% 100_0402_5%
2
<8> VSSSENSE VCCSENSE <8>
1
PR529 PR527
+5VALW 0_0402_5% 0_0402_5%
1 1
2
1
PR525
2.2_0402_1%
1
VCC
2
VCC PR530 PC511
1
0_0402_5% PL501
1
PR540 PR520 PR521 PR522 PR523 100P_0402_50V8J PR537 PR538 +CPU_B+ HCB2012KF-121T50_0805
PC512 130K_0402_1% 4.7_0402_1%
249K_0402_1%
10U_0805_25V6K
10U_0805_25V6K
2
2
2.2U_0603_10V6K
51K_0402_1%
10K_0402_1%
10K_0402_1%
1 2 1 2 1 2
240K_0402_1%
1 B+
68U_25V_M
0.1U_0402_25V6
2
2
+
PC549
PC536
PC552
PC550
1
PR535
1
PC566 2
9.1K_0402_1%
RNTC1N
2
SETINIA 0.1U_0402_25V6
5
SETINI
RNTC1P
2
TEMPMAX PR505 PC505
0_0603_5% 0.22U_0603_10V7K PQ501
ICCMAX 1 2 1 2 4 AON7408L_DFN8-5
ICCMAXA +CPU_CORE
PL502
1
1
PR599 PR598 PR517 PR518 PR519 1UH_PCMC063T-1R0MN_11A_20%
3
2
1
1
@ @
33K_0402_1%
1 2
2.2K_0402_1%
5.1K_0402_1%
0_0402_5% PR536
0_0402_5%
1
39K_0402_1%
Ipeak=4.234A
2
2
PR506 PH505 @ Imax=2.9638A
2
PC502 4.7_1206_5% 10K_0402_1%_ERTJ0EG103FA
F=313KHz
2
VCC RNTC1N1 2RNTC1P
33P_0402_50V8J
1 2
4 PR541 Total Capacitor 660uF,
3.65K_0402_1%
ESR 4.5mohm
2
10K_0402_1%_ERTJ0EG103FA PQ502
10K_0402_1%_ERTJ0EG103FA
AON7702L_DFN8-5 PC506 PR543 @ PR542 @
1
680P_0603_50V7K 0_0402_5% 0_0402_5%
10K_0402_1%
3
2
1
2
1
PR544 1.69K_0402_1%PR545 0_0402_5%
1
2
1
2 10K_0402_1% PR587 1 2 1 2 2
PH503
PH502
VCC PC534
PR586
1 2
0.1U_0402_25V6
1
2
PR546 @ 0.1U_0402_25V6
1
10K_0402_1%
10K_0402_1%
1 2
1
PR539
PC544
10
2
9
1
PU500
1
560_0402_1%
0.1U_0402_25V6
SETINIA
GFXPS2
FB
COMP
ISEN1P
BOOT1
VCC
RGND
ISEN1N
TONSET
2
2
PC530 PR588
1
PC535
560_0402_1%
0.1U_0402_25V6
2
PR589
1
41
2
GND
1
1
11 40 PC513
2
SETINI UGATE1 +5VALW

12 39
2.2U_0603_10V6K
2
TMPMAX PHASE1
1 2
PR582 OCSET 13 38 PR547
PR584 0_0402_5% 35.7K_0402_1% ICCMAX LGATE1 0_0603_5%
VCC 1 2 1 2 14 37
ICCMAXA PVCC PVCC
15 36
1
PH501 TSEN LGATEA

10K_0402_1%
1 2 16 RT8165BGQW_WQFN40_5X5 35
PR580 OCSET PHASEA
VR_ON <25>
@ 10K_0402_1%_ERTJ0EG103FA 17 34
TSENA UGATEA
2
18 33
OCSETA BOOTA PR550 0_0402_5% +CPU_B+
PR583 OCSETA 19 32 1 2 PR552 PR553
PR585 10K_0402_1% 35.7K_0402_1% IBIAS EN 130K_0402_1% 2.2_0402_1%
1
VCC 1 2 1 2 PR590 20 31 1 2 1 2 PC537
10U_0805_25V6K
10U_0805_25V6K
VRHOT TONSETA
53.6K_0402_1%
0.1U_0402_25V6
1
5
PH500
10K_0402_1%
2
VRA_READY
PR581 PC545
PC546
PC548
1 2
VR_READY
0.1U_0402_25V6
2
2
ISENAN
COMPA
ISENAP
RGNDA
@ 10K_0402_1%_ERTJ0EG103FA PC515
ALERT
1
VCLK
0.22U_0603_10V7K
VDIO
FBA
2
1 2 1 2 4
1
PC539 PR515 0_0603_5%
3 PR576 75_0402_1% PQ503 3
21
22
23
24
25
26
27
28
29
30
1 2 VR_HOT 0.1U_0402_25V6 AON7408L_DFN8-5
+1.05VS VR_HOT <7>
2
PL503 +GFX_CORE
3
2
1
PR574 10K_0402_1% 2.2UH_PCMC063T-2R2MN_8A_20%
1 2 VGATE 1 2
+3VS
GFXPG
5
PR575 @ 10K_0402_1% SVID_ALERT#
1 2 SVID_DATA
1
SVID_CLK
PR577 150_0402_1% PH504 @
Ipeak=1.94A
+1.05VS 1 2 PR516 10K_0402_1%_ERTJ0EG103FA Imax=1.358A
2
4 4.7_1206_5% RNTCAP1 2RNTCAN
PR578 130_0402_1% PR556
F=313KHz
1 2
1
2
1 2 10K_0402_1% Total Capacitor 660uF,
1
PC565 PQ504 PR559 @ PR560 @

PR573 27P_0402_50V8J AON7702L_DFN8-5 PC516 0_0402_5% 0_0402_5% ESR 7.5mohm
2
3
2
1
1
680P_0603_50V7K
43K_0402_1%
1 2
1
1
@ PC540 PR579 130_0402_1% PR557 2K_0402_1% PR558 0_0402_5%

2
1 2 1 2
0.1U_0402_25V6
RNTCAN
RNTCAP
2
PC538
<7> SVID_ALERT# 0.1U_0402_25V6
1 2
<7> SVID_DATA PR561 0_0402_5%
1
PR572 1 2
9.1K_0402_1%
<7> SVID_CLK
1
PC541 PR562 @ 0_0402_5%
0.1U_0402_25V6 1 2 VCC
2
2
<9,13,25,28,34> VGATE
1
PR567
0_0402_5%
PC514
2
100P_0402_50V8J
2
1
4 4
PR570 PR568
0_0402_5% 0_0402_5%
2
<8> VSS_GFXSENSE VCC_GFXSENSE <8>

1
@ PR571 PR569 @
10_0402_5% 10_0402_5%
Compal Electronics, Inc.

2
Security Classification Compal Secret Data

+GFX_CORE
CPU GPU CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A2 Cedar trail 0.3
A B C D E F G H
5 4 3 2 1
PIR (Product Improve Record)

QBU00 LA-6858P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
01. 04/ 26 06 Delete C948,C949,C950,C951 ES2 CPU only support 2 pairs DMI
D
02. 04/ 26 06 Add DDR_A_MA15 signal in CPU side Cedar Trail platform supports MA0-MA15 total sixteen address signals D
03. 04/ 26 07 Reserve 0 ohm for DDC_SCL / SDA , HPD, BREF1P5V, BREFREXT connect to GND. Follow Intel V1.0 check list to disable HDMI
04. 04/ 26 07 Add CRT DAC,SYNC signals and add RV155,RV156,RV157 150 ohm pull down resistor for CRT DAC signal. Follow Intel V1.0 check list to enable RGB I/F
05. 04/ 26 08 Reserve 0 ohm for VCCADP / VCCADP_SFR connect to GND Follow Intel V1.0 check list to disable HDMI
06. 04/ 26 08 Add R1004,C166 for +VCCDIO / R535,C1125 for +VCC_CRT_DAC Follow Intel V1.0 check list to enable RGB I/F
07. 04/ 26 10 Add MA15 signal for SODIMM connector Cedar Trail platform supports MA0-MA15 total sixteen address signals
08. 04/ 26 11 Stuff R544 System will change to non-share ROM design, PCH STRAP2/1 will be 01
09. 04/ 26 12 Change PCIe port arrangement Follow BIOS team's request to re-arrang PCIe port for power saving.
10. 04/ 26 13 Use BOM option for R931,R932,R933,R934 Follow Intel V1.0 check list to disable HDMI
11. 04/ 26 13 Add J2 and C1087 for PCH GPIO12 BIOS will use GPIO12 for clean password function.
12. 04/ 26 13 Add R566,R567,R618 10K pull high resistors for PCH SPI I/F System will change to non-share ROM design
13. 04/ 26 15 Add CRT circuit Follow Intel PDG and V1.0 check list to implement CRT circuit
14. 04/ 26 19 Change USB charger(US1) solution to MAX14566B Follow A51 common design
15. 04/ 26 19 Reserve US2 bus switch Support BIOS team's new debug card.
16. 04/ 26 19 Change US4 USB power switch to 2A Support USB charge V1.1 SPEC--->support 1.8A
17. 04/ 26 23 Change LOM_WAKE# control signal to EC_SWI# LOM WAKE# will connect to PCH directly and change net name to "EC_SWI#"
C
18. 04/ 26 25 Change KBC to KB930/KB9012 Follow EC team KB930/KB9012 common design C
19. 04/ 26 26 Add U22 -->2MB SPI ROM System will change to non-share ROM design
20. 04/ 28 18 Reserve 0 ohm and test points in JGPS pin1/3/5/44/46/51 Cougar 2.0 will support new 3G/LTE module
21. 04/ 29 25 Delete C211,C212,C216,C217 RF team has no necessity
22. 04/ 29 07 Delete 220p caps for sideband signals. EMC team has no necessity
23. 04/ 29 09 Delete C940,C941 RF team has no necessity
24. 04/ 29 09 Delete C1067,C1066 RF team has no necessity
25. 04/ 29 09 Reserve R305,C392 for SMBus_CLK Reserve R-C for RF team's requirement
26. 04/ 29 17 Delete C227,C228,C290,C230,C231,C232,C1074,C1075 RF team has no necessity
27. 04/ 29 18 Delete C307,C298,C297 RF team has no necessity
28. 05/ 03 07 Add R984 0 ohm resistor for XDP pin17 Reserve 0 ohm for XDP when XDP connector no use.
29. 05/ 04 16 Change Q42,Q43 to dual package Save layout space and cost
30. 05/ 06 07 Add R989 (0 ohm) for XDP signal Reserve 0 ohm for XDP when XDP connector no use.
31. 05/ 10 15 Delete D53,F1,C1110 Share 5V with CRT circuit.
32. 05/ 10 07 Change XDP un-define net name Follow naming rule
B
QBU00 LA-6858P SCHEMATIC CHANGE LIST B

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
01. 06/ 07 07 Remove XDP connector XDP debug port is no necessary in PVT
02. 06/ 07 08 Keep +VCCADP_1.05, +VCCADP_SFR power rail even disable DDI interface Intel correct their DDI disable guideline
03. 06/ 07 26 Change U36 Symbol and footprint Fix DFB issue
04. 06/ 10 13 Change J1 to JCMOS, J2 to JPW Follow A51 jumper naming rule
05. 06/ 10 19 Remove US2 USB bus switch PVT won't reserve USB debug port
06. 06/ 14 08 Stuff 1u (C1007,C1008,C1009) on GFX_CORE To solve ESD issue
07. 06/ 14 28 Add 0.1u (C1128) on +0.75VS power rail To solve ESD issue
08. 06/ 14 10 Add 0.1u (C116) on +0.75VS power rail To solve ESD issue
09. 06/ 14 10 Add 0.1u (C119) on +1.5V power rail To solve ESD issue
10. 06/ 14 10 Add 0.1u (C406) on +1.5V power rail To solve ESD issue
11. 06/ 14 27 Add 1u (C406) on touch pad power rail To solve ESD issue
12. 06/ 15 13 Change PCH SPI I/F pull high to +3VS To solve S3/S5 +3VS power plan leakage issue
A
13. 06/ 16 20 Stuff 0.1u (C280) on +3VS power rail To solve ESD issue A
14. 06/ 18 07 Add R1009, R1010 for DDI1_DDC_SCL/SDA Follow Intel DDI disable guideline

HW PIR
0.3
QBU00
5 4 3 2 1
5 4 3 2 1
PIR (Product Improve Record)


-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
01. 06/ 29 09 Swap CLK Gen output for CPU_SCDREFFCLK and CPU_DREFCLK Intel recommend CPU_SSCDREFFCLK use SSC CLK
D D


-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
01. 08/ 29 07 Change R975 from 10ohm to 0 ohm Follow Intel CRB design.
02. 08/ 29 25 Un-stuff R312,R313 KSO1,KSO2 of KB930 don't need to pull high.
03. 08/ 29 27 Add 1u(C406) on touch pad power rail. To solve ESD issue
C C
B B
A A

HW PIR
0.3
QBU00
5 4 3 2 1
--------------------------------------------------------------------------------------------------------------------------------
2011/06/14 32 PR336, PR356 to 1206 4.7ohm; PC336, PC356 to 0603 680pF For EMI Solution
2011/06/14 35 PR526, PR528, PR569, PR571 to @
PR506, PR516 to 1206 4.7ohm; PC506, PC516 to 0603 680pF For EMI Solution
2011/06/14 33 PU150 change to RT8209MGQW

For OCP Solution
2011/06/14 33 PR157 change to S RES 1/16W 7.87K +-1% 0402
2011/06/14 35 PC550 to @ Reserve PC550 location and change it to 5.3mm cap ( SF000003Z00 ) for ME solution
2011/06/21 35 PC536 to 42.2K Change PR536 to 42.2Kohm to meet Cedar Trail loadline spec
2011/06/27 35 PH505, PR542, PR543, PH504, PR559, PR560 to @ For Cedar Trail loadline spec
PR545, PR558, PR530, PR567 to 0ohm
PR541 to 3.62K, PR544 to 1.69K, PR556 to 10K
PR557 to 2K, PR536 to 39K
2011/06/27 35 PR582, PR583 to 35.7K For CPU & GFX OCP Solution
2011/06/27 35 PL503 to 2.2uH Base on GFX_Core ripple & dynamic test result
2011/06/27 35 PR584 to 0_0402_5% For AP Code material
2011/11/1 29 PF1 change to SART 5A_32V_S1206-H-5.0A For burn out issue

2011/11/1 30 PF2 change to Cooper 7A_32V_TR/3216FF-R For burn out issue
2011/11/1 32 PU330 change to RT8205EGQW For burn out issue
2011/11/1 35 PC550 change to Lelon 68uF 5.3H For acoustic issue

Power PIR
Custom 0.3
PEQAE LA-7291P M/B

Toshiba N500 N520 (Compal LA-6858P)

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Toshiba N500 N520 (Compal LA-6858P)

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

CRT Conn. RGB

1.5V DDRIII 1066MHz

Security Classification Compal Secret Data Compal Electronics, Inc.

EC SM Bus1 address EC SM Bus2 address

NM10 SM Bus address

Clock Generator 1101 001Xb

DDR DIMMA 1010 000Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/06/27 Deciphered Date 2011/6/27 Title

B+ DESIGN CURRENT 250mA Cougar Power Map

Ipeak=3.98A, Imax=2.8A +5VALWP +-5%

APL5930KA DESIGN CURRENT 151mA

N-CHANNEL DESIGN CURRENT 294mA

SY8033BDBC Ipeak=1.308A, Imax=4A +1.05VSP +-5%

B Imax=3.5A DESIGN CURRENT 4500mA +CPU_COREP B

RT8165BGQW DESIGN CURRENT 2000mA +GFX_COREP

DESIGN CURRENT 500mA

Security Classification Compal Secret Data Compal Electronics, Inc.

<10> DDR_A_DQS[0..7] N2600@

+1.5V pull up must be placed DDR_A_WE# AH10 AE29 DDR_A_D17

DRAM_VR_PWRGD 1 2 PCH_POK_R 22.6_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

HDMI@ Y3 H_FERR#_CPU 1 2 H_FERR#

1 HDMI@ E11 H2 R509 be placed U1.R22 J19 CLK_CPU_HPLCLK CLK_CPU_HPLCLK <9>

DDI1_TXP2 LVDS_TXN0 RSVD_F19

CRT@ 1 BREFREXT BREF1P5V LVDS_CLKP XDP_TRST#_R B24 TMS

<13> HDA_BITCLK_CPU AZIL_BCLK RSVD_R5

+3VS 1 2 place near the hottest spot area for

Security Classification Compal Secret Data Compal Electronics, Inc.

VCC_CPU_18 U22 AC10 VSS VSS L7

0_0603_5% B5 VCCADP_1 VCC_CPU_28 V29 AD5 VSS VSS N27

D6 VCCADP_3 AE1 VSS VSS N4

D31 VCCAGPIO_2 VCC_GFX_08 T13 AF21 VSS VSS U9

0_0603_5% VCC_CPUSENSE VCCSENSE <35> AK9 VSS

HDMI@ +VCCPLLCPU1 C29 AL19 A27

CRT@ G15 L14

0_1206_5% 2 2 2 2 C1093 G17 D13

2011.04.25 Add for RGB I/F 2 2

+1.5VS +1.5VS +1.5VS

R924 R925 R926

Security Classification Compal Secret Data Compal Electronics, Inc.

@ 2010/06/27 2011/6/27 Title

Normal Power Low Power

56 CLK_PCIE_WLAN# LAN_CLKREQ# R101 2 1 10K_0402_5%

FSB <13> H_STP_PCI# PCI_STOP#

+3VS R608 1 2 H_STP_PCI#_R 1 2 63 CPU_ITP# 0_0402_5% R983@

0_0402_5% 33_0402_5% 1 2 R103 CLK_PCI_DDR_R CLK_PCIE_LAN

@ R491 Pin28/29 : 27M/27M_SS 69 58 WLAN_CLKREQ#

+DIMM_VREF +1.5V +1.5V

<6> DDR_A_D[0..63] JDDR1

2.2U_0603_6.3V6K DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3

DDR_A_DQS#4 135 136 DDR_A_DM4

201 202 CLK_SMBCLK <9,18>

R208 205 206 0.65A@0.75V

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

PORT #EVT DEVICE

Security Classification Compal Secret Data Compal Electronics, Inc.

8.2K_0402_5% @R579 PM_CLKRUN#

8.2K_0402_5% R581 GPIO6

1K_0402_5% 1 R585 2 MCH_SYNC#

A 1 GND D6 R126 @ R590 A