Logic Design

Chap – 07: Latches and Flip-Flops

Dr. Muhammad Hanif

D Flip Flop
A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting
Q back to D as shown.
This is useful in some counters as you will see in Chapter 8.

For example, if Q is LOW, Q is HIGH and the flip-flop D Q

will toggle on the next clock edge. Because the flip-flop
CLK CLK
only changes on the active edge, the output will only
change once for each clock pulse.
Q

D flip-flop hardwired for

a toggle mode
Synchronous and Asynchronous inputs

Synchronous inputs are transferred in the triggering

edge of the clock (for example the D or J-K inputs). Most
flip-flops have other inputs that are asynchronous,
meaning they affect the output independent of the
clock. PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These
Q
inputs are usually active LOW. A J-K
flip flop with active LOW preset and
CLK
CLR is shown.
Q

CLR
Timing Parameters for Sequential Logic
• Sequential circuits exhibit certain timing characteristics.
• Unlike combinational circuits, timing characteristics are specified in relation
to the clock input.
• Timing parameters can be specified in relation to the rising (for positive
edge-triggered) or falling (for negative-edge triggered) clock edge.
• The operating characteristics for flip-flops (regardless of the particular form
of the circuit) can be define using following parameters.
• Propagation delay
• Contamination delay
• Setup time
• Hold time
Example
Timing Parameters: Propagation delay
• Propagation delay is fundamentally important to sequential logic.
• The amount of time needed for a change in the flip flop-clock input
(e.g. rising/falling edge) to result in a permanent change at the flip-
flop output (Q).
• When the clock edge arrives, the D input value is transferred to
output Q.
• The longer the propagation delay, the slower your clock is able to
run.
 Flip-Flops
Flip-flop Operating Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-flop characteristics

Another propagation delay time specification is the time

required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.

PRE 50% point CLR 50% point

Q 50% point Q 50% point

tPHL tPLH

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Contamination delay (tcd)

• This value indicates the amount of time needed for a change in the flip-flop
clock input to result in the initial change at the flip-flop output (Q).
• The output of the flip-flop maintains its initial value until time tcd has
passed.
• The flip-flop is guaranteed not to show any output change in response to
an input change until after tcd has passed.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-flop characteristics

Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.

D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts

D
Hold time is the minimum time
for the data to remain after the CLK
clock.

Hold time, tH

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-flop characteristics
Flip-flop Characteristics

Other specifications include maximum clock frequency,

minimum pulse widths for various inputs, and power
dissipation. The power dissipation is the product of the
supply voltage and the average current required.
A useful comparison between logic families is the speed-power product
which uses two of the specifications discussed: the average propagation
delay and the average power dissipation. The unit is energy.
What is the speed-power product for 74AHC74A? Use
the data from Table 7-4 to determine the answer.
From Table 7-4, the average propagation delay is 4.6 ns.
The quiescent power dissipated is 1.1 mW. Therefore, the
speed-power product is 5 pJ

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-flop applications
Output
lines
Principal flip-flop applications are for D Q0
temporary data storage, as frequency C

dividers, and in counters (which are R

covered in detail in Chapter 8). D Q1

C

Q2
Typically, for data storage applications, D

C
a group of flip-flops are connected to Parallel data
parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

Clock C

R
Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-flop applications
Data Storage
Output
lines
D Q0
C

D Q1
C

D Q2
C
Parallel data
input lines R

D Q3
Clock C

R
Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-Flop Applications
Frequency Division
 Flip-flop applications
Frequency Division

For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH

One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty
fin
cycle.
Waveforms:
fout

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Flip-Flop Applications
Counting

• Another important
application of flip-flops
is in digital counters,
which are covered in
detail in Chapter 9.
Counting