Introduction to Digital VLSI

Lecture 9
Dr. Shaeen Kalathil
Edge-Triggered D Flip-Flops
 Master-Slave D Flip-Flop
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

(a) Circuit

The circuit consists of two D flip-flops connected together. When the clock is high, the D input is stored in the first
latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second
latch, but the first latch cannot change state.
The result is that output can only change state when the clock makes a transition from high to low.
 Negative-Edge-Triggered Master-Slave D Flip-Flop
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

Positive-Edge-Triggered Master-Slave D Flip-Flop

Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

 Negative-Edge-Triggered Master-Slave D Flip-Flop
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

Positive-Edge-Triggered Master-Slave D Flip-Flop

Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

 Negative-Edge-Triggered Master-Slave D Flip-Flop
Master Slave
Qm Qs
D D Q D Q Q D Q

Clock Clk Q Clk Q Q Q

Positive-Edge-Triggered Master-Slave D Flip-Flop

Master Slave
Qm Qs
D D Q D Q Q D Q

Clock Clk Q Clk Q Q Q

What happens if both clock and input transition occur at same time?
Output will be unpredictable
 Review Questions
1. Define Setup time and Hold time.
2. Explain the reason for setup time and hold time with the help of circuit diagram.
3. What is metastability?
4. What is the difference between latches and flip-flops?
5. Draw the diagram, symbol and CMOS implementation of negative edge triggered Master – Slave D flipflop. How
does the behaviour of master slave D flipflop differ from that of D Latch.
6. Draw the circuit diagram of a CMOS positive edge-triggered master-slave D flip-flop and explain the working.