Acer Nitro AN515-54 EH50F EH51F EH5VF EH70F Compal LA-H501P Rev 1A Schematic Diagram

A B C D E
1 1
Compal Confidential
EH50F/EH51F
2
EH5VF/EH70F 2
MB Schematic Document
LA-H501P
3
Rev:1A 3
2019.02.22
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/10/30 Deciphered Date 2018/10/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EH5VF M/B LA-H501P 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, February 22, 2019 Sheet 1 of 101
A B C D E
A B C D E
HDMI Conn. eDP

1
Fan Control*2 1
page 77
Interleaved Memory
page 40
page 38 Memory BUS 260 pin DDR4-SO-DIMM X1
BANK 0, 1, 2, 3 page 23
eDP
Dual Channel
CoffeeLake H Processor
1.2V DDR4 2400/2666 260pin DDR4-SO-DIMM X1
BGA1440 BANK 4, 5, 6, 7 page 24
N18P-G0 with gDDR5 x4
or
PEG x16
8GT/s
(42X28) (CFL-H_6+2)
HDMI x 4 lanes
N17P-G0-K1 with gDDR5 x3
page 25~36 Processor page 06~13 USB 3.0
conn x1
USB (port 1)
2 X4 DMI USB 3.0 USB 3.0 CMOS 2

page 52 page 68 page 68
NGFF conn x1 Type-C Camera
WLAN PCIE 1.0 PCIE 3.0 x4 PCIE 3.0 x4 USB (port 3) USB (port 2) USB (port 5)
USB port 7 2.5GT/s 8GT/s 8GT/s
Port 9-12 Port 21-24
port 15
Flexible IO
page 51 page 67 Cannonlake PCH - H USBx8
Finger_Print USB charger
PCIE 2.0 SATA3.0 FCBGA(25X24) USB (port 8) SLGC55544
5GT/s 6.0 Gb/s
port 14 port 4 page 66
48MHz page 72 page 42,43 page 38 page 71

LAN(GbE) SATA Re-Driver
Realtek 8118ASA PARADE PS8527 874pin FCBGA HD Audio 3.3V 24MHz
page 14~21
RJ45 conn. SATA HDD Conn. HDA Codec

LPC/eSPI BUS ALC255
page 42
3 3
CLK=24MHz
page 32. ENE

page 47 KB9022 TPM
page 58 page 66
Int. Speaker Int. DMIC UAJ
SPI
RTC CKT. Sub Board on Camera/B on Sub/B
page 42 page 48 page 48
page 20
Touch Pad Int.KBD
PS2 / I2C
HS/B page 66 SPI ROM x1
Power On/Off CKT.
page 16
page 63
page 63
page 63
IO/B page 73
DC/DC Interface CKT.

page 78
4 4
Power Circuit DC/DC
page 81~97

2017/07/20 2018/07/20 Title
Issued Date Deciphered Date Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5VF M/B LA-H501P
A B C D E
A B C D E
Board ID Table for AD channel Power State

Vcc 3.3V +/- 5% BOM Structure Table SIGNAL
Ra 100K +/- 1% STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Board ID Rb V BID min V BID typ V BID max EC AD BOM Option Table S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
0 0 0.000 V 0.300 V 0x00 - 0x13 Item BOM Structure
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x14 - 0x1E S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
Unpop @
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
Connector CONN@
1 3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 1
CMC CMC@ S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A
dGPU circuit VGA@
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45
N18P GPU N18P@
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
N17P GPU N17P@
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64
TPM TPM@ Voltage Rails
8 75K +/- 1% 1.398 V 1.414 V 1.430 V 0x65 - 0x76 Power Plane Description
For Acer IOAC IOAC@ S0 S3 S4 S5
9 100K +/- 1% 1.634 V 1.650 V 1.667 V 0x77 - 0x87 +RTCVCC RTC Battery Power ON ON ON
No Acer IOAC NIOAC@ ON
10 130K +/- 1% 1.849 V 1.865 V 1.881 V 0x88 - 0x96 +19V_VIN Adapter power supply N/A N/A N/A
KB backlight KBLED@ N/A
11 160K +/- 1% 2.015 V 2.031 V 2.046 V 0x97 - 0xA4 +12.6V_BATT Battery power supply N/A N/A N/A
KB LED driver LED14P@ N/A
12 200K +/- 1% 2.185 V 2.200 V 2.215 V 0xA5 - 0xAF +19VB AC or battery power rail for power circuit. N/A N/A N/A
OVRM-ON ON_X76@ N/A
13 240K +/- 1% 2.316 V 2.329 V 2.343 V 0xB0 - 0xB7 +3VLP +19VB to +3VLP power rail for suspend power
OVRM-uPI uPI_X76@ ON ON ON ON
14 270K +/- 1% 2.395 V 2.408 V 2.421 V 0xB8 - 0xBF +5VALW +5V Always power rail ON ON ON ON
15 330K +/- 1% 2.521 V 2.533 V 2.544 V 0xC0 - 0xC9 +3VALW System +3VALW always on power rail ON*
Thermal sensor TMS@ ON ON ON
16 430K +/- 1% 2.667 V 2.677 V 2.687 V 0xCA - 0xD4 +3VALW_DSW +3VALW power for PCH DSW rails
for SW debug board UART@ ON ON ON ON
17 560K +/- 1% 2.791 V 2.800 V 2.808 V 0xD5 - 0xDD
Intel CNVi CNVI@
18 750K +/- 1% 2.905 V 2.912 V 2.919 V 0xDE - 0xF0
Finger Print FP@
19 NC 3.000 V 3.000 V 0xF1 - 0xFF
FinerPrint(with PBA) PBA@ +1.05VALW +1.05V Always power rail ON ON ON ON
2
+1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF 2
EMI requirement EMI@ +1.05V_VCCST Sustain voltage for processor in Standby modes
I2C Address Table EMI require reserve XEMI@ +5VS System +5V power rail
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
Address(8bit) ESD requirement ESD@ +3VS System +3V power rail ON OFF OFF OFF
BUS Device Address(7 bit)
Write Read ESD require reserve XESD@ +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF
I2C_0 (+3VS) FP ESD requirement FPESD@ +0.6VS_VTT DDR +0.6VS power rail for DDR terminator . ON OFF OFF OFF
I2C_1 (+3VS) TM-P3393-003 (Touch Pad) Pidgey ESD requirement PGESD@ +VCC_CORE Core voltage for CPU ON OFF OFF OFF
SA577C-12A0 (Touch Pad) SATA HDD W REDRIVER SATARD@ +VCC_GT Sliced graphics power rail ON OFF OFF OFF
DIMM1 SATA HDD WO REDRIVER SATANRD@ +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF
PCH_SMBCLK +VCC_SA System Agent power rail
(+3VS) DIMM2 ON OFF OFF OFF
+1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
N18P-G0/N17P-G0-K1 (VGA) 0x9E i5 CPU i5@ +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF
PCH_SML1CLK +NVVDD1 Core voltage for VGA (merge core & core_s)
EC_SMB_CK2 Thermal Sensor (W83L771) 1001_100xb 1001_1001b 1001_1000b i7 CPU i7@ ON OFF OFF OFF
PCH 0x90 H62 CPU H62@ +1.35VSDGPU +1.35VS power rail for GPU
(+3VS) ON OFF OFF OFF
H82 CPU H82@ +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF OFF
LAN LDO mode LDO@ +1.8VALW System +1.8VALW always on power rail ON ON ON ON*
EC_SMB_CK1 BQ24780 (Charger IC) 0x12 LAN Switch mode SWR@

(+3VLP) BATTERY PACK 0x16
3 3
LED driver 0xC0
EC_SMB_CK3
(+3VALW) Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
43 level BOM table
43 Level Description BOM Structure Board ID PCB Revision Board ID PCB Revision
0 2050 Rev0.1 10
431AC5BOL01 SMT MB AF952 DH53F I5PG1 4G 28P 8L HDMI 255@/CHG@/CMC@/CNVI@/FP@/G0@/I5@/IOAC@/LDO@/SATARD@/TYPEC@/V15@/VGA@/X76@ 1 2050 Rev0.2 11
2 2050 Rev0.3 12
3 2050 Rev1.0/1A 13
4 2060 Rev0.1 14
5 2060 Rev0.2 15
6 2060 Rev0.3 16
7 2060 Rev1.0 17
8 18
4
9 19 4

Notes List
A B C D E
5 4 3 2 1
DC_IN
PL101,2,3
PJP101
+19V_VIN
AC CONN. +2.5VP JDIMM1
+12.6V_BATT+ PU2501 PJ2502 +2.5V
+12.6V_BATT DDR4 Conn.
PL201,2 BATTERY +1.0VSDGPUP
JDIMM2
+1.0VSDGPU GPU
PJP201 PU1002 PJ1003
D IMVP8 D
+19VB_CPU
PUZ2,3,4,5 +VCC_CORE CPU UQ1 JPQ1 +3VS
PUB1 +19VB PLZ1,2,3,4 UO1 +3VS SATA Re-driver
EN:DRVON
R19 +3VALW_TPM U5 TPM
UV45 +3VSDGPU GPU
UM1 +3VS_WLAN JNGFF1 WLAN CARD Conn.
+19VB_CPU +3VS_WLAN
RM11 JNGFF1 WLAN CARD Conn.
CHARGER +19VB
PRG5 PLG1 +VCC_GT CPU UL1 +3V_LAN UL2 LAN
EN:DRVON R20 +3VS_TPM U5 TPM
UK1 +3V_PTP JTP1 TP Conn.
UX1 +LCDVDD JEDP1 PANEL
+19VB_CPU UM2 RM54 +3VS_SSD1 JSSD1 SSD Conn. +3VS_DVDDIO
PRA3 RA2 CODEC
PLA1 +VCC_SA CPU +3VS_SSD2
+19VB UM2 RM55 JSSD2 SSD Conn. +3VS_DVDD
EN:DRVON RA4 CODEC
RH101 +3VALW_HDA PCH
+3VALWP
EN:3V_EN +3VALW RH99 +3VALW_DSW PCH
PJ302
+19VB
PU301 +FP_VCC
EC,LID +3VLP
UK2 JFP1 FP Conn.
C C
+1.2VP
CPU,Memory JPH1 +1.05VALW_PRIM PCH
EN:SYSON +1.2V_VDDQ +1.2V_VCCPLL_OC
PJM2 RC24 CPU
RH94 +1.05VALW_PCH PCH
+19VB
PUM1 EN:SM_PG_CTRL RH102 +1.05VALW_VCCAZPLL
+0.6VSP RH103 +1.05VALW_VCCAMPHYPLL
+0.6VS_VTT +1.05VALW_XTAL
PCH
PJM3 RH105
+1.05VALWP
PU1101 +1.05VALW UQ2 RQ5 +1.05V_VCCST
+19VB
PJ1101 CPU
EN:+1.8_PG
UC4 +1.05VS_VCCSTG
EN:DGPU_PWR_EN
+1.0VS_VCCIOP
+1.8VSDGPU_AON UV48 +FP_FUSE_GPU GPU
+VCCIO
CPU
+19VB
PUH1 PJH1 +1.8VSDGPU_MAIN GPU
EN:SUSP# UG27
B UQ2 RQ9 +1.8VS RA3 +1.8VS_VDDA CODEC B

+1.8VALWP
PU1801 PJ1801 +1.8VALW RH100 +1.8VALW _PRIM PCH

+19VB
EN:SPOK_3V
RS127 +5VALW_MUX US3 CC logic/U3 MUX
+5VALWP +5VALW
PU501 JIO1 JIO1 IO/B Conn.
+19VB
PJ502 +5VALW
US11 +USB3_VCCC JTYPEC1 Type-C Conn.
US12 +USB_VCCA JUSB1 USB3.0 Conn. +VCC_FAN1

RF4 JFAN1 FAN1 Conn.
US13 +USB_VCCB JUSB2 USB3.0 Conn. +VCC_FAN2
+19VB
NVVDD_B+ RF7 JFAN1 FAN2 Conn.
GPU
PUV1 PUV2,3 PLV2,3 +NVVDD1 UE5 +5V_LEDPWR JBL2 KB BackLight Conn. +VDDA
JPA1 UA1 CODEC
UK2 +FP_VCC JFP1 FP Conn. +5VS_BL
U4 JBL1 KB BackLight Conn.
UQ1 JPQ2 +5VS +5VS_HDD
EN:1.35VSDGPU_EN RO4 JHDD1 HDD Conn.
+19VB
GPU_B+ GPU +HDMI_5V_OUT
A +1.35VSDGPU UY2 JHDMI1 HDMI Conn. A
PUW1 PLW1
+TS_PWR
RX7 JEDP1 Touch Screen
+19VB → +19VB_CPU
LX1 +INVPWR_B+
PANEL
Security Classification
2017/10/30
Compal Secret Data
2018/10/30 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
5 4 3 2 1
A B C D E
DH5VF_EVT Power Sequence AC mode

BIOS ver: V0.02W1
EC: ver: V002AT04
1 1
Plug in Power On S3 S3 Resume Power Off

+3VLP
+3VLP
EC_ON
→ 330.8ms
EC_ON
+5VALW
→ 333.3ms
+5VALW
ON/OFFBTN#
ON/OFFBTN#
→ 92.03ms
+3VALW +3VALW
→ 94.88ms → 293.7us
+1.05VALW +1.05VALW
→ 29.19ms
EC_RSMRST# EC_RSMRST#
20.1ms
2.439ms → ← →
PBTN_OUT# PBTN_OUT#
174.6ms → 19.18ms
PM_SLP_S4# PM_SLP_S4#
→ 19.22ms 100.5us
PM_SLP_S3# PM_SLP_S3#
→ 72.1us → 152.8us
2 SYSON SYSON 2
→ 275.9us → 88.37us
+1.05V_VCCST +1.05V_VCCST
→ 692.9us → 367.6us
+1.2V_VDDQ +1.2V_VDDQ
→ 910.1us 2.266ms
+2.5VS
→ +2.5VS
→ 12.7ms 13.01us 67.04ms 13us
SUSP#
→ → → SUSP#
→ 8.378us → 55.47us → 8.502us → 68.53us
+1.05VS_VCCSTG +1.05VS_VCCSTG
→ 877.7us → 618.5us → 906.0us → 686.0us
+5VS +5VS
→ 630.4us → 8.679ms → 656.1us → 11.65ms
+3VS +3VS
→ 412us → 347.6us → 424.9us 446.2us
+1.8VS +1.8VS
→ 25.34ms → 0us → 25.25ms 0us
EC_VCCST_PG EC_VCCST_PG
→ 25.35ms → 0us → 25.25ms → 13.97ms
SM_PG_CTRL SM_PG_CTRL
→ 25.36ms → 3.819ms → 25.26ms → 2.034ms
+0.6VS_VTT +0.6VS_VTT
→ 25.19ms → 26.91us → 25.59ms → 27.06us
VR_ON VR_ON
→ 1.759ms → 51.25us → 1.757ms → 48.00us
+VCC_SA +VCC_SA
→ 173.0ms → 87.75us → 167.1ms → 112.0us
3 +VCC_CORE +VCC_CORE 3
→ NA → NA → NA NA
+VCC_GT +VCC_GT
→ 12.42ms → 47.39us → 12.18ms → 47.83us
PCH_PWROK PCH_PWROK
→ 150.3ms → 61.95us → 150.6ms → 62.37us
SYS_PWROK SYS_PWROK
→ 152.3ms → 318.7us → 151.8ms
PLT_RST# PLT_RST#
4 4
2017/10/30
Compal Secret Data
2018/10/30 Title
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A B C D E
A B C D E
ZZZ ZZZ1
PCB10@ PCB1A@
PCB EH5VF LA-H501P LS-H501P/H502P PCB EH5VF LA-H501P LS-H501P/H502P

DAZ2K700100 DAZ2K700101
1 1
Coffee Lake-H CPU SKU

UC1 UC1
I5@ I5RQS@
S IC CL8068403373522 SR3Z0 U0 2.3G ABO! S IC CL8068404121905 QRR5 U0 2.4G FCBGA

SA0000BPJ40 SA0000COG00
UC1 UC1
I7@ I7RQS@
S IC CL8068403359524 SR3YY U0 2.2G ABO! S IC CL8068404121817 QRR2 U0 2.6G FCBGA 1440

SA0000BPZ40 SA0000COF10
UC1
CFL-H
I5QS@ UC1D
S IC CL8068403373522 QP89 U0 2.3G BGA

K36 D29 EDP_TXP0
SA0000BPJ10 DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <38>
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <38>
2 J35 F28 2
DDI1_TXP_1 EDP_TXP_1 EDP_TXN1 EDP_TXP1 <38>
J34 E28
DDI1_TXN_1 EDP_TXN_1 EDP_TXP2 EDP_TXN1 <38>
H37 A29
EDP_TXP2 <38>
H36 DDI1_TXP_2
DDI1_TXN_2
EDP_TXP_2
EDP_TXN_2
B29 EDP_TXN2
EDP_TXP3 EDP_TXN2 <38>
eDP
J37 C28
DDI1_TXP_3 EDP_TXP_3 EDP_TXN3 EDP_TXP3 <38>
J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <38>
D27 C26 EDP_AUXP
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <38>
E27 B26 EDP_AUXN <38>
DDI1_AUXN EDP_AUXN
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
Cannon Lake PCH SKU F35 DDI2_TXP_2
DDI2_TXN_2 DISP_RCOMP
D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
UH1 DDI2_TXN_3 Max Trace Length: 600 mil
PCH@ F26
E26 DDI2_AUXP
DDI2_AUXN
S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO!
SA0000BVP10 C34
D34 DDI3_TXP_0
UH1 B36 DDI3_TXN_0
B34 DDI3_TXP_1
PCHQS@ F33 DDI3_TXN_1
E33 DDI3_TXP_2
3 C33 DDI3_TXN_2 3
S IC FHHM370 QNYF B0 BGA 874P PCH-H DDI3_TXP_3
SA0000BPF10 B33
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_SDO_R CPU_DISPA_BCLK_R <18>
A27 G25 CPU_DISPA_SDO_R <18>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI_R <18>
follow CRB
NV GPU SKU CFL-H_BGA1440
@
UV1
N17P@
S IC N17P-G0-K1-A1 FCBGA 908P GPU ABO !
SA0000CFM20
UV1
N18PQS@
S IC N18P-G0-A1 QS FCBGA 960P GPU ABO !
SA0000CK210
UV1
4
N18PMP@ 4
S IC N18P-G0-MP-A1 FCBGA 960P GPU ABO !
SA0000CK230

CFL-H(1/8)DDI/eDP
A B C D E
A B C D E
CHANNEL-A
Interleaved Memory
UC1A
CFL-H
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_W E# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4 DDR_A_MA1 <23>
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2
AA5 AP5 DDR_A_MA3 <23>
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <23>
AB4 AP1 DDR_A_MA5 <23>
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
V4 AE3 DDR_A_MA13 <23>
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23>
U4 AU3 DDR_A_ACT# <23>
DDR_A_D48 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT#
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5 DDR_A_ALERT# <23>
DDR_A_D51 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT#
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
M5 L3 DDR_A_DQS#7 <23>
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3 DDR_A_DQS1 <23>
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR4 BC3 DDR_A_DQS3 <23>
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS5 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5 <23>
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 13
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
@
4 4

CFL-H(2/8)DIMMA
A B C D E
A B C D E
CHANNEL-B
Interleaved Memory
UC1B
CFL-H
<24> DDR_B_D[0..63] DDR CHANNEL B

1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <24>
BR11 AN9 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <24>
BR8 AM8 DDR_B_CLK#1 <24>
DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
BL8 AT10 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
BJ7 AE7 DDR_B_CS#1 <24>
DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
BF11 AE8 DDR_B_ODT1 <24>
DDR_B_D21 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_W E# DDR_B_MA16_RAS# <24>
BC11 AH11 DDR_B_MA14_W E# <24>
DDR_B_D26 BB8 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 AF8 DDR_B_MA15_CAS#
DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24>
BB10 AH9 DDR_B_BA1 <24>
DDR_B_D30 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0
DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <24>
AA10 AK6 DDR_B_MA1 <24>
DDR_B_D34 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
AC10 AL5 DDR_B_MA3 <24>
DDR_B_D36 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <24>
AA8 AM6 DDR_B_MA5 <24>
DDR_B_D38 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <24>
AC7 AN10 DDR_B_MA7 <24>
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
W7 AR11 DDR_B_MA9 <24>
DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
V11 AN11 DDR_B_MA11 <24>
DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
W10 AF9 DDR_B_MA13 <24>
DDR_B_D46 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24>
V8 AT9 DDR_B_ACT# <24>
DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT#
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <24>
P7 AR8 DDR_B_ALERT# <24>
DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT#
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#1 DDR_B_DQS#0 <24>
R7 BL9 DDR_B_DQS#1 <24>
3 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2 3
L11 BC9 DDR_B_DQS#3 <24>
DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
L7 W9 DDR_B_DQS#5 <24>
DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
L10 M9 DDR_B_DQS#7 <24>
DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS1 DDR_B_DQS0 <24>
L8 BJ9 DDR_B_DQS1 <24>
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3 <24>
AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS5 DDR_B_DQS4 <24>
AY8 V9 DDR_B_DQS5 <24>
AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS7 DDR_B_DQS6 <24>
AY10 L9 DDR_B_DQS7 <24>
AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 For ECC DIMM
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
4 @ 4

CFL-H(3/8)DIMMB
A B C D E
A B C D E
PEG&DMI
To DGPU
1 To DGPU PEG Lane Reversed
1
PEG Lane Reversed CFL-H

UC1C
CC1 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K 2 1VGA@ CC2
<27> PEG_CRX_C_GTX_P15 PEG_CRX_GTX_N15 PEG_RXP_0 PEG_TXP_0 PEG_CTX_GRX_N15 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P15 <27>
<27> PEG_CRX_C_GTX_N15 CC3 VGA@ 1 2 0.22U_0201_6.3V6K D25 A25 2 1VGA@ CC4
PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 <27>
<27> PEG_CRX_C_GTX_N14 CC6 VGA@ 1 2 0.22U_0201_6.3V6K F24 C24 2 1VGA@ CC12
<27> PEG_CRX_C_GTX_P9 PEG_CRX_GTX_N9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <27>
<27> PEG_CRX_C_GTX_N9 CC27 VGA@ 1 2 0.22U_0201_6.3V6K D19 A19 0.22U_0201_6.3V6K 2 1VGA@ CC28
<27> PEG_CRX_C_GTX_N8 CC31 VGA@ 1 2 0.22U_0201_6.3V6K F18 C18 0.22U_0201_6.3V6K 2 1VGA@ CC32
CC33 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0201_6.3V6K 2 1VGA@ CC34
2
<27> PEG_CRX_C_GTX_N7 CC35 VGA@ 1 2 0.22U_0201_6.3V6K E17 B17 0.22U_0201_6.3V6K 2 1VGA@ CC36 2
CC37 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0201_6.3V6K 2 1VGA@ CC38
<27> PEG_CRX_C_GTX_N6 CC39 VGA@ 1 2 0.22U_0201_6.3V6K E16 B16 0.22U_0201_6.3V6K 2 1VGA@ CC40
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<14> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <14>
<14> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <14>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<14> DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 <14>
DMI_RXN_1 DMI_TXN_1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
<14> DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2 <14>
DMI_RXN_2 DMI_TXN_2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<14> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <14>
<14> DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3 <14>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
@
4 4

PEG/DMI
A B C D E
A B C D E
CFL-H
UC1E
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

<15> PCH_CPU_BCLK_P PCH_CPU_BCLK_N BCLKP CFG_0
<15> PCH_CPU_BCLK_N A32 BN27 CFG2 RC8 1 2 1K_0402_5%
BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG5 RC10 1 @ 2 1K_0402_5%
<15> PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCI_BCLKP CFG_3
<15> PCH_CPU_PCIBCLK_N C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<15> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLK24P CFG_6
571391_CFL_H_PDG_Rev0p5 <15> PCH_CPU_24M_CLK_N D31 BP20 CFG7
CLK24N CFG_7 BR23
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).
2. Route the Alert signal between the Clock and the Data signals. CFG_8 BR22
1 1
3. Place those resistors close CPU side. CFG_9 BT23 The CFG signals have a default value of '1' if not terminated on the board.
PGESD@ CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
1000P_0402_50V7K 1 2 CC95 CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13
PGESD@ BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
1000P_0402_50V7K 1 2 CC96 CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
CPU_SVID_CLK BH32 VIDALERT# CFG_15 * 0 = Lane numbers reversed.
<89> CPU_SVID_CLK CPU_SVID_DAT VIDSCK CFG[4]: eDP enable:
PGESD@ BH29 BN23
1000P_0402_50V7K 1 2 CC97 H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 1 = Disabled.
PROCHOT# CFG_16 BP22 * 0 = Enabled.
PGESD@ DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
1000P_0402_50V7K 1 2 CC98 DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
XDP_BPM#0 10 = 2 x8 PCI Express*
XESD@ BR27 TC1 @ 11 = 1 x16 PCI Express*
1000P_0402_50V7K 1 2 CC99 BPM#_0 BT27 XDP_BPM#1 *
Sensitive BPM#_1 TC2 @
BM31 XDP_BPM#2 CFG[7]: PEG Training:
BPM#_2 TC3 @
PGESD@ EC_VCCST_PG H13 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 @ 0 = PEG Wait for BIOS for training.
1000P_0402_50V7K 1 2 CC100
H_CPUPW RGD BT31 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<18> H_CPUPW RGD H_PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
PGESD@ <17> H_PLTRST_CPU# BP35 BT28
1000P_0402_50V7K 1 2 CC101 H_PM_SYNC_R BM34 RESET# PROC_TDO BL32 CPU_XDP_TDI CPU_XDP_TDO <18>
<17> H_PM_SYNC_R H_PM_DOW N PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <18>
BP31 BP28
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <18>
PGESD@ BT34 BR28
<17,58> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <18> To be confirm
1000P_0402_50V7K 1 2 CC102 RC17 1 @ 2 0_0402_5% J31
<17> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <21>
PGESD@ @ TC5 SKTOCC# BR33 BL30 TC19 @
1000P_0402_50V7K 1 2 CC103 BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY#
PROC_SELECT# PROC_SELECT# PROC_PRDY# TC20 @
2
should be unconnected on CFL processor CATERR# BM30 2
@ TC6
EDS1.2 8/21 CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1% XDP_PREQ#
CFG_RCOMP XDP_PRDY# XDP_PREQ# <21>
AT13
XESD@ AW13 ZVM# XDP_PRDY# <21>
0.1U_0201_10V6K 1 2 CC65 H_CPUPW RGD MSM# Trace Width/Space: 4 mil/ 12 mil
AU13 Max Trace Length: 600 mil
ESD@ AY13 RSVD1
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RSVD2
5 OF 13
XESD@ +1.05VS_VCCSTG
0.1U_0201_10V6K 1 2 CC67 H_THERMTRIP# CFL-H_BGA1440 Place to CPU side
@
ESD@ RC76 2 CMC@ 1 51_0402_5% CPU_XDP_TMS
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG
+1.2V_VDDQ
RC77 2 CMC@ 1 51_0402_5% CPU_XDP_TDI
RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

Near CPU side CC69 +3VS
follow 1050 Request 0.1U_0201_10V6K Place to CPU side
2 1
8/21
1
RC79 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
+1.05V_VCCST RC23
RH1 1 2 1K_0402_5% H_THERMTRIP# 330K_0402_5% RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
PCH_JTAG_TCK1 <18>
5
1
UC3
RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
2
Vcc
DDR_PG_CTRL 2 NC 4
A Y SM_PG_CTRL <85>
G
3 +1.05VS_VCCSTG
PU 330K follow CRB 3
74AUP1G07SE-7_SOT353-5
8/21
3
1
RC21
1K_0402_5%
SVID
2
RC14 1 2 499_0402_1% H_PROCHOT#_R

<58,83> H_PROCHOT#
+1.05V_VCCST
+1.05V_VCCST
1
RC22
1K_0402_5%
RC19 RC20
56_0402_1% 100_0402_1%
2
RC15 1 2 60.4_0402_1% EC_VCCST_PG

<58,78> EC_VCCST_PG_R
RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

<17> H_PM_DOW N_R <89> CPU_SVID_ALERT#_R
4 4
1
CPU_SVID_DAT
<89> CPU_SVID_DAT
RH2
@ 13_0402_5%
2

CFL-H(5/8)CFG,SVID
A B C D E
A B C D E
GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 VCCGT66 VCCGT145 @ 3
BC32 BM16 AG37 VCCSENSE
VCCGT67 VCCGT146 VCC_SENSE VCCSENSE <89>
BC35 BM17 9 OF 13 AG38 VSSSENSE
VCCGT68 VCCGT147 VSS_SENSE VSSSENSE <89>
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 @ 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
AH37 VSSGT_SENSE
11 OF VSSGT_SENSE VSSGT_SENSE <89>
13 AH38 VCCGT_SENSE
VCCGT_SENSE VCCGT_SENSE <89>
CFL-H_BGA1440
@ 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
4 4

CFL-H(6/8)VCC_CORE/GT
A B C D E
A B C D E
+1.2V_VDDQ
Max: 3300mA
+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

UC1L
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6
VCCSA1 VDDQ1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
Max: 11100mA K29 AE12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 VCCSA2 VDDQ2 AF5
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12
+VCC_IO M35 VCCSA20 VDDQ20 L6 RC24 1 @ 2 0_0402_5%
Max: 6400mA VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
M36 R6
VCCSA22 VDDQ22
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23 W6
VDDQ24 1 1 1 1 @
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <89>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <89>
J26 150mA
J27 VCCIO20 H14 VCCIO_SENSE
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <88>
J14 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
12 OF 13 VSSIO_SENSE VSSIO_SENSE <88>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4

CFL-H(7/8)VCCSA/VCCIO/VDDQ
A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 Impedance Spectrum Tool Trigger @ TC7
IST_TRIG E3 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 @ TC8
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
VSS_5 VSS_86 VSS_167 VSS_248 VSS_330 VSS_414 @ TC9 RSVD_TP4
A22 AL34 BA10 BJ30 BP24 F25 @ TC10 D1
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 @ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 @ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <21> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <21> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 @
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 @
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 @
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 @
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 @
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 @
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@
4 4

CFL-H(8/8)GND/RSVD
A B C D E
A B C D E
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<9> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <71>
<9> DMI_CTX_PRX_P0 J35 J2 USB3 MB
DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <71>
<9> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <43>
<9> DMI_CRX_PTX_P0 B33 N15 TYPE C
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <43>
<9> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <72>
<9> DMI_CTX_PRX_P1 F34 K3 USB3 MB
<9> DMI_CRX_PTX_N1 C32 M10
<9> DMI_CRX_PTX_P1 B32 L9 USB2 (SUB/B)
DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <73>
<9> DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <38>
<9> DMI_CTX_PRX_P2 J32 L2 Camera
<9> DMI_CRX_PTX_N2 C31 K7
1 <9> DMI_CRX_PTX_P2 B31 K6 TS 1
DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_P6 <38>
<9> DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3
<9> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<9> DMI_CRX_PTX_N3 C29 G4
<9> DMI_CRX_PTX_P3 B29 G5 FingerPrint
DMI3_TXP USB2P_8 USB20_P8 <66> +3VALW
A25 M6
B25 RSVD USB2N_9 N8
The 30 HSIO lanes on PCH-H supports the following configurations: P24 RSVD USB2P_9 H3
1. Up to 24 PCIe* Lanes R24 RSVD USB2N_10 H2 USB_OC0# RH200 1 2 10K_0402_5%
‧
— A maximum of 16 PCIe* Ports (or devices) can be enabled
When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
C26
B26
RSVD
RSVD
USB2P_10
USB2N_11
R10
P9
USB_OC1# RH201 1 2 10K_0402_5%
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1) F26 RSVD USB2P_11 G1

— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe* G26 RSVD USB2N_12 G2
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
B27 RSVD USB2P_12 N3
21-24 (PCIe* Controller #6) can be individually configured RSVD USB2N_13
2. Up to 6 SATA Lanes C27 N2
— A maximum of 6 SATA Ports (or devices) can be enabled L26 RSVD USB2P_13 E5 USB20_N14
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18 RSVD USB2N_14 USB20_P14 USB20_N14 <52>
M26 F6 BT For CNVI follow 571906_CNL_PCH_TA_WW11.pdf
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19 RSVD USB2P_14 USB20_P14 <52>
3. Up to 10 USB 3.1 Lanes
D29
E28 RSVD AH36 USB_OC0#
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled RSVD GPP_E9/USB2_OC0# USB_OC0# <43>
4. Up to 4 GbE Lanes K29 AL40 USB_OC1#
— A maximum of 1 GbE Port (or device) can be enabled RSVD GPP_E10/USB2_OC1# USB_OC1# <71>
M29 AJ44
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage RSVD GPP_E11/USB2_OC2# AL41 +3VALW
devices GPP_E12/USB2_OC3#
— x2 and x4 PCIe* NVMe SSD G17 AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configurations A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
1
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA, PCIE2_RXN/USB31_8_RXN RH3
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft P21 F4 USB2_RCOMP RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE 10K_0402_5%
Straps discussed in the SPI Programming Guide and B18 F3 RH5 1 @ 2 0_0402_5%
through the IntelR Flash Image Tool (FIT) tool. C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
2
2 GPD_7 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID 1 2 0_0402_5%
PCIE3_RXN/USB31_9_RXN USB2_ID
RH6 @ STRAP
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
1
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP RH7
N18 G45
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_P24 <68> 10K_0402_5%
R18 G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_DRX_N24 <68> @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40 PCIE_PRX_DTX_P24 <68>
2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48 PCIE_PRX_DTX_N24 <68>
PCIE5_RXN PCIE23_TXP PCIE_PTX_DRX_P23 <68> X'tal Input:
G20 G49 High: Differential
B21 PCIE5_RXP PCIE23_TXN W44 PCIE_PTX_DRX_N23 <68> Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
K21 PCIE5_TXP PCIE23_RXN H48 PCIE_PRX_DTX_N23 <68>
J21 PCIE6_RXN PCIE22_TXP H47 PCIE_PTX_DRX_P22 <68>
D21 PCIE6_RXP PCIE22_TXN U41 PCIE_PTX_DRX_N22 <68>
C21 PCIE6_TXN PCIE22_RXP U40 PCIE_PRX_DTX_P22 <68>
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PRX_DTX_N22 <68>
C23 PCIE7_TXP PCIE21_TXP G47 PCIE_PTX_DRX_P21 <68>
J24 PCIE7_TXN PCIE21_TXN R44 PCIE_PTX_DRX_N21 <68>
L24 PCIE7_RXP PCIE21_RXP T43 PCIE_PRX_DTX_P21 <68>
F24 PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
3 3
4 4

PCH(1/8)DMI/PCIE/USB2
A B C D E
A B C D E
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H
XTAL_24M_PCH_OUT XTAL_24M_PCH_OUT_R
remove TP as C5PRH UH1G
1 EMI@ 2 BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<10> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# @ TH2
C6 Y4 @ TH3
XTAL_24M_PCH_IN 1 EMI@ 2 XTAL_24M_PCH_IN_R <10> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
1 2
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6
<10> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <10>
C8 A6
<10> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <10>
YH1
24MHZ_18PF_7R24000001 XTAL_24M_PCH_OUT_R U9 AJ6
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA# <27>
1 U10 AJ7 DGPU 1
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <27>
3 1
3 1 XCLK_BIASREF
33P_0402_50V8J
18P_0402_50V8J
RH10 1 2 60.4_0402_1% T3 AH9
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN# <51>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <51>
CH5
CH6
XCLK_BIASREF (PDG) BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN# <52>
8/24 AE15 NGFF WL+BT(KEY E)
VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <52>
BF31
BE31 GPP_B5/SRCCLKREQ0# AE6
<51> LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF1# <68>
<52> W LAN_CLKREQ# AR32 AE7 M2 SSD1
GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF1 <68>
<68> SSD1_CLKREQ# BB30
BA30 GPP_B8/SRCCLKREQ3# AC2
PCH_RTCX1 <68> SSD2_CLKREQ# GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_NGFF2# <68>
AN29 AC3 M2 SSD2
GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_NGFF2 <68>
AE47
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
1 2 AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
RH12 10M_0402_5% AC41 GPP_H3/SRCCLKREQ9# W4
remove no use srcclkreq AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15#
10P_0402_50V8J
10P_0402_50V8J
1 1 AC14
V2 CLKOUT_PCIE_N8 AC15
32.768KHZ_9PF_X1A000141000200
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 Trace Space: 15 mil 2 T2 CLKOUT_PCIE_N9 U3
Max Trace Length: 1000 mil T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 CLKOUT_PCIE_P14 AC9 2
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
use same part w C5MMH AC7 CLKOUT_PCIE_N11 AE11
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6
CLKIN_XTAL REFCLK_CNV <52>
+3VS CNP-H_BGA874 Rev1.0
1
@
RH14
RH204 1 2 10K_0402_5% LAN_CLKREQ# 10K_0402_5%
RH205 1 2 10K_0402_5% VGA_CLKREQ# <27>
RH206 1 2 10K_0402_5% W LAN_CLKREQ#
2
RH207 1 2 10K_0402_5% SSD1_CLKREQ#
RH220 1 2 10K_0402_5% SSD2_CLKREQ#
CNP-H
UH1M
AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <52>
For DDX03 R02 BE9 BE3 CLK_CNV_PRX_DTX_P <52>
BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 <52>
BG8 BB4
+1.8VALW _PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <52>
remove SD signal from PCH BE8 BA3
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <52>
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <52>
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_BRI_PTX_DRX CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <52> 3
RH15 1 2 4.7K_0402_5% AP3 BB6 CLK_CNV_PTX_DRX_P <52>
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. STRAP GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <52>
AM7 BD7 CNV_PTX_DRX_P0
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
remove CPU_C10_GATE# GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <52>
CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <52>
Notes: AV6 BF6
1. The internal pull-down is disabled after RSMRST# GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_W T_RCOMP CNV_PTX_DRX_P1 <52>
AY3 BA1 RH16 1 2 150_0402_1%
de-asserts.
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7 B12 RH17 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW _PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <52> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
checked CRB
<52> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH20 1
BA4 BE1 2 200_0402_1%
<52> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2
<52> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
The signal has a weak internal pull-down 20K GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
0 = VCCPSPI is connected to 3.3V rail
STRAP RSVD3
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin BC1
+1.8VALW _PRIM 13 OF 13 RSVD1 AL35
strap must be a ‘ 1’ fo r th e prope r functionalit y @ TH4
of the SPI (Flash) I/Os TP
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0
Recommend external test point
+1.8VALW _PRIM RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX @
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
RH22 2 1 10K_0402_5% CNV_RGI_PTX_DRX a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
4 4
STRAP
RH23 2 @ 1 10K_0402_5%
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification Compal Secret Data Compal Electronics, Inc.
PCH(2/8)CLK/CNVI/SD
A B C D E
A
CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8
no follow naming GPP_I6/DDPB_CTRLDATA
AT6 AN13
AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10
<27,40> HDMI_HPD_PCH GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA
AP9 AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40
08/18 GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
AN6 GPP_F14/PS_ON#
<38> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
DDP[B..F]CTRLDATA GPP_H23/TIME_SYNC0
This signal has a weak internal Pull-down. CNP-H_BGA874 Rev1.0
remove CIO_PLUG_EVENT#
0 = Port B~D is not detected. intel critical net recommend
1 = Port B,C,D is detected. (Default) @
Notes: RH198 1 2 100K_0201_5%
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts. CNP-H
2. This signal is in the primary well. UH1A PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 EC_PME#_R BE36 AV29 PLT_RST#
<51,58> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <27,58,66>
RH24 0_0402_5% XESD@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
RSVD1 GPP_K12/GSXDOUT Y48 provided by the PCH to expand the GPIOs
CRB connect GND GPP_K13/GSXSLOAD on a platform that needs more GPIOs than the
W46 ones provided by the PCH.
RH186 1 @ 2 0_0402_5% AL37 GPP_K14/GSXDIN AA45
AN35 VSS GPP_K15/GSXSRESET#
TH6 @ TP
RH258 1 NTPM@ 2 0_0402_5% PCH_SPI_SI AU41 AL47
<66> PCH_SPI_SI_R SPI0_MOSI GPP_E3/CPU_GP0
RH259 1 NTPM@ 2 0_0402_5% PCH_SPI_SO BA45 AM45
<66> PCH_SPI_SO_R PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 TP_INT# +3VS
BF32 2 1
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 EC_TP_INT# <58,63>
RH260 1 NTPM@ 2 0_0402_5% AW47 BC33 DH1
<66> PCH_SPI_CLK_R SPI0_CLK GPP_B4/CPU_GP3
AW48 RB751V-40_SOD323-2
SPI0_CS1# AE44 TP_INT# RH28 2 1 100K_0402_5%
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
* wait confirm CG7 SPI0_IO3 GPP_H16/SML4CLK GPP_H15
PDG P348 quad mode support PH1K AT40 AC47
<66> PCH_SPI_CS#2 SPI0_CS2# GPP_H15/SML3ALERT#
CRB PU 20k AD48
+3VALW BE19 GPP_H14/SML3DATA AF47
#571182_CFL_PCH_EDS_Rev1.0 recommend 100k GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK
#571391_CFL_H_PDG_Rev0p71 BF19 AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <19> +RTCVCC
BF18 AD47
RH25 2 1 1K_0402_5% PCH_SPI_IO2 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
RH26 2 1 1K_0402_5% PCH_SPI_IO3 BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
RH27 2 1 1K_0402_5% PCH_SPI_SI_R A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
+3VALW
RH29 2 1 100K_0402_5% GPP_H15 STRAP

#571182_CNL_PCH_H_EDS_V1_Rev0.7
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. RH258 TPM@ RH259 TPM@ RH260 TPM@
571007_CFL_MOW_Archive_WW22_2017
STUFF R on GPP_H15
4.99_0402_1% 4.99_0402_1% 4.99_0402_1%
SD034499B80 SD034499B80 SD034499B80
PCH_SPI_CLK_R RH195 1 @ 2 100K_0201_5%
intel critical net recommend
PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%

SPI ROM ( 16MByte ) +3VALW
+3VALW +3VS
CH10 0.1U_0201_10V6K CH11
UH2 PCH_SPI_CS#0
1 2 1 @ 2 0.1U_0201_10V6K
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% 1 2
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R
/WP(IO2) CLK
5
4 5 PCH_SPI_SI_0_R UH3
GND DI(IO0)
VCC
PLT_RST# 1
W 25Q128FVSIQ_SO8 IN1 4
OUT PLT_RST_BUF# <51,52,68>
XMC P/N: SA0000B8400 2
GND
IN2
1
PCH_SPI_SI_0_R RH107 1 2 33_0402_1% PCH_SPI_SI_R RH199
PCH_SPI_SO_0_R RH108 1 2 33_0402_1% PCH_SPI_SO_R 100K_0201_5%
3
XEMI@ XEMI@ PCH_SPI_IO3_0_R RH109 1 2 33_0402_1% PCH_SPI_IO3
PCH_SPI_CLK_0_R 1 2 1 2 PCH_SPI_CLK_0_R RH110 1 2 33_0402_1% PCH_SPI_CLK_R MC74VHC1G08DFT2G_SC70-5 @
2
PCH_SPI_IO2_0_R RH111 1 2 33_0402_1% PCH_SPI_IO2
RH33 CH12
0_0402_5% 68P_0402_50V8J

PCH(3/8)DDC/SPI
A
A B C D E
‧‧
#571391_CFL_H_PDG_Rev0p5
eSPI clock and eSPI data mismatched: <500 mils.
‧eSPI clock and eSPI chip select mismatched: <500 mils.
eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
UH1F
F9 BB39 LPC_AD0
<71> USB3_PTX_DRX_N1 USB31_1_TXN 1.8V GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <58>
F7 AW37 LPC Bus check straps
<71> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <58>
USB3 MB <71> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <58>
<71> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <58>
C3
<42> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<42> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <58> +3VS
1 USB3 Type C <42> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <58,66> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<42> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 RCIN#
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST# RH261 1 @ 2 0_0402_5% RCIN# 2 1 RH219
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# OVRM_EN <36,58>
C16
USB31_6_TXP CLK_LPC 10K_0402_5%
G14 BB36 RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_R <58>
F14 BB34
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1
B15 USB31_5_TXN T48
J13 USB31_5_TXP GPP_K19/SMI# T47
K13 USB31_5_RXN GPP_K18/NMI#
USB31_5_RXP
G12 AH40
<72> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 SSD_DEVSLP1
F11 AH35
<72> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <68>
USB3 MB <72> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47 +3VS
<72> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7
CONFIRM WITH SW
AN37
C14 GPP_F8/SATA_DEVSLP6 AN46
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
J15 USB31_4_TXN GPP_F6/SATA_DEVSLP4 AP48 TPM_SERIRQ 2 1 RH37
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
USB31_4_RXN 10K_0402_5%
CNP-H_BGA874 Rev1.0
LPC_PIRQA# 1 2 RH38
@
10K_0402_5%
CNP-H
2 UH1C 2
CL_CLK AR2 G36 PCIE_PRX_DTX_N9
TH10 @ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <68>
For Intel CLINK TH11 @ AT5 F36
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <68>
TH12 @ CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <68>
M.2 SSD PCIE L3
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <68>
V47 GPP_K8
V48 GPP_K9 K37 PCIE_PRX_DTX_N10
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP C35 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <68>
M.2 SSD PCIE L2
L47 B35
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <68>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <52>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 .1U_0402_16V7K PCIE_PRX_DTX_P15 <52> NGFF
N48 B40 1 2 CH1
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2
PCIE_PTX_C_DRX_N15 <52> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <52>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<68> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<68> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD PCIE L1 <68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP SATA_PRX_DTX_N4
G38 K43
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 <67>
AR42 PCIE17_RXP/SATA4_RXP A42 SATA_PTX_DRX_N4 SATA_PRX_DTX_P4 <67>
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 <67>
HDD
AR48 B42
DGPU_PRSNT# AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 <67>
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN +3VS
R40
3 CH3 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 3
<51> PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
CH4 2 1 .1U_0402_16V7K D39 D42
<51> PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
GLAN <51> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<51> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43 SATA_GP1 RH39 2 1 10K_0402_5%
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <68>
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 RH187 1 PBA@ 2 10K_0402_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 M.2 SSD PCIE/SATA select pin
AM46
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5
<68> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 @ TH13
D38 AM47 CONFIRM WITH SW
<68> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48
M.2 SSD PCIE L0 <68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
H42
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48 PCH_BKL_PW M
GPP_F21/EDP_BKLTCTL PCH_BKL_PW M <38>
B44 AV46 ENBKL
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL <58>
A44 AV44
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <38>
R37 #571391_CFL_H_PDG_Rev0p5.pdf
R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <10>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <10,58>
C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <10>
N42 AG5
PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <10>
M44 AE2
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <10>
1
CNP-H_BGA874 Rev1.0
RH43 @
10K_0402_5% UMA@ XESD@
H_PECI 0.1U_0201_10V6K 1 2 CH50
2
4 4
DGPU_PRSNT#
1
RH44
GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% VGA@ DGPU_PRSNT# 2017/10/30 2018/10/30 Title
DIS,Optimus 0 PCIE/SATA/USB3/eSPI
2
Custom 1A
UMA 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
A B C D E
+1.2V_VDDQ
<58> ME_EN 1 @ 2
RH45 0_0402_5%
2
RH208 1 2 33_0402_5% HDA_RST# RH46
<56> HDA_RST#_R HDA_BIT_CLK
<56> HDA_BIT_CLK_R RH209 1 2 33_0402_5% 470_0402_1%
RH210 1 2 33_0402_5% HDA_SDOUT
<56> HDA_SDOUT_R HDA_SYNC
<56> HDA_SYNC_R RH211 1 2 33_0402_5%
1
DRAM_RESET# 1 @ 2
DDR_DRAMRST#_R <23,24>
RH47 0_0402_5%
2 1
1 CH13 0.1U_0201_10V6K 1
100K_0201_5% 2 1RH196 HDA_BIT_CLK CNP-H @
100K_0201_5% 2 1RH197 HDA_RST# UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
intel critical net recommend <56> HDA_SDIN0 HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC @ TH14
del RF reserve cap on HDA HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# @ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33 TYPEC_3A
GPP_B1/GSPI1_CS1#/TIME_SYNC1 LAN_GPO TYPEC_3A <43>
BE29
RH48 1 CPU_DISPA_SDO GPP_B0/GSPI0_CS1# PCH_GPP_K17 LAN_GPO <51>
2 30_0402_5% AM2 R47 @ TH19
<6> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11
AN3 AP29 @ TH20
<6> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <58,78>
<6> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
FOR Jefferson Peak RESET pin is glitch free,it AV18 BB47 W AKE#
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 PM_SLP_A#
is recommended that a pull-down resistor of 75K CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SLP_LAN# @ TH37
ohm on GPP_D5(CNV_RF_RESET#) <52> CLKREQ_CNV# CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# PM_SLP_S0# @ TH21
BE16 BC28 @ TH38
<52> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3#
<56> PCH_DMIC_DATA0 BF15 BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# BE42 PM_SLP_S4# PM_SLP_S3# <58,78>
<56> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <58,78>
+RTCVCC TH22 @ AV16 BC42 @ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
TH24 @ GPP_D17/DMIC_CLK1/SNDW3_CLK
PCH_SRTCRST# BE45 SUSCLK
RH50 1 2 20K_0402_1% GPD8/SUSCLK PM_BATLOW # SUSCLK <52,68>
BF44
GPD0/BATLOW# BE35 SUSACK#_R
CH18 1 2 1U_0201_6.3V6M PCH_RTCRST# GPP_A15/SUSACK# @ T207
2 BE47 BC37 1 @ 2 2
<58> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPW RDNACK <58>
CLR ME BD46 RH51 0_0402_5%
SRTCRST#
Delay 18~25 ms
PCH_PW ROK AY42 BG44 LAN_W AKE#
PCH_RTCRST# <58,78> PCH_PW ROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R
RH52 1 2 20K_0402_1% <58> EC_RSMRST# BA47 BG42 RH53 1 @ 2 0_0402_5% AC_PRESENT <58>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS#
SLP_SUS# PBTN_OUT#_R @T208 --No Support Deep Sx
BE46 1 @ 2 0_0402_5% PBTN_OUT# <58>
CH19 1 2 1U_0201_6.3V6M PCH_DPW ROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# RH54
PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
ECLR CMOS <19> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPW RGD PCH_SPKR <19,56>
JCMOS1 1 @ 2 0_0603_5% Delay 18~25 ms BE26 AE3
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <10>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE T209
<19> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 @
BF25 AH4 CPU_XDP_TCK0 <10>
PCH_SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <10>
<19> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <10> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <10>
PCH_SML1DATA BE27 4 OF 13 AJ3 PCH_JTAG_TCK1
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <10>
CNP-H_BGA874 Rev1.0
@
RH55 2 1 1K_0402_5% W AKE#
RH56 2 1 8.2K_0402_5% PM_BATLOW # PM_SLP_S3# RH193 1 2 100K_0201_5%

PM_SLP_S4# RH194 1 2 100K_0201_5%
RH57 1 @ 2 100K_0402_5% AC_PRESENT_R

intel critical net recommend
RH58 1 @ 2 100K_0402_5% PBTN_OUT#_R
+3VS
3 EC_RSMRST# 1 @ 2 PCH_DPW ROK 3
RH59 0_0402_5%
5
G
QH7B +3VALW
2N7002KDW _SOT363-6 +3VALW _DSW
2 1 SYS_RESET#
PCH_SMBCLK D_CK_SCLK
(DDR,G-Sensor)
3 4 RH183 10K_0402_5%
S
D_CK_SCLK <23,24> LAN_W AKE# RH212 1 2 10K_0402_5%

D
+3VS
2
PCH_PW ROK RH213 1 2 10K_0402_5%

G
QH7A EC_RSMRST# RH214 1 2 10K_0402_5%

2N7002KDW _SOT363-6 100K_0402_5% 1 @ 2 RH184 SYS_PW ROK
RH60 2 1 8.2K_0402_5% PM_CLKRUN#
PCH_SMBDATA 6 1D_CK_SDATA
S
D_CK_SDATA <23,24> PCH_DPW ROK

100K_0402_5% 1 @ 2 RH61
D
RH191 2 1 2.2K_0402_5% D_CK_SCLK XESD@

RH192 2 1 2.2K_0402_5% D_CK_SDATA 0.1U_0201_10V6K 1 2 CH20 SYS_RESET# +3VALW
XESD@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%

0.1U_0201_10V6K 1 2 CH21 SYS_PW ROK
+3VALW
XESD@
0.1U_0201_10V6K 1 2 CH22 PCH_PW ROK
RH251 2 1 2.2K_0402_5% PCH_SMBCLK
RH252 2 1 2.2K_0402_5% PCH_SMBDATA XESD@
RH253 2 1 2.2K_0402_5% 100P_0402_50V8J 1 2 CH51 EC_RSMRST#
PCH_SML1CLK <27,58,66>
RH254 2 1 2.2K_0402_5% (EC,VGA,Thermal Sensor)
PCH_SML1DATA <27,58,66>
4 4
From ESD Team Request
1 2 PCH_SML0CLK Near PCH side
RH63 499_0402_1%
1 2 PCH_SML0DATA
RH64 499_0402_1%
PCH(5/8)PMU/HDA/SMBUS/DMIC
A B C D E
A B C D E
+3VALW
CNP-H
RH215 1 2 2.2K_0402_5% I2C_1_SCL UH1K
RH216 1 2 2.2K_0402_5% I2C_1_SDA
RH217 1 2 2.2K_0402_5% I2C_0_SCL GSPI1_MOSI BA26 BA20 GPP_D9
RH218 1 2 2.2K_0402_5% I2C_0_SDA BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 GPP_D10
EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PROJECT_ID0
<58> EC_SCI# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<27> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN SUB_DET
BF29 BF17
<38,58> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 CPU_ID 1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD
check for remove (PCH or Both) BB24
check needed? DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<27,58,83> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS AP24
GPU_EVENT# BA24 GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 <27> GPU_EVENT# GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PW R_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<27> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<27,37> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34
<52> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
+3VALW <52> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34
<63> I2C_1_SCL I2C_1_SDA GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
<Touch PAD> <63> BF21 BD34
GPP_H12 I2C_1_SDA I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 PANEL_OD_EN <38>
RH74 1 @ 2 4.7K_0402_5% BC22 BF35
GPP_H12 <16> I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
BF23 BD38
This signal has a weak internal pull-down. GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
STRAP
BE15
1 = Slave Attached Flash Sharing (SAFS) enabled.
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
Notes: GPP_D23/ISH_I2C2_SCL/I2C3_SCL
1. This signal is in the primary well.
Warning: This strap must be configured to ‘ 0’ i f th e CNP-H_BGA874 Rev1.0
eSPI or LPC strap is configured to ‘ 0’
@
+1.8VALW _PRIM
2 CPU_ID RH255 1 H82@ 2 1K_0402_5% 2
+3VALW RH256 1 H62@ 2 10K_0402_5%
RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <18> +1.8VALW _PRIM
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS) SUB_DET RH185 1 @ 2 1K_0402_5%
RH113 1 @ 2 4.7K_0402_5%
PCH_SML0ALERT# <18>
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected
+1.8VALW _PRIM
+1.8VALW _PRIM
RH114 1 2 150K_0402_1% GPP_D9 RH84 1 @ 2 1K_0402_5%
PCH_SML1ALERT# <18> PROJECT_ID0 RH88 1SATARD@ 2 1K_0402_5%
SML1ALERT# / GPP_B23 has an internal pull-down. RH85 1 2 10K_0402_5%
0 = Disable IntelR DCI-OOB (Default) RH89 1SATANRD@2 10K_0402_5%
*1 = Enable IntelR DCI-OOB
STRAP
GPP_D10 RH86 1 @ 2 1K_0402_5%
PROJECT_ID1 RH90 1 2 1K_0402_5%
+3VS RH87 1 2 10K_0402_5%
3 RH91 1 @ 2 10K_0402_5% 3
RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

The signal has a weak internal Pull-down.
0 = Disable “ No Reboot” mode . (Default)
1 = Enable “ No Reboot” mod e (PC H wil l disabl e th e Project_ID1 Project_ID0
TCO Timer system reboot feature). This function is Project ID
useful when running ITP/XDP.
Notes: GPP_D10 GPP_D9 GPP_D12 GPP_D11
1. The internal Pull-down is disabled after
PCH_PWROK is high.
Reserved 0 0 EH50F(2060 WO RD) 0 0
Reserved 0 1 EH50F(2060 W RD) 0 1
Reserved 1 0 EH5VF(2050 WO RD) 1 0
@ GSPI1_MOSI
RH80 1 2 150K_0402_1% STRAP for 8 Layer 1 1 *EH5VF(2050 W RD) 1 1
This Signal has a weak internal Pull-down.
0: SPI (Default)
1: LPC SCI capability is available on all GPIOs
Notes:
1. The internal Pull-down is disabled after PCH_PWROK is high. ‧‧PCHGPP_B14,
GPIOs that can be routed to generate SMI# or NMI:
GPP_B20, GPP_B23
‧‧ GPP_C[23:22]
GPP_D[4:0]
RH83 2 @ 1 100K_0402_5% PCH_SPKR ‧‧ GPP_G[7:0]

GPP_E[8:0]
GPP_I[3:0]
(support SMI# only).
PCH_SPKR <18,56>
Top Swap Override STRAP The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
0 = Disable “ Top Swap” mode. (Default
) except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
1 = Enable “ Top Swap” mode
.
4 The internal Pull-down is disabled after PCH_PWROK is high. All GPIOs have programmable internal pull-up/pull-down resistors which are off by default. 4
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.

PCH(6/8)GPIO/I2C/UART/STRAP
A B C D E
A B C D E
GPIO Group Voltage
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
@ JPH1 AA23 VCCPRIM_1P051 VCCPRIM_3P32
1 2 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
1 2 HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 GPPD 3.3V
+VCCRTCEXT
1U_0201_6.3V6M
AB22 BG47 +VCCRTCEXT * 1.8V
JUMP_43X79 AB23 VCCPRIM_1P054 DCPRTC2
1 VCCPRIM_1P055 +3VALW
CH23
AB27 V23 0.095A GPPE
VCCPRIM_1P056 VCCPRIM_3P35
0.1U_0201_10V6K
AB28 3.3V
VCCPRIM_1P057 GPPF
CH24
AB30 AN44 0.05A 1
2 AD20 VCCPRIM_1P058 VCCSPI +RTCVCC
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49
AD28 VCCPRIM_1P0511 VCCRTC2 2
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518
GPPI 3.3V Only
6.6A AC35 0.262A
6.6A U26 VCCPGPPHK1 AC36
VCCPRIM_1P0523 VCCPGPPHK2 GPPJ
22U_0603_6.3V6M
1U_0201_6.3V6M
U29 AE35 0.174A 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
1 1 VCCPRIM_1P0525 VCCPGPPEF2 +1.8VALW_PRIM
CH26
V27
VCCPRIM_1P0526 GPD
CH25
V28 AN24 0.14A 3.3V Only
V30 VCCPRIM_1P0527 VCCPGPPD AN26 +1.8VALW_PRIM
2 2 +1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0201_6.3V6M
1 1
Place Near UH1 VCCPRIM_1_0523~29 0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
3-5MM FROM PACKAGE EDGE BE48
0.42A W22 VCCDSW_3P31 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY 2
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
1 W20 Short pins AJ22,AJ23,AK22,AK23 together

VCCA_SRC_1P052
CH29
CH30
1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71

VCCDPHY_1P241
CH31
0.0198A C1 AJ23 Internal LDO

C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 RH96 1 @ 2 0_0402_5%
2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
VCCMPHY_SENSE VSSMPHY_SENSE @ TH27
0.021A B1 K46 @ TH28
B2 VCCAPLL_1P051 VSSMPHY_SENSE For DDX03 R02
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053 +1.24V_PRIM_MAR
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @
4.7U_0402_6.3V6M
1
CH32
+1.05VALW_PCH
+1.05VALW_PCH 2
+1.05VALW_PCH
0.1U_0201_10V6K
1U_0201_6.3V6M
CH34
0.1U_0201_10V6K
1 1
1U_0201_6.3V6M
CH54
1 1
CH33
+3VALW
CH35
2 2 +3VALW
2 2 +3VALW +3VALW
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE +3VALW_DSW +1.8VALW +1.8VALW_PRIM
1 1 1 1
CH36
CH39
CH37
CH38
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3
RH99 1 @ 2 0_0402_5%
2 2 2 2
0.1U_0201_10V6K
1 RH100 1 2 0_0603_5%
CH40
@
3 3
2
1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE

+1.05VALW_PCH +3VALW_HDA FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_VCCAZPLL RH101 2 @ 1 0_0402_5%
RH102 1 @ 2 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
1P_0402_50V8
1P_0402_50V8
CH41
CH42
1 1
reserved for cnvi
CH43
CH44
2 2
@ @
2 2 +1.8VALW_PRIM +1.8VALW_PRIM
@ @ reserve filter follow CRB
8/21
1-3MM FROM PACKAGE EDGE
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1
CH52
CH53
+1.05VALW_VCCAMPHYPLL
2 2
@
RH103 1 @ 2 0_0402_5%
22U_0603_6.3V6M
1U_0201_6.3V6M
1 1
CH46
CH45
+RTCBATT
2 2 change to 10k DH2 +RTCVCC +RTCBATT
near AG19/AG20
LC filter close to pin JRTC1
RH104 2 1 1K_0402_5% 2
+CHGRTC 1 1
1uF 1-3MM FROM PACKAGE EDGE 1
3 2
2
4 4
3
BAV70W_SOT323-3 GND
1U_0201_6.3V6M
0.1U_0201_10V6K
1 1 4
+1.05VALW_XTAL GND
CH48
CH47
ACES_50271-0020N-001
RH105 1 @ 2 0_0402_5% CONN@
2 2
SP02000RO00
22U_0603_6.3V6M
1
CH49
2 Issued Date 2017/10/30 Deciphered Date 2018/10/30 Title
PCH(7/8)Power
A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <10>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <10>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# PCH_TRIGOUTRH106 1 PCH_TRIGOUT_R CPU_XDP_TRST# <10>
AA27 AN38 D8 R16 AK3 2 30_0402_5%
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <13>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <13>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4

PCH(8/8)GND/RSVD
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5 4 3 2 1
5 4 3 2 1
CHANNEL-A BOT REVERSE TYPE

<7>
<7>
(4 mm)
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D0
DDR_A_D1
DDR_A_CLK1 DDR_A_D2
Interleaved Memory <7> DDR_A_CLK1 138 20

DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D3
<7> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4
4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<7> DDR_A_CKE0 DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D6
TOP: JDIMM1 CONN Non-ECC DIMM <7> DDR_A_D[0..15]
<7>
<7>
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#0
DDR_A_CS#1
149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS#0 DDR_A_DQS0 <7>
157 11
<7> DDR_A_D[16..31] <7> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <7>
D
162 D
165 S2#/C0 28 DDR_A_D8
<7> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<7> DDR_A_D[48..63] <7> DDR_A_ODT0 DDR_A_ODT1 ODT0 DQ10 DDR_A_D11
161 42
<7> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
24
JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <7> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
<7> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V_VDDQ 112 VDD1 VDD11 142 +1.2V_VDDQ <7> DDR_A_BA0 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <7> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <7>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <7>
123 VDD4 VDD14 153 <7> DDR_A_MA0 DDR_A_MA1 133 A0 50 DDR_A_D16
VDD5 VDD15 <7> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D17
124 154 132 49
129 159 131 62
130 160 128 63
135 163 126 46
+3VS VDD9 VDD19 <7> DDR_A_MA5 DDR_A_MA6 A5 DQ20 DDR_A_D21
136 127 45
VDD10 <7> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
<7> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D23
255 258 125 59
VDDSPD VTT +0.6VS_VTT <7> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<7> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2 DDR_A_DQS2 <7>
0.1U_0201_10V6K
164 257 146 53
2.2U_0402_6.3V6M
+0.6V_DDR_VREFCA VREFCA VPP1 259 +2.5V <7> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <7>
2 2 VPP2 <7> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
CD1
119 70
<7> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
CD2
1 99 158 71
VSS VSS <7> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <7> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <7>
<7>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<7> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <7> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <7>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <7>1 DDR_A_ALERT#
240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <7>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<18,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <18,24> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
VSS VSS <18,24> D_CK_SCLK SCL DQ36 DDR_A_D37
31 188 169
35 VSS VSS 189 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <7>
VSS VSS DQS4#(C) DDR_A_DQS#4 <7>
43 197
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS
VSS
VSS
VSS
213 For ECC DIMM 100 CB5_NC
CB6_NC
DQ45
DQ46
203 DDR_A_D46
DDR_A_D47
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 60 214 104 204

61 VSS VSS 217 97 CB7_NC DQ47 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#5 DDR_A_DQS5 <7>
CD3
CD4
CD5
CD6
CD7
CD8
CD9
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <7>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <7>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <7>
89 244
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 CD10 ESD@ 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
VSS VSS 33P_0201_50V8J DQ57
B 1 249 DDR_A_D58 B
262 261 DQ58 250 DDR_A_D59
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
246
0.1uF*1 CONN@
PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) DDR_A_DQS#7 DDR_A_DQS7 <7>
2 2 240
DQS7#(C) DDR_A_DQS#7 <7>
CD11 CD12
0.1U_0201_10V6K 2.2U_0402_6.3V6M
Part Number: SP07001CY00
1 1 Part Value: S SOCKET LOTES ADDR0206-P001A 260P DDR4 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 2 1K_0402_1%
CD13 @
1
0.1U_0201_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2
1 signals
330uF*1
2
+1.2V_VDDQ CD15
RD10 CD14 0.022U_0402_16V7K
2
1K_0402_1% 0.1U_0201_10V6K
1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 @ 2 @ 2 2 2 2 2 2 2 2 2
1
DDRIV_CHA: DIMM0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1A
5 4 3 2 1
5 4 3 2 1
CHANNEL-B BOT STD (4 mm)

TOP: JDIMM2 CONN Non-ECC DIMM Interleaved Memory <8> DDR_B_D[0..15]
<8> DDR_B_CLK0
<8> DDR_B_CLK#0
<8> DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM2A
CK0(T)
CK0#(C)
CK1(T)
STD
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
<8> DDR_B_CLK#1 CK1#(C) DQ3 4 DDR_B_D4
<8> DDR_B_D[16..31] DDR_B_CKE0 DQ4 DDR_B_D5
109 3
<8> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D6
<8> DDR_B_D[32..47] <8> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D7
DDR_B_CS#0 149 DQ7 13 DDR_B_DQS0
D <8> DDR_B_D[48..63] <8> DDR_B_CS#0 DDR_B_CS#1 157 S0# DQS0(T) 11 DDR_B_DQS#0 DDR_B_DQS0 <8> D
<8> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#0 <8>
JDIMM2B
STD 165 S2#/C0 28 DDR_B_D8
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ 112 VDD1 VDD11 142
+1.2V_VDDQ DDR_B_ODT0 155 DQ9 41 DDR_B_D11
VDD2 VDD12 <8> DDR_B_ODT0 DDR_B_ODT1 ODT0 DQ10 DDR_B_D15
117 147 161 42
118 VDD3 VDD13 148 <8> DDR_B_ODT1 ODT1 DQ11 24 DDR_B_D14
123 VDD4 VDD14 153 DDR_B_BG0 115 DQ12 25 DDR_B_D10
124 VDD5 VDD15 154 <8> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
VDD6 VDD16 <8> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
129 159 150 37
130 VDD7 VDD17 160 <8> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
135 VDD8 VDD18 163 <8> DDR_B_BA1 BA1 DQS1(T) 32 DDR_B_DQS#1 DDR_B_DQS1 <8>
+3VS VDD9 VDD19 DDR_B_MA0 DQS1#(C) DDR_B_DQS#1 <8>
136 144
VDD10 <8> DDR_B_MA0 DDR_B_MA1 A0 DDR_B_D16
133 50
<8> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <8> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
0.1U_0201_10V6K
164 257 128 63
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D22
2 2 VPP2 <8> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
CD33
127 45
CD34
1 99 122 58
VSS VSS <8> DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D21
2 102 125 59
1 1 VSS VSS <8> DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS <8> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <8>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <8> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <8>
VSS VSS <8> DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <8> DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D30
DDR_B_D25
VSS VSS <8> DDR_B_MA13 DDR_B_MA14_WE# A13 DQ25 DDR_B_D26
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <8>
<8>
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84 DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<8> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D27
DDR_B_ACT# DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26 VSS
VSS
VSS
VSS
180
181 <8> DDR_B_ACT#
DDR_B_PAR
114
ACT# DQ30
DQ31
79
80 DDR_B_D31
DDR_B_DQS3
27 184 143 76
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <8> DDR_B_PAR
<8> DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<8>
<8>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
VSS VSS <18,23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <18,23> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
VSS VSS <18,23> D_CK_SCLK SCL DQ36 DDR_B_D38
44 201 169
47 VSS VSS 202 +3VS 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <8>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <8>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40 DDR_B_D41
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 60 214 91 194
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42 DDR_B_D43
CD35
CD36
CD37
CD38
CD39
CD40
CD41
64 218 105 208

2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D46
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_B_DQS#5 DDR_B_DQS5 <8>
77 231 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_B_DQS#5 <8>
78 234
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
Layout Note: VSS VSS DM6#/DBI6# DQ55 DDR_B_DQS6
98 252 241 221
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <8>
FROM THE JDIMM3 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <8>
262 261
GND GND
B LOTES_ADDR0205-P001A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57 DDR_B_D60
+0.6V_DDRB_VREFCA 249
2.2uF*1 DQ58 DDR_B_D56
250
0.1uF*1 DQ59 232 DDR_B_D62
Part Number: SP07001HW00 DQ60 233 DDR_B_D59
2 2 DQ61
Part Value: S SOCKET LOTES ADDR0205-P001A DDR4 STD 261
GND1 DQ62
245 DDR_B_D63
DDR_B_D58
CD42 CD43 262 246
GND2 DQ63 242 DDR_B_DQS7
0.1U_0201_10V6K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <8>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
DQS7#(C) DDR_B_DQS#7 <8>
LOTES_ADDR0205-P001A
CONN@
2
Layout Note: DIMM Side CPU Side
2
CD44 @
Place near JDIMM3 0.1U_0201_10V6K RD19
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 1
signals
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RD21 CD45
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD51 1K_0402_1% 0.1U_0201_10V6K CD55

1
CD46
CD47
CD48
CD49
CD50
CD52
CD53
CD54
0.1U_0201_10V6K 0.022U_0402_16V7K
1 2
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@ @ RD22
24.9_0402_1%
1
DDRIV_CHB: DIMM0
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
+1.8VSDGPU_AON
VGA_OVERT# RV327 2 VGA@ 1 10K_0201_5%

UV1A VGA_ALERT# RV328 2 VGA@ 1 10K_0201_5%
FRM_LCK# RV329 2 VGA@ 1 10K_0201_5%
AN12 Part 1 of 7 ACIN_BUF RV330 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P0 PEX_RX0 GPU_EVENT#_1
AM12 P6 RV331 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N0 PEX_RX0_N GPIO0 GC6_FB_EN1V8 NVVDD_VID <95> 1.8VSDGPU_MAIN_EN
AN14 M3 VGA@ RV1 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P1 PEX_RX1 GPIO1 GPU_EVENT#_1 NVVDD_PSI
AM14 L6 DV8 2 1 RV4 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N1 PEX_RX1_N GPIO2 GPU_EVENT# <19>
AP14 P5
<9> PEG_CTX_C_GRX_P2 PEX_RX2 GPIO3 1.8VSDGPU_MAIN_EN SYS_PEX_RST_MON#
AP15 P7 RB751S40T1G_SOD523-2 RV332 2 N17P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N2 PEX_RX2_N GPIO4 FRM_LCK# GPU_PEX_RST_HOLD#
AN15 L7 RV82 2 N17P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P3 PEX_RX3 GPIO5
AM15 M7
<9> PEG_CTX_C_GRX_N3 PEX_RX3_N GPIO6 NVVDD_PSI <95> FBVDDQ_PSI
AN17 N8 RV335 2 N18P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_P4 PEX_RX4 GPIO7 GPIO22_OC_WARN#
AM17 L3 RV386 2 N18P@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N4 PEX_RX4_N GPIO8 VGA_ALERT# VRAM_VDD_CTL <93>
AP17 M2
AP18 L1
1 <9> PEG_CTX_C_GRX_N5 PEX_RX5_N GPIO10 VRAM_VREF_CTL <32,33> VGA_I2CS_SDA 1
AN18 M5 RV2 1 VGA@ 2 1.8K_0402_1%
<9> PEG_CTX_C_GRX_P6 PEX_RX6 GPIO11 ACIN_BUF VGA_I2CS_SCL
AM18 N3 DV2 2 1 RV3 1 VGA@ 2 1.8K_0402_1%
<9> PEG_CTX_C_GRX_N6 PEX_RX6_N GPIO12
GPIO
AN20 M4 VGA@ DGPU_AC_DETECT <19,58,83>
<9> PEG_CTX_C_GRX_P7 PEX_RX7 GPIO13 VGA_I2CC_SDA
AM20 N4 RB751S40T1G_SOD523-2 RV5 1 VGA@ 2 2K_0402_5%
<9> PEG_CTX_C_GRX_N7 PEX_RX7_N GPIO14 VGA_I2CC_SCL
AP20 P2 RV6 1 VGA@ 2 2K_0402_5%
<9> PEG_CTX_C_GRX_P8 PEX_RX8 GPIO15 SYS_PEX_RST_MON#
AP21 R8
AN21 M6
AM21 R1
<9> PEG_CTX_C_GRX_N9 PEX_RX9_N GPIO18 NVVDD_PSI
AN23 P3 RV398 2 @ 1 10K_0201_5%
AM23 P4
<9> PEG_CTX_C_GRX_N10 PEX_RX10_N GPIO20 VRAM_VREF_CTL
AP23 P1 RV333 2 VGA@ 1 100K_0201_5%
<9> PEG_CTX_C_GRX_P11 PEX_RX11 GPIO21 GC6_FB_EN1V8
AP24 P8 RV334 2 VGA@ 1 10K_0201_5%
<9> PEG_CTX_C_GRX_N11 PEX_RX11_N GPIO22 GPU_PEX_RST_HOLD# GPIO22_OC_WARN# <36>
AN24 T8
<9> PEG_CTX_C_GRX_P12 PEX_RX12 GPIO23 GPU_PEX_RST_HOLD#
AM24 L2 RV396 2 N18P@ 1 100K_0201_5%
AN26 R4
<9> PEG_CTX_C_GRX_P13 PEX_RX13 GPIO25 FBVDDQ_PSI <93>
AM26 R5
<9> PEG_CTX_C_GRX_N13 PEX_RX13_N GPIO26 HDMI_HPD_GPU# GPIO26_FP_FUSE <37>
AP26 U3
AP27
<9> PEG_CTX_C_GRX_N14 PEX_RX14_N +1.8VSDGPU_MAIN +1.8VSDGPU_MAIN
AN27
<9> PEG_CTX_C_GRX_P15 PEX_RX15
AM27
<9> PEG_CTX_C_GRX_N15 PEX_RX15_N
QV13A N18P@ QV2A VGA@
5
AK14 AN9 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
<9> PEG_CRX_C_GTX_P0 PEX_TX0 ADC_IN ADC_IN_P <36>
AJ14 AM9
G
<9>
<9>
PEG_CRX_C_GTX_N0
PEG_CRX_C_GTX_P1
AH14 PEX_TX0_N OVR-M ADC_IN_N ADC_IN_N <36> VGA_I2CC_SCL 4 3
VGA_I2CC_SCL_PWR <95>
VGA_I2CS_SCL 4 3
PCH_SML1CLK <18,58,66>
PEX_TX1 +1.8VSDGPU_AON
D
<9> PEG_CRX_C_GTX_N1 AG14
AK15 PEX_TX1_N
<9> PEG_CRX_C_GTX_P2 PEX_TX2 TS_AVDD RV385 1 N18P@ 2 0_0402_5%
<9> PEG_CRX_C_GTX_N2
AJ15 AG10 QV13B N18P@ QV2B VGA@
PEX_TX2_N TS_AVDD
2
AL16 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
<9> PEG_CRX_C_GTX_P3 PEX_TX3
AK16 CV377 1 2 1U_0201_6.3V6M
Thermal Sensor
G
<9> PEG_CRX_C_GTX_N3 PEX_TX3_N VGA_I2CC_SDA VGA_I2CS_SDA
<9> PEG_CRX_C_GTX_P4 AK17 1 6 VGA_I2CC_SDA_PWR <95> 1 6 PCH_SML1DATA <18,58,66>
AJ17 PEX_TX4
D
<9> PEG_CRX_C_GTX_N4 N18P@
AH17 PEX_TX4_N
<9> PEG_CRX_C_GTX_P5 PEX_TX5
AG17 AK9
<9> PEG_CRX_C_GTX_N5
RES
AK18 PEX_TX5_N RES AL10 27MHZ_10PF_XRCGB27M000F2P18R0
<9> PEG_CRX_C_GTX_P6 PEX_TX6 RES
<9> PEG_CRX_C_GTX_N6 AJ18 AL9 RV80 VGA@ XV1
AL19 PEX_TX6_N RES AP8 470_0402_1%
<9> PEG_CRX_C_GTX_P7 PEX_TX7 RES
AK19 XTALOUT 2 1 XTALOUT_R 1 3 XTALIN
PCI EXPRESS
<9> PEG_CRX_C_GTX_N7 PEX_TX7_N 1 3

AK20
<9> PEG_CRX_C_GTX_P8 PEX_TX8 +1.8VSDGPU_AON NC NC
AJ20 AP9 1 1
<9> PEG_CRX_C_GTX_N8 PEX_TX8_N TS_VREF
<9> PEG_CRX_C_GTX_P9 AH20
AG20 PEX_TX9 unused pin PH 2K to 1V8AON CV1 VGA@ VGA@ 2 4 CV2 VGA@
2 <9> PEG_CRX_C_GTX_N9 PEX_TX9_N 2
AK21 R7 RV86 1 VGA@ 2 2K_0402_5% 18P_0402_50V8J 18P_0402_50V8J
<9> PEG_CRX_C_GTX_P10 PEX_TX10 I2CB_SCL 2 2
AJ21 R6 RV85 1 VGA@ 2 2K_0402_5%
<9> PEG_CRX_C_GTX_N10 PEX_TX10_N I2CB_SDA
AL22
<9> PEG_CRX_C_GTX_P11 PEX_TX11 VGA_I2CC_SCL +1.8VSDGPU_MAIN
AK22 R2 Crystals must have a max ESR of 80 ohm
I2C
<9> PEG_CRX_C_GTX_N11 PEX_TX11_N I2CC_SCL VGA_I2CC_SDA

AK23 R3
<9> PEG_CRX_C_GTX_P12 PEX_TX12 I2CC_SDA
AJ23 SM01000JX00
<9> PEG_CRX_C_GTX_N12 PEX_TX12_N VGA_I2CS_SCL +GPU_PLLVDD
<9> PEG_CRX_C_GTX_P13
AH23 T4 3000ma 33ohm@100mhz DCR 0.04
AG23 PEX_TX13 I2CS_SCL T3 VGA_I2CS_SDA +1.8VSDGPU_AON +1.8VSDGPU_AON
<9> PEG_CRX_C_GTX_N13 PEX_TX13_N I2CS_SDA
<9> PEG_CRX_C_GTX_P14 AK24 VGA@
AJ24 PEX_TX14 LV1 1 2
<9> PEG_CRX_C_GTX_N14 PEX_TX14_N
1
<9> PEG_CRX_C_GTX_P15
AL25 TAI-TECH HCB1608KF-330T30 VGA@ VGA@
PEX_TX15
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
22U_0603_6.3V6M
AK25 H26 1 1 1 1 1 1 SM01000JX00 CG340 RG180
<9> PEG_CRX_C_GTX_N15 PEX_TX15_N GPCPLL_AVDD
CV195 VGA@
CV5 VGA@
CV6 VGA@
CV3 VGA@
CV42 CV4 2 1 10K_0201_5%
AD8
AJ11 XSN_PLLVDD VGA@ VGA@ 0.1U_0201_10V6K
No support S0ix
2
PEX_WAKE#
5
AE8 2 2 2 2 2 2 HDMI_HPD_GPU#
AL13 SP_PLLVDD
Near
VCC
<15> CLK_PEG_VGA PEX_REFCLK
6
AK13 AD7 GPU 1
<15> CLK_PEG_VGA# VGA_CLKREQ#_R PEX_REFCLK_N VID_PLLVDD <16,40> HDMI_HPD_PCH IN B D
AK12 Near Near Near Near 4 2 G QV5B
+1.8VSDGPU_AON PEX_CLKREQ_N PLTRST_VGA#_1V8 2 OUT Y PJT138KA 2N SOT363-6
H26 AD7 AD8 AE8
GND
IN A 1 S
CLK
RV7 1 VGA@ 2 10K_0201_5% AJ26 H3 XTALIN @ VGA@
1
AK26 NC XTAL_IN H2 XTALOUT CV201
NC XTAL_OUT VGA@ 0.1U_0201_10V6K
3
PLTRST_VGA#_1V8 AJ12 J4 XTAL_OUTBUFF RV9 1 VGA@ 2 100K_0201_5% UG28 2
1 2 PEX_TREMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN RV11 1 VGA@ 2 10K_0201_5% NL17SZ08DFT2G_SC70-5
PEX_TERMP EXT_REFCLK_FL
RV10 VGA@
2.49K_0402_1%
N18P-G0_FCBGA960~D
@
+1.8VSDGPU_AON +1.8VSDGPU_AON
PU at PCH side
2
UV11
VGA_CLKREQ# <15>
VGA@ RV83 @
5
NL17SZ08DFT2G_SC70-5 10K_0201_5%
VCC
3
1VSDGPU_PG 1 QV5A
1
IN B 4 ALL_GPWRGD 5 G
D
PJT138KA 2N SOT363-6
2 OUT Y VGA@
GND
<93> 1.35VSDGPU_PG IN A 1 S
3 VGA@ 3
4
CV226
0.1U_0201_10V6K
3
2 VGA_CLKREQ#_R
+1.8VSDGPU_AON
+1.8VSDGPU_AON
1
UV2
NL17SZ08DFT2G_SC70-5 RV100 @
5
VGA@ 10K_0201_5%
+3VS
VCC
PLT_RST# 1.8VSDGPU_MAIN_EN3V3 <37>

1
<16,58,66> PLT_RST#
2
IN B 4 PLTRST_VGA#_1V8
DGPU_HOLD_RST# 2 OUT Y +3VS
GND
<19> DGPU_HOLD_RST# IN A
1
RV16 1 VGA@ 2 100K_0201_5%
RV106 VGA@
3
CV200 1 2 0.1U_0201_10V6K 100K_0201_5% RV108 UV10 VGA@
5
VGA@ VGA@ 10K_0201_5% NL17SZ08DFT2G_SC70-5
VCC
2
2
1
IN B 4
OUT Y GPUCORE_EN <37>
3
2
GND
5 G
D
IN A
6
S
1.8VSDGPU_MAIN_EN 2 G
D
QV7A
3
QV7B S VGA@ @
PJT138KA 2N SOT363-6 DV4 2 1
DGPU_PWR_EN <19,37> NVVDD1_EN <37,95>
1
VGA@
RB751S40T1G_SOD523-2
2 1
RV105 2
12K_0402_1%
VGA@ CV197 VGA@
GC6 2.0 function +1.8VSDGPU_MAIN 0.22U_0402_16V7K
GPU_OVERT# DV7 1 2 1
+3VS DV3
1
GC6_FB_EN3V3 2 RB751S40T1G_SOD523-2 VGA@

PU at EC side
1 RV131 VGA@ DV5 1 2
1.35VSDGPU_EN <37,93> GPU_OVERT# <58> 1VSDGPU_EN <94>
1
3 VGA@ 100K_0201_5%
<94> 1VSDGPU_PG
RV113 VGA@ VGA@ RB751S40T1G_SOD523-2
1
4 10K_0201_5% BAV70W_SOT323-3 4
6 2
5 1 2
D
RV111 VGA@ RV12 G QV1A
100K_0201_5% 100K_0201_5% S
PJT138KA 2N SOT363-6 RV103
3 2
GC6_FB_EN3V3 VGA@ VGA_OVERT# 2

D
VGA@ 28.7K_0402_1% 2
G
GC6_FB_EN3V3 <19> <29> VGA_OVERT#
4
S VGA@
6 2
D
5 G QV1B CV196 VGA@
1
S PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6 0.22U_0402_16V7K

GC6_FB_EN1V8 2 G
D
QV8A VGA@ 1
4
QV8B S VGA@
1
VGA@

N17P PEG 1/7
A B C D E
A B C D E
GDDR5 Mode H Mapping

UV1B UV1C
<32> FBA_D[63..0] FBA_CMD[31..0] <32> <33> FBB_D[63..0] FBB_CMD[31..0] <33> DATA Bus
Part 2 of 7 Part 3 of 7
FBA_D0 L28 U30 FBA_CMD0 FBB_D0 G9 D13 FBB_CMD0 Address
FBA_D1 FBA_D0 FBA_CMD0 FBA_CMD1 FBB_D1 FBB_D0 FBB_CMD0 FBB_CMD1
0..31 32..63
M29 T31 E9 E14
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_CMD2 FBB_D2 G8 FBB_D1 FBB_CMD1 F14 FBB_CMD2
CMD0 CS#
M28 R34 F9 A12
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_CMD4 FBB_D4 F11 FBB_D3 FBB_CMD3 B12 FBB_CMD4
CMD1 A3_BA3
P29 U32 G11 C14
FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_CMD6 FBB_D6 F12 FBB_D5 FBB_CMD5 B14 FBB_CMD6
CMD2 A2_BA0
P28 U28 G12 G15
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_CMD8 FBB_D8 G6 FBB_D7 FBB_CMD7 F15 FBB_CMD8
CMD3 A4_BA2
H29 V29 F5 E15
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_CMD10 FBB_D10 E6 FBB_D9 FBB_CMD9 D15 FBB_CMD10
1 FBA_D11 FBA_D10 FBA_CMD10 FBA_CMD11 FBB_D11 FBB_D10 FBB_CMD10 FBB_CMD11
CMD4 A5_BA1 1
H28 U34 F6 A14
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_CMD12 FBB_D12 F4 FBB_D11 FBB_CMD11 D14 FBB_CMD12
CMD5 WE#
E31 V34 G4 A15
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CMD14 FBB_D14 E2 FBB_D13 FBB_CMD13 B15 FBB_CMD14
CMD6 A7_A8
F30 Y32 F3 C17
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CMD16 FBB_D16 C2 FBB_D15 FBB_CMD15 D18 FBB_CMD16
CMD7 A6_A11
D32 AA29 D4 E18
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_CMD18 FBB_D18 D3 FBB_D17 FBB_CMD17 F18 FBB_CMD18
CMD8 ABI#
C33 AC34 C1 A20
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_CMD20 FBB_D20 B3 FBB_D19 FBB_CMD19 B20 FBB_CMD20
CMD9 A12_RFU
F32 AA32 C4 C18
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_CMD22 FBB_D22 B5 FBB_D21 FBB_CMD21 B18 FBB_CMD22
CMD10 A0_A10
H32 Y28 C5 G18
FBA_D24 P34 FBA_D23 FBA_CMD23 Y29 FBA_CMD24 FBB_D24 A11 FBB_D23 FBB_CMD23 G17 FBB_CMD24
CMD11 A1_A9
P32 W31 C11 F17
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_CMD26 FBB_D26 D11 FBB_D25 FBB_CMD25 D16 FBB_CMD26
CMD12 RAS#
P33 AA34 B11 A18
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_CMD28 FBB_D28 D8 FBB_D27 FBB_CMD27 D17 FBB_CMD28
CMD13 RST#
L34 Y34 A8 A17
MEMORY INTERFACE B
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CMD30 FBB_D30 C8 FBB_D29 FBB_CMD29 B17 FBB_CMD30
CMD14 CKE#
L33 V31 B8 E17
FBA_D32 AG28 FBA_D31 FBA_CMD31 R28 FBB_D32 F24 FBB_D31 FBB_CMD31 G14
FBA_D33 FBA_D32 FBA_CMD32 FBB_D33 FBB_D32 FBB_CMD32 CMD15 CAS#
AF29 AC28 G23 G20
FBA_D34 AG29 FBA_D33 FBA_CMD33 R32 FBB_D34 E24 FBB_D33 FBB_CMD33 C12
FBA_D35 FBA_D34 FBA_CMD34 FBB_D35 FBB_D34 FBB_CMD34 CMD16 CS#
AF28 AC32 G24 C20
FBA_D36 AD30 FBA_D35 FBA_CMD35 FBB_D36 D21 FBB_D35 FBB_CMD35
FBA_D37 FBA_D36 FBB_D37 FBB_D36 CMD17 A3_BA3
AD29 E21
FBA_D38 AC29 FBA_D37 FBB_D38 G21 FBB_D37
AD28 F21
FBA_D40 AJ29 FBA_D39 FBB_D40 G27 FBB_D39
AK29 D27
FBA_D42 AJ30 FBA_D41 FBB_D42 G26 FBB_D41
AK28 E27
MEMORY INTERFACE
FBA_D44 AM29 FBA_D43 FBB_D44 E29 FBB_D43

FBA_D45 FBA_D44 FBB_D45 FBB_D44 CMD21 WE#
AM31 R30 F29 D12
2 FBA_D46 FBA_D45 FBA_CLK0 FBA_CLKA0 <32> FBB_D46 FBB_D45 FBB_CLK0 FBB_CLKA0 <33> 2
AN29 R31 E30 E12 CMD22 A7_A8
FBA_D47 FBA_D46 FBA_CLK0_N FBA_CLKA0# <32> FBB_D47 FBB_D46 FBB_CLK0_N FBB_CLKA0# <33>
AM30 AB31 D30 E20
FBA_D48 FBA_D47 FBA_CLK1 FBA_CLKA1 <32> FBB_D48 FBB_D47 FBB_CLK1 FBB_CLKA1 <33>
AN31 AC31 A32 F20 CMD23 A6_A11
FBA_D49 FBA_D48 FBA_CLK1_N FBA_CLKA1# <32> FBB_D49 FBB_D48 FBB_CLK1_N FBB_CLKA1# <33>
AN32 C31
FBA_D50 AP30 FBA_D49 FBB_D50 C32 FBB_D49
FBA_D51 FBA_D50 FBB_D51 FBB_D50 CMD24 ABI#
AP32 B32
FBA_D52 AM33 FBA_D51 K31 FBB_D52 D29 FBB_D51 F8
FBA_D53 FBA_D52 FBA_WCK01 FBA_WCK01 <32> FBB_D53 FBB_D52 FBB_WCK01 FBB_WCK01 <33> CMD25 A12_RFU
AL31 L30 A29 E8
FBA_D54 FBA_D53 FBA_WCK01_N FBA_WCK01# <32> FBB_D54 FBB_D53 FBB_WCK01_N FBB_WCK01# <33>
AK33 H34 C29 A5 CMD26 A0_A10
FBA_D55 FBA_D54 FBA_WCK23 FBA_WCK23 <32> FBB_D55 FBB_D54 FBB_WCK23 FBB_WCK23 <33>
AK32 J34 B29 A6
AD34 AG30 B21 D24 CMD27 A1_A9
FBA_D57 FBA_D56 FBA_WCK45 FBA_WCK45 <32> FBB_D57 FBB_D56 FBB_WCK45 FBB_WCK45 <33>
AD32 AG31 C23 D25
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK45# <32> FBB_D58 A21 FBB_D57 FBB_WCK45_N B27 FBB_WCK45# <33>
FBA_D59 FBA_D58 FBA_WCK67 FBA_WCK67 <32> FBB_D59 FBB_D58 FBB_WCK67 FBB_WCK67 <33> CMD28 RAS#
A
AD33 AK34 C21 C27

AF31 B24 CMD29 RST#
FBA_D61 AG34 FBA_D60 FBB_D61 C24 FBB_D60
FBA_D62 AG32 FBA_D61 FBB_D62 B26 FBB_D61
FBA_D63 FBA_D62 FBB_D63 FBB_D62 CMD30 CKE#
AG33 J30 C26 D6
FBA_D63 FBA_WCKB01 J31 FBB_D63 FBB_WCKB01 D7
<32> FBA_DBI[7..0] FBA_DBI0 FBA_WCKB01_N <33> FBB_DBI[7..0] FBB_DBI0 FBB_WCKB01_N CMD31 CAS#
P30 J32 E11 C6
FBA_DBI1 F31 FBA_DQM0 FBA_WCKB23 J33 FBB_DBI1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DBI2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBB_DBI2 A3 FBB_DQM1 FBB_WCKB23_N F26
FBA_DBI3 M32 FBA_DQM2 FBA_WCKB45 AJ31 FBB_DBI3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DBI4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 FBB_DBI4 F23 FBB_DQM3 FBB_WCKB45_N A26
FBA_DBI5 AL29 FBA_DQM4 FBA_WCKB67 AJ33 FBB_DBI5 F27 FBB_DQM4 FBB_WCKB67 A27
FBA_DBI6 AM32 FBA_DQM5 FBA_WCKB67_N FBB_DBI6 C30 FBB_DQM5 FBB_WCKB67_N
FBA_DBI7 AF34 FBA_DQM6 FBB_DBI7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
<32> FBA_EDC[7..0] FBA_EDC0 <33> FBB_EDC[7..0] FBB_EDC0
M31 D10
FBA_EDC1 G31 FBA_DQS_WP0 +1.8VSDGPU_MAIN FBB_EDC1 D5 FBB_DQS_WP0
FBA_EDC2 E33 FBA_DQS_WP1 FBB_EDC2 C3 FBB_DQS_WP1
FBA_EDC3 M33 FBA_DQS_WP2 VGA@ FBB_EDC3 B9 FBB_DQS_WP2
FBA_EDC4 AE31 FBA_DQS_WP3 K27 +FB_PLLAVDD LV3 1 2 FBB_EDC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
FBA_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD TAI-TECH HCB1608KF-330T30 FBB_EDC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD
FBA_EDC6 AN33 FBA_DQS_WP5 FBB_EDC6 FBB_DQS_WP5
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
1 1 1 1 SM01000JX00 B30 1 1
FBA_EDC7 AF33 FBA_DQS_WP6 FBB_EDC7 FBB_DQS_WP6
CV9 VGA@
CV10 VGA@
CV11 VGA@
CV379 VGA@
CV7 VGA@
CV12 VGA@
3 A23 3
FBA_DQS_WP7 U27 FBB_DQS_WP7
FBA_PLL_AVDD SM01000JX00
M30 3000ma 33ohm@100mhz DCR 0.04 D9
H30 RES 2 2 2 2 E4 RES 2 2
E34 RES B2 RES
M34 RES H31 FB_VREF A9 RES
AF30 RES FB_VREF D22 RES
AK31 RES D28 RES
RES Near Near RES Near
AM34 U27 K27 A30 H17
AF32 RES B23 RES
RES RES
N18P-G0_FCBGA960~D N18P-G0_FCBGA960~D
@ @
+1.35VSDGPU FB_VREF
+1.35VSDGPU
1
FBA_CMD14
3.9P_0402_50V8C
CV378
49.9_0402_1%
RV393
2 VGA@ 1 1
RV87 10K_0402_5% FBB_CMD14 2 VGA@ 1
FBA_CMD30 2 VGA@ 1 RV91 10K_0402_5%
CKE FBB_CMD30
RV88 10K_0402_5% signal 2 VGA@ 1
2
N18P@
N18P@
RV92 10K_0402_5%
2
FBA_CMD13 2 VGA@ 1
RV89 10K_0402_5% FBB_CMD13 2 VGA@ 1
FBA_CMD29 2 VGA@ 1 RV93 10K_0402_5%
RST
RV90 10K_0402_5% FBB_CMD29 2 VGA@ 1
signal
RV94 10K_0402_5%
4 4

N17P VRAM 2/7
A B C D E
A B C D E
UV1D
Part 4 of 7
AM6
IFPA_L3 +1.8VSDGPU_AON
MULTI LEVEL
AN6
AP3 IFPA_L3_N
IFPA_L2 NC
AC6 +1.8VSDGPU_MAIN STRAPS
AN3 AJ28
AN5 IFPA_L2_N NC AJ4
AM5 IFPA_L1 NC AJ5 strap0 strap1 strap2 strap3 strap4 strap5
AL6 IFPA_L1_N NC AL11
IFPA_L0 NC
2
AK6 C15 RV26 RV27 RV78 RV31 RV32
AJ6 IFPA_L0_N NC D19 100K_0402_5% 100K_0402_5% RV28 RV29 RV30 100K_0402_5% 100K_0402_5% 100K_0402_5% RV33
AH6 IFPA_AUX_SCL NC D20 @ @ 100K_0201_5% 100K_0201_5% 100K_0201_5% @ N17P@ N17P@ 100K_0201_5%
NC
IFPA_AUX_SDA_N NC D23 @ VGA@ @ N17P@
NC D26
1
AJ9 NC
AH9 IFPB_L3
1 IFPB_L3_N 1
AP6 V32 STRAP0
AP5 IFPB_L2 NC STRAP1 ROM_SI
AM7 IFPB_L2_N STRAP2 ROM_SO
AL7 IFPB_L1 STRAP3 ROM_SCLK
AN8 IFPB_L1_N STRAP4
AM8 IFPB_L0 STRAP5
AK8 IFPB_L0_N
IFPB_AUX_SCL
2
AL8
IFPB_AUX_SDA_N
2
L4 RV34 RV35 RV79 RV39
VDD_SENSE NVVDD1_VCC_SENSE <95> 100K_0402_5% 100K_0402_5% RV36 RV37 RV38 100K_0402_5% 100K_0402_5% RV40 RV41
AK1 @ @ 100K_0201_5% 100K_0201_5% 100K_0201_5% VGA@ N18P@ 10K_0402_5% 100K_0201_5%
<40> GPU_DP2_P0 AJ1 IFPC_L0 @ @ VGA@ N18P@ N18P@
<40> GPU_DP2_N0
1
AJ3 IFPC_L0_N L5
<40> GPU_DP2_P1 NVVDD1_VSS_SENSE <95>
1
IFPC_L1 GND_SENSE
HDMI <40>
<40>
GPU_DP2_N1
GPU_DP2_P2
AJ2
AH3 IFPC_L1_N
IFPC_L2
TMDS
AH4
X76 BOM
2.0 <40>
<40>
<40>
GPU_DP2_N2
GPU_DP2_P3
GPU_DP2_N3
AG5
AG4
IFPC_L2_N
IFPC_L3
IFPC_L3_N
TEST +1.8VSDGPU_AON
AM1 AK11 TESTMODE RV42 1 VGA@ 2 10K_0402_5%
AM2 IFPD_L0 NVJTAG_SEL +1.8VSDGPU_AON
AM3 IFPD_L0_N AM10 JTAG_TCK_VGA @ TV5
AM4 IFPD_L1 JTAG_TCK AM11 JTAG_TDI @ TV6
AL3 IFPD_L1_N JTAG_TDI AP12 JTAG_TDO @ TV7
IFPD_L2 JTAG_TDO
1
AL4 AP11 JTAG_TMS @ TV8
IFPD_L2_N JTAG_TMS JTAG_RST 1
AK4 AN11 RV43 1 VGA@ 2 10K_0402_5% RV336 N18P@ CV355 N18P@
AK5 IFPD_L3 JTAG_TRST_N N18P@ 10K_0402_5% 0.1U_0201_10V6K
IFPD_L3_N RV337
33_0402_5% UV49 2 N18P@
2
AD2 ROM_CS# 1 2 ROM_CS_R# 1 8 RV339
AD3 IFPE_L0 ROM_SO 1 2 ROM_SO_R 2 CS# VCC 7 33_0402_5%
AD1 IFPE_L0_N 3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R 1 2 ROM_SCLK
AC1 IFPE_L1 SERIAL RV338 @ 4 WP#(IO2) CLK 5 ROM_SI_R 1 2 ROM_SI
AC2 IFPE_L1_N H6 ROM_CS# 0_0402_5% GND DI(IO0)
2 AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK W25Q80EWSSIG_SO8 RV340 2
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI N18P@ 33_0402_5%
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO SA00009QP00 N18P@
AE3
AE4 NC DGPU VBIOS ROM 8Mb
AF4 NC
AF5 NC
AD4 NC GENERAL
AD5 NC E1 GPU_BUFRST# @ TV9
AG1 NC BUFRST_N
AF1 NC M1
NC OVERT VGA_OVERT# <27>
AG3
<40> GPU_DP2_CTRL_CLK IFPC_AUX_SCL
AG2
<40> GPU_DP2_CTRL_DAT IFPC_AUX_SDA_N J2 STRAP0
STRAP0 J7 STRAP1
AK3 STRAP1 J6 STRAP2
AK2 IFPD_AUX_SCL STRAP2 J5 STRAP3
IFPD_AUX_SDA_N STRAP3 J3 STRAP4
STRAP4 J1 STRAP5
AB3 STRAP5
AB4 IFPE_AUX_SCL
IFPE_AUX_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 NC
NC
N18P-G0_FCBGA960~D
3 3
@
SMB_ATL_ADDR
* LOW Single GPU

High Dual GPU
DEVID_SEL
4 4
* LOW Orig. Device ID
High Support G-Sync GPUID
VGA_DEVICE
LOW 3D Device
High VGA Device
*
PCIE_CFG Security Classification Compal Secret Data Compal Electronics, Inc.
* LOW Normal signal swing Issued Date 2017/10/30 Deciphered Date 2018/10/30 Title
High Reduce the signal amplitude
N17P STRAP 3/7
A B C D E
A B C D E
+1.35VSDGPU CHA
/6*1uF+2*10uF
Under
GPU
2*22uF+3*10uF+3*4.7uF+6*1uF
0.47U_0201_6.3V6K
CV395
0.47U_0201_6.3V6K
CV396
1U_0201_6.3V6M
CV18
1U_0201_6.3V6M
CV19
1U_0201_6.3V6M
CV20
1U_0201_6.3V6M
CV21
1U_0201_6.3V6M
CV22
1U_0201_6.3V6M
CV23
10U_0402_6.3V6M
CV24
10U_0402_6.3V6M
CV26
1 1 1 1 1 1 1 1 1 1 Under Near
+1.0VSDGPU
GPU GPU
2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1U_0201_6.3V6M
CV134
1U_0201_6.3V6M
CV13
1U_0201_6.3V6M
CV14
1U_0201_6.3V6M
CV33
1U_0201_6.3V6M
CV385
1U_0201_6.3V6M
CV386
4.7U_0402_6.3V6M
CV29
4.7U_0402_6.3V6M
CV16
4.7U_0402_6.3V6M
CV387
10U_0402_6.3V6M
CV28
10U_0402_6.3V6M
CV388
10U_0402_6.3V6M
CV389
22U_0603_6.3V6M
CV34
22U_0603_6.3V6M
CV390
1 1 1 1 1 1 1 1 1 1 1 1 1 1
@
@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
reserve
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
1
UV1E 1
CHB
/6*1uF+2*10uF Part 5 of 7
AA27 AG19
FBVDDQ_0 PEX_DVDD_0
0.47U_0201_6.3V6K
CV397
0.47U_0201_6.3V6K
CV398
1U_0201_6.3V6M
CV126
1U_0201_6.3V6M
CV127
1U_0201_6.3V6M
CV128
1U_0201_6.3V6M
CV129
1U_0201_6.3V6M
CV130
1U_0201_6.3V6M
CV131
10U_0402_6.3V6M
CV132
10U_0402_6.3V6M
CV133
1 1 1 1 1 1 1 1 1 1 AA30 AG21
AB27 FBVDDQ_1 PEX_DVDD_1 AG22
AB33 FBVDDQ_2 PEX_DVDD_2 AG24
AC27 FBVDDQ_3 PEX_DVDD_3 AH21
2 2 2 2 2 2 2 2 2 2 FBVDDQ_4 PEX_DVDD_4
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
AD27 AH25
FBVDDQ_5 PEX_DVDD_5
@
VGA@
VGA@
AE27
AF27 FBVDDQ_6
FBVDDQ_7 2*22uF+3*10uF+3*4.7uF+7*1uF
AG27 AG13 Near
B13 FBVDDQ_8 PEX_HVDD_0 AG15 +1.8VSDGPU_MAIN
reserve FBVDDQ_9 PEX_HVDD_1 Under GPU
B19 AG16 GPU
E13 FBVDDQ_11 PEX_HVDD_2 AG18
FBVDDQ_12 PEX_HVDD_3
1U_0201_6.3V6M
CV399
1U_0201_6.3V6M
CV381
1U_0201_6.3V6M
CV380
1U_0201_6.3V6M
CV137
1U_0201_6.3V6M
CV136
1U_0201_6.3V6M
CV25
1U_0201_6.3V6M
CV15
4.7U_0402_6.3V6M
CV382
4.7U_0402_6.3V6M
CV17
4.7U_0402_6.3V6M
CV32
10U_0402_6.3V6M
CV30
10U_0402_6.3V6M
CV27
10U_0402_6.3V6M
CV383
22U_0603_6.3V6M
CV31
22U_0603_6.3V6M
CV384
E19 AG25 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
H10 FBVDDQ_14 PEX_HVDD_4 AH15
FBVDDQ_17 PEX_HVDD_7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
GPU H13 AH27
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
/5*22uF+2*10uF H14 AJ27
H18 FBVDDQ_19 PEX_HVDD_9 AK27
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 H19 AL27
CV37
CV38
CV202
CV36
CV39
CV40
CV41
H20 AM28
H21 FBVDDQ_24 PEX_HVDD_12 AN28
POWER
H22 FBVDDQ_25 PEX_HVDD_13
2 2 2 2 2 2 2 H23 FBVDDQ_26
FBVDDQ_27
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
H24
H8 FBVDDQ_28 AH12
FBVDDQ_29 PEX_PLL_HVDD +1.8VSDGPU_MAIN
H9 1
L27 FBVDDQ_30 +FP_FUSE_GPU CV43 VGA@
M27 FBVDDQ_31 1U_0201_6.3V6M
Place close to N27 FBVDDQ_32 AG12 12mils
P27 FBVDDQ_33 FP_FUSE_SRC 2
GPU FBVDDQ_34 Near
R27 GPU 3*4.7uF+5*1uF
2 T27 FBVDDQ_35 +1.8VSDGPU_MAIN +1.8VSDGPU_AON 2
T30 FBVDDQ_36 AG26
T33 FBVDDQ_37 NC
FBVDDQ_38
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
CV135
1U_0201_6.3V6M
CV49
1U_0201_6.3V6M
CV51
1U_0201_6.3V6M
CV391
1U_0201_6.3V6M
CV392
4.7U_0402_6.3V6M
CV50
4.7U_0402_6.3V6M
CV393
4.7U_0402_6.3V6M
CV394
1 1 1 1 1 1 1 Y27 1 1 1 1 1 1 1 1
FBVDDQ_43
CV217
CV218
CV219
CV220
CV221
CV222
CV223
J8
1V8_AON K8
2 2 2 2 2 2 2 1V8_AON 2 2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
L8
B16 NC M8
FBVDDQ NC
@
E16
H15 FBVDDQ
H16 FBVDDQ
V27 FBVDDQ AH8
near GPU for NV update spec 1210 FBVDDQ IFPAB_PLLVDD Under Near
W27 AJ8 GPU GPU
W30 FBVDDQ IFPAB_RSET +1.8VSDGPU_MAIN
+1.35VSDGPU FBVDDQ 2*4.7uF+1*1uF+2*0.1uF
W33 RV394 2 N17P@ 1 0_0402_5%
FBVDDQ AF7
IFPCD_PLLVDD
2
0.1U_0201_10V6K
CV52
0.1U_0201_10V6K
CV53
1U_0201_6.3V6M
CV54
4.7U_0402_6.3V6M
CV55
AF8 2 1 1 1 1 1
RV45 IFPCD_RSET RG38 1K_0402_1%
@ 0_0402_5% VGA@
AB8
IFPE_PLLVDD 2 2 2 2
N17P@
N17P@
N17P@
N17P@
AD6
1
FB_VDDQ_SENSE F1 IFPE_RSET
<93> FB_VDDQ_SENSE FBVDDQ_SENSE
TV10@ FB_GND_SENSE F2 AG8 Under

PROBE_FB_GND IFP_IOVDD AG9
IFP_IOVDD GPU Near
+1.35VSDGPU
FB_CAL_PD_VDDQ GPU
RV47 1 VGA@ 2 40.2_0402_1% J27 AF6
FB_CAL_PD_VDDQ IFP_IOVDD AG6
IFP_IOVDD
FB_CAL_PU_GND +GPU_PLLVDD
RV48 1 VGA@ 2 40.2_0402_1% H27 AC7
FB_CAL_PU_GND IFP_IOVDD
1U_0201_6.3V6M
CV215
1U_0201_6.3V6M
CV216
AC8 1 1
IFP_IOVDD
1 N17P@ 2 FB_CAL_TERM_GND H25
3 RV49 60.4_0402_1% FB_CAL_TERM_GND AG7 3
NC 2 2
VGA@
VGA@
AN2
NC
RV49 N18P@ Under GPU
1 per ball
N18P-G0_FCBGA960~D
@ 3*4.7uF+9*1uF +1.0VSDGPU
40.2_0402_1%
SD034402A80
1U_0201_6.3V6M
CV214
1U_0201_6.3V6M
CV213
1U_0201_6.3V6M
CV212
4.7U_0402_6.3V6M
CV205
4.7U_0402_6.3V6M
CV204
4.7U_0402_6.3V6M
CV203
1 1 1 1 1 1
2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
Near
GPU
1U_0201_6.3V6M
CV211
1U_0201_6.3V6M
CV210
1U_0201_6.3V6M
CV209
1U_0201_6.3V6M
CV208
1U_0201_6.3V6M
CV207
1U_0201_6.3V6M
CV206
1 1 1 1 1 1
2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
Under GPU 1
4 per ball 4

N17P POWER 4/7
A B C D E
A B C D E
UV1F
N17P VDDS
1uF*5/4.7uF*5 (under GPU) Part 6 of 7
330uF*1/22uF*3/10uF*2/4.7uF*2 A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
AB12 GND_4 GND_104 E25
AB14 GND_5 GND_105 E5
UV1G AB16 GND_6 GND_106 E7
+NVVDD1 +NVVDD1 AB19 GND_7 GND_107 F28
AB2 GND_8 GND_108 F7
AA14 Part 7 of 7 V17 AB21 GND_9 GND_109 G10
AA21 VDD_1 VDD_56 V20 A33 GND_10 GND_110 G13
1 VDD_4 VDD_58 GND_11 GND_111 1
AB13 V22 AB23 G16
AB15 VDD_6 VDD_59 W12 AB28 GND_12 GND_112 G19
AB22 VDD_10 VDD_65 Y13 AB7 GND_16 GND_116 G28
AC12 VDD_11 VDD_66 Y15 AC13 GND_17 GND_117 G3
M12 VDD_17 VDD_70 Y22 AA13 GND_21 GND_121 G5
M16 VDD_18 VDD_71 AC20 GND_22 GND_122 G7
M19 VDD_20 AC22 GND_23 GND_123 K2
M23 VDD_21 AE2 GND_24 GND_124 K28
N13 VDD_23 U1 AE28 GND_25 GND_125 K30
VDD_24 RSVD_VDDS_SENSE
NVVDD & NVVDDS merge GND_26 GND_126
N15 U2 confirm NV nc or not AE30 K32
N17 VDD_25 RSVD_GNDS_SENSE AE32 GND_27 GND_127 K33
N18 VDD_26 +NVVDD1 AE33 GND_28 GND_128 K5
N20 VDD_27 AE5 GND_29 GND_129 K7
N22 VDD_28 U4 AE7 GND_30 GND_130 M13
P14 VDD_29 XVDD_4 U5 AH10 GND_31 GND_131 M15
POWER
P21 VDD_31 XVDD_5 U6 AA15 GND_32 GND_132 M17
R13 VDD_34 XVDD_6 U7 AH13 GND_33 GND_133 M18
R15 VDD_36 XVDD_7 U8 AH16 GND_34 GND_134 M20
R17 VDD_37 XVDD_8 AH19 GND_35 GND_135 M22
R18 VDD_38 AH2 GND_36 GND_136 N12
R20 VDD_39 V1 AH22 GND_37 GND_137 N14
R22 VDD_40 XVDD_9 V2 AH24 GND_38 GND_138 N16
T12 VDD_41 XVDD_10 V3 AH28 GND_39 GND_139 N19
U13 VDD_47 XVDD_14 V7 AH33 GND_43 GND_143 N28
U15 VDD_48 XVDD_15 V8 AH5 GND_44 GND_144 N30
GND
U18 VDD_49 XVDD_16 AH7 GND_45 GND_145 N32
2 U20 VDD_51 W2 AJ7 GND_46 GND_146 N33 2
U22 VDD_52 XVDD_17 W3 AK10 GND_47 GND_147 N5
V13 VDD_53 XVDD_18 W4 AK7 GND_48 GND_148 N7
V15 VDD_54 XVDD_19 W5 AL12 GND_49 GND_149 P13
VDD_55 XVDD_20 W7 AL14 GND_50 GND_150 P15
XVDD_21 W8 AL15 GND_51 GND_151 P17
XVDD_22 AL17 GND_52 GND_152 P18
AL18 GND_53 GND_153 P20
AA12 AL2 GND_54 GND_154 P22
AA16 VDD_72 Y1 AL20 GND_55 GND_155 R12
AA19 VDD_73 XVDD_20 Y2 AL21 GND_56 GND_156 R14
AA23 VDD_74 XVDD_21 Y3 AL23 GND_57 GND_157 R16
AC14 VDD_75 XVDD_22 Y4 AL24 GND_58 GND_158 R19
AC21 VDD_76 XVDD_23 Y5 AL26 GND_59 GND_159 R21
M14 VDD_77 XVDD_24 Y6 AL28 GND_60 GND_160 R23
M21 VDD_78 XVDD_25 Y7 AL30 GND_61 GND_161 T13
P12 VDD_79 XVDD_26 Y8 AL32 GND_62 GND_162 T15
P16 VDD_80 XVDD_27 AL33 GND_63 GND_163 T17
P19 VDD_81 AL5 GND_64 GND_164 T18
P23 VDD_82 AA1 AM13 GND_65 GND_165 T2
T14 VDD_83 XVDD_28 AA2 AM16 GND_66 GND_166 T20
T21 VDD_84 XVDD_29 AA3 AM19 GND_67 GND_167 T22
U17 VDD_85 XVDD_30 AA4 AM22 GND_68 GND_168 AG11
V18 VDD_86 XVDD_31 AA5 AM25 GND_69 GND_169 T28
W14 VDD_87 XVDD_32 AA6 AN1 GND_70 GND_170 T32
W21 VDD_88 XVDD_33 AA7 AN10 GND_71 GND_171 T5
VDD_89 XVDD_34 AA8 AN13 GND_72 GND_172 T7
XVDD_35 AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AB11 R11 AN22 GND_75 GND_175 U16
AB24 VDD_90 VDD_106 R24 AN25 GND_76 GND_176 U19
AD11 VDD_91 VDD_107 U11 AN30 GND_77 GND_177 U21
AD13 VDD_92 VDD_108 U24 AN34 GND_78 GND_178 U23
AD15 VDD_93 VDD_109 V11 AN4 GND_79 GND_179 V12
AD17 VDD_94 VDD_110 V24 AN7 GND_80 GND_180 V14
3 AD18 VDD_95 VDD_111 Y11 AP2 GND_81 GND_181 V16 3
AD20 VDD_96 VDD_112 Y24 AP33 GND_82 GND_182 V19
AD22 VDD_97 VDD_113 B1 GND_83 GND_183 V21
AD24 VDD_98 B10 GND_84 GND_184 V23
L11 VDD_95 B22 GND_85 GND_185 W13
L13 VDD_96 B25 GND_86 GND_186 W15
L15 VDD_97 B28 GND_87 GND_187 W17
L17 VDD_98 B31 GND_88 GND_188 W18
L18 VDD_99 B34 GND_89 GND_189 W20
L20 VDD_100 B4 GND_90 GND_190 W22
L22 VDD_101 B7 GND_91 GND_191 W28
L24 VDD_102 C10 GND_92 GND_192 Y12
N11 VDD_103 C13 GND_93 GND_193 Y14
N24 VDD_104 C19 GND_94 GND_194 Y16
VDD_105 C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
N18P-G0_FCBGA960~D C7 GND_98 GND_198
GND_99
@
L21 AA11
L23 GND_214 GND_200 AA24
M11 GND_215 GND_201 AC11
M24 GND_216 GND_202 AC24
P11 GND_217 GND_203 AD12
T11 GND_218 GND_204 AD14
T24 GND_219 GND_205 AD16
W11 GND_220 GND_206 AD19
W24 GND_221 GND_207 AD21
P24 GND_222 GND_208 AD23
GND_223 GND_209 L12
GND_210 L14
GND_211 L16
GND_212 L19
GND_213
4 AH11 RV395 2 N17P@ 1 0_0402_5% 4

NC
C16
GND_OPT W32
GND_OPT
N18P-G0_FCBGA960~D
@

N17P POWER & GND 5/7
A B C D E
A B C D E
MF=1
MF=0
<28> FBA_D[63:0] 2 OF 2 2 OF 2
UV4B +1.35VSDGPU UV5B
K4 A4 FBA_D0 K4 A4 FBA_D56
<28> FBA_CMD6 A8/A7 DQ0 <28> FBA_CMD26 A8/A7 DQ0
1
H5 A2 FBA_D1 H5 A2 FBA_D57
<28> FBA_CMD11 A9/A1 DQ1 FBA_D2 <28> FBA_CMD23 A9/A1 DQ1 FBA_D58
H4 B4 RV50 H4 B4
<28> FBA_CMD10 K5 A10/A0 DQ2 B2 FBA_D3 <28> FBA_CMD22 K5 A10/A0 DQ2 B2 FBA_D59
549_0402_1%
<28> FBA_CMD7 A11/A6 DQ3 FBA_D4 <28> FBA_CMD27 A11/A6 DQ3 FBA_D60
J5 E4 VGA@ J5 E4
<28> FBA_CMD9 A12/RFU#J5/NC#J5 DQ4 E2 FBA_D5 <28> FBA_CMD25 A12/RFU#J5/NC#J5 DQ4 E2 FBA_D61
RV51
2
H11 DQ5 F4 FBA_D6 931_0402_1% H11 DQ5 F4 FBA_D62
<28> FBA_CMD2 BA0/A2 DQ6 FBA_D7 FBA_VREFC_R FBA0_VREFC <28> FBA_CMD19 BA0/A2 DQ6 FBA_D63
K10 F2 1 2 K10 F2
1 <28> FBA_CMD4 K11 BA1/A5 DQ7 A11 FBA_D8 <28> FBA_CMD17 K11 BA1/A5 DQ7 A11 FBA_D48 1
<28> FBA_CMD3 H10 BA2/A4 DQ8 A13 FBA_D9 <28> FBA_CMD18 H10 BA2/A4 DQ8 A13 FBA_D49
VGA@
<28> FBA_CMD1 BA3/A3 DQ9 <28> FBA_CMD20 BA3/A3 DQ9
1
B11 FBA_D10 B11 FBA_D50
J4 DQ10 B13 FBA_D11 RV52 J4 DQ10 B13 FBA_D51
<28> FBA_CMD8 ABI# DQ11 FBA_D12 <28> FBA_CMD24 ABI# DQ11 FBA_D52
G3 E11 1.33K_0402_1% G3 E11
<28> FBA_CMD12 RAS# DQ12 FBA_D13 <28> FBA_CMD31 RAS# DQ12 FBA_D53
G12 E13 G12 E13
<28> FBA_CMD0 L3 CS# DQ13 F11 FBA_D14 <28> FBA_CMD21 L3 CS# DQ13 F11 FBA_D54
VGA@
<28> FBA_CMD15 <28> FBA_CMD28
2
CAS# DQ14 CAS# DQ14
1
L12 F13 FBA_D15 L12 F13 FBA_D55
<28> FBA_CMD5 WE# DQ15 U11 FBA_D16 <28> FBA_CMD16 WE# DQ15 U11 FBA_D40
QV3 VGA@
Drain
Source
J12 DQ16 U13 FBA_D17 J12 DQ16 U13 FBA_D41
LBSS139WT1G_SC70-3
Gate
<28> FBA_CLKA0 J11 CK DQ17 T11 FBA_D18 <28> FBA_CLKA1 J11 CK DQ17 T11 FBA_D42
<28> FBA_CLKA0# J3 CK# DQ18 T13 FBA_D19 <28> FBA_CLKA1# J3 CK# DQ18 T13 FBA_D43
<28> FBA_CMD14 CKE# DQ19 FBA_D20 <28> FBA_CMD30 CKE# DQ19 FBA_D44
N11 N11
3
D2 DQ20 N13 FBA_D21 D2 DQ20 N13 FBA_D45
<28> FBA_DBI0 DBI0# DQ21 FBA_D22 <28> FBA_DBI7 DBI0# DQ21 FBA_D46
D13 M11 D13 M11
P13 M13 P13 M13
P2 U4 P2 U4
<28> FBA_DBI3 DBI3# DQ24 FBA_D25 <27,33> VRAM_VREF_CTL <28> FBA_DBI4 DBI3# DQ24 FBA_D33
U2 U2
J2 DQ25 T4 FBA_D26 J2 DQ25 T4 FBA_D34
<28> FBA_CMD13 RESET# DQ26 FBA_D27 <28> FBA_CMD29 RESET# DQ26 FBA_D35
T2 T2
J10 DQ27 N4 FBA_D28 J10 DQ27 N4 FBA_D36
FBA0_ZQ1 J13 SEN DQ28 N2 FBA_D29 +1.35VSDGPU FBA1_ZQ3 J13 SEN DQ28 N2 FBA_D37
J1 ZQ DQ29 M4 FBA_D30 J1 ZQ DQ29 M4 FBA_D38
MF DQ30 M2 FBA_D31 MF DQ30 M2 FBA_D39
D4 DQ31 D4 DQ31
<28> FBA_WCK01 WCK01 <28> FBA_WCK67 WCK01
D5 C2 D5 C2
<28> FBA_WCK01# WCK01# EDC0 FBA_EDC0 <28> <28> FBA_WCK67# WCK01# EDC0 FBA_EDC7 <28>
C13 C13
EDC1 FBA_EDC1 <28> EDC1 FBA_EDC6 <28>
P4 R13 P4 R13
<28> FBA_WCK23 WCK23 EDC2 FBA_EDC2 <28> <28> FBA_WCK45 WCK23 EDC2 FBA_EDC5 <28>
P5 R2 P5 R2
<28> FBA_WCK23# WCK23# EDC3 FBA_EDC3 <28> <28> FBA_WCK45# WCK23# EDC3 FBA_EDC4 <28>
1
1
@ @
VRAM4G@ H5GC2H24BFR-T2C_FBGA170 VGA@ H5GC2H24BFR-T2C_FBGA170
RV58 RV61
121_0402_1% 121_0402_1%
2 2
2
2
+1.35VSDGPU
UV4A 1 OF 2 +1.35VSDGPU
UV5A 1 OF 2
C5 B5
C10 VDD VSS B10 C5 B5
D11 VDD VSS D10 C10 VDD VSS B10
G1 VDD VSS G5 D11 VDD VSS D10
VDD VSS FBA_CLKA0 FBA_CLKA0# +1.35VSDGPU VDD VSS
G4 G10 G1 G5
G11 VDD VSS H1 G4 VDD VSS G10
VDD VSS VDD VSS
1
G14 H14 G11 H1
+1.35VSDGPU VDD VSS VDD VSS
L1 K1 RV63 RV95 G14 H14
VDD VSS VDD VSS
1U_0201_6.3V6M
CV58
1U_0201_6.3V6M
CV59
1U_0201_6.3V6M
CV67
1U_0201_6.3V6M
CV56
1U_0201_6.3V6M
CV57
1U_0201_6.3V6M
CV60
1U_0201_6.3V6M
CV68
L4 K14 40.2_0402_1% 40.2_0402_1% 1 1 1 1 1 1 1 L1 K1
L11 VDD VSS L5 VRAM4G@ VRAM4G@ L4 VDD VSS K14
L14 VDD VSS L10 L11 VDD VSS L5
2
VDD VSS VDD VSS
1U_0201_6.3V6M
CV61
1U_0201_6.3V6M
CV62
1U_0201_6.3V6M
CV63
1U_0201_6.3V6M
CV64
1U_0201_6.3V6M
CV65
1U_0201_6.3V6M
CV66
1U_0201_6.3V6M
CV69
1 1 1 1 1 1 1 P11 P10 L14 L10

VDD VSS 2 2 2 2 2 2 2 VDD VSS
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
R5 T5 1 P11 P10
VDD VSS VDD VSS
0.01U_0402_16V7K
R10 T10 VRAM4G@ R5 T5
VDD VSS VDD VSS
CV190
R10 T10
2 2 2 2 2 2 2 VDD VSS
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
B1 A1
B3 VDDQ VSSQ A3 2 B1 A1
B12 VDDQ VSSQ A12 B3 VDDQ VSSQ A3
B14 VDDQ VSSQ A14 B12 VDDQ VSSQ A12
D1 VDDQ VSSQ C1 B14 VDDQ VSSQ A14
VDDQ VSSQ Close to VDDQ VSSQ
D3 C3 VRAM D1 C1
D12 VDDQ VSSQ C4 D3 VDDQ VSSQ C3
VDDQ VSSQ VDDQ VSSQ
1U_0201_6.3V6M
CV173
1U_0201_6.3V6M
CV85
1U_0201_6.3V6M
CV140
10U_0402_6.3V6M
CV73
10U_0402_6.3V6M
CV74
10U_0402_6.3V6M
CV75
10U_0402_6.3V6M
CV76
Close to D14 C11 1 1 1 1 1 1 1 D12 C4
E5 VDDQ VSSQ C12 D14 VDDQ VSSQ C11
VRAM VDDQ VSSQ VDDQ VSSQ
E10 C14 E5 C12
VDDQ VSSQ VDDQ VSSQ
1U_0201_6.3V6M
CV77
1U_0201_6.3V6M
CV78
1U_0201_6.3V6M
CV79
10U_0402_6.3V6M
CV169
10U_0402_6.3V6M
CV81
10U_0402_6.3V6M
CV82
10U_0402_6.3V6M
CV83
1 1 1 1 1 1 1 F1 E1 E10 C14
VDDQ VSSQ 2 2 2 2 2 2 2 VDDQ VSSQ
VGA@
VGA@
VGA@
F3 E3 F1 E1
VDDQ VSSQ VDDQ VSSQ
VGA@
VGA@
VGA@
VGA@
F12 E12 F3 E3
F14 VDDQ VSSQ E14 FBA_CLKA1 FBA_CLKA1# F12 VDDQ VSSQ E12
2 2 2 2 2 2 2 VDDQ VSSQ VDDQ VSSQ
VRAM4G@
VRAM4G@
VRAM4G@
3 G2 F5 F14 E14 3
VDDQ VSSQ VDDQ VSSQ
1
1
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
G13 F10 G2 F5
H3 VDDQ VSSQ H2 RV96 RV62 G13 VDDQ VSSQ F10
H12 VDDQ VSSQ H13 40.2_0402_1% 40.2_0402_1% H3 VDDQ VSSQ H2
K3 VDDQ VSSQ K2 VGA@ VGA@ H12 VDDQ VSSQ H13
VDDQ VSSQ Close to VDDQ VSSQ
K12 K13 VRAM K3 K2
2
L2 VDDQ VSSQ M5 K12 VDDQ VSSQ K13

L13 VDDQ VSSQ M10 L2 VDDQ VSSQ M5
Close to VDDQ VSSQ 1 VDDQ VSSQ
0.01U_0402_16V7K
10U_0402_6.3V6M
CV84
10U_0402_6.3V6M
CV142
22U_0603_6.3V6M
CV70
22U_0603_6.3V6M
CV71
22U_0603_6.3V6M
CV72
22U_0603_6.3V6M
CV138
22U_0603_6.3V6M
CV139
VRAM M1 N1 VGA@ 1 1 1 1 1 1 1 L13 M10
VDDQ VSSQ VDDQ VSSQ
CV191
M3 N3 M1 N1
M12 VDDQ VSSQ N12 M3 VDDQ VSSQ N3
VDDQ VSSQ 2 VDDQ VSSQ
10U_0402_6.3V6M
CV86
10U_0402_6.3V6M
CV87
22U_0603_6.3V6M
CV143
22U_0603_6.3V6M
CV144
22U_0603_6.3V6M
CV145
22U_0603_6.3V6M
CV146
22U_0603_6.3V6M
CV147
1 1 1 1 1 1 1 M14 N14 M12 N12

N5 VDDQ VSSQ R1 2 2 2 2 2 2 2 M14 VDDQ VSSQ N14
VDDQ VSSQ VDDQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N10 R3 N5 R1
P1 VDDQ VSSQ R4 N10 VDDQ VSSQ R3
2 2 2 2 2 2 2 P3 VDDQ VSSQ R11 P1 VDDQ VSSQ R4
VDDQ VSSQ VDDQ VSSQ
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
P12 R12 P3 R11

P14 VDDQ VSSQ R14 P12 VDDQ VSSQ R12
VDDQ VSSQ (3GHz and VDDQ VSSQ
T1 U1 up) P14 R14
T3 VDDQ VSSQ U3 T1 VDDQ VSSQ U1
VDDQ VSSQ Around VDDQ VSSQ
T12 U12 VRAM T3 U3
T14 VDDQ VSSQ U14 T12 VDDQ VSSQ U12
VDDQ VSSQ T14 VDDQ VSSQ U14
Around FBA0_VREFC VDDQ VSSQ
VRAM J14 A5
VREFC VPP/NC#A5 FBA0_VREFC
1U_0201_6.3V6M
CV161
1U_0201_6.3V6M
CV160
1U_0201_6.3V6M
CV158
1U_0201_6.3V6M
CV162
1U_0201_6.3V6M
CV163
1U_0201_6.3V6M
CV164
1U_0201_6.3V6M
CV159
1U_0201_6.3V6M
CV165
U5 1 1 1 1 1 1 1 1 J14 A5
VPP/NC#U5 VREFC VPP/NC#A5
1U_0201_6.3V6M
CV166
1U_0201_6.3V6M
CV168
1U_0201_6.3V6M
CV167
1U_0201_6.3V6M
CV170
1U_0201_6.3V6M
CV80
1U_0201_6.3V6M
CV172
1U_0201_6.3V6M
CV171
1U_0201_6.3V6M
CV141
1 1 1 1 1 1 1 1 A10 U5
VREFD VPP/NC#U5
820P_0402_50V7K
1 U10 1 A10
CV89 VREFD U10 VREFD
2 2 2 2 2 2 2 2 VREFD
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
820P_0402_50V7K
VRAM4G@ CV88
2 2 2 2 2 2 2 2
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
VRAM4G@
@ VGA@
2 H5GC2H24BFR-T2C_FBGA170 2 @
H5GC2H24BFR-T2C_FBGA170
x32
x32 only
4 only 4

N17P GDDR5 CHA 6/7
A B C D E
A B C D E
MF=1
<28> FBB_D[63:0] MF=0 UV7B 2 OF 2
UV6B 2 OF 2 K4 A4 FBB_D56
<28> FBB_CMD26 H5 A8/A7 DQ0 A2 FBB_D57
+1.35VSDGPU
FBB_D0 <28> FBB_CMD23 A9/A1 DQ1 FBB_D58
K4 A4 H4 B4
<28> FBB_CMD6 H5 A8/A7 DQ0 A2 FBB_D1 <28> FBB_CMD22 K5 A10/A0 DQ2 B2 FBB_D59
<28> FBB_CMD11 A9/A1 DQ1 <28> FBB_CMD27 A11/A6 DQ3
1
H4 B4 FBB_D2 J5 E4 FBB_D60
<28> FBB_CMD10 K5 A10/A0 DQ2 B2 FBB_D3 <28> FBB_CMD25 A12/RFU#J5/NC#J5 DQ4 E2 FBB_D61
RV67
<28> FBB_CMD7 J5 A11/A6 DQ3 E4 FBB_D4 H11 DQ5 F4 FBB_D62
549_0402_1%
<28> FBB_CMD9 A12/RFU#J5/NC#J5 DQ4 FBB_D5 <28> FBB_CMD19 BA0/A2 DQ6 FBB_D63
E2 VGA@ K10 F2
1
H11 DQ5 F4 FBB_D6 <28> FBB_CMD17 K11 BA1/A5 DQ7 A11 FBB_D48 1
RV68
<28> FBB_CMD2 <28> FBB_CMD18
2
K10 BA0/A2 DQ6 F2 FBB_D7 931_0402_1% H10 BA2/A4 DQ8 A13 FBB_D49
<28> FBB_CMD4 BA1/A5 DQ7 FBB_D8 FBB_VREFC_R FBB0_VREFC <28> FBB_CMD20 BA3/A3 DQ9 FBB_D50
K11 A11 1 2 B11
<28> FBB_CMD3 BA2/A4 DQ8 FBB_D9 DQ10 FBB_D51
H10 A13 J4 B13
<28> FBB_CMD1 BA3/A3 DQ9 FBB_D10 <28> FBB_CMD24 ABI# DQ11 FBB_D52
B11 VGA@ G3 E11
DQ10 <28> FBB_CMD31 RAS# DQ12
1
J4 B13 FBB_D11 G12 E13 FBB_D53
<28> FBB_CMD8 G3 ABI# DQ11 E11 FBB_D15 <28> FBB_CMD21 L3 CS# DQ13 F11 FBB_D54
RV70
<28> FBB_CMD12 RAS# DQ12 FBB_D13 <28> FBB_CMD28 CAS# DQ14 FBB_D55
G12 E13 1.33K_0402_1% L12 F13
<28> FBB_CMD0 L3 CS# DQ13 F11 FBB_D14 <28> FBB_CMD16 WE# DQ15 U11 FBB_D40
<28> FBB_CMD15 CAS# DQ14 FBB_D12 DQ16 FBB_D41
L12 F13 VGA@ J12 U13
<28> FBB_CMD5 <28> FBB_CLKA1
2
WE# DQ15 CK DQ17
1
U11 FBB_D16 J11 T11 FBB_D42
J12 DQ16 U13 FBB_D17 <28> FBB_CLKA1# J3 CK# DQ18 T13 FBB_D43
QV4 VGA@
Drain
Source
<28> FBB_CLKA0 CK DQ17 FBB_D18 <28> FBB_CMD30 CKE# DQ19 FBB_D44
J11 T11 LBSS139WT1G_SC70-3 N11
Gate
<28> FBB_CLKA0# CK# DQ18 FBB_D19 DQ20 FBB_D45
J3 T13 D2 N13
<28> FBB_CMD14 CKE# DQ19 FBB_D22 <28> FBB_DBI7 DBI0# DQ21 FBB_D46
N11 D13 M11
DQ20 FBB_D21 <28> FBB_DBI6 DBI1# DQ22 FBB_D47
D2 N13 P13 M13
<28> FBB_DBI0 <28> FBB_DBI5
3
D13 DBI0# DQ21 M11 FBB_D23 P2 DBI2# DQ23 U4 FBB_D32
<28> FBB_DBI1 DBI1# DQ22 FBB_D20 <28> FBB_DBI4 DBI3# DQ24 FBB_D33
P13 M13 U2
<28> FBB_DBI2 DBI2# DQ23 FBB_D24 DQ25 FBB_D34
P2 U4 J2 T4
<28> FBB_DBI3 DBI3# DQ24 FBB_D25 <28> FBB_CMD29 RESET# DQ26 FBB_D35
U2 T2
DQ25 FBB_D26 <27,32> VRAM_VREF_CTL DQ27 FBB_D36
J2 T4 J10 N4
<28> FBB_CMD13 RESET# DQ26 FBB_D27 +1.35VSDGPU FBB1_ZQ3 J13 SEN DQ28 FBB_D37
T2 N2
J10 DQ27 N4 FBB_D28 J1 ZQ DQ29 M4 FBB_D38
FBB0_ZQ1 J13 SEN DQ28 N2 FBB_D29 MF DQ30 M2 FBB_D39
J1 ZQ DQ29 M4 FBB_D31 D4 DQ31
MF DQ30 FBB_D30 <28> FBB_WCK67 WCK01
M2 D5 C2
DQ31 <28> FBB_WCK67# WCK01# EDC0 FBB_EDC7 <28>
D4 C13
<28> FBB_WCK01 WCK01 EDC1 FBB_EDC6 <28>
D5 C2 P4 R13
<28> FBB_WCK01# WCK01# EDC0 FBB_EDC0 <28> <28> FBB_WCK45 WCK23 EDC2 FBB_EDC5 <28>
C13 P5 R2
EDC1 FBB_EDC1 <28> <28> FBB_WCK45# WCK23# EDC3 FBB_EDC4 <28>
P4 R13
<28> FBB_WCK23 WCK23 EDC2 FBB_EDC2 <28>
P5 R2
<28> FBB_WCK23# WCK23# EDC3 FBB_EDC3 <28>
1
@
VGA@ H5GC2H24BFR-T2C_FBGA170
1
@ RV72
VGA@ H5GC2H24BFR-T2C_FBGA170 121_0402_1%
2 2
RV74
2
121_0402_1%
2
+1.35VSDGPU
UV7A 1 OF 2
+1.35VSDGPU C5 B5
+1.35VSDGPU VDD VSS
UV6A 1 OF 2 C10 B10
D11 VDD VSS D10
+1.35VSDGPU VDD VSS
C5 B5 G1 G5
C10 VDD VSS B10 G4 VDD VSS G10
VDD VSS VDD VSS
1U_0201_6.3V6M
CV90
1U_0201_6.3V6M
CV94
1U_0201_6.3V6M
CV96
1U_0201_6.3V6M
CV97
1U_0201_6.3V6M
CV91
1U_0201_6.3V6M
CV95
1U_0201_6.3V6M
CV98
D11 D10 1 1 1 1 1 1 1 G11 H1
G1 VDD VSS G5 G14 VDD VSS H14
VDD VSS VDD VSS
1U_0201_6.3V6M
CV99
1U_0201_6.3V6M
CV100
1U_0201_6.3V6M
CV101
1U_0201_6.3V6M
CV92
1U_0201_6.3V6M
CV93
1U_0201_6.3V6M
CV102
1U_0201_6.3V6M
CV103
1 1 1 1 1 1 1 G4 G10 L1 K1
G11 VDD VSS H1 L4 VDD VSS K14
VDD VSS FBB_CLKA0 FBB_CLKA0# 2 2 2 2 2 2 2 VDD VSS
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
G14 H14 L11 L5
L1 VDD VSS K1 L14 VDD VSS L10
VDD VSS VDD VSS
1
2 2 2 2 2 2 2
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
L4 K14 P11 P10

L11 VDD VSS L5 RV76 RV77 R5 VDD VSS T5
L14 VDD VSS L10 40.2_0402_1% 40.2_0402_1% R10 VDD VSS T10
P11 VDD VSS P10 VGA@ VGA@ VDD VSS
R5 VDD VSS T5 B1 A1
2
R10 VDD VSS T10 B3 VDDQ VSSQ A3
VDD VSS Close to VDDQ VSSQ
1 VRAM B12 A12
VDDQ VSSQ
0.01U_0402_16V7K
Close to B1 A1 B14 A14
VDDQ VSSQ VDDQ VSSQ
CV193
1U_0201_6.3V6M
CV104
1U_0201_6.3V6M
CV180
1U_0201_6.3V6M
CV181
10U_0402_6.3V6M
CV174
10U_0402_6.3V6M
CV108
10U_0402_6.3V6M
CV189
10U_0402_6.3V6M
CV110
VRAM B3 A3 1 1 1 1 1 1 1 D1 C1
B12 VDDQ VSSQ A12 D3 VDDQ VSSQ C3
1U_0201_6.3V6M
CV111
1U_0201_6.3V6M
CV112
1U_0201_6.3V6M
CV113
10U_0402_6.3V6M
CV114
10U_0402_6.3V6M
CV115
10U_0402_6.3V6M
CV116
10U_0402_6.3V6M
CV117
1 1 1 1 1 1 1 B14 A14 D12 C4

D1 VDDQ VSSQ C1 D14 VDDQ VSSQ C11
VDDQ VSSQ 2 2 2 2 2 2 2 VDDQ VSSQ
VGA@
VGA@
VGA@
D3 C3 E5 C12
VDDQ VSSQ VDDQ VSSQ
VGA@
VGA@
VGA@
VGA@
D12 C4 E10 C14
2 2 2 2 2 2 2 VDDQ VSSQ VDDQ VSSQ
VGA@
VGA@
VGA@
D14 C11 F1 E1
VDDQ VSSQ VDDQ VSSQ
VGA@
VGA@
VGA@
VGA@
E5 C12 VGA@ F3 E3
E10 VDDQ VSSQ C14 F12 VDDQ VSSQ E12
F1 VDDQ VSSQ E1 F14 VDDQ VSSQ E14
3 F3 VDDQ VSSQ E3 FBB_CLKA1 FBB_CLKA1# G2 VDDQ VSSQ F5 3
F12 VDDQ VSSQ E12 G13 VDDQ VSSQ F10
VDDQ VSSQ
1 Close to VDDQ VSSQ
1
F14 E14 VRAM H3 H2
G2 VDDQ VSSQ F5 RV97 RV98 H12 VDDQ VSSQ H13
Close to VDDQ VSSQ VDDQ VSSQ
VRAM G13 F10 40.2_0402_1% 40.2_0402_1% K3 K2
VDDQ VSSQ VDDQ VSSQ
10U_0402_6.3V6M
CV118
10U_0402_6.3V6M
CV119
22U_0603_6.3V6M
CV153
22U_0603_6.3V6M
CV155
22U_0603_6.3V6M
CV154
22U_0603_6.3V6M
CV156
22U_0603_6.3V6M
CV157
H3 H2 VGA@ VGA@ 1 1 1 1 1 1 1 K12 K13
H12 VDDQ VSSQ H13 L2 VDDQ VSSQ M5
2
VDDQ VSSQ VDDQ VSSQ

10U_0402_6.3V6M
CV120
10U_0402_6.3V6M
CV121
22U_0603_6.3V6M
CV148
22U_0603_6.3V6M
CV149
22U_0603_6.3V6M
CV150
22U_0603_6.3V6M
CV152
22U_0603_6.3V6M
CV151
1 1 1 1 1 1 1 K3 K2 L13 M10
K12 VDDQ VSSQ K13 M1 VDDQ VSSQ N1
VDDQ VSSQ 1 2 2 2 2 2 2 2 VDDQ VSSQ
0.01U_0402_16V7K
L2 M5 M3 N3
VDDQ VSSQ VDDQ VSSQ
CV192
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
L13 M10 M12 N12
2 2 2 2 2 2 2 M1 VDDQ VSSQ N1 M14 VDDQ VSSQ N14
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
M3 N3 N5 R1
M12 VDDQ VSSQ N12 N10 VDDQ VSSQ R3
M14 VDDQ VSSQ N14 P1 VDDQ VSSQ R4
N5 VDDQ VSSQ R1 P3 VDDQ VSSQ R11
N10 VDDQ VSSQ R3 P12 VDDQ VSSQ R12
VDDQ VSSQ Around VDDQ VSSQ
P1 R4 VGA@ VRAM P14 R14
P3 VDDQ VSSQ R11 T1 VDDQ VSSQ U1
Around VDDQ VSSQ (3GHz and VDDQ VSSQ
VRAM P12 R12 up) T3 U3
P14 VDDQ VSSQ R14 T12 VDDQ VSSQ U12
VDDQ VSSQ VDDQ VSSQ
1U_0201_6.3V6M
CV182
1U_0201_6.3V6M
CV184
1U_0201_6.3V6M
CV183
1U_0201_6.3V6M
CV185
1U_0201_6.3V6M
CV175
1U_0201_6.3V6M
CV188
1U_0201_6.3V6M
CV187
1U_0201_6.3V6M
CV109
T1 U1 1 1 1 1 1 1 1 1 T14 U14
T3 VDDQ VSSQ U3 VDDQ VSSQ
T12 VDDQ VSSQ U12 FBB0_VREFC J14 A5
VDDQ VSSQ VREFC VPP/NC#A5
1U_0201_6.3V6M
CV107
1U_0201_6.3V6M
CV176
1U_0201_6.3V6M
CV186
1U_0201_6.3V6M
CV177
1U_0201_6.3V6M
CV178
1U_0201_6.3V6M
CV179
1U_0201_6.3V6M
CV105
1U_0201_6.3V6M
CV106
1 1 1 1 1 1 1 1 T14 U14 U5
VDDQ VSSQ 2 2 2 2 2 2 2 2 VPP/NC#U5
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A10
FBB0_VREFC J14 A5 U10 VREFD
VREFC VPP/NC#A5 1 VREFD
U5
2 2 2 2 2 2 2 2 VPP/NC#U5
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
820P_0402_50V7K
A10 CV122
U10 VREFD VGA@ @
VREFD 2 H5GC2H24BFR-T2C_FBGA170
1 x32
CV123 only
820P_0402_50V7K
VGA@ @
x32 H5GC2H24BFR-T2C_FBGA170
2
only
4 4

N17P GDDR5 CHB 7/7
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
+3V_OVRM
CSSP_B+ RV343 1 N18P@ 2 75K_0402_1% PFM_CH1_BS_IN1
1
CV361 RV344
2K_0402_5%
RV345
2K_0402_5%
RV346
2K_0402_5%
RV347
2K_0402_5%
RV348
1 2 1 1 2 1
649_0402_1%
1000P_0402_50V7K +3V_OVRM N18P@ N18P@ N18P@ N18P@
ON_X76@
N18P@
2
PFM_CH1_SH_IN_P3
CSSP_NVVDD RV349 1 N18P@ 2 75K_0402_1% PFM_CH1_BS_IN2 RV351 1 uPI_X76@
2 0_0402_5% PFM_CH1_SH_IN_N3
+3VSDGPU SNN_PFM_CH1_SH_IN_P4
CV362 RV350 SNN_PFM_CH1_SH_IN_N4
2 1 1 2
0730 FAE CF suggest RV399 1 ON_X76@
2 0_0402_5% +3VLP
2
649_0402_1%
0_0402_5%
RV352
0_0402_5%
RV353
1000P_0402_50V7K
N18P@
ON_X76@ 0727 FAE CF suggest
1
1
@ @ N18P@
CV363
UV47 1U_0201_6.3V6M
2
3 27
6 BS_IN1 VCC
PFM_CH1_BS_IN3 11 BS_IN2 2 PFM_CH1_SH_IN_P1 RV355 1 N18P@ 2 100_0402_1% CSSP_B+
PFM_CH1_BS_IN4 14 BS_IN3 SH_IN_P1 PFM_CH1_SH_IN_N1 CSSN_B+ CSSP_B+ <96>
1 RV356 1 @ 2 0_0402_5%
BS_IN4 SH_IN_N1 PFM_CH1_SH_IN_P2 CSSN_B+ <96>
5 RV357 1 N18P@ 2 100_0402_1% CSSP_NVVDD
SH_IN_P2 PFM_CH1_SH_IN_N2 CSSN_NVVDD CSSP_NVVDD <96>
4 RV358 1 @ 2 0_0402_5%
PFM_FILTER_GND_FET SH_IN_N2 PFM_CH1_SH_IN_P3 CSSN_NVVDD <96>
@1 RV354 2 9 12
GND_FET SH_IN_P3 13 PFM_CH1_SH_IN_N3
0_0402_5% SH_IN_N3 15 SNN_PFM_CH1_SH_IN_P4
RV359 1 2
ON_X76@ 475_0402_1% 32 SH_IN_P4 16 SNN_PFM_CH1_SH_IN_N4
RV360 1 2
ON_X76@ 475_0402_1% 7 SH_O1 SH_IN_N4 N18P@
2 RV361 1 @ 2 169_0402_1% 10 SH_O2 20 ADC_IN_P RV362 1 @ 2 0_0402_5% CV364 1 2 47P_0402_50V8J 2
RV363 1 @ 2 169_0402_1% 17 SH_O3 DIFF_OUT_P 19 ADC_IN_N RV364 1 @ 2 0_0402_5% CV365 1 2 47P_0402_50V8J
SH_O4 DIFF_OUT_N N18P@
1 1 1 1
PFM_PF_BSOK_R
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
0.015U_0402_16V7K
30
BS_OK ADC_IN_P <27>
CV366
CV367
CV368
CV369
RV365
PFM_ADC_MUX_SEL_R 29 SNN_ADC_CUSTOM8 ADC_IN_N <27>
1 @ 2 8
2 2 2 2 0_0402_5% MUX_SEL NC 18 SNN_ADC_CUSTOM18
NC 21 SNN_ADC_CUSTOM21
PFM_ADC_FILTER_EN 28 NC 31 SNN_ADC_CUSTOM31
ENABLE NC ON_X76@ 243K_0402_1%
23 PFM_BG_REF_OUT RV366 1 2
PFM_SKIP_R 25 BG_REF_OUT 24 PFM_BS_REF
@ @ N18P@ N18P@ SKIP BS_REF 22 PFM_CM_REF_IN
CM_REF_IN RV367
1 1 1
1
<27> GPIO22_OC_W ARN# PFM_ADC_FILTER_MODE
1000P_0402_50V7K
CV370
1000P_0402_50V7K
CV371
1000P_0402_50V7K
CV372
10K_0402_1%
RV369
26 33 1 2 1
MODE_SEL GND
1000P_0402_50V7K
CV373
365K_0402_1%
1
681K_0402_1%
RV368
2 2 2 N18P@
NCP45491XMNTW G_QFN32_4X4
2
N18P@
SA0000C9Q00
N18P@
N18P@
ON_X76@ N18P@ N18P@ N18P@
2
+3V_OVRM
+3V_OVRM
1
RV370 +3V_OVRM
@ 10K_0402_1% RV371
3 1K_0402_1% 3
1
2
PFM_ADC_FILTER_EN RV372
2
N18P@ 10K_0402_1%
N18P@
1
PFM_SKIP_R
1
D
RV373
2
10K_0402_1% 2
OVRM_EN <17,58>
N18P@ G
1
S QV16 @ PFM_PF_BSOK_R
2
L2N7002W T1G_SC-70-3 RV400 VGA@ UV47 uPI_X76@

SB00001GE00 100K_0402_5%
S IC US5650QQKI W QFN 32P POW ER MONITOR

2
+3V_OVRM
SA0000CMA00 0730 FAE CF suggest , reserve pull high only
RV344 uPI_X76@ RV359 uPI_X76@ RV366 uPI_X76@

1
RV374
@ 10K_0402_1% 487_0402_1% 357_0402_1% 324K_0402_1%
SD00000EL80 SD034357080 SD034324380
2
PFM_ADC_FILTER_MODE
RV350 uPI_X76@ RV360 uPI_X76@
1
RV375
4 10K_0402_1% 487_0402_1% 357_0402_1% 4
@
SD00000EL80 SD034357080
2

OVR-M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EH5VF M/B LA-H501P 1A
A B C D E
5 4 3 2 1
+1.8V_AON/+3VSDGPU +1.8V_MAIN
+1.8VALW
+1.8VSDGPU_AON UV45
+1.8VALW UG27 1 +1.8VSDGPU_MAIN
1 14 2 VIN1
VIN1 VOUT1 1 VIN2
2 13 VGA@ CV357
VIN1 VOUT1 CG335 220P_0402_50V8J 1U_0201_6.3V6M 7 6
1V8_AON_EN VIN thermal VOUT
10U_0402_6.3V6M
3 12 1 2 1
+5VALW ON1 CT1 2
CG334 VGA@
10U_0402_6.3V6M
0.1U_0201_10V6K
CV360
D 3 D
PU at GPU side +5VALW VBIAS 1 1
CV359 VGA@
4 11 VGA@
VBIAS GND CG336 220P_0402_50V8J 4 5
3VSDGPU_EN_R 5 10 1 2 2 <27> 1.8VSDGPU_MAIN_EN3V3 ON GND
ON2 CT2 +3VSDGPU 2 2
+3VS 1 1
VGA@
1 6 9 VGA@ @ CV400 VGA@ CV358 AOZ1334DI-01_DFN8-7_3X3
CG337 7 VIN2 VOUT2 8 0.1U_0201_10V6K 0.1U_0201_10V6K
VIN2 VOUT2 VGA@
0.1U_0201_10V6K
2 2 SA000070V00
10U_0402_6.3V6M
VGA@ 15 1
2 +1.8VALW GPAD
CG338 VGA@
EM5209VF_DFN14_2X3
VGA@ 2
22U_0603_6.3V6M
For Power down sequence
1
CG339
VGA@
N18P@ DV9
2 +3VS 1 2
RB751S40T1G_SOD523-2
5
UV46
RV341
VCC
DGPU_PWR_EN 1 10K_0402_5%
IN B 4 3VSDGPU_EN_1 1 2 3VSDGPU_EN_R
1.8VSDGPU_MAIN_EN3V3 2 OUT Y N18P@
GND
IN A
1
1
N18P@ CV356 RV342
NL17SZ08DFT2G_SC70-5 0.1U_0201_10V6K 1M_0402_5%
3
N18P@ VGA@
2
2
For Power down sequence
C DV1 VGA@ C
2 1 1V8_AON_EN
<19,27> DGPU_PWR_EN
RB751S40T1G_SOD523-2 +1.8VSDGPU_AON
1 2
1 1
RV22 CV374
200K_0402_1% CV35 2.2U_0402_6.3V6M +FP_FUSE_GPU
VGA@ 0.1U_0201_10V6K N18P@
2 VGA@ 2 UV48 12mils
6 1
5 VIN1 VOUT1 2
VIN2 VOUT2
1
1
4 3 CV376 RV384
VSS EN 2.2U_0402_6.3V6M 2.21K_0402_1%
GS7616SC-R_SOT363-6 N18P@ N18P@
2
@
2
2 @ 1 GPIO26_FP_FUSE_R
<27> GPIO26_FP_FUSE
RV382 1
10K_0201_5%
0_0402_5% @
RV383
CV375
N18P@ 0.1U_0201_10V6K +1.8VSDGPU_AON
2
UV50 +FP_FUSE_GPU
1
1
2 VIN1
+5VALW VIN2
7 6
VIN thermal VOUT
3
B VBIAS B
4 5
ON GND
AOZ1334DI-01_DFN8-7_3X3
N18P@
SA000070V00
+3VSDGPU +1.0VSDGPU
+NVVDD1
+1.35VSDGPU
2
VGA@
2
+5VS N18P@ +5VS RV377 +5VS
2
RV380 20_0402_5% +5VS VGA@ VGA@
1_0603_5% RV116 RV118
2
2
N18P@ VGA@ 20_0402_5% VGA@ 1_0603_5%
1
2
RV381 RV376 VGA@ RV117
1
100K_0402_5% 100K_0402_5% RV115 100K_0402_5%
1
100K_0402_5%
6
6
D D D
1
1
6
3VSDGPU_EN_R# 2 QV15A GPUCORE_EN# 2 QV14A VGA@ D NVVDD_EN# 2
1
G 2N7002KDW_SOT363-6 G 2N7002KDW_SOT363-6 1.35VSDGPU_EN# 2 G
3
N18P@ G D
3
S S D 5 S
<27,95> NVVDD1_EN
1
1
3
D D 5 S G QV10A
<27,93> 1.35VSDGPU_EN
1
3VSDGPU_EN_R 5 5 G QV11A 2N7002KDW_SOT363-6
G <27> GPUCORE_EN G S
2N7002KDW_SOT363-6 VGA@
4
S VGA@ QV10B
4
A S S QV11B A
2N7002KDW_SOT363-6
4
QV15B QV14B 2N7002KDW_SOT363-6 VGA@

2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 VGA@
N18P@ VGA@

GPU DC INTERFACE
1A
5 4 3 2 1
A B C D E
SM01000EJ00 3000ma
220ohm@100mhz
LCD POWER CIRCUIT DCR 0.04
+3VS +LCDVDD +19VB_CPU +INVPW R_B+

Place closed to
UX1 W=60mils JEDP1 +LCDVDD
+3VS
1U_0201_6.3V6M
CX2
5 1 W=60mils W=60mils
IN OUT LX1 EMI@
1 1 1
10U_0402_6.3V6M
2 1 1 HCB2012KF-221T30_0805
0.1U_0201_10V6K
0.1U_0201_10V6K
GND
10U_0402_6.3V6M
1 2 CX7 1 1 1
CX3
4 3 CX4 1 @
2 EN OC
CX1
0.1U_0201_10V6K 1 CX6 CX8
SY6288C20AAC_SOT23-5 2 2 CX5 1000P_0402_50V7K
@ 2 2 2
68P_0402_50V8J EMI@
<17> PCH_ENVDD 2
XEMI@
1
2
RX1
100K_0402_5%
2
+INVPW R_B+_BOOST +INVPW R_B+
RX3
0_0402_5%
+LCDVDD 1 @ 2 EDP_HPD_R RX13 1 @ 2 0_0603_5%
<16> EDP_HPD
LED PANEL Conn.
1
1
RX4 +INVPW R_B+ JEDP1

RX11
W=60mils 1
100K_0402_5% 1
10K_0402_5% 2
3 2
2
4 3
2
PANEL_OD_EN 5 4
PCH_BKL_PW M 6 5
2 BKOFF# 7 6 2
7
1
+LCDVDD EDP_HPD_R 8
RX12 @ 9 8
10 9
10K_0402_5% 10
PCH_BKL_PW M 1 @ 2 11
<17> PCH_BKL_PW M 11
RX10 100K_0402_5% 12
<19> PANEL_OD_EN
2
XESD@ 13 12
CX9 1 2 220P_0402_50V7K EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
<6> EDP_AUXN EDP_AUXP CX19 EDP_AUXP_C 14
<6> EDP_AUXP 1 2 0.1U_0201_10V6K 15
XESD@ 16 15
BKOFF# CX10 1 2 220P_0402_50V7K EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
<58> BKOFF# <6> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
1 2 0.1U_0201_10V6K 18
<6> EDP_TXN0 18
19
RX5 1 @ 2 10K_0402_5% EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20 19
<6> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
1 2 0.1U_0201_10V6K 21
<6> EDP_TXN1 21
22
EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
1 2 0.1U_0201_10V6K 24
<6> EDP_TXN2 24
25
EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
1 2 0.1U_0201_10V6K 27
<6> EDP_TXN3 27
28
USB20_P6 29 28
USB Touch Screen <14> USB20_P6
<14> USB20_N6
USB20_N6 30 29
30
31
+TS_PW R 32 31
Touch +TS_PW R 32
+5VS +3VS 33
Screen TS_EN 33
RX6 1 @ 2 0_0603_5% 34
<19,58> TS_EN 34
+3VS 35 41
3 RX7 1 2 0_0603_5% USB20_N5_CAMERA 36 35 GND 42 3
USB20_P5_CAMERA 37 36 GND 43
For 37 GND
Camera 38 44
DMIC_CLK_R 39 38 GND 45
<56> DMIC_CLK_R DMIC_DATA_R 39 GND
40 46
Camera <56> DMIC_DATA_R 40 GND
ACES_50203-04001-002
CONN@
USB20_N5 RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
<14> USB20_N5 DMIC_CLK_R SP010014B10
USB20_P5 RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<14> USB20_P5 DMIC_DATA_R
2
DX1
YSLC05CH_SOT23-3
XESD@
1
4 4

eDP CONN.
A B C D E
A B C D E
1 1
2 2
Reserve Page
3 3
4 4

DP CONN
Custom 1A
A B C D E
A B C D E
HDMI_CLKN RY27 1 2 499_0402_1% HDMI_GND

CY22 1 2 .1U_0402_16V7K HDMI_CLKP HDMI_CLKP RY28 1 2 499_0402_1%
<29> GPU_DP2_P3 HDMI_CLKN HDMI_TX_N0
CY24 1 2 .1U_0402_16V7K RY29 1 2 499_0402_1%
<29> GPU_DP2_N3 HDMI_TX_P0 RY30 1 2 499_0402_1%
1 CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 1
<29> GPU_DP2_P2 HDMI_TX_N0
CY17 1 2 .1U_0402_16V7K
<29> GPU_DP2_N2
CY18 1 2 .1U_0402_16V7K HDMI_TX_P1
<29> GPU_DP2_P1 HDMI_TX_N1 HDMI_TX_N1
CY19 1 2 .1U_0402_16V7K RY31 1 2 499_0402_1%
<29> GPU_DP2_N1 HDMI_TX_P1 RY32 1 2 499_0402_1%
CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 HDMI_TX_N2 RY33 1 2 499_0402_1%
<29> GPU_DP2_P0 HDMI_TX_N2 HDMI_TX_P2
CY21 1 2 .1U_0402_16V7K RY34 1 2 499_0402_1%
<29> GPU_DP2_N0
HDMI_CLKP RY15 1 2 6.04_0402_1% HDMI_R_CLKP +5VS W=40mils +HDMI_5V_OUT
3
D
2
1
+3VS 5 QY2B
G UY2
CY26 XEMI@ RY36 XEMI@ 2N7002KDW _SOT363-6
3.3P_0402_50V8 150_0402_1%
1
S 3
4
OUT
1
2
HDMI_CLKN RY14 1 2 6.04_0402_1% HDMI_R_CLKN 1
IN CY23
2 0.1U_0201_10V6K
HDMI_TX_P0 RY16 1 2 6.04_0402_1% HDMI_R_TX_P0 GND 2
1
AP2330W -7_SC59-3
RY37 XEMI@
150_0402_1%
2
2 HDMI_TX_N0 RY17 1 2 6.04_0402_1% HDMI_R_TX_N0 2
HDMI_TX_P1 RY18 1 2 6.04_0402_1% HDMI_R_TX_P1

+HDMI_5V_OUT
1
RY38 XEMI@
150_0402_1% DY2 XESD@ HDMI_CTRL_DAT RY40 1 2 2.2K_0402_5% +1.8VSDGPU_AON
HDMI_R_CLKN 1 9 HDMI_R_CLKN HDMI_CTRL_CLK RY41 1 2 2.2K_0402_5%
GPU_DP2_CTRL_CLK RY42 1 2 2.2K_0402_5%
2
HDMI_TX_N1 RY19 1 2 6.04_0402_1% HDMI_R_TX_N1 HDMI_R_CLKP 2 8 HDMI_R_CLKP GPU_DP2_CTRL_DAT RY43 1 2 2.2K_0402_5%
HDMI_R_TX_N0 4 7 HDMI_R_TX_N0
HDMI_TX_P2 RY20 1 2 6.04_0402_1% HDMI_R_TX_P2
HDMI_R_TX_P0 5 6 HDMI_R_TX_P0
1
RY39 XEMI@
150_0402_1%
3
2
HDMI_TX_N2 RY22 1 2 6.04_0402_1% HDMI_R_TX_N2 TVW DF1004AD0_DFN9

SC300003Z00 +HDMI_5V_OUT HDMI connector
JHDMI1
DY3 XESD@ HDMI_HPD 19
HDMI_R_TX_N1 1 9 HDMI_R_TX_N1 18 HP_DET
17 +5V
+3VS +3VS HDMI_R_TX_P1 2 8 HDMI_R_TX_P1 HDMI_CTRL_DAT 16 DDC/CEC_GND
3 HDMI_CTRL_CLK 15 SDA 3
HDMI_R_TX_N2 4 7 HDMI_R_TX_N2 14 SCL
Reserved
2
13
HDMI_R_TX_P2 5 6 HDMI_R_TX_P2 HDMI_R_CLKN 12 CEC 20
RY24 11 CK- GND 21
CK_shield GND
2
1M_0402_5% HDMI_R_CLKP 10 22
G
QY2A HDMI_R_TX_N0 9 CK+ GND 23

1
2N7002KDW _SOT363-6 3 8 D0- GND

HDMI_R_TX_P0 7 D0_shield
1 6 HDMI_HPD TVW DF1004AD0_DFN9 HDMI_R_TX_N1 6 D0+
S
<16,27> HDMI_HPD_PCH D1-

D
5
SC300003Z00 HDMI_R_TX_P1 4 D1_shield
D1+
2
HDMI_R_TX_N2 3
RY11 DY1 2 D2-
RY11 design guide rev2.0 use 20K pull down. 100K_0402_5% HDMI_HPD 6 3 HDMI_CTRL_DAT HDMI_R_TX_P2 1 D2_shield
I/O4 I/O2 D2+
ACON_HMR2E-AK120D
1
CONN@
5 2
VDD GND DC232000Y00
+1.8VSDGPU_AON
HDMI_CTRL_CLK 4 1
I/O3 I/O1 +HDMI_5V_OUT
AZC099-04S.R7G_SOT23-6
XESD@
5
QY1A
PJT138KA_SOT363-6 SC300001G00
G
4 3 HDMI_CTRL_CLK
4 <29> GPU_DP2_CTRL_CLK 4
S
QY1B
PJT138KA_SOT363-6
G
1 6 HDMI_CTRL_DAT
<29> GPU_DP2_CTRL_DAT Security Classification Compal Secret Data Compal Electronics, Inc.
S
3ohm/10pF Issued Date 2017/10/30 Deciphered Date 2018/10/30 Title
HDMI CONN.
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
+5VALW +5VALW _MUX
US14
5 1
IN OUT
10U_0402_6.3V6M
0.1U_0201_10V6K
2 1 1
GND
D D
CS116
CS15
4 3
<58,72,73> USB_EN EN OC
SY6288C20AAC_SOT23-5 2 2
Close to Pin19
+5VALW _MUX +USB3_VCCC
CC1_VCONN CS130 1 2 220P_0402_50V8J

CC2_VCONN CS129 1 2 220P_0402_50V8J
1
RS20 RS134
4.7K_0402_5% 200K_0402_1%
US3
2
OCP_DET# VMON
1
VMON 17 12 CC1_VCONN
VMON CC1 CC2_VCONN CC1_VCONN <43>
RS135 14 CC2_VCONN <43>
RS128 10K_0402_1% OCP_DET# 16 CC2
<43> OCP_DET# OCP_DET
10K_0402_5%
USBC_EN 15
2
<43> USBC_EN VBUS_EN Type-C Port Side

C 11 USB3_CC_TX_P2 CS112 1 2 .1U_0402_16V7K USB3_CC_TX_P2_C C
USB3.0 (Port 2) System side C_TX2_1P/2N 10 USB3_CC_TX_N2 CS113 1 2 .1U_0402_16V7K USB3_CC_TX_N2_C USB3_CC_TX_P2_C <43>
C_TX2_1N/2P USB3_CC_TX_N2_C <43>
CS125 1 2 0.22U_0201_6.3V6M USB3_PRX_C_DTX_P2 4
<17> USB3_PRX_DTX_P2 USB3_PRX_C_DTX_N2 SSRX_1P/2N USB3_CC_RX_P2
CS126 1 2 0.22U_0201_6.3V6M 5 24 CS121 1 2 0.33U_0201_6.3V6M USB3_CC_RX_P2_C USB3_CC_RX_P2_C <43>
<17> USB3_PRX_DTX_N2 SSRX_1N/2P C_RX2_1P/2N USB3_CC_RX_N2
1 CS122 1 2 0.33U_0201_6.3V6M USB3_CC_RX_N2_C USB3_CC_RX_N2_C <43>
C_RX2_1N/2P
CS127 1 2 0.22U_0201_6.3V6M USB3_PTX_C_DRX_P2 6 10 Gbps 2:1 MUX 8 USB3_CC_TX_P1 CS114 1 2 .1U_0402_16V7K USB3_CC_TX_P1_C
<17> USB3_PTX_DRX_P2 USB3_PTX_C_DRX_N2 SSTX_1P/2N C_TX1_1P/2N USB3_CC_TX_N1 USB3_CC_TX_N1_C USB3_CC_TX_P1_C <43>
<17> USB3_PTX_DRX_N2 CS128 1 2 0.22U_0201_6.3V6M 7 9 CS115 1 2 .1U_0402_16V7K
SSTX_1N/2P C_TX1_1N/2P USB3_CC_TX_N1_C <43>
2 USB3_CC_RX_P1 CS123 1 2 0.33U_0201_6.3V6M USB3_CC_RX_P1_C

C_RX1_1P/2N USB3_CC_RX_N1 USB3_CC_RX_P1_C <43>
3 CS124 1 2 0.33U_0201_6.3V6M USB3_CC_RX_N1_C USB3_CC_RX_N1_C <43>
PLUG_ORI 23 C_RX1_1N/2P
M1 21 GPIO
M0 22 CURRENT_M1
CURRENT_M0
USB3_CC_RX_P2_C
USB3_CC_RX_N2_C
VCON_IN
LDO_3V3
18
REXT
2
5V_IN
1
RS129 25 RS130 RS131

6.2K_0402_1% E-PAD 220K_0201_1% 220K_0201_1%
RTS5441E-GRT_QFN24_4X4
20
19
13
+3VO_MUX +3VO_MUX
1
2
+3VO_MUX +5VALW _MUX

B B
1
1 1
1
CS14 CS117 USB3_CC_RX_P1_C

RS1 RS3 4.7U_0402_6.3V6M 0.1U_0201_10V6K USB3_CC_RX_N1_C
RS114 @ 10K_0402_5% 10K_0402_5%
10K_0402_5% 2 2
Close to Pin13
2
2
2
PLUG_ORI M1 M0 1 2 RS132 RS133

TYPEC_1P5A_EC <43,58>
RS137 0_0402_5% 220K_0201_1% 220K_0201_1%
1
1
RS115 RS2 @ RS4 @
10K_0402_5% 10K_0402_5% 10K_0402_5%
2
5441E Current Limit RTS5441 M0 truth table by 2018 BIOS spec

M1 M0 MODE TYPEC_1P5A_EC MODE limit point Condition
L H 0.9A H 3A 3.5A AC mode or Battery >30%
H L 1.5A L 1.5A 1.92A Battery <30% when DC mode
A H H 3A A
confirm realtek hand-shake

CC+USB TYPE C
5 4 3 2 1
5 4 3 2 1
+5VALW +USB3_VCCC
RSET
SGA00003700
150U_D2_6.3VY_R15M
CS95
1
1
0.1U_0201_10V6K
0.1U_0402_25V6
22U_0805_25V6M
22U_0805_25V6M
1 1 1 1
CS96
CS97 @
CS98 @
CS99 @
+ RS113 RS109 RS110
6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5%
2 2 2 2 2
3 2
US11
D
6 1 5 TYPEC_3A <18>
IN OUT G
D D
RSET 5 2 S QS2B
4
SET GND 1 @ 2 2N7002KDW _SOT363-6
OCP_DET# <42>
6
RS136 0_0402_5% D
4 3 1 2 2 TYPEC_1P5A_EC <42,58>
<42> USBC_EN EN FLAG USB_OC0# <14> G
RS112 0_0402_5%
1
G518B1TP1U_TSOT23-6 1
RB77 S QS2A
1
47K_0402_5% footprint : G518 CS100 2N7002KDW _SOT363-6
PN : SA0000BDN00(SILERGY SY6861B1) 0.1U_0201_10V6K check bios
2
1050 is use PCH output
2
G518 MOS Current Limit
For ESD request GPP_B1 GPP_B4 RSET(kΩ ) MODE limit point
(TYPEC_1P5A) (TYPEC_3A)
DS3 ESD@
USB3_CC_TX_P1_C
L L 6.2 0.9A 1.09A
<42> USB3_CC_TX_P1_C 1 9
USB3_CC_TX_N1_C L H 3.53 1.5A 1.92A
<42> USB3_CC_TX_N1_C 2 8
CC1_VCONN CC1_VCONN
H L 2.54 2A 2.67A
4 7
TBTA_SBU1 TBTA_SBU1
*H H 1.94 3A 3.5A
5 6
C C
3
TVW DF1004AD0_DFN9
SC300003Z00
DS4 ESD@
1 9
2 8
4 7 USB3_CC_TX_N2_C
<42> USB3_CC_TX_N2_C
5 6 USB3_CC_TX_P2_C +USB3_VCCC +USB3_VCCC
<42> USB3_CC_TX_P2_C
3
JTYPEC1
TVW DF1004AD0_DFN9 A1 B12
GND GND
SC300003Z00 USB3_CC_TX_P1_C A2 B11 USB3_CC_RX_P1_C
USB3_CC_TX_N1_C A3 SSTXP1 SSRXP1 B10 USB3_CC_RX_N1_C
0.1U_0402_25V6 2 1 CS84 SSTXN1 SSRXN1
DS6 ESD@ A4 B9 CS87 1 2 0.1U_0402_25V6
USB20_P2_L 1 9 USB20_P2_L VBUS VBUS
1
CS13 A5 B8 TBTA_SBU2
USB20_N2_L USB20_N2_L <42> CC1_VCONN CC1 SBU2
2 8 10U_0603_25V6M
B USB20_P2_L A6 B7 USB20_N2_L B
4 7 USB3_CC_RX_N2_C 2 USB20_N2_L A7 DP1 DN2 B6 USB20_P2_L
<42> USB3_CC_RX_N2_C DN1 DP2
3
5 6 USB3_CC_RX_P2_C 2 TBTA_SBU1 A8 B5 CC2_VCONN <42>

<42> USB3_CC_RX_P2_C SBU1 CC2
0.1U_0402_25V6
2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
DS19 ESD@ VBUS VBUS
3 PESD24VS2UT_SOT23-3 USB3_CC_RX_N2_C A10 B3 USB3_CC_TX_N2_C
SCA00004500 USB3_CC_RX_P2_C A11 SSRXN2 SSTXN2 B2 USB3_CC_TX_P2_C
1
TVW DF1004AD0_DFN9 SSRXP2 SSTXP2
SC300003Z00 A12 B1
GND GND
DS5 ESD@ 1 5
CC2_VCONN 1 9 CC2_VCONN 2 GND GND 6
3 GND GND 7
TBTA_SBU2 2 8 TBTA_SBU2 4 GND GND 8
GND GND
4 7 USB3_CC_RX_N1_C DEREN_40-42407-0246300RHF
<42> USB3_CC_RX_N1_C
CONN@
5 6 USB3_CC_RX_P1_C
<42> USB3_CC_RX_P1_C DC23300RC00
3
CC1_VCONN & CC2_VCONN need 20miil trace width.
TVW DF1004AD0_DFN9
SC300003Z00
A A
LS10 EMI@
USB20_P2 2 1 USB20_P2_L
<14> USB20_P2 2 1
USB20_N2 3 4 USB20_N2_L Security Classification Compal Secret Data Compal Electronics, Inc.
<14> USB20_N2 3 4
DLM0NSN900HY2D_4P
SM070005U00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC+USB TYPE C
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
+3V_LAN Rising time (10%~90%) must >0.5mS and <100mS

RTL8111H LDO mode
+3VALW +3V_LAN
RTL8118ASA SWR mode
RL2 @
0_0805_5% LDO@
1 2 W=60mil RL1 1 2 0_0603_5% W=60mil Place near Pin 11,32
+LAN_VDD +3V_LAN
60mil 60mil 300mA 300mA W=60mil
UL1 SWR@
5 1 +REGOUT LL1 1 2
1 IN OUT 1
2 2.2UH_HPC252012NF-2R2M_20%
GND
1 IDC=1200mA 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL1
4.7U_0402_6.3V6M
CL2
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL4
0.1U_0201_10V6K
CL5
0.1U_0201_10V6K
CL6
0.1U_0201_10V6K
CL7
0.1U_0201_10V6K
CL8
1U_0201_6.3V6M
CL9
0.1U_0201_10V6K
CL10
0.1U_0201_10V6K
CL11
4.7U_0402_6.3V6M
CL12 SWR@
0.1U_0201_10V6K
CL13 SWR@
4.7U_0402_6.3V6M
CL14 @
4.7U_0402_6.3V6M
CL15 @
4 3
EN OC
2
SY6288C20AAC_SOT23-5 Using for Switch mode
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
LDO@
SWR@
SWR@
CL16
1U_0201_6.3V6M The trace length from
1 LAN_PWR_EN Lx to PIN48 (REGOUT)
LAN_PWR_EN <58>
and from C to Lx must
< 200mils.
Place near Pin 3,8,22,30 Place near Pin 22
11/27: P/N change to SH00000RT00 Place near Pin 11,32
From EC
( S COIL 2.2UH +-20%
High active. HPC252012NF-2R2M 1.3A) Using for Switch mode
Reserve for surge improvement
EN threshold voltage min:1.2V The trace length
typ:1.6V max:2.0V from C to Place near Pin 11,32
Current limit threshold 1.5~2.8A
PIN46,47(VDDREG)
+3V_LAN Rising time must >0.5ms and <100ms must < 200mils.
+3VS UL2
1
RL3
2 1K_0402_5% 2
+3V_LAN +LAN_VDD LAN_MIDI0+ 1 17 PCIE_PRX_C_DTX_P14 .1U_0402_16V7K 2 1 CL17

PCIE_PRX_DTX_P14 <17>
2
ISOLATEB LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_PRX_C_DTX_N14 .1U_0402_16V7K 2 1 CL18

3 MDIN0 HSON 19 PCIE_PRX_DTX_N14 <17>
AVDD10 PERSTB PLT_RST_BUF# <16,52,68>
2
LAN_MIDI1+ 4 20 ISOLATEB
RL5 LAN_MIDI1- 5 MDIP1 ISOLATEB 21 LAN_PME# 0_0402_5% 1 @ 2 RL4
LAN_MIDI2+ MDIN1 LANWAKEB EC_PME# <16,58>
15K_0402_5% 6 22 10K_0402_5% 2 1 RL6
LAN_MIDI2- MDIP2 DVDD10 +LAN_VDD +3V_LAN
7 23
MDIN2 VDDREG +3V_LAN
8 24 +REGOUT reserve EC_PME# pull high 47K to +3VLP_EC
1
LAN_MIDI3+ 9 AVDD10 REGOUT 25 LAN_LED2 T1 @

LAN_MIDI3- 10 MDIP3 LED2 26 LAN_LED1_GPO 2 @ 1
LAN_CLKREQ# pull up at PCH side 11 MDIN3 LED1/GPIO 27 LAN_LED0 T2 @ 0_0402_5% RL7
LAN_GPO <18>
12 AVDD33 LED0 28 XTLI for disable PHY
<15> LAN_CLKREQ# 13 CLKREQB CKXTAL1 29 XTLO reserve 0 ohm
<17> PCIE_PTX_C_DRX_P14 HSIP CKXTAL2
14 30
<17> PCIE_PTX_C_DRX_N14 HSIN AVDD10 LAN_RST
YL1 15 31 1 2
<15> CLK_PCIE_LAN REFCLK_P RSET
25MHZ_20PF_XRCGB25M000F2P18R0 16 32 RL8
<15> CLK_PCIE_LAN# REFCLK_N AVDD33 33 2.49K_0402_1%
XTLI 3 1 XTLO_R RL14 1 2 XTLO GND
3 1 680_0402_5%
NC NC
1 1
CL21 4 2 CL22 +3V_LAN
18P_0402_50V8J 18P_0402_50V8J
2 2 RTL8111GS-CG_QFN32_4X4 LAN_LED1_GPO 10K_0402_5% 2 @ 1 RL9
SA0000B9F20
P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0) SA0000B9F20, S IC RTL8118ASA-CG QFN 32P E-LAN CTRL
3 3
LAN Connector
JRJ45
TL1
LAN_TERMAL 1 24 RJ45_MIDI3- 8
LAN_MIDI3- 2 TCT1 MCT1 23 RJ45_MIDI3- PR4-
LAN_MIDI3+ 3 TD1+ MX1+ 22 RJ45_MIDI3+ RJ45_MIDI3+ 7
TD1- MX1- PR4+
4 21 RJ45_MIDI1- 6
LAN_MIDI2+ 6 TD2+ MX2+ 19 RJ45_MIDI2+ RJ45_MIDI2- 5
TD2- MX2- PR3-
7 18 RJ45_MIDI2+ 4
LAN_MIDI1- 8 TCT3 MCT3 17 RJ45_MIDI1- PR3+
LAN_MIDI1+ 9 TD3+ MX3+ 16 RJ45_MIDI1+ RJ45_MIDI1+ 3
TD3- MX3- PR2+
10 15 RJ45_MIDI0- 2
LAN_MIDI0+ 12 TD4+ MX4+ 13 RJ45_MIDI0+ RJ45_MIDI0+ 1 CL23
TD4- MX4- PR1+ 12
40mil 40mil
10P_0402_50V8J
GND 11 LANGND 2 1 RJ45_GND
GND 10
GST5009-E GND 9
GND
2
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
SP050006B10
1
MESC5V02BD03_SOT23-3
1 SANTA_130460-5 @
CONN@ DL1
RL11
RL12
RL10
RL13
ESD@ JPL1
CL24 DC234007W00 JUMP_43X118
0.1U_0201_10V6K 2
2
4 4
LANGND
1
RJ45_GND

LAN RTL8118ASA
Custom 1A
A B C D E
A B C D E
Wireless LAN
+3VALW W=60mils +3VS_W LAN
UM1
1U_0201_6.3V6M
CM15
5 1
IN OUT
1
2
@ GND
1 1
4 3
2 <58> W LAN_ON EN OC
SY6288C20AAC_SOT23-5
IOAC@
+3VALW +3VS_W LAN
RM44 1 @ 2 0_0805_5% UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%

UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <19>
RM43 1 UART@ 2 0_0402_5%
+3VS UART_2_PTXD_DRXD <19>
reserve for cnvi
RM11 1 NIOAC@ 2 0_0805_5%
Co-layout with CNVi for SW debug
0.1U_0201_10V6K
0.1U_0201_10V6K
CM14
60mil 1 1 1 1@
CM13 @
CM12 CM19
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
2 2 2 2 reserve 1000p for cnvi
KEY E +3VS_W LAN

CM18 1
@
2 1000P_0402_50V7K
JNGFF1
1 2
GND_1 3.3VAUX_2 CNVI@
3 4 1 RM41 2
<14> USB20_P14 USB_D+ 3.3VAUX_4
(For BT) 5 6 @ T52 75K_0402_1%
<14> USB20_N14 USB_D- LED1#
7 8
2 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 @ 2 0_0201_5% 2
<15> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <18>
<15> CNV_PRX_DTX_P1 11 12
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 @ 2 0_0201_5%
SDIO_DAT0 PCM_IN CLKREQ_CNV# <18>
<15> CNV_PRX_DTX_N0 15 16 @ T53
17 SDIO_DAT1 LED2# 18
<15> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18
19 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 0_0402_5%
<15> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <15>
23
<15> CLK_CNV_PRX_DTX_P SDIO_RST
24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 0_0402_5%
UART_RX CNV_RGI_PTX_DRX <15>
25 26
GND_33 UART_RTS CNV_RGI_PRX_DTX <15>
27 28 CNV_BRI_PTX_DRX <15>
<17> PCIE_PTX_C_DRX_P15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM12 1 @ 2 0_0201_5%
<17> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <58>
31 32 RM13 1 @ 2 0_0201_5%
NGFF WL+BT (KEY E) (link to PICE Port 3)
PCIE X1
<17> PCIE_PRX_DTX_P15 33
35
GND_39
PER_TX_P0
CLink_DATA
CLink_CLK
34
36
E51RXD_P80CLK <58>
<17> PCIE_PRX_DTX_N15 PER_TX_N0 COEX3

37 38
39 GND_45 COEX2 40
<15> CLK_PCIE_W LAN REFCLK_P0 COEX1 SUSCLK_R
41 42 RM14 1 @ 2 0_0201_5%
<15> CLK_PCIE_W LAN# REFCLK_N0 SUSCLK(32KHz) W L_RST#_R SUSCLK <18,68>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0201_5%
GND_51 PERST0# BT_ON PLT_RST_BUF# <16,51,68>
PCIE CLK <15> W LAN_CLKREQ# 45 46
W LAN_PME# CLKREQ0# W_DISABLE2# W L_OFF# BT_ON <58>
47 48
PEWAKE0# W_DISABLE1# W L_OFF# <58>
49 50
51 GND_57 I2C_DAT 52
<15> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
53 54
<15> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ REFCLK_CNV_R
55 56 RM40 1 ESD@ 2 0_0402_5% REFCLK_CNV <15>
57 GND_63 RSVD_64 58
<15> CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
59 60
<15> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62 1
3 63 GND_69 RSVD_70 64 CM17 XESD@ 3
<15> CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72
65 66 0.1U_0201_10V6K
<15> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67
GND_75 68 2 For ESD req reserve LC filter
69 GND1 close PCH
GND2
BELLW _80152-3221
CONN@ E51TXD_P80DATA_R
SP070013E00
1
RM19
100K_0402_5%
2 1 W LAN_PME#
+3VS_W LAN
RM16 10K_0402_5%
2
reserve for BT_ON OD pull high (1.0)
BT_ON 1 @ 2
4 +3VS_W LAN 4
8.2K_0402_5% RM45

M.2 Key E (WLAN)
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
HD Audio Codec 2000mA 600ohm@100MHz

DCR 0.1
+5VS
40mil +5VS_PVDD
LA1
TAI-TECH HCB1608KF-601T20
1 2
SM01000UN00
+5VS
1 1 1 1
+5VS_AVDD
10U_0402_6.3V6M
CA1
0.1U_0201_10V6K
CA2
10U_0402_6.3V6M
CA29
0.1U_0201_10V6K
CA3
Use LV1 symbol.
20mil RA1 @
0_0603_5%
2 2 2 2 1 2
1 1 1 1
0.1U_0201_10V6K
CA5
10U_0402_6.3V6M
CA6
2 2
near Pin41 near Pin46
GNDA
CA7 1 2 0.1U_0201_10V6K
near Pin26 +1.8VS
near Pin9 CA8 1 2 10U_0402_6.3V6M
+3VS +1.8VS_VDDA 1 @ 2
1 @ 2 +3VS_DVDDIO RA3 0_0402_5%
1 1
0.1U_0201_10V6K
CA11
10U_0402_6.3V6M
CA12
RA2 0_0402_5%
+3VS_DVDD
Int. Speaker Conn.
+3VS 20mil 2 2
1 @ 2 GNDA
RA4 0_0402_5% 1 1
10U_0402_6.3V6M
CA9
0.1U_0201_10V6K
CA10
40mil
JSPK2
2 2 HDA_BIT_CLK_R SPKL+ LA4 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_L+ 1
SPKL- LA5 EMI@ 1 2 PBY160808T-121Y-N_2P SPK_L- 2 1
near Pin1 Place near Pin40 2
2
3
41
46
26
40
G1
9
10P_0402_50V8J 2 1 CA27 DMIC_CLK UA1 RA5 4
G2
0_0402_5%
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
XEMI@ CVILU_CI4202M2HR0-NH
Reserved for RF CONN@
1
XEMI@
LINE1_L 22 43 SPKL- SP02001CK00
LINE1_R LINE1-L(PORT-C-L) SPK-OUT-L- 2
21 42 SPKL+ GND
LINE1-R(PORT-C-R) SPK-OUT-L+ CA13
24 45 SPKR+ SPKR+ <73> 22P_0402_50V8J
2 23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 SPKR- 1 2
+MICBIAS LINE2-R(PORT-E-R) SPK-OUT-R- SPKR- <73>
XEMI@
31
30 LINE1-VREFO-L 32 HP_LEFT
LINE1-VREFO-R HPOUT-L(PORT-I-L) 33 HP_RIGHT
+3VS RING2 17 HPOUT-R(PORT-I-R)
2 1 SENSE_A SLEEVE 18 MIC2-L(PORT-F-L) /RING
RA13 100K_0402_1%
40mil MIC2-R(PORT-F-R) /SLEEVE 10 HDA_SYNC_R
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <18>
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK 5 HDA_SDOUT_R HDA_BIT_CLK_R <18>
GPIO1/DMIC-CLK SDATA-OUT 8 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <18>
<58> EC_MUTE#
47
PDB
SDATA-IN RA10 33_0402_5%
HDA_SDIN0 <18>
Digital MIC
48
11 SPDIF-OUT/GPIO2
<18> HDA_RST#_R RESETB 16 MIC BOM upload by Audio Team
MONO_IN 12 MONO-OUT
PCBEEP +MIC2_VREFO
Close codec
<73> HP_PLUG# RA12 2 1 200K_0402_1% SENSE_A 13 29
14 HP/LINE1 JD(JD1) MIC2-VREFO
RA17 2 @ 1 20K_0402_5% 15 MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3 7 CA14 1 2 10U_0402_6.3V6M
1 LDO3-CAP GND
37 39 CA16 1 2 10U_0402_6.3V6M TO eDP cable
CA15 35 CBP LDO2-CAP 27 CA17 1 2 10U_0402_6.3V6M DMIC_DATA 2 @ 1 DMIC_DATA_R
GNDA CBN LDO1-CAP DMIC_DATA_R <38>
1U_0201_6.3V6M 10mil RA14 1 2 100K_0402_5% RA7 0_0402_5%
2
CODEC_VREF GNDA PCH_DMIC_DATA0 2
+3VS_DVDD
36 28 <18> PCH_DMIC_DATA0 @ 1
CPVDD VREF RA8 33_0402_5%
CA20 1 2 2.2U_0402_6.3V6M
20 PCH_DMIC_CLK0 2 @ 1
+3VALW VD33 STB <18> PCH_DMIC_CLK0
CA21 @1 2 0.1U_0201_10V6K RA9 33_0402_5%
GNDA CA19 1 2 19 34 CPVEE
MIC CAP CPVEE DMIC_CLK DMIC_CLK_R
1U_0201_6.3V6M
CA22
1 2 1
10U_0402_6.3V6M LA6 EMI@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
GNDA
SM01000Q500
RA19 2 @ 1 0_0402_5% 4 25 change PN to SM01000Q500
3 49 DC DET AVSS1 38 2 3
Thermal PAD AVSS2
ALC255-CG_MQFN48_6X6
GND SA000082700
GNDA
Headphone Out
+MIC2_VREFO
TO IO/B
RA15 1 2 2.2K_0402_5% SLEEVE SLEEVE <73>
RA18 1 2 2.2K_0402_5% RING2 RING2 <73>
HP_LEFT RA20 1 @ 2 0_0603_5% HPOUT_L_1 HPOUT_L_1 <73>

HP_RIGHT RA21 1 @ 2 0_0603_5% HPOUT_R_1
HPOUT_R_1 <73>
LINE1_L CA23 1 2 4.7U_0402_6.3V6M

RA22
22K_0402_5% CA25 LINE1_R CA24 1 2 4.7U_0402_6.3V6M
1U_0201_6.3V6M
2 1 BEEP#_R 1 2 MONO_IN RA25 1 @ 2 0_0402_5% RA26 1 @ 2 0_0402_5%
<58> BEEP#
+MICBIAS DA3
2
RA27 XESD@ 1 RA29 1 @ 2 0_0402_5% RA30 1 @ 2 0_0402_5% 2 2 RA23 1

22K_0402_5% 4.7K_0402_5%
100P_0402_50V8J
CA26
4 2 1 RA24 1 4
<18,19> PCH_SPKR 4.7K_0402_5% RA31 1 @ 2 0_0402_5% RA32 1 @ 2 0_0402_5%
2 3 2 RA28 1
1
4.7K_0402_5%
RA33 1 @ 2 0_0402_5% RA34 1 @ 2 0_0402_5% BAT54A-7-F_SOT23-3
SCSBAT54100
GND
GND GNDA GND GNDA
HD Audio Codec ALC255
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
Board ID
+3VLP_EC
+3VLP_EC +3VLP_ECA
2
+3VLP LB1
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA 100K_0402_1%
+3VLP_EC 1 2 Ra
JUMP_43X39
1
EC_PME# AD_BID
0.1U_0201_10V6K
0.1U_0201_10V6K
RB4 1 @ 2 47K_0402_5% @ 1 1 1
CB1
CB2
CB3
2
+3VALW
1
1 For Power consumption @ RB2 0.1U_0201_10V6K RB3 @ CB4 1
RB78 1 2 10K_0402_5% TURBO_EN# 2 2 2 0.1U_0201_10V6K
Measurement 0_0402_5% 20K_0402_1% Rb
ECAGND 2
ECAGND <66,82>
1
+3VLP_LPC
CB14 1 2 0.1U_0201_10V6K EC_RST#
111
125
Analog Board ID definition,
22
33
96
67
9
UB1
ESPI Bus Pin : 1~5.7.8.10.12.14 Please see page 3.
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
For turn off internal LPC module of KB9032 SUSPWRDNACK 1 21 EC_VCCST_PG_R

<18> SUSPWRDNACK CHG_CTL3 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <10,78>
2 23 BEEP#
<71> CHG_CTL3 TPM_SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 FAN_PWM1 BEEP# <56>
XESD@ 3 26
1 2 100P_0402_50V8J PLT_RST# <17,66> TPM_SERIRQ LPC_FRAME# SERIRQ EC_FAN_PWM/GPIO12 FAN_PWM2 FAN_PWM1 <77>
CB5 4 PWM Output 27
<17> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <77>
5 near SOC
<17> LPC_AD3 LPC_AD2 LPC_AD3 PCH_RTCRST# <18>
7
<17> LPC_AD2 LPC_AD2
1
CB6 1 2 100P_0402_50V8J AC_IN LPC_AD1 8 63 BATT_TEMP D
<17> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 CHG_CTL1 BATT_TEMP <82,83> EC_CLR_CMOS
10 LPC & MISC 64 2 QB6
<17> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I CHG_CTL1 <71>
65 G L2N7002WT1G_SC-70-3
ADP_I/AD2/GPIO3A ADP_I <82,83>
1
XEMI@ XEMI@ CLK_LPC_R 12 66 AD_BID
AD Input S SB00001GE00
3
2 1 2 1 CLK_LPC_R <17> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 RB26
<16,27,66> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 VRAM_TEMP <66>
CB7 RB6 37 76 10K_0402_5%
<77> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 EC_PME# <16,51>
22P_0402_50V8J 33_0402_5% 20
<19> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38
<52> WLAN_ON
2
CLKRUN#/GPIO1D
68 LAN_PWR_EN
<63> KSI[0..7] DA0/GPIO3C EC_TP_INT# LAN_PWR_EN <51>
DA Output EN_DFAN1/DA1/GPIO3D 70
VR_PWRGD EC_TP_INT# <16,63>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72
+3VLP_EC KSI1/GPIO31 DA3/GPIO3F GPU_OVERT# <27>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN EC_MUTE# <56> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% KSI4 59 84 1 @ 2 SYS_PWROK <18,78>
2 1 2 2.2K_0402_5% EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_EN <42,72,73> 2
RB11 KSI5 60 85 RB7 0_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C EC_SMB_CK3 <63>
KSI6 61 PS2 Interface 86
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK EC_SMB_DA3 <63>
KSI7 62 87
+5VALW <63> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <63>
KSO0 39 88
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <63> +3VS
KSO1 40
RB79 1 2 4.7K_0402_5% EC_SMB_CK3 KSO2 41 KSO1/GPIO21
RB80 1 2 4.7K_0402_5% EC_SMB_DA3 KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <17>
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_EN TP_PWR_EN <63>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <18> GPU_OVERT# RB12 1 VGA@ 2 10K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <82>
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B BT_ON SPOK_5V <84>
KSO10 49 120
SPOK_3V KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <52> +3VLP_EC
RB72 1 @ 2 0_0402_5% KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <66> EC Internal PU
KSO13 52
SPOK_5V RB73 1 @ 2 0_0402_5% SPOK_3V5V KSO14 53 KSO13/GPIO2D LID_SW# RB13 1 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R TYPEC_1P5A_EC <42,43>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89
KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S <83>
90
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 BATT_BLUE_LED# <73>
For Thermal Portect Shutdown
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# LEDPWR_EN <63>
77 GPIO 92
SPOK_3V5V EC_RSMRST# <82,83> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <73>
1 2 78 93
<82,83> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <73>
DB2 RB751V-40_SOD323-2 SYSON DB1
<18,27,66> PCH_SML1CLK EC_SMB_CLK2/GPIO46 SYSON/GPIO56 VR_ON SYSON <78,85,87>
80 121 RB751V-40_SOD323-2
<18,27,66> PCH_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 CHG_ILMSEL VR_ON <78,88,89> 3V_EN
127 MAINPWON 1 2
PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <71> 3V_EN <84>
1 2 PU at CPU side SM Bus 1
DB3 RB751V-40_SOD323-2 RB14
PM_SLP_S3# 6 100 EC_RSMRST# CB8 3V_EN_R 1 2 RB15 1 2
<18,78> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <18>
0.1U_0201_10V6K 1M_0402_5%
EC_VCCST_PG_R <17,36> OVRM_EN GPIO07 GPXIOA04 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <19,27,83> 2
1 2 15 102 XESD@ 1K_0402_5%
<84,87> SPOK_3V TP_EN GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <82>
DB4 RB751V-40_SOD323-2 16 103
<63> TP_EN TS_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<19,38> TS_EN WL_OFF# GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <77,82,84>
3 18 105 BKOFF# 3
<52> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 THERMAL_ALERT# BKOFF# <38>
<18> AC_PRESENT AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R THERMAL_ALERT# <66>
25 107
<63> KBL_EN FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10
28 108
VCOUT1_PROCHOT <77> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CHG_EN <71>
29
<77> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA EC_TX/GPIO16
2
E51RXD_P80CLK 31 110 AC_IN

<52> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <83>
RB19 32 112
<18,78> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <84>
@ 0_0402_5% ON/OFFBTN#
<73> PWR_SUSP_LED# TURBO_EN# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <63>
36 GPI 115
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <66>
116 SUSP#
SUSP# <68,78,83,85,87,88>
1
SUSP#/GPXIOD05 117 SW_PROCHOT#

DGPU_AC_DETECT SW_PROCHOT# GPXIOD06 118 EC_PECI 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <10,17>
122 RB16 33_0402_1%
<18> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D
@ @ 123 124
<18,78> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
QB1A QB1B @ RB17
6
AGND
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 0_0402_5%

GND
GND
GND
GND
GND
VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT 1 2 VR_HOT#

G G VR_HOT# <89>
KB9022QD_LQFP128_14X14 @ RB18
11
24
35
94
113
ECAGND 69
S S 0_0402_5%
CO-LAY with KB9032QA (SA000080J00) 20mil
1
H_PROCHOT# 1 2 SW_PROCHOT#
<10,83> H_PROCHOT#
CB9 1 2 BATT_TEMP
100P_0402_50V8J
LB2 2 1
FBMA-L11-160808-800LMT_0603
2015/1/9 acer require:

reserved protact circuit when
XESD@ adaptor 107% happen
CB10 1 2 .1U_0402_16V7K SUSP#
XESD@ RB76 2 @ 1 0_0402_5% VR_PWRGD

<89> VCCCORE_VR_PWRGD
4 CB11 1 2 .1U_0402_16V7K 4
XESD@
CB12 1 2 .1U_0402_16V7K SYSON
XESD@
CB13 1 2 .1U_0402_16V7K

EC ENE-KB9022
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3VALW
+3VS
2.2K +3VS 2.2K
D
PCH_SMBCLK D_CK_SCLK D
(QH7)
PCH_SMBDATA 2N7002DW D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
+3VALW 1.8K
PCH_SML0DATA 499
Cannonlake 2K
2.2K +1.8VSDGPU_AON
PCH - H 1.8K +1.8VSDGPU_AON
+3VALW 2K
2.2K +1.8VSDGPU_MAIN I2CB_SCL
PCH_SML1CLK EC_SMB_CK2 VGA_I2CS_SCL
I2CB_SDA
(RH189/RH190) (QV2)
PCH_SML1DATA R-short EC_SMB_DA2 PJT138KA VGA_I2CS_SDA 2K
2.2K N17P-G0-K1 2K
+1.8VSDGPU_AON
2.2K
+3VLP_EC N18P-G0 I2CC_SCL
EC_SMB_CK1 100 ohm EC_SMB_CK1-1 I2CC_SDA NVVDD controller

BATTERY
EC_SMB_DA1 100 ohm EC_SMB_DA1-1 CONN
C C
KB9022 0 ohm EC_SMB_CK1_CHGR

2.2K
0 ohm EC_SMB_DA1_CHGR Charger
+3VS
+3VS 2.2K
EC_SMB_CK2
TMS_SMB_CLK
(QF1)
EC_SMB_DA2 2N7002DW THERMAL SENSOR
TMS_SMB_DATA
4.7K 2.2K
+5VALW +5VS_BL
4.7K 2.2K
+5VS_BL
EC_SMB_CK3 EC_SMB_CK3_LEDDRV
(QE62)
EC_SMB_DA3 2N7002DW EC_SMB_DA3_LEDDRV LED driver
0 ohm
0 ohm
B B
A A

N17E-GDDR5_D
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
+3V_PTP
Touch Pad +3VALW

+3V_PTP
2 @ 1
ON/OFF BTN UK1
+3VALW
+3VS
0_0402_5%
2 @
RK5
1
4.7U_0402_6.3V6M
5 1 0_0402_5% RK6
IN OUT +3V_PTP
2 1
CK2
2 @ CK1
CK3 GND 0.1U_0201_10V6K JTP1
2
1U_0201_6.3V6M 4 3 2 1 1
1 EN OC 2 TP_CLK 2 1
SY6288C20AAC_SOT23-5 RK7 TP_DATA 3 2
R17 10K_0402_5%
EC PS2 4 3
+3VLP 100K_0402_5% I2C_1_SDA_R 5 4
1 1
1
2 1 EC_TP_INT# I2C_1_SCL_R 6 5
<58> TP_PWR_EN PCH I2C EC_TP_INT# 7 6
<16,58> EC_TP_INT# TP_EN 7
TP_PWR_EN follow SYSON behavior 8
<58> TP_EN 8
ON/OFFBTN# 9
<58> ON/OFFBTN# GND
10
GND
+3V_PTP +3V_PTP JXT_FP202DH-008M10M
CONN@
Test Only RK18 1 @ 2 0_0603_5% SP010020L00
1
TOP
1
2
DK2 XESD@ RK8 RK9 +3V_PTP
G
TP_DATA 6 3 TP_EN QK1A 2.2K_0402_5% 2.2K_0402_5%
I/O4 I/O2 2N7002KDW_SOT363-6
1
6 1 I2C_1_SCL_R
S
<19> I2C_1_SCL
5 2 RK10 RK11
D
+3V_PTP VDD GND 1 @ 2 CK6 33P_0402_50V8J 4.7K_0402_5% 4.7K_0402_5%
RK12 0_0402_5%
XESD@
2
5
TP_CLK 4 1 EC_TP_INT#
G
I/O3 I/O1 QK1B CK7 33P_0402_50V8J
AZC099-04S.R7G_SOT23-6 2N7002KDW_SOT363-6 TP_CLK
TP_DATA TP_CLK <58>
XESD@
3 4 I2C_1_SDA_R TP_DATA <58>
<19> I2C_1_SDA
S
D
1 2
RK13 @ 0_0402_5%
2 LED driver +5VS_BL +5VS_BL

2
1
1
2.2K_0402_5%
RE69 @
2.2K_0402_5%
RE70 @
KB Conn. / Backlight
5
G
QE62B @
2
2N7002KDW_SOT363-6
JKB1
4 3 EC_SMB_CK3_LEDDRV 30
S
<58> EC_SMB_CK3 GND2

D
29
KSO16 28 GND1
KSI[0..7] KSO17 27 28
KSI[0..7] <58> 27
2
KSO0 26
G
KSO[0..17] KSO1 25 26
KSO[0..17] <58> 25
KSO2 24
KSO3 23 24
1 6 EC_SMB_DA3_LEDDRV KSO4 22 23
S
<58> EC_SMB_DA3 22
D
KSO5 21
QE62A @ KSO6 20 21
+5VS KSO7 19 20
2N7002KDW_SOT363-6 19
+5VALW KSO8 18
+5VS_BL KSO9 17 18
R41 1 2 0_0603_5% JBL1 KSO10 16 17
KBLED@ +5VS_BL 1 KSO11 15 16
U4 2 1 KSO12 14 15
R42 1 2 0_0603_5% 5 1 3 2 KSO13 13 14
LED14P@ IN OUT 4 3 KSO14 12 13
4 12
0.1U_0201_10V6K
2 KSO15 11
GND 11
C32
5 KSI0 10
R18 1 2 0_0201_5% 4 3 6 GND KSI1 9 10
<58> KBL_EN EN OC 1 GND 9
KBLED@ KSI2 8
SY6288C20AAC_SOT23-5 @ ACES_51524-0040N-001 KSI3 7 8
R43 1 2 0_0201_5% CONN@ KSI4 6 7
<58> LEDPWR_EN 2 6
LED14P@ KSI5 5
3 SP010022M00 KSI6 4 5 3
follow SYSON KSI7 3 4
3
2
ON/OFFBTN# 1 2
1
ACES_85201-2805
CONN@
JBL2
SP01000GO00
16
15 GND
+5VS_BL
AD3 AD2 AD1 AD0 +5VS_BL +5VS_BL GND
0 0 0 1
1
RE65 LED14P@ 14
4.7K_0402_1% 13 14
1 KB_A_LED_R_DRV# 13
CE3 LED14P@ 12
UE4 0.1U_0201_10V6K KB_A_LED_G_DRV# 11 12
KB_A_LED_B_DRV# 10 11
2
24 27 2 KB_B_LED_R_DRV# 9 10
RESET Vcc KB_B_LED_G_DRV# 8 9
3 KB_A_LED_R_DRV# KB_B_LED_B_DRV# 7 8
EC_SMB_CK3 RE1 2 @ 1 0_0402_5% EC_SMB_CK3_LEDDRV 25 OUT0 4 KB_A_LED_G_DRV# AD0 KB_C_LED_R_DRV# 6 7
EC_SMB_DA3 RE2 2 @ 1 0_0402_5% EC_SMB_DA3_LEDDRV 26 SCL OUT1 5 KB_A_LED_B_DRV# AD1 KB_C_LED_G_DRV# 5 6
SDA OUT2 6 KB_B_LED_R_DRV# AD2 KB_C_LED_B_DRV# 4 5
AD0 31 OUT3 8 KB_B_LED_G_DRV# AD3 KB_D_LED_R_DRV# 3 4
AD1 32 A0 OUT4 9 KB_B_LED_B_DRV# KB_D_LED_G_DRV# 2 3
A1 OUT5 2
1
1
AD2 1 10 KB_C_LED_R_DRV# KB_D_LED_B_DRV# 1
AD3 2 A2 OUT6 11 KB_C_LED_G_DRV# RE75 RE74 RE73 RE72 1
A3 OUT7 14 KB_C_LED_B_DRV# 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1% 4.7K_0402_1%
12 OUT8 15 KB_D_LED_R_DRV# LED14P@ LED14P@ LED14P@ LED14P@ ACES_51522-01401-P01
13 N.C. OUT9 16 KB_D_LED_G_DRV# CONN@
2
28 N.C. OUT10 17 KB_D_LED_B_DRV#

4 29 N.C. OUT11 19 SP01001R800 4
30 N.C. OUT12 20
N.C. OUT13 21
OUT14
1
22
RE64 OUT15
@ 10K_0402_5% 7 23
18 GND GND 33
GND GND
set RE7 to 10k / output = 1.875mA
2
TLC59116FIRHBR_VQFN32_5X5
LED14P@
KB & TP & TPM Connector
Raptor: NC for 59116F MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EH5VF M/B LA-H501P
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
THERMAL SENSOR +3VS +3VS

Close to VRAM choke
+3VLP_ECA
1
RF9
To Hall sensor/B RF10 2.2K_0402_5%
5
TMS@ 2.2K_0402_5% TMS@
G
QF1B TMS@
1
2N7002KDW_SOT363-6
+3VLP 3 4 TMS_SMB_CLK RF12 TMS@
<18,27,58> PCH_SML1CLK
S
D 16.5K_0402_1% D
2
JHS1 TMS@
2
1 QF1A
2 1 2N7002KDW_SOT363-6
<58> LID_SW# 2 <58> VRAM_TEMP
3
4 3 6 1 TMS_SMB_DATA
<18,27,58> PCH_SML1DATA
S
4
1
0.1U_0201_10V6K
D
C60
1 5 RH250 TMS@
6 GND 100K_0402_1%_TSM0B104F4251RZ
GND SL200002H00
PGESD@ ACES_51524-0040N-001
2
2 CONN@ +3VS
+3VS
SP010022M00
ECAGND <58,82>
1
TMS@ CF20
1
0.1U_0201_10V6K TMS@
UF2 RF24
2 1 8 TMS_SMB_CLK 10K_0402_5%
VDD SCL
2 7 TMS_SMB_DATA
2
D+ SDA
3 6
D- ALERT# THERMAL_ALERT# <58>
1 TMS@ 2 TH_THERM# 4 5
+3VS T_CRIT# GND
RF23 10K_0402_5%
NCT7718W_MSOP8 SMBUS ADDRESS

TMS@ 1001_1000b
SA000067P00
C C
TPM Finger Print

+3VALW R45 +3VALW_TPM +3VS R46 +3VS_TPM
0_0603_5% 0_0603_5%
1 @ 2 1 @ 2
10U_0402_6.3V6M
0.1U_0201_10V6K
10U_0402_6.3V6M
0.1U_0201_10V6K
C57
0.1U_0201_10V6K
C58
0.1U_0201_10V6K
C55
1 1 1 1 1 1
C56
C59
C54
+3VALW @
near RK14 1 2 0_0402_5%
2 2 2 2 2 2 +FP_VCC
TPM@
TPM@ TPM@ TPM@ TPM@ TPM@

pin1 +5VALW
JFP1
RK15 1 FP@ 2 0_0402_5%
8
+FP_VCC USB20_P8_L 7 8 10
2 USB20_N8_L 7 G2
6 9
near FP@ CK4 UK2 5 6 G1
+3VALW pin8,22 1U_0201_6.3V6M 5 1 4 5
R48 TPM@ 1 IN OUT 3 4
1 3
10K_0402_5% 2 FP@ 2
1 2 PCH_SPI_CS#2 GND CK5 1 2
FP_PWR_EN 4 3 4.7U_0402_6.3V6M 1
<58> FP_PWR_EN EN OC 2 ACES_51522-00801-001
B SY6288C20AAC_SOT23-5 B
SP01001AE00
FP@
CONN@
R50 1 TPM@ 2 33_0402_1% PCH_SPI_SO_TPM_R
<16> PCH_SPI_SO_R 1 TPM@ 2 33_0402_1% PCH_SPI_SI_TPM_R
R51
<16> PCH_SPI_SI_R R52 1 TPM@ 2 33_0402_1% PCH_SPI_CLK_TPM_R
<16> PCH_SPI_CLK_R
1 @ 2 USB20_N8_L
<14> USB20_N8
RK16 0_0402_5%
U9 +3VALW_TPM 1 @ 2 USB20_P8_L
<14> USB20_P8
TH41 1 RK17 0_0402_5%
@ 29 VSB +3VS_TPM
30 SDA/GPIO0 8
SCL/GPIO1 VHIO 22
0_0402_5% 1 @ 2 R47 TPM_BADD 6 VHIO
GPIO3 2 PIN ETU801 FA577E-1200
PCH_SPI_SO_TPM_R 24 NC 3
PCH_SPI_SI_TPM_R 21 MISO NC 5 DK1 FPESD@ 1 +FP_VCC(5V) +FP_VCC(3V)
18 MOSI/GPIO7 NC 7 6 3 USB20_P8_L
<17,58> TPM_SERIRQ PIRQ/GPIO2 NC 9 I/O4 I/O2 2 USBP D+
NC 10
PCH_SPI_CLK_TPM_R 19 NC 11 3 USBN D-
20 SCLK NC 12 5 2
<16> PCH_SPI_CS#2 17 SCS/GPIO5 NC 14
+FP_VCC VDD GND 4 GND GND
<16,27,58> PLT_RST# 27 PLTRST NC 15
13 NC NC 26 5 NC NC
GPIO4 NC 25 4 1 USB20_N8_L
NC 28 I/O3 I/O1 6 NC NC
4 NC 31 AZC099-04S.R7G_SOT23-6
PP/GPIO6 NC 32 7 NC
A NC A
16 8 NC
GND 23
GND 33
PGND
NPCT750AAAYX_QFN32_5X5
TPM@
SA0000AQ250 Security Classification Compal Secret Data Compal Electronics, Inc.
SA0000AQ250, S IC NPCT750AABYX QFN 32P TPM Sensors/FP/TPM
1A
5 4 3 2 1
A B C D E
SATA Re-Driver and cable HDD Conn.

SATANRD@ RO21 1 2 0_0201_5% SATA_PTX_C_DRX_P4_NRD
<17> SATA_PTX_DRX_P4
SATANRD@ RO22 1 2 0_0201_5% SATA_PTX_C_DRX_N4_NRD
<17> SATA_PTX_DRX_N4
SATANRD@ RO23 1 2 0_0201_5% SATA_PRX_C_DTX_N4_NRD
<17> SATA_PRX_DTX_N4 2 0_0201_5% SATA_PRX_C_DTX_P4_NRD
SATANRD@ RO24 1
<17> SATA_PRX_DTX_P4
B_EQ1
A_EQ2
A_EQ1
DEW
1 CO1 +3VS 1
SATARD@
2 1
0.01U_0201_6.3V7K UO1
20
19
18
17
16
PS8527CTQFN20GTR2A_TQFN20_4X4
SATARD@
DEW
VDD2
B_EQ1
A_EQ2
A_EQ1
SATA_PTX_DRX_P4 SATARD@ CO4 2 1 0.01U_0201_6.3V7K SATA_PTX_C_RD_DRX_P4 1 15 SATA_PTX_RD_DRX_P4
SATA_PTX_DRX_N4 SATARD@ CO5 2 1 0.01U_0201_6.3V7K SATA_PTX_C_RD_DRX_N4 2 A_INP A_OUTP 14 SATA_PTX_RD_DRX_N4
3 A_INN A_OUTN 13 B_EQ2
SATA_PRX_DTX_N4 SATARD@ CO8 2 1 0.01U_0201_6.3V7K SATA_PRX_C_RD_DTX_N4 4 GND1 B_EQ2 12 SATA_PRX_RD_DTX_N4
SATA_PRX_DTX_P4 SATARD@ CO9 2 1 0.01U_0201_6.3V7K SATA_PRX_C_RD_DTX_P4 5 B_OUTN B_INN 11 SATA_PRX_RD_DTX_P4
21 B_OUTP B_INP
GND2
VDD1
REXT
B_DE
A_DE
FFC Type
EN
6
7
8
9
10
JHDD1
SATARD@ 14
+3VS RO7 2 1 +5VS +5VS_HDD 13 GND
+3VS +3VS GND
0.1U_0201_10V6K
4.99K_0402_1%
B_DE
A_DE
A_DE 1
RO6 1 @ 2 4.7K_0402_5% SATARD@ RO4 1 @ 2 0_0805_5% 12
1 RO9 @ 2 11 12
B_DE 11
CO10
RO8 1 @ 2 4.7K_0402_5% 4.7K_0402_5% 10
2 RO25 1 2 0_0201_5% G_INT2_R 9 10
RO10 1 @ 2 4.7K_0402_5% B_EQ1 8 9
7 8
RO11 1 @ 2 4.7K_0402_5% A_EQ1 SATA_PRX_RD_DTX_P4 SATARD@ CO7 1 2 0.01U_0201_6.3V7K SATA_PRX_C_DTX_P4 6 7
SATA_PRX_RD_DTX_N4 SATARD@ CO6 1 2 0.01U_0201_6.3V7K SATA_PRX_C_DTX_N4 5 6
RO12 1 2 4.7K_0402_5% A_EQ2 4 5
2
@ USE 8527 re-driver SATA_PTX_RD_DRX_N4 SATA_PTX_C_DRX_N4 4 2
SATARD@ CO3 1 2 0.01U_0201_6.3V7K 3
RO13 1 @ 2 4.7K_0402_5% B_EQ2 SA00007JU10 SATA_PTX_RD_DRX_P4 SATARD@ CO2 1 2 0.01U_0201_6.3V7K SATA_PTX_C_DRX_P4 2 3
1 2
RO14 1 @ 2 4.7K_0402_5% DEW 1
ACES_51625-01201-001
CONN@
SATA_PRX_C_DTX_P4_NRD SATANRD@ CO14 2 1 0.01U_0201_6.3V7K
SATA_PRX_C_DTX_N4_NRD SP010028W00
SATANRD@ CO15 2 1 0.01U_0201_6.3V7K
RO15 1 @ 2 4.7K_0402_5% A_DE
SATA_PTX_C_DRX_N4_NRD SATANRD@ CO16 2 1 0.01U_0201_6.3V7K
RO16 1 @ 2 4.7K_0402_5% B_DE SATA_PTX_C_DRX_P4_NRD SATANRD@ CO17 2 1 0.01U_0201_6.3V7K
RO17 1 @ 2 4.7K_0402_5% B_EQ1
RO18 1SATARD@ 2 4.7K_0402_5% A_EQ1
RO19 1SATARD@ 2 4.7K_0402_5% A_EQ2
RO20 1SATARD@ 2 4.7K_0402_5% B_EQ2
+3VS +5VS_HDD
100mils
10U_0402_6.3V6M
CO12
1 1
1
CO11 CO13
0.1U_0201_10V6K 0.1U_0201_10V6K
2
3 2 @ 2 @ 3
4 4

HDD/ Re-Driver/ G-sensor
Custom 1A
A B C D E
5 4 3 2 1
+3VALW
UM2 +3VS_SSD1
1 14 +3VS_SSD_1 1 @ 2
2 VIN1 VOUT1 13 RM54 0_0805_5%
VIN1 VOUT1
RM53 1 @ 2 0_0201_5% +3V_NGFF_GATE 3 12 1 2
<58,78,83,85,87,88> SUSP# ON1 CT1 CM37 1000P_0402_50V7K
+3VS_SSD1
0.1U_0201_10V6K
1 4 11
+5VALW VBIAS GND
CM32 @
+3VS_SSD1 5 10 1 2
ON2 CT2 CM38 1000P_0402_50V7K
M.2 SSD 1
2 6
VIN2 VOUT2
9
+3VS_SSD_2 1
+3VS_SSD2
10U_0402_6.3V6M
0.1U_0201_10V6K
1 2 7 8 @ 2
D JSSD1 + CM3 VIN2 VOUT2 RM55 0_0805_5% D
1 2 CM1 CM2 150U_D2_6.3VY_R15M 15
3 GND 3P3VAUX 4 SGA00003700 GPAD
PCIE_PRX_DTX_N9 5 GND 3P3VAUX 6 2 1 2 +3VALW EM5209VF_DFN14_2X3
<17> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 PERn3 NC 8 +3VS_SSD_1 +3VS_SSD_2
<17> PCIE_PRX_DTX_P9 9 PERp3 NC 10
PCIE_PTX_C_DRX_N9 GND DAS/DSS#
1U_0201_6.3V6M
1U_0201_6.3V6M
CM6 1 2 0.22U_0402_16V7K 11 12 2 2 2 2
<17> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETn3 3P3VAUX
CM33
CM34
CM4 1 2 0.22U_0402_16V7K 13 14
<17> PCIE_PTX_DRX_P9 15 PETp3 3P3VAUX 16 CM35 CM36
PCIE_PRX_DTX_N10 17 GND 3P3VAUX 18
PERn2 3P3VAUX 0.1U_0201_10V6K 0.1U_0201_10V6K
<17> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 20 XESD@ 1 1 1 1
<17> PCIE_PRX_DTX_P10 21 PERp2 NC 22 PLT_RST_BUF# CM16 2 1 100P_0402_50V8J
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND NC 24
<17> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 NC 26
<17> PCIE_PTX_DRX_P10 27 PETp2 NC 28
PCIE_PRX_DTX_N11 GND NC Place close to JSSD pin 50 Place CM33 close UM2 pin 1&2
29 30
<17> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERn1 NC 32 Place CM34 close UM2 pin 6&7
ESD request to reserve.
<17> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <17>
39 40
PCIE_PRX_DTX_P12 41 GND NC 42
<17> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 PERn0/SATA-B+ NC 44
<17> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC 46
<17> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA-A- NC 50
<17> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# SSD1_CLKREQ#_R PLT_RST_BUF# <16,51,52>
51 52 RM7 1 @ 2 0_0201_5%
GND CLKREQ# SSD1_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF1# REFCLKN PEWake#
55 56
<15> CLK_PCIE_NGFF1 REFCLKP NC
57 58
GND NC
C C
Pull high at PCH side
67 68 SUSCLK_SSD1 RM8 1 @ 2 0_0201_5%
NC SUSCLK(32kHz) SUSCLK <18,52,68>
RM10 1 @ 2 0_0201_5% SSD1_DET# 69 70
<17> SATA_GP1 PEDET(NC-PCIE/GND-SATA) 3P3VAUX
71 72
73 GND 3P3VAUX 74
75 GND 3P3VAUX
GND 76
SSD_DET# GND1 77
GND2
SATA Device 0
LOTES_APCI0079-P005A
PCIE Device 1 CONN@
SP07001EZ00
+3VS_SSD2
+3VS_SSD2
M.2 SSD
JSSD2
1 2 1
GND 3P3VAUX
10U_0402_6.3V6M
0.1U_0201_10V6K
3 4 1 2
5 GND 3P3VAUX 6 + CM20
<14> PCIE_PRX_DTX_N24 7 PERn3 NC 8 CM28 CM26 150U_D2_6.3VY_R15M
<14> PCIE_PRX_DTX_P24 9 PERp3 NC 10 SGA00003700
CM23 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N24 11 GND DAS/DSS# 12 2 1 2
<14> PCIE_PTX_DRX_N24 CM31 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P24 13 PETn3 3P3VAUX 14
<14> PCIE_PTX_DRX_P24 15 PETp3 3P3VAUX 16
17 GND 3P3VAUX 18
B <14> PCIE_PRX_DTX_N23 19 PERn2 3P3VAUX 20 B
<14> PCIE_PTX_DRX_P23 27 PETp2 NC 28 XESD@
29 GND NC 30 PLT_RST_BUF# CM21 2 1 100P_0402_50V8J
<14> PCIE_PRX_DTX_N22 31 PERn1 NC 32
<14> PCIE_PTX_DRX_N22 PCIE_PTX_C_DRX_P22 PETn1 NC Place close to JSSD pin 50
CM24 1 2 0.22U_0402_16V7K 37 38
<14> PCIE_PTX_DRX_P22 39 PETp1 DEVSLP 40
41 GND NC 42
ESD request to reserve.
<14> PCIE_PRX_DTX_P21 43 PERn0/SATA-B+ NC 44
<14> PCIE_PRX_DTX_N21 45 PERp0/SATA-B- NC 46
<14> PCIE_PTX_DRX_N21 CM25 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P21 49 PETn0/SATA-A- NC 50 PLT_RST_BUF#
<14> PCIE_PTX_DRX_P21 51 PETp0/SATA-A+ PERST# 52 SSD2_CLKREQ#_R RM48 1 @ 2 0_0201_5%
GND CLKREQ# SSD2_CLKREQ# <15>
53 54
<15> CLK_PCIE_NGFF2# REFCLKN PEWake#
55 56
<15> CLK_PCIE_NGFF2 REFCLKP NC
57 58
GND NC
67 68 SUSCLK_SSD2 RM52 1 @ 2 0_0201_5%

SSD2_DET# NC SUSCLK(32kHz) SUSCLK <18,52,68>
69 70
T210 @ PEDET(NC-PCIE/GND-SATA) 3P3VAUX
71 72
73 GND 3P3VAUX 74
75 GND 3P3VAUX
GND 76
GND1 77
GND2
A LOTES_APCI0079-P005A A
CONN@
SP07001EZ00

SATA/PCIE-SSD
Custom 1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
USB3.0
DS1 ESD@
USB3_PTX_L_DRX_P1 1 9 USB3_PTX_L_DRX_P1 +USB3_VCCA
1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1 USB3_PTX_L_DRX_N1 2 8 USB3_PTX_L_DRX_N1

W=100mils
<17> USB3_PTX_DRX_P1
CS2 .1U_0402_16V7K
1 2 USB3_PTX_C_DRX_N1 RS89 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N1 USB3_PRX_L_DTX_P1 4 7 USB3_PRX_L_DTX_P1
1 2
1 <17> USB3_PTX_DRX_N1 1
CS3 .1U_0402_16V7K
USB3_PRX_L_DTX_N1 5 6 USB3_PRX_L_DTX_N1 CS5 + CS6 EMI@
RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1 150U_D2_6.3VY_R15M 0.1U_0201_10V6K
<17> USB3_PRX_DTX_P1 1
SGA00003700
RS91 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N1 2
<17> USB3_PRX_DTX_N1 3 USB3.0 Conn.
TVWDF1004AD0_DFN9 JUSB1
1
SC300003Z00 CHR_USB20_N1_R 2 VBUS
CHR_USB20_P1_R 3 D-
4 D+
DS2 ESD@ USB3_PRX_L_DTX_N1 5 GND
6 3 CHR_USB20_N1_R USB3_PRX_L_DTX_P1 6 StdA-SSRX- 10
LS3 EMI@ I/O4 I/O2 7 StdA-SSRX+ GND 11
CHR_USB20_P1 2 1 CHR_USB20_P1_R +USB3_VCCA USB3_PTX_L_DRX_N1 8 GND-DRAIN GND 12
2 1 USB3_PTX_L_DRX_P1 9 StdA-SSTX- GND 13
5 2 StdA-SSTX+ GND
CHR_USB20_N1 3 4 CHR_USB20_N1_R VDD GND ACON_TARAC-9V1391
3 4
CONN@
DLM0NSN900HY2D_4P
SM070005U00
CHR_USB20_P1_R 4
I/O3 I/O1
1 DC23300AG00
AZC099-04S.R7G_SOT23-6
SC300001G00
2 2
USB Host Charger

0 0904 vendor recommend
1 +5VALW
+5VALW
1
CHG_CTL2
22U_0603_6.3V6M
0.1U_0201_10V6K
1 RS14 1 2 10K_0402_5% 1 1
CS9
CS7
@
@ +USB3_VCCA
RS15 1 2 10K_0402_5% CHG_ILMSEL 2 2 US12
1 12
VIN VOUT
0911 Rerserve PU, vendor suggest to EC control
2
if future need support SDP2 RS11
<14> USB20_N1 3 DM_OUT
3 <14> USB20_P1 DP_OUT 10 CHR_USB20_P1 3
0_0201_5%
2 @ 1 13 DP_IN 11 CHR_USB20_N1
<14> USB_OC1# FAULT# DM_IN
1 4
<58> CHG_ILMSEL ILIM_SEL
CS8 5 15 0831 Reserve ILIM_L R as vendor recommend
<58> CHG_EN EN ILIM_L 16
0.1U_0201_10V6K
USB Host Charger Truth Table @ 2 ILIM_HI
1
6
<58> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note 7 9
CTL2 NC
RS12
RS13
Setting 8 14
<58> CHG_CTL3 CTL3 GND 17
Thermal Pad ILM R vaule
0 1 0 1 SDP1-OFF ILIM_H Port power off @
Ios(mA)=50250/R(Kohm)
2
0 1 0 1 SDP1 ILIM_H Data Lines Connected SLGC55544CVTR_TQFN16_3X3 ILIM_Hi=2273mA
ILIM_L=1288mA(reserve)
0 1 1 1 DCP ILIM_H Data Lines Disconnected
Aut o
1 1 1 1 CDP ILIM_H Data Lines Connected
4 4

USB3.0 Conn/USB Charger
Custom 1A
A B C D E
5 4 3 2 1
USB3.0
+5VALW
For ESD request +USB3_VCCB
D 1 2 USB3_PTX_C_DRX_P3 RS124 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P3 CS107 EMI@ D
<17> USB3_PTX_DRX_P3 DS20 ESD@
CS109 .1U_0402_16V7K 0.1U_0201_10V6K US13
USB3_PTX_L_DRX_P3 1 9 USB3_PTX_L_DRX_P3 1 2 5 1
IN OUT W=60mils
1 2 USB3_PTX_C_DRX_N3 RS123 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N3
<17> USB3_PTX_DRX_N3 USB3_PTX_L_DRX_N3 2 USB3_PTX_L_DRX_N3
CS108 .1U_0402_16V7K 8 2
GND
USB3_PRX_L_DTX_P3 4 7 USB3_PRX_L_DTX_P3 4 3
<42,58,73> USB_EN EN OC
USB3_PRX_L_DTX_N3 5 6 USB3_PRX_L_DTX_N3 SY6288C20AAC_SOT23-5
USB3_PRX_DTX_P3 RS126 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P3 3

<17> USB3_PRX_DTX_P3
TVWDF1004AD0_DFN9
USB3_PRX_DTX_N3 RS125 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N3
<17> USB3_PRX_DTX_N3 SC300003Z00 +USB3_VCCB
W=100mils
1 2
CS111 + CS110 EMI@
150U_D2_6.3VY_R15M 0.1U_0201_10V6K
SGA00003700 1
2
U2DN3_L 6
DS21 ESD@
3
USB3.0 Conn.
I/O4 I/O2 JUSB2
+USB3_VCCB 1
U2DN3_L 2 VBUS
LS13 EMI@ 5 2 U2DP3_L 3 D-
C 3 4 U2DN3_L VDD GND 4 D+ C
<14> USB20_N3 3 4 USB3_PRX_L_DTX_N3 5 GND
USB3_PRX_L_DTX_P3 6 StdA-SSRX- 10
2 1 U2DP3_L 4 1 U2DP3_L 7 StdA-SSRX+ GND 11
<14> USB20_P3 2 1 I/O3 I/O1 USB3_PTX_L_DRX_N3 8 GND-DRAIN GND 12
DLM0NSN900HY2D_4P AZC099-04S.R7G_SOT23-6 USB3_PTX_L_DRX_P3 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
SM070005U00 SC300001G00 ACON_TARAC-9V1391
CONN@
DC23300AG00
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
IO/B CONN
JIO2
26
GND2
25
HPOUT_L_1 24 GND1
<56> HPOUT_L_1 HPOUT_R_1 24
<56> HPOUT_R_1 23
SLEEVE 22 23
<56> SLEEVE 22
1 <56> RING2 RING2 21 1
HP_PLUG# 20 21
<56> HP_PLUG# 20
GNDA 19
18 19
<56> SPKR+ 18
17
16 17
DLM0NSN900HY2D_4P <56> SPKR- 16
15
USB20_P4 1 2 USB20_L_P4 BATT_AMB_LED# 14 15
<14> USB20_P4 1 2 <58> BATT_AMB_LED# BATT_BLUE_LED# 14
<58> BATT_BLUE_LED# 13
PWR_SUSP_LED# 12 13
USB20_N4 USB20_L_N4 <58> PW R_SUSP_LED# PW R_LED# 12
4 3 <58> PW R_LED# 11
<14> USB20_N4 4 3 11
+5VALW 10
EMI@ LS12 9 10
8 9
SM070005U00 7 8
6 7
USB_EN 5 6
<42,58,72> USB_EN 5
4
USB20_L_P4 3 4
USB20_L_N4 2 3
1 2
1
CVILU_CF35242D0RD-NH
CONN@
2 2
3 3
4 4

IO/B
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
+5VS
1 @ 2 +VCC_FAN1
Screw Hole
RF4 0_0603_5% 40mil
1 @ 2 +VCC_FAN2
1 1 RF7 0_0603_5%
CF6 CF5
1000P_0402_50V7K 10U_0402_6.3V6M
2 2 @ H2 @ H3 @ H4 @ H5 @ H17 @ H18 @ H19 @ H20 @ GASKET1 @ GASKET2 @ GASKET3
@ @
H_3P0 H_3P0 H_3P0 H_3P0 H_2P5N H_3P2 H_3P2 H_3P0X2P5N GS-002C-302520 GS-002C-302520 GS-002C-302520
1
@ H6 @ H7 @ H8 @ H9
H_4P0 H_4P0 H_4P0 H_4P0
+3VS FAN Conn FD1 FD2
1
@ @
1
1
1 FIDUCIAL_C40M80 FIDUCIAL_C40M80
RF3 CF13 @ H10 @ H11 @ H12 @ H13
10K_0402_5% 4.7U_0402_6.3V6M H_3P3 H_3P3 H_3P3 H_3P3 FD3 FD4
2 JFAN1
2
+VCC_FAN1 1 @ @
1
2 1
<58> FAN_SPEED1 FAN_PWM1 3 2 FIDUCIAL_C40M80 FIDUCIAL_C40M80
<58> FAN_PWM1
1 4 3
CF7 5 4 @ H14 @ H15 @ H16
1000P_0402_50V7K 6 G1 H_3P8 H_3P8 H_3P8
XEMI@ G2
2 ACES_50278-00401-001
CONN@
1
SP02000RR00
+3VS
1
1
RF5 CF12
10K_0402_5% 4.7U_0402_6.3V6M
2 JFAN2
2
+VCC_FAN2 1
2 1
<58> FAN_SPEED2 FAN_PWM2 2
3
<58> FAN_PWM2 3
1 4
CF10 5 4
1000P_0402_50V7K 6 G1
XEMI@ G2
2 ACES_50278-00401-001
CONN@
SP02000RR00
+3VLP 1 @ 2
MAINPWON <58,82,84>
R23 0_0402_5%
Reset Circuit
1 @ 2
EC_RST# <58>
2
R24 0_0402_5%
R25
10K_0402_5%
1
Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
side 2N7002KDW_SOT363-6
S
1
1
3
Q1B D C40
BI_GATE 5 0.1U_0201_10V6K
<82> BI_GATE G 2
2N7002KDW_SOT363-6
S
4
Reset Button
@
SW3
BI_GATE 1 2 BI_GATE
3 4
SKRPABE010_4P
SN10000CV00
change PN to SN10000CV00

FAN & Screw Hole
A B C D E
System DC inferface For Power ON/Off Sequence

@
CQ2 1 2 0.1U_0201_10V6K UQ1 @ JPQ2 PM_SLP_S3
1 14 +5VS_OUT 1 2 +3VALW
+5VALW VIN1 VOUT1 1 2 +5VS
2
2 13
G
VIN1 VOUT1
1
JUMP_43X118
SUSP# RQ1 1 @ 2 0_0402_5% 5VS_ON 3 12 1 2 R37 Q10A
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5% 2N7002KDW_SOT363-6
4 11 1 6
S
+5VALW VBIAS GND EC_VCCST_PG_R <10,58>
D
1 1
2
RQ2 2 @ 1 0_0402_5% 3VS_ON 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion
5
@ 6 9 @ JPQ1
G
+3VALW VIN2 VOUT2 +3VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +3VS
Q10B
15 JUMP_43X118 2N7002KDW_SOT363-6
GPAD Q11A 4 3
S
VR_ON <58,88,89>
D
EM5209VF_DFN14_2X3 2N7002KDW_SOT363-6 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<18,58> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
G
2 2 2 2
S
1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0201_6.3V6M 1U_0201_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
Place CQ7 close UQ1 pin 1&2
G
@
Place CQ8 close UQ1 pin 6&7 Q12A
2N7002KDW_SOT363-6
1 6
S
SYS_PWROK <18,58>
D
5
G
+3VALW @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ Q12B
2N7002KDW_SOT363-6
1
4 3
S
PCH_PWROK <18,58>
2
D
R38
2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @
2
2 PM_SLP_S4 2
1
1
discharge Q13A
5
SUSP discharge SYSON# 2N7002KDW_SOT363-6 D
G
trace 20 mils 2
trace 20 mils <18,58> PM_SLP_S4# G Q13B
2N7002KDW_SOT363-6
6
Q7A D D Q7B S 4 3 SYSON
S
1
3
D
2 5 SUSP Q8B D D Q8A MOW14, For tPLT15 200us(max)
<58,68,83,85,87,88> SUSP# G G SYSON 5 2 SYSON# SLP_S4# to VDDQ ramp down
<58,85,87> SYSON G G
@ @
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
4
1
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
R32 @ @
10K_0402_5% P/N: SB00000EO00 footprint use SB00000ZU00
@
2
+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW
@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1.05V_VCCST_OUT RQ5 1 @ 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0201_6.3V6M
VIN1 VOUT1 1 UC4 +1.05VS_VCCSTG
SYSON RQ4 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1
4 11 VIN2
+5VALW VBIAS GND 7 6
SUSP# RQ8 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1.8VS_OUT VBIAS 2
+1.8VALW
6 9 RQ9 1 @ 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 @ 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2
+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us
+1.05VALW +1.05V_VCCST_OUT +1.8VS_OUT

+1.8VALW
2 2 2
2
CQ11 CQ9 CQ22
1U_0201_6.3V6M CQ24 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1 1
1U_0201_6.3V6M
1
4 4


DC Interface
A B C D E
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
A B C D E
1
@ ACES_50299-00601-001
+19V_ADPIN FBMA-L11-201209-800LMA50T
EMI@ PL101 +19V_VIN 1
1 1 2
1 2 EMI@ PL102
2
EMI@ PC104
3
1000P_0402_50V7K
FBMA-L11-201209-800LMA50T
3
1
4
EMI@ PC102
PR103
100P_0402_50V8J
7 4 5 1 2 PR102
G7 5
1
8 6 4.7_1206_5% EMI@ PL103
G8 6
1
FBMA-L11-201209-800LMA50T 4.7_1206_5%
2
PJP101
2
1 2
2
1
1
PC101 EMI@ EMI@ PC105
0.1U_0603_25V7K Bead SM01000U600 0.1U_0603_25V7K
2
2 2
3 3
@0@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
4 4

DCIN
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
A B C D E
A B C D E
+3VLP
1
1 1
PC205 @
1
0.1U_0603_25V7K
2
@
PR207 100_0402_1% @ PR215 PR214
100K_0402_1%
1 2 26.7K_0402_1% 21.5K_0402_1%
EC_SMB_DA1 <58,83>
PR213
PR205 100_0402_1%
2
1
1 2
EC_SMB_CK1 <58,83>
PU201 @
1 8
VCC TMSNS1
(Common Part)
PR202 2 7 2 1
Battery Bot Side <45,47> SL200002H00
2
200K_0402_1% GND RHYST1
@
1
1 2 MAINPWON 3 6 @ PR216
+3VLP <58,77,84> MAINPWON OT1 TMSNS2
100K_0402_1%_NCP15WF104F03RC
@ PJP201 10K_0402_1% @
PIN1 GND 1 4 5 2 1
1 2 OT2 RHYST2
PIN2 GND 2 3
1 2
BATT_TEMP <58,83>
1
EC_SMB_DA1-1
PH202
G718TM1U_SOT23-8 @ PR218
PIN3 SMD
2
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% 14K_0402_1%
4 5 BATT_TS
100K_0402_1%_NCP15WF104F03RC
PIN4 SMC 5 6 BATT_B/I
6 7
PIN5 TEMP
PH203
(Common Part)
2
7 8
PIN6 BI 8 9 +RTCVCC SL200002H00
GND 10
PIN7 Batt+ GND
PIN8 Batt+ PH3 Near VGA. @
CVILU_CI9908M2HR0-NH
1
PR212
100K_0402_5%
1
2 D 2
2 PQ201
<77> BI_GATE G LBSS139LT1G 1N SOT-23-3
S
3
+12.6V_BATT+
EMI@ PL201
FBMA-L11-201209-800LMA50T
1 2 BI_S
+12.6V_BATT
EMI@ PL202 When PR204=18.7K
1
FBMA-L11-201209-800LMA50T
1 2 PR217 For KB9022
0_0402_5% OTP Active Recovery
2
design reserve VCIN0_PH(V) 89'C, 1V 56'C, 2V
1
PC201 EMI@ PC202 EMI@
1000P_0402_50V7K 0.01U_0402_50V7K
2
PH202(ohm) 8.0524K 26.11K
3/27 thermal PH1 92'C ->89'C

+3VLP_ECA
PR206
10K_0402_1%
1 2
ADP_I <58,83>
1
3 3
PR204
18.7K_0402_1%
VCIN1_ADP_PROCHOT <58>
2
VCIN0_PH <58>
1
PC203 must close to EC pin
1
PR208
10K_0402_1% PH201
2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2
0.1U_0402_25V6
1
T202@ PH201 is Common Part SL200002H00
T201@
ECAGND <58,66>
T202 T201 must close to PH201
ADP_I=20*I(adapter)*0.01
4
I(adapter)=adapter(W)*130%/19 4
2016/11/03
Compal Secret Data
2017/06/14 Title
BATTERY CONN/OTP
A B C D E
5 4 3 2 1
Module model information

ISL95520_Hybrid_Boost_V2.mdd
Protection for reverse input
Vgs = 20V
Vds = 60V PQB3
Id = 250mA L2N7002WT1G_SC70-3
1
D
D D
2
G max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
S CSR rating: 1W
3
+19VB
1 2 1 2 VCSIP-VCSIN spec < 81mV
PRB1 PRB2
1M_0402_1% 3M_0402_5%
PQB11 PQB12
Need check the SOA for inrush EMP21N03HC_N_DFN56-8-5 +19V_P1 AON7380_DFN3X3-8-5
PRB4
5 1 1 +19V_P2 0.005_1206_1% EMI@ PLB11 +19VB_CHG
+19V_VIN 2 2 FBMA-L11-201209-800LMA50T
3 3 5 1 4 1 2
EMI@
EMI@
EMI@
2200P_0402_50V7K
2 3 Isat: 10A
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
CSIP_CHG_R
DCR: 14mohm
1
CSIN_CHG_R
PCB2
PCB3
PCB4
PCB6
PCB5
2
2
1 2
@ PCB1
1000P_0402_50V7K
1
1_0402_5%
2_0402_5%
1
PRB5
PRB6
1
PRB7
2
499K_0402_1%
2
PCB7
PQB13
2
4.02K_0402_1%
4.02K_0402_1%
0.033U_0402_25V7K
1 2 AON7380_DFN3X3-8-5
0.1U_0402_25V6
PCB25
1
1
0.1U_0402_25V6
PCB24
L->H 2
2.04 vin min w/o 2M =17.41 5 3
@
2
C H->L PRB10 C
PCB9 0.22U_0603_25V7K
2.02 vin min w 2M =17.77 100_0402_1%
4
PRB8
PRB9
1 2 +12.6V_BATT
1
CMSRC_CHG
2200P_0402_50V7K
66.5K_0402_1%
@ PCB10
1
PRB11
PCB8
1
ASGATE_CHG 1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0402_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10Ω
m
1 VDD_CHG
BIT0 = 1.14uA/W PQB1
@
BIT1 = 0.285uA/W PDB2
AON7506_DFN33-8-5
========================================================= 30MA_30V_0.5UA_0.4V_SOD323-2
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20 m
Ω VDDP_CHG
100K_0402_1%
support Turbo boost : 2200P 1 2 Support max charge 3.5A
32
31
30
29
28
27
26
25
BIT0 = 2.28uA/W PUB1
BIT1 = 0.57uA/W
no support Turbo boost : 0.1u Choke 4.7uH SH00000YC00 (Common Part) Power loss: 0.245W
PRB12
  
CSIP
ASGATE
QPCP
BGATE
CSIN
CMSRC
OPCN
VBAT
PRB13 PCB11 4 (Size:6.6 x 7.3 x 3 mm) CSR rating: 1W
Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBA
T ) 0_0603_5% 0.22U_0603_25V7K (DCR:28m~33m) VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R
1 2
R_Psys = 1.2V / Ipsys
2
ACIN BOOT PRB16

KPSYS = 1.14uA/W UG_CHG
adapter wattage = 45W 2 23 PLB1 0.01_1206_1%
3
2
1
<58> AC_IN @0@ PRB14 0_0402_5% ACOK UGATE 4.7UH_PCMB063T-4R7MS_8A_20% +12.6V_BATT
Battery wattage = 40Wh
1
EC_SMB_DA1_R 3 LX_CHG +17.4V_BATT_CHG 1

158K_0402_1%
1 2 22 1 2 4
Ipsys = 1.14 x (45+40) = 96.9uA <58,82> EC_SMB_DA1 SDA PHASE
PRB15
@0@ PRB17 0_0402_5%

R_Psys = 1.2V / 96.9uA = 12.3K-ohm. EC_SMB_CK1_R 4 LG_CHG
4.7_1206_5%
1 2 21 2 3
<58,82> EC_SMB_CK1 SCL LGATE
1
=====================================
EMI@ PRB19
@0@ PRB18 0_0402_5% PQB2
5
adapter wattage = 65W 1 2 5 20 VDDP_CHG EMB12N03V_N_DFN33-8-5
2
PROCHOT# VDDP
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
Battery wattage = 40Wh <10,58> H_PROCHOT#
1
2 1K_0402_1%AMON_ISL95520 6 VDD_CHG
PCB12
PCB13
PCB14
PCB26
Ipsys = 1.14 x (65+40) = 119.7uA PRB201 19 1 2
R_Psys = 1.2V / 96.9uA = 10K-ohm. <58,82> ADP_I AMON VDD
2
PRB221 2 1K_0402_1%BMON_ISL95520 7 ISL88739AHRZ-T_QFN32_4X4 18 PRB21 4.7_0402_5%
2
BMON DCIN
680P_0402_50V7K
**Design Notes** 4
BATGONE
Close to EC. 8 17 PCB15 PCB16
For 45W/65W /90W system, 2S/3S/4S battery NC NTC
@
CCLIM 1U_0402_6.3V6K 1U_0402_6.3V6K
2
ACLIM
COMP
B Maximum Charging current 3.5A
1
PROG
B
AGND
CSON
CSOP
EMI@ PCB17
FSET
PRB24
1
Maximum Battery discharge power 55W 100K_0402_1%
3
2
1
1
#Register Setting PCB18 PCB19 @0@
2
0.1U_0402_25V6 0.1U_0402_25V6 PRB23 PDB1
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
33
10
11
12
13
14
15
16
Follow adapter and 0_0402_5% PRB25 10_1206_5% 3
+19V_VIN
2
2. Disable turbo when AC only battery wattage in 1 2 1
2
#Circuit Design Close to Vsys current source. 2
2
2
FSET_CHG
EC.
PCB20
1U_0603_25V6
1. ACLIM and CCLIM are devider voltage control. Base on CPU Core VR design. VF = 0.38V For 4S per cell 4.35V battery
The resistor is pop on CPU VR schematic. S SCH DIO BAS40CW SOT-323
1
2. Use 7X7 choke and 3X3 H/L side MOSFET
1
Charge current 3A PRB27
ACIN_CHG
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) VDD_CHG 10K_0402_1%
VDD=5V @0@ PRB26
Power density : 0.61 (23X16) 0_0603_5%
2
#Protect function 1 2
+12.6V_BATT
1
CCLIM_CHG
1. ACOVP : VCC voltage > 24V
200K_0402_1%
4S_BATT@ PRB28
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
1
ACLIM_CHG 2M_0402_1%
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PRB29
PRB30
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
4. CHGOCP : based on charge current setting 200K_0402_1%
2
5. BATOVP : 4.6V/Cell +3VS Pull high on HW side COMP_CHG PRB31 2_0402_5%
2
1
6. BATLOWV : No.
@ PRB32 PR333=0 ohm, Fs=500KHZ ~ +/- 15%
7. TSHUT : 150C PCB21 4S_BATT@ PQB4
1
1
0.033U_0402_16V7K 100_0402_1%
76.8K_0402_1% 0.1U_0402_25V6
2
560P_0402_50V7K
PRB33
1 2 LTC015EUBFS8TL_UMT3F
1
CSON_CHG CSON_CHG_R
150K_0402_1%
PCB22
@0@ 1 2
1
1
PRB37
@VGA@ @VGA@ PQB7 @ OCCP setting PRB34
1
300K_0402_1%
PRB35 PRB36 L2N7002WT1G_SC70-3 0_0402_5% @0@ PRB38 0_0402_5%

2
2
1
D
110K_0402_1%
10K_0402_1% 10K_0402_1% @
2
1
AC_IN
PRB39
2 4S_BATT@ PRB40
2
G BATT_TEMP <58,82> 100K_0402_1%

2
1
PRB41
PCB23
S 1 2 2
3
<58> BATT_4S
BATGONE(BATT_TEMP)
2
<19,27,58> DGPU_AC_DETECT logic high: above 2.4V

2
Hybrid boost power mode logic low: under 0.8V 4S_BATT@ PQB8
Cell = 4s L2N7002WT1G_SC70-3
3
1
D
6
D 2
2 <58,68,78,85,87,88> SUSP#
A G A
G S
3
@VGA@ @VGA@ @VGA@
PQB6 PQB5B S PQB5A
1
1
RUM001L02_VMT3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 ICClimit : 7.73A

Delta I : 1.44A
3
1C charge current :6.48A

D
H_PROCHOT# 2 AC_IN 5
G Battery current limimed by CCLIm ~ 3.89A.
Adapter current limimed by ACLIm ~ 4.33A.
S (PR779 and PQ741 are for change ACLIm when AC in)
4

3
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2 Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
============================================================= PWR_CHARGER
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ). THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC_LIM = VccLIM / 32 x Rs2
============================================================= MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AC_LIM = Vac_LIM / 32 x Rs1 Date: Friday, February 22, 2019 Sheet 83 of 100
5 4 3 2 1
A B C D E
PR301
499K_0402_1%
ENLDO_3V5V 1 2
EN1 and EN2 dont't floating
+19VB
1
150K_0402_1%
+19VB
PR302
EMI@ PL311 @0@ PR303 PC301
FBMA-L11-201209-800LMA50T 0_0603_5% 0.1U_0603_25V7K
1
1 2 +19VB_3V BST_3V 1 2 1 2 1
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
2
EMI@ PC302
@EMI@ PC303
EMI@ PC304
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@ PC305
PC306
Choke 2.2uH SH00000YV00 (Common Part)
1
PU301
2
PL301
BS
IN
IN
IN
IN
2.2UH_7.8A_20%_7X7X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
@ PC307
PC308
PC309
@ PC310
PC311
PC312
SY8288BRAC_QFN20_3X3 @EMI@
SPOK_3V 9 17 PR304
+3VLP
2
PG LDO 4.7_1206_5%
1 3V_SN
10 16
2
NC NC
1
PC313
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR305 GND @EMI@
100K_0402_5% PC314
11
12
13
14
15
680P_0402_50V7K
2
Vout is 3.234V~3.366V
<58,87> SPOK_3V
3.3V LDO 150mA~300mA
ENLDO_3V5V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
3V_FB 1 2 1 2
<58> 3V_EN
@ PJ302
+3VALWP 1 2 +3VALW
1 2
keep short pad, JUMP_43X118
2 snubber is for EMI only. 2
5V10A@
+19VB EMI@ PL511 @0@ PR501 PC501
FBMA-L11-201209-800LMA50T 0_0402_5% 0.1U_0603_25V7K
1 2 +19VB_5V BST_5V 1 2 BST_5V_R 1 2
Choke 1.5uH SH000016700 (Common Part)
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
(Size:6.8 x 6.47 x 3 mm)

10U_0603_25V6M
10U_0603_25V6M
5V10A@ PU501
13
(DCR:14m~15m Ohm)
1
SY8270CTMC_QFN13_4X3
1
1
@EMI@ PC517
PC502
PC503
EMI@ PC504
@EMI@ PC505
BS
IN PL501
2
LX_5V 2 12 1.5UH_9A_20%_7X7X3_M
LX LX LX_5V 1 2 +5VALWP
3 11
GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+3VLP
1
1
VCC_5V
PR502
PC507
PC508
PC509
PC510
PC511
PC512
4 10 1 2
4.7_1206_5%
PG VCC
@EMI@
2
1
5V10A@ PC506
OUT
LDO
EN2
EN1
2.2U_0402_6.3V6M @
FF
PR503
2
100K_0402_5%
5
9
2
15V_SN
680P_0402_50V7K
<58> SPOK_5V +5VLP
ENLDO_3V5V
@EMI@
PC513
5V LDO 150mA~300mA
4.7U_0402_6.3V6M
2
1
5V10A@ PC514
PR504
2.2K_0402_5% 5V_3V_EN
2
1 2 Iocp=12A
<58> EC_ON @0@ PR505
0_0402_5%
1 2 EN1 and EN2 dont't be floating.
3
<58,77,82> MAINPWON EN :H>0.8V ; L<0.4V 5V10A@ PC515 5V10A@ PR506 @ PJ502
3
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
5V_FB 1 2 5V_FB_1 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_3V_EN
1M_0402_1%
1
1
PR507
@0@ PR509 5V8A@ PC521

PC516 0_0402_5% 0.1U_0603_25V7K
4.7U_0402_6.3V6M +19VB_5V BST_5V_8A 1 2 BST_5V_8A_R 1 2
2
2
5V8A@ PU502
5
SY8288CRAC_QFN20_3X3
BS
IN
IN
IN
IN
LX_5V 6 20 LX_5V
LX LX
7 19
GND LX
8 18
GND GND
SPOK_5V 9 17 VCC_5V_8A 1 2
PG VCC
10 16
NC NC 5V8A@ PC518
OUT
LDO
EN2
EN1
21 2.2U_0402_6.3V6M
FF
GND
11
12
13
14
15
+5VLP_5V_8A
4.7U_0402_6.3V6M
5V8A@ PC519
1
ENLDO_3V5V
5V_3V_EN
2
4 4
+5VALWP
5V_8A_FB 1 2 5V_8A_FB_1 1 2
5V8A@ PC520 5V8A@ PR508

1000P_0402_50V7K 1K_0402_1%

+3VALW/+5VALW
Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH5AV_JV_0V_LA-G021P
A B C D E
A B C D E
@ PJM1
JUMP_43X79 Pin19 need pull separate from +1.35VP.
1 2
1 2 +19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +19VB_1.2VP PRM11 Peak Current 1A
+19VB @EMI@ PLM11 2.2_0603_5%
HCB2012KF-121T50_0805 BST_1.2VP_R 1 2 BST_1.2VP
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
1 +1.2VP 1
1
@EMI@ PCM1
EMI@ PCM2
PCM3
PCM4
EMI@ PCM20
UG_1.2VP +0.6VSP
1
PCM5
0.1U_0603_25V7K LX_1.2VP
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
PCM6
PCM7
16
17
18
19
20
4 PUM1
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
PQM1 LG_1.2VP 15 1
1
2
3
LGATE VTTGND
EMB20N03V_DFN8-5
IOCP
14 2
PLM1 PRM1 PGND VTTSNS
1UH_PCMC063T-1R0MN_11A_20% 20K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP13 3
+1.2VP PCM8 CS RT8207PGQW _W QFN20_3X3 GND
1
1U_0201_6.3V6K
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM2 PQM2 PRM3 VDDP VTTREF
5
4.7_1206_5% EMB12N03V_N_DFN33-8-5 5.1_0603_5% 35.4
VDD_1.2VP
PCM9
1 2 11 5
PCM10
PCM11
PCM12
PCM13
PCM14
+1.2VP
1 2
VDD VDDQ
1
PGOOD
PCM16
1 1 1 1 1 1 +5VALW 2 1
TON
1
2 @EMI@ PCM15 PCM17 0.033U_0402_16V7K 2
FB
S5
S3
2
1
@
680P_0402_50V7K 4 PDM1
2
1U_0201_6.3V6K 30MA_30V_0.5UA_0.4V_SOD323-2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10
6
2 2 2 2 2 2 PRM4
35.4
2.2_0402_1%
FB_1.2VP
1
2
3
EN_1.2VP
PRM5
EN_0.6VSP
6.19K_0402_1%
TON_1.2VP
+5VALW Frequency 1 2 +1.2VP
PRM6
470K_0402_1%
1
+19VB_1.2VP 1 2
Vout=0.75V* (1+Rup/Rdown)
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm @0@ PRM8 PRM7 =0.75*(1+(6.19/10))
0_0402_5% 10K_0402_1%
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A 1 2 =1.214V 1.2%
2
<58,78,87> SYSON
L/S AON7506 Rds(on) :typ:13m Ohm, max:15.8m Ohm
1
Idsm(TA=25)=12A, Idsm(TA=70)=10.5A @ PCM18
0.1U_0402_16V7K
=0.75*(1+(8.2/10))
2
Choke 1uH SH00000YE00 (Common Part) Choke: SH00000YE00 Size:7x7x3 (Common Part) =1.365V 1.1%
(Size:6.86 x 6.47 x 3 mm) Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC @
PRM9
(DCR:6.2m~7.2m Ohm) Rdc=Xmohm(Typ), 11mohm(Max) TOKO 0_0402_5%
Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers 1 2
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech <58,68,78,83,87,88> SUSP#
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin @ PJM2
3 @0@ PRM10 JUMP_43X118 3
Mode Level +0.675VSP VTTREF_1.35V Rdc=6.9± 15% Panasonic
0_0402_5% +1.2VP 1 2 +1.2V_VDDQ
S5 L off off 1 2 1 2
S3 L off on Switching Frequency: 530kHz <10> SM_PG_CTRL
S0 H on on Imax=A, Iocp=A
1
@ PCM19 @ PJM3
Iocp=10.63~12.76A JUMP_43X39
Note: S3 - sleep ; S5 - power off OVP: 110%~120% 0.1U_0402_16V7K 1 2
+0.6VSP +0.6VS_VTT
2
1 2
VFB=0.607V, Vout=1.214V
4 4

DDR4
A B C D E
A B C D E
Choke 1uH SH00000YE00 (Common Part)

(Size:6.86 x 6.47 x 3 mm)
(DCR:6.2m~7.2m Ohm)
Choke: SH00000YE00 Size:7x7x3 (Common Part)
Rdc=6.7mohm(Typ), 7.4mohm(Max) CYNTEC
Rdc=Xmohm(Typ), 11mohm(Max) TOKO
Rdc=6.2mohm(Typ), 7.2mohm(Max) Maglayers
Rdc=8.3mohm(Typ), 10mohm(Max) Tai-Tech
Rdc=6.7mohm(Typ), 7.4mohm(Max) Chilisin
Rdc=6.9± 15% Panasonic
+19VB_1VALW
1 1
EN pin don't floating @EMI@ PR1101 @EMI@ PC1101
4.7_1206_5% 680P_0402_50V7K @ PJ1101
If have pull down resistor at HW side, pls delete PR702 SNUB_1VALW
+19VB @ PJ1102
JUMP_43X79
+19VB_1VALW
PU1101 @0@ PR1102
1 2 1 2
+1.05VALWP
JUMP_43X118
1
1 2
2
+1.05VALW
1 2 2 9 PC1106
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K
10U_0603_25V6M
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL1101
EMI@ PC1102
0.1U_0603_25V7K
2200P_0402_50V7K
IN BS
1
1UH_11A_20%_7X7X3_M
EMI@ PC1103
@EMI@ PC1104
PC1105
LX_1VALW
4
IN LX
6 1 2
+1.05VALWP
220U_B2_4VM_R35M
2
2
5 19 1
15.4K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
7 20 +
PR1104
PC1107
PC1108
PC1109
PC1110
PC1111
@ PC1112
GND LX
8 14 FB_1VALW Rup
2
GND FB PR1110 2
2
18 17 LDO_3V 1K_0402_1%
GND VCC 1 2
1
EN_1VALW 11 10
EN NC PC1113 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
LDO_3V ILMT NC
15 16 PR1106
+3VALW BYP NC Rdown 20K_0402_1%
1
21
2
@0@ PAD
PR1103 SY8288RAC_QFN20_3X3
1
0_0402_5%
PC1114
2
ILMT_1VALW 1U_0201_6.3V6M
2
1
@
PR1105
0_0402_5% =0.6*(1+(15.4/20))
Vout=1.062V
2
2 2
PR1107
10K_0402_1%
1 2
8288RAC +1.8_PG <87>
Min @ PR1108
ILMT='0' 8A 10K_0402_1%
ILMT=Floating 12A EN_1VALW 1 2
ILMT='1' 16A +3VALW
1
@ PC1115
PR1109
0.22U_0402_16V7K
2
1M_0402_1%
2
3 3
4 4

1V
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1A
A B C D E
5 4 3 2 1
PR1809
100K_0402_5%
2 1
+3VALW
+1.8_PG <86>
+19VB @ PJ1802 PU1801

1 2 +19VB_1.8VALWP 2 9 @0@ PR1808 PC1810 @EMI@ PR1802 @EMI@ PC1806
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
3 1 1.8VALWP_BST 1 2 1 2 1 2 1.8VALWP_SNB 1 2
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
JUMP_43X79 IN BS
1
PC1801
PC1802
D D
4 6
EMI@ PC1816
EMI@ PC1815
@EMI@ PC1808
IN LX
2
5 19 PL1801
IN LX 1UH_6.6A_20%_5X5X3_M
1.8VALWP_LX
7
GND LX
20
1.8VALWP_FB
1 2
+1.8VALWP
8 14
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
1
@0@ PR1801 18 17 1.8VALWP_LDO
0_0402_5% GND VCC (R1)
PC1812
PC1813
PC1814
PC1804
PC1805
PC1817
330P_0402_50V7K
1
1
1 2 11 10 PC1809
2
EN NC
1
<58,84> SPOK_3V 2.2U_0402_6.3V6M PR1803
PC1803
1.8VALWP_ILMT 13 12 20.5K_0402_1%
2
ILMT NC @ @
2
1
15 16
+3VALW
2
BYP NC
1
PR1805
1M_0402_1% @ PC1811 21 PR1810
PAD
1
0.47U_0402_6.3V6K 1K_0402_1%
2
PC1807 SY8286RAC_QFN20_3X3 1 2
2
1.8VALWP_LDO 1U_0201_6.3V6M
2
FB = 0.6V
1
@0@ @ PJ1801
PR1807 JUMP_43X79
1
0_0402_5% 1 2
PR1804 +1.8VALWP 1 2 +1.8VALW
2
1.8VALWP_ILMT 10K_0402_1%
(R2)
1
2
@ +3VALW
PR1806 Vout=0.6V* (1+Rup/Rdown)
0_0402_5% Vout=0.6V*(1+20.5/10)
+5VALW =1.83V (x1.017)
2
2
PJ2501
2
C JUMP_43X79 C
@
1
8288RAC
Min 1
1
PC2501
ILMT='0' 8A
ILMT=Floating 12A 1U_0402_6.3V6K
2
ILMT='1' 16A
1
PC2502
PU2501
FB=0.8V
22U_0603_6.3V6M Note:Iload(max)=4A
2
G9661MF11U_SO8 @ PJ2502
@0@ PR2501 4 5 JUMP_43X79
0_0402_5% VIN_2.5V 3 VPP NC 6 1 2
<58,78,85> SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP +2.5VP 1 2 +2.5V
GND
1 VEN ADJ 8
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND
1
0.1U_0402_16V7K
1
PR2503
PC2504
9
1
1
PR2502
Rup
PC2503
PC2505
@ PC2506
21.5K_0402_1%
2
1M_0402_5%
2
2
2
@ FB_2.5V
1
PR2504
10K_0402_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
2
B B
2s_battery_EMI@ 2s_battery_EMI@
PCT1 PRT1
P-MOS 680P_0603_50V7K 4.7_1206_5%
2 1 2 1
2s_battery@ PQT1
2s_battery bead@ PLT12 AONR21321_DFN8-5 2s_battery@ PLT1 2s_battery@ PDT1
5A_Z120_25M_0805_2P 1 4.7UH_PCME051E-4R7MS_3A_20% SS3P4-M3-84A_SMP2
1 2 2 5 1 2 2 1 +12VSP 1 2
+5VALW 3 +INVPWR_B+_BOOST
SH00000OG00
10U_0603_25V6M
2s_battery@ PCT4
2s_battery bead@ PLT11

1500P_0402_50V7K
1
LX_12VSP
2s_battery@ PCT3
5A_Z120_25M_0805_2P
100P_0402_50V8J
1
@2s_battery@ PCT5
4
2s_battery@ PCT8
2s_battery@ PCT9
2s_battery@ PRT2 2s_battery@ 2s_battery@ PRT3
2s_battery@ PCT10
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2
PCT7
100K_0402_1% PCT2 2s_battery@ PCT6 88.7K_0402_1%
PCT11
0.1U_0402_25V6
2200P_0402_50V7K
2
0.022U_0402_25V7K 10U_0603_25V6M
2
2
6
1
2 1
2
LX
LX
1
2
2s_battery_EMI@
2s_battery_EMI@
8 2FB_12VSP
2s_battery@ PRT4 Vin FB
10K_0402_1%
9 10 SS_12VSP 1 2
2
FREQ SS
2s_battery@ PCT12
1
@2s_battery@ PRT5 1COMP_12VSP 0.01U_0402_50V7K

COMP
1
0_0402_5% D
2s_battery@ EN_12VSP 3
1 2 2 PQT2 EN 2s_battery@
<58,68,78,83,85,88> SUSP#
1
2N7002KW_SOT323-3 PRT6
G
Vout=1.24*(1+88.7/10)=12.2V
GND
GND
PAD
S 2s_battery@ 10K_0402_1%
3
2
1
2s_battery@ PUT1 PRT7

2s_battery@ RT9297GQW_WDFN10_3X3 10K_0402_1%
11
PCT13 SA00004JV00
2
A 0.1U_0402_25V7K A
1
2s_battery@
PCT14
4700P_0402_25V7K
2

1.5VS/2.5V
5 4 3 2 1
5 4 3 2 1
D D
Choke: SH00000Z300 (Common Part)

Rdc=10mohm(Typ), 12mohm(Max) Size:6*5.4*3 Tai-Tech
Rdc=11mohm(Typ), 12mohm(Max) Size:5.3*4.9*3 Maglayers
@EMI@ PRH1 @EMI@ PCH1 @ PJH1

can improve CNVI lose issue 4.7_1206_5% 680P_0402_50V7K 1 2
1 2 SNB_+VCCIOP 1 2 +1.0VS_VCCIOP 1 2 +VCCIO
JUMP_43X118
EMI@ PLH11
HCB2012KF-121T50_0805
1 2
Imax=3.85A, Ipeak=5.5A, Iocp:6.6A
@ PJH2 PUH1 @0@ 0_0603_5%
1 2 +VCCIOP_B+ 2 9 PCH4
+19VB 1 2 IN PG PRH2
0.1U_0603_25V7K
JUMP_43X79 3 1 +VCCIOP_BST 1 2+VCCIOP_BST_R 1 2 PLH1
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
PCH2 0.68UH_7.9A_20%_5X5X3_M
PCH3
PCH5
+VCCIOP_LX
2
4
IN LX
6 1 2
+1.0VS_VCCIOP
1
5 19
PCH10
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
@EMI@
1
EMI@
7 20
PCH6
PCH7
PCH8
PCH9
Note:Iload(max)=5.5A
PCH11
PCH12
10_0402_1%
2
GND LX @
PRH3
8 14 +VCCIOP_FB
IOCP=7A~8A(typ)
2
GND FB
2
PRH4
1K_0402_1%
18 17 +VCCIOP_LDO_3V @
2
GND VCC
1
+VCCIOP_EN 11 10 PCH13 @
EN NC 2.2U_0402_6.3V6M
1
+VCCIOP_ILMT 13 12 FB = 0.6V Rup
2
ILMT NC 1 2 =0.6*(1+(12k/20.5k))
15 16
+3VALW BYP NC PRH5 OVP=0.95V*115%=1.0925V
1
21 12K_0402_1%
C PCH14 PAD Vout=0.951 V 2% C
20.5K_0402_1%
1
1U_0201_6.3V6M SY8286RAC_QFN20_3X3
Rdown
2
PRH6
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
2
PRH7 @0@ 0_0402_5%
VCCIO_SENSE_R 1 2 VCCIO_SENSE
+VCCIOP_LDO_3V VCCIO_SENSE <12>
PRH8 @0@ 0_0402_5%

1
@ PRH9 1 2 VSSIO_SENSE
VSSIO_SENSE <12>
0_0402_5%
@ PRH10 VR_ON 1 2
0_0402_5% <58,78,89> VR_ON
2
+VCCIOP_ILMT PRH11
1K_0402_5%
1
SUSP# 1 2 +VCCIOP_EN
<58,68,78,83,85,87> SUSP#
@ PRH12
0.1U_0402_25V6
1M_0402_5%
1
1
PCH15
check delay time with HW
PRH13
0_0402_5%
2
2
2
8286RAC
Min Typ Max
ILMT='0' 6.5A 7.5A 8.5A
ILMT=Floating 9.5A 10.5A 11.5A
ILMT='1' 12.5A 13.5A 14.5A
B B
A A

DH53F M/B LA-F991P
C 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0VS_VCCIO
5 4 3 2 1
1 2 3 4 5
Place close to Choke in VCCSA first phase circuit

PHZ1 PRZ1 PRZ2 PR1199 NA, need confirm
100K_0402_1%_TSM0B104F4251RZ 12K_0402_1% 7.5K_0603_1%
PCZ1 1 2 1 2 1 2
PRZ3 100_0402_1% 2200P_0402_50V7K
<91> CSN_1PH SW_1PH <91> +1.05V_VCCST
1
1 2 1 2 PCZ2
100_0402_1%
1
2
PRZ4 0.01U_0402_50V7K
499_0402_1%
45.3_0402_1%
45.3_0402_1%
@0@ PRZ9 PRZ10 10_0402_1% 1 2 PCZ3
PRZ5
PRZ6
PRZ7
PRZ8
A 0_0402_5% 1K_0402_5% A
0.1U_0402_25V6
1
1 2 1 2 VSN_1PH
<12> VSSSA_SENSE
2
@
2
2
2 1 1 2 @
PCZ4 LA-F611PR01_0531D.DSN
CSP_1PH
1000P_0402_50V7K PRZ12 PCZ5 PCZ6 PRZ13 PROCHOT# change to H_PROCHOT#(P.72 PUZ01.39)
470P_0402_50V8J
1
1.62K_0402_1% 3300P_0402_50V7-K 2200P_0402_50V7K 100_0402_1%
LA-F611PR01_0531C.DSN
1
1 2 1 2 VSP_1PH CSN_1PH_R 81215_VR_HOT
1 2
28K_0402_1%
PCZ7
<12> VCCSA_SENSE +3VS PCH_PWROK change to IMVP_VR_PG(P.72 PUZ01.45)
VR_HOT# <58>
PRZ14
@0@ PRZ11 PCZ8
2
PRZ15 100_0402_1% 0_0402_5% 1 2 1000P_0402_50V7K 81215_SCLK 1 2
CPU_SVID_CLK <10>
1 2 1 2 PRZ16 49.9_0402_1%
IMON_1PH
+VCC_SA PWM1_1PH/ICCMAX1 <91>
1
PCZ9
1000P_0402_50V7K PRZ19 81215_ALERT 2 1
CPU_SVID_ALERT#_R <10>
12.4K_0402_1% PRZ17
2 1 10K_0402_1% PRZ23 @0@ PRZ18 0_0402_5%
PRZ21 100_0402_1% 34.8K_0402_1% 81215_SDIO 1 2
<58> VCCCORE_VR_PWRGD CPU_SVID_DAT <10>
2
1 2 PRZ22 PCZ10 PRZ20 10_0402_1%
+VCC_CORE 1.5K_0402_1% 0.01U_0402_25V7K 1 2
@0@ PRZ24 2 1 2 1 CPU_EN
0_0402_5% 81215_SCLK
<11> VCCSENSE
1 2 VSP_4PH 81215_ALERT 1 2
VR_ON <58,78,88>
LA-F611PR01_0531C.DSN
81215_SDIO
1 2 IMVP_VR_ON change to VR_ON(P.72 PUZ01.43)
2
@0@ PRZ25
PCZ12 PCZ11 0_0402_5% PRZ26 100_0402_1%
1000P_0402_50V7K PRZ28 15P_0402_50V8J 1 2 +VCC_GT
1
1K_0402_1%
1 2 1 2 VSN_4PH VSN_1PH @0@ PRZ30
<11> VSSSENSE
0_0402_5%
ILIM_1PH
COMP_1PH
@0@ PRZ27 1 2
VSP_1PH VCCGT_SENSE <11>
PRZ29 100_0402_1% 0_0402_5% 1 2
1 2
1
PCZ13 PCZ14
2200P_0402_50V7K PRZ31 1000P_0402_50V7K
1.37K_0402_1%
2
1 2 1 2 VSSGT_SENSE <11>
@0@ PRZ32
PUZ1 1 2 0_0402_5% PRZ33 100_0402_1%
PCZ16 PRZ34 PCZ17 H62@ PRZ35 1 2
53
52
51
50
49
48
47
46
45
44
43
42
41
40
NCP81215MNTXG_QFN52_6X6
15P_0402_50V8J 49.9_0402_1% 470P_0402_50V8J 28K_0402_1% PCZ15
1 2 1 2 1 2 H82@ PRZ35 2200P_0402_50V7K
TAB
VR_RDY
SCLK
ALERT#
SDIO
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
PWM_1PH/ICCMAX_1PH
EN
B B
25.5K_0402_1%
PRZ36 PRZ37 2 1 PRZ38 PCZ19 PCZ20
3.65K_0402_1% 1K_0402_1% PRZ39 49.9_0402_1% 470P_0402_50V8J 15P_0402_50V8J
1 2 1 2 1 2 29.4K_0402_1% 1 2 1 2 1 2
PCZ21 VSP_4PH 1 39 81215_VR_HOT 1 2
PCZ18 470P_0402_50V8J VSN_4PH 2 VSP_4PH VRHOT# 38 VSP_2PH PCZ23 2 1 1 2 1 2
2200P_0402_50V7K 2 1 3 VSN_4PH VSP_2PH 37 VSN_2PH 470P_0402_50V8J
DIFFOUT_4PH 4 IMON_4PH VSN_2PH 36 1 2 PRZ40 PRZ41 PCZ22
FB_4PH 5 DIFFOUT_4PH IMON_2PH 35 DIFFOUT_2PH 1K_0402_1% 3.65K_0402_1% 2200P_0402_50V7K
COMP_4PH 6 FB_4PH DIFFOUT_2PH 34 FB_2PH
1 2 ILIM_4PH 7 COMP_4PH FB_2PH 33 COMP_2PH
Place close to Choke in VCORE CSCOMP_4PH ILIM_4PH COMP_2PH ILIM_2PH
PRZ42 30.1K_0402_1% 8 32 1 2
first phase circuit CSCOMP_4PH ILIM_2PH
1
CSSUM_4PH 9 31 PRZ43 12K_0402_1% CSCOMP_2PH

75K_0402_1%
CSSUM_4PH CSCOMP_2PH
1
PHZ2 10 30 CSSUM_2PH
220P_0402_50V8J
75K_0402_1%
PRZ44
680P_0402_50V7K
CSP1_4PH 11 CSREF_4PH CSSUM_2PH 29 PHZ3
PRZ45
680P_0402_50V7K
100P_0402_50V8J
CSP1_4PH CSREF_2PH
1
CSP2_4PH CSP1_2PH
PWM1_4PH/ICCMAX_4PH
PWM1_2PH/ICCMAX_2PH
220K_0402_5%_ERTJ0EV224J 12 28 220K_0402_5%_ERTJ0EV224J
PCZ24
PCZ25
PWM4_4PH/ROSC_MPH
CSP2_4PH CSP1_2PH
2
1
CSP3_4PH
PWM2_2PH/ROSC_1PH
PCZ26 13 27 2 1 Place close to Choke in VCCGT first phase circuit
PCZ27
PCZ28
+5VALW
2
1 2
CSP3_4PH CSP2_2PH
TTSENSE_1PH/PSYS
PRZ47
165K_0402_1%
1 2
2
PWM3_4PH/VBOOT
1
90.9K_0603_1% 0.1U_0402_25V7K PRZ46
PWM2_4PH/ADDR
1
2
1 2 1K_0402_1% PCZ29
PRZ48
<89,90> SW1_4PH
TTSENSE_2PH
PRZ50 0.1U_0402_25V7K @ PRZ49
TSENSE_4PH
2
90.9K_0603_1% 274K_0402_1% PRZ51
CSP4_4PH
1 2 100K_0603_1%
<89,90> SW2_4PH
2
PRZ52 1 2
SW1_2PH <89,91>
2
DRON
VRMP
90.9K_0603_1%
VCC
1 2 2 1
<89,90> SW3_4PH
PRZ54 +5VALW
90.9K_0603_1% PRZ55 @ PRZ53
14
15
16
17
18
19
20
21
22
23
24
25
26
1 2 1K_0402_1% 1K_0402_1%
<89,90> SW4_4PH
1 2 PCZ30
+19VB_CPU 0.1U_0402_25V6 CSP4_4PH
CSREF_4PH PCZ31 2 1 TSENSE_4PH PCZ32
<90> CSREF_4PH
0.01U_0402_50V7K 0.1U_0402_25V6 PRZ57
1 2 TSENSE_2PH 1 2 24.9K_0402_1% CSREF_2PH
CSREF_2PH <91>
1 2 1 2
1U_0402_6.3V6K
<90,91> DRVON
PRZ59 +5VALW PRZ56 PWM2_2PH/ROSC1 1 2
1
2.15K_0402_1% 2.2_0603_5% PRZ58

PCZ33
1 2 CSP1_4PH 25.5K_0402_1%
110K_0402_1%
H82@ PRZ61
<89,90> SW1_4PH
1
H62@ PRZ61
2
2
102K_0402_1%
4.32K_0402_1%
24.9K_0402_1%
97.6K_0402_1%
97.6K_0402_1%
PWM1_2PH/ICCMAX2 <91>
1
C PCZ34 @ PRZ60 C
PRZ66
PRZ62
PRZ63
PRZ64
PRZ65
0.1U_0402_25V6 100K_0402_1%
1
2.15K_0402_1%
2
CSREF_4PH CSP1_2PH 1 2
<90> PWM1_4PH/ICCMAX4 SW1_2PH <89,91>
1
PRZ67
2
2.15K_0402_1%
1 2 CSP2_4PH PCZ35
<89,90> SW2_4PH <90> PWM2_4PH/ADDR
0.1U_0402_25V6
1
2
PCZ36 @ PRZ68 CSREF_2PH

0.1U_0402_25V6 100K_0402_1%
1
CSREF_4PH <90> PWM3_4PH/VBOOT

1
PRZ69
2.15K_0402_1%
CSP3_4PH <90> PWM4_4PH/ROSCM
1 2
<89,90> SW3_4PH
2
PCZ37 @ PRZ70
0.1U_0402_25V6 100K_0402_1%
1
CSREF_4PH
1
TSENSE_4PH TSENSE_2PH
PRZ71
1
1
2.15K_0402_1%
0_0402_5%
0_0402_5%
@0@ PRZ72
@0@ PRZ73
1 2 CSP4_4PH
<89,90> SW4_4PH
2
PCZ38 @ PRZ74 Place close to H-side,L-side MOS

2
0.1U_0402_25V6 100K_0402_1% Place close to H-side,L-side MOS in VCCGT first phase

1
in VCORE first phase

1
CSREF_4PH
1
PHZ4 PRZ75 PHZ5 PRZ76

61.9K_0402_1% 61.9K_0402_1%
220K_0402_5%_ERTJ0EV224J 220K_0402_5%_ERTJ0EV224J
2
2
2
D D
Security Classification Compal Secret Data

2016/02/01 2017/12/31 Title
Issued Date Deciphered Date Compal Electronics, Inc.
Custom 1A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. CPU IC SKL_H 42
1 2 3 4 5
5 4 3 2 1
Main Func = CORE
MOSFET: DFN 5X6E

H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)
L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)
EMI@ PLZ11
HCB2012KF-121T50_0805
PRZ85 +19VB_CPU 1 2
0_0603_5% +19VB
1 2 DRVH1_VCORE-1 PCZ39 PCZ46 EMI@ PLZ12
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
HCB2012KF-121T50_0805
1
10U_0603_25V6M
10U_0603_25V6M
1 2
EMI@ PCZ58
EMI@ PCZ59
EMI@ PCZ60
1 1 1
33U_25V_M
33U_25V_M
33U_25V_M
D + + + D
PRZ77 @ PQZ1 PQZ2
PCZ48
PCZ47
PCZ65
2
2
2.2_0603_5% AON6962_DFN5X6D-8-7 AON6962_DFN5X6D-8-7
BOOT1_VCORE
2
1 2
2 2 2
G1
D1
G1
D1
@
PCZ50
0.22U_0603_25V7K 7 7
PUZ2 D2/S1 D2/S1 PLZ1
1
NCP81151MNTBG_DFN8_2X2 0.15UH_NA__36A_20%
1 9 1 4
G2
G2
S2
S2
S2
S2
S2
S2
BST FLAG +VCC_CORE
2
2 8 DRVH1_VCORE 2 3
<89> PWM1_4PH/ICCMAX4
3
PWM DRVH
VSW1_VCORE SH00001D800 Choke: SH00001D800 Size:7x7x4 Maglayers
3 7
<89,91> DRVON EN SW 7x7X4 DCR:0.67mΩ +/-5% Isat: 45A
Isat:45A
1
4 6 @EMI@
+5VALW VCC GND PRZ78 DCR:0.67mΩ +/-5%
5 DRVL1_VCORE
DRVL 4.7_1206_5%
1 2 CSREF_4PH <89>
1
PCZ49
2
PRZ89 10_0402_1%
2.2U_0402_6.3V6M SNB1_VCORE
2
SW1_4PH <89>
1
@EMI@
PCZ51
680P_0402_50V7K
2
PRZ84
0_0603_5% +19VB_CPU
1 2DRVH2_VCORE-1 PCZ66 PCZ67
+VCC CORE
1
10U_0603_25V6M
10U_0603_25V6M
TDC= 80A->86A
PRZ79 @ PQZ3 PQZ4
Peak Current= 128A->140A
2
2.2_0603_5% AON6962_DFN5X6D-8-7 AON6962_DFN5X6D-8-7
BOOT2_VCORE
2
1 2 OCP Current= 154A->168A
G1
D1
G1
D1
Load Line= 1.8mV/A
PCZ53
0.22U_0603_25V7K 7 7
Vboot= 0V
1
1 9 1 4
G2
G2
S2
S2
S2
S2
S2
S2
C
BST FLAG +VCC_CORE C
2
2 8 DRVH2_VCORE 2 3
<89> PWM2_4PH/ADDR
3
PWM DRVH
VSW2_VCORE SH00001D800
DRVON 3 7
EN SW 7x7X4
4 6 Isat:45A
+5VALW VCC GND
1
DRVL2_VCORE
@EMI@ DCR:0.67mΩ +/-5%
5 PRZ80
DRVL
4.7_1206_5%
1
PCZ52 1 2
2
2.2U_0402_6.3V6M PRZ90 10_0402_1%
2
SNB2_VCORE
SW2_4PH <89>
1
@EMI@
PCZ54
680P_0402_50V7K
2
PRZ83
0_0603_5% +19VB_CPU
1
10U_0603_25V6M
10U_0603_25V6M
PRZ81 @ PQZ6
2
2.2_0603_5% PQZ5 AON6962_DFN5X6D-8-7
BOOT3_VCORE 1
1
2
2
G1
D1
G1
D1
PCZ56
0.22U_0603_25V7K 7 7
1
1 9 1 4
G2
G2
S2
S2
S2
S2
S2
S2
BST FLAG +VCC_CORE
2
2 8 DRVH3_VCORE 2 3
<89> PWM3_4PH/VBOOT
6
3
PWM DRVH AON6962_DFN5X6D-8-7
DRVON 3 7
EN SW 7x7X4
4 6 Isat:45A
+5VALW VCC GND
1
DRVL3_VCORE
@EMI@ DCR:0.67mΩ +/-5%
5 PRZ82
DRVL
4.7_1206_5%
1
PCZ55 1 2
B B
2
2.2U_0402_6.3V6M PRZ91 10_0402_1%
2
SNB3_VCORE
SW3_4PH <89>
1
@EMI@
PCZ57
680P_0402_50V7K
2
PRZ86
0_0603_5% +19VB_CPU
1
10U_0603_25V6M
10U_0603_25V6M
PRZ87 @ PQZ8
2
2.2_0603_5% PQZ7 AON6962_DFN5X6D-8-7
BOOT4_VCORE
1
1 2
G1
D1
G1
D1
PCZ62
0.22U_0603_25V7K 7 7
1
1 9 1 4
G2
G2
S2
S2
S2
S2
S2
S2
BST FLAG +VCC_CORE

2
2 8 DRVH4_VCORE 2 3
<89> PWM4_4PH/ROSCM
6
PWM DRVH AON6962_DFN5X6D-8-7

DRVON 3 7
EN SW 7x7X4
4 6 Isat:45A
+5VALW VCC GND
1
DRVL4_VCORE
@EMI@ DCR:0.67mΩ +/-5%
5 PRZ88
DRVL
4.7_1206_5%
1
PCZ61 1 2
2
2.2U_0402_6.3V6M PRZ92 10_0402_1%

2
SNB4_VCORE
SW4_4PH <89>
1
A @EMI@ A
PCZ64
680P_0402_50V7K
2
Security Classification Compal Secret Data

CPU_CORE
5 4 3 2 1
5 4 3 2 1
Main Func = VCCGT/+VCCSA

+19VB_CPU
PCG4 PCG3 PCG8 PCG9
1
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
PRG1
2
D 2.2_0603_5% D
BOOT1_VCCGT 1 2
DRVH1_VCCGT-1
SH00001D800
1 2
7x7X4 +VCCGT
Isat:45A
1
PCG6 PRG3 0_0603_5% TDC= 25A
2
0.22U_0603_25V7K PQG1 DCR:0.67mΩ +/-5%
PUG1 AON6962_DFN5X6D-8-7 Peak Current= 32A
G1
D1
2
1
NCP81151MNTBG_DFN8_2X2
9
PLG1
0.15UH_NA__36A_20%
OCP Current= 39A
BST FLAG 7
D2/S1
VSW1_VCCGT 1 4
+VCC_GT
Load Line= 2.7mV/A
2 8 DRVH1_VCCGT
<89> PWM1_2PH/ICCMAX2 PWM DRVH 2 3
Vboot= 0V
DRVON 3 7 VSW1_VCCGT
G2
S2
S2
S2
EN SW
4 6 near choke
+5VALW
3
VCC GND
1
@EMI@
5 DRVL1_VCCGT PRG2 PRG4
DRVL 10_0402_1%
4.7_1206_5%
CSREF_2PH <89>
1
PCG5 1 2
2
2.2U_0402_6.3V6M
2
SNB1_GT
SW1_2PH <89>
1
@EMI@
PCG7
680P_0402_50V7K
2
C C
+19VB_CPU
PCA2 PCA1
1
10U_0603_25V6M
10U_0603_25V6M
2
2
PRA2 PCA5
2.2_0603_5% 0.22U_0603_25V7K
1 2 BST_R_+VCC_SA 1 2 HG_+VCC_SA
+VCCSA
TDC= 10A
Choke 0.47uH SH00001ED00 (Commom Part) Peak Current = 11A
PQA1 (Size:5.7 x 5.4 x 3.0 mm)
PUA1
(DCR:6.2m +-5%) OCP Current= 13A
1
NCP81253MNTBG_DFN8_2X2 EMB09A03VP_EDFN3X3-8-10
Load Line= 10.3mV/A
G1
D1
D1
D1
BST_+VCC_SA 1 8 PLA1
BST DRVH 0.47UH_MMD05CZR47M_12A_20% Vboot= 1.05V
B 2 7 SW_+VCC_SA 9 10 SW_+VCC_SA 1 4 B
<89> PWM1_1PH/ICCMAX1 PWM SW D2/S1 D1 +VCC_SA
3 6 2 3
<89,90> DRVON EN GND
G2
S2
S2
S2
4 5
+5VALW
PAD
VCC DRVL
1
@EMI@
8
PRA1
4.7_1206_5%
9
1
PCA4
CSN_1PH <89>
2
2.2U_0402_6.3V6M LG_+VCC_SA
2
SNB_SA
1
@EMI@
PCA6 SW_1PH <89>
680P_0402_50V7K
2
A A

+VCC_GT/+VCC_SA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C1PRG LA-E051P
5 4 3 2 1
A
B
C
D
for
+VCC_CORE
Reverse
2 1 2 1 2 1 2 1 2 1 2 1 2 1 Acoustic
2
1
+
@
@
PCZ159 PCZ149 PCZ139 @ PCZ134 PCZ124 H82@ PCZ114 PCZ104 PCZ176
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R4.5M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
5
5
2
1
+
@
@
PCZ160 PCZ150 PCZ140 @ PCZ135 PCZ125 PCZ115 PCZ105 PCZ101

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2_2V_Y
+VCC_CORE
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
@
PCZ161 PCZ151 PCZ141 @ PCZ136 PCZ126 H82@ PCZ116 PCZ106 PCZ102
3
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
PCZ162 PCZ152 PCZ142 @ PCZ137 H82@ PCZ127 PCZ117 H82@ PCZ107 PCZ103
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
@
@
@ PCZ163 PCZ153 PCZ143 @ PCZ138 PCZ128 PCZ118 PCZ108 PCZ170

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PCZ164 PCZ154 PCZ144 PCZ129 PCZ119 PCZ109 PCZ171

24 +6@ X 1uF_0201
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
X 220uF_D2_2V

2 1 2 1 2 1 2 1 2 1 2 1 2 1
@

22 +19@ X 22uF_0603_X5R for H62
28 +13@ X 22uF_0603_X5R for H82
2 1 2 1 2 1 2 1 2 1 2 1 2 1
H82 Total VCORE Output Capacitor:

4
4
2 1 2 1 2 1 2 1 2 1 2 1 2 1
@ PCZ168 PCZ158 PCZ148 PCZ133 H82@ PCZ123 H82@ PCZ113 PCZ175

2 1 2 1 2 1 2 1
+VCC_GT
PCG133 PCG123 PCG113 PCG103

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PCG134 PCG124 PCG114 PCG104

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PCG135 PCG125 PCG115 PCG105

2
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PCG101
2 1 2 1 2 1 2 1 220U_D2_2V_Y

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+VCC_GT
2
1
+
2 1 2 1 2 1 2 1 PCG102
220U_D2_2V_Y
3
3

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

2
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
12+8@
18+2@
Issued Date
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
X 1uF_0201
@ PCG141 PCG131 @ PCG121 PCG111

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
X 220uF_D2_2V
NA
2 1 2 1 2 1 2 1
X 22uF_0603_X5R
@ PCG142 PCG132 @ PCG122 PCG112

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Total VCCGT Output Capacitor:
2
2
Compal Secret Data

Deciphered Date
+VCC_SA
2 1 2 1
2 1
@
PCA107 PCA101
PCA113 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
1+4@
10+2@
2 1 2 1
2014/07/04
2 1
PCA108 PCA102
@ PCA114 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
2 1 2 1
2 1
@
PCA109 PCA103
@ PCA115 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
2 1 2 1
Title
X 1uF_0201
Date:
2 1
X 22uF_0603
Custom
PCA110 PCA104
@ PCA116 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
2 1 2 1
2 1
@
PCA111 PCA105
@ PCA117 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M
Total VCCSA Output Capacitor:
Size Document Number
2 1 2 1
@
PCA112 PCA106
22U_0603_6.3V6M 22U_0603_6.3V6M
Friday, February 22, 2019
1
1
DH53F M/B LA-F991P
Sheet
92
of
100
R ev
1A
A
B
C
D
5 4 3 2 1
Samesung VRAM
When,VRAM_VDD_CTL=High
Vboot=Vref*R2/(R1+R2+80)
=2*35.7K/(10K+35.7K+80) EMI@ PLW11
=1.56V B+_+1.35VS_VGAP
FBMA-L11-201209-800LMA50T
1 2
When,VRAM_VDD_CTL=Low GPU_B+
Vboot=Vref*R2/(R1+R2+80)
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
0.1U_0402_25V6
=2*(35.7K//52.3K)/(10K+(35.7K//52.3K)+80) PRW1
PCW1
PCW2
EMI@ PCW19
1
1
=1.356V 1K_0402_1%
PCW3
PCW4
PCW5
1 2
<27,37> 1.35VSDGPU_EN
D D
2
@EMI@
@EMI@
PCW6
Micron & Hynix VRAM 0.1U_0402_25V6 MOSFET: DFN 5X6E
When,VRAM_VDD_CTL=High 1 2
H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)
Vboot=2*30.9K/(10K+30.9K+80) +3VALW L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)
=1.51V UG1_+1.35VS_VGAP +1.35VSDGPU
When,VRAM_VDD_CTL=Low TDC 14A
1
SW1_+1.35VS_VGAP
Vboot=2*(30.9K//68.1K)/(10K+(30.9K//68.1K)+80) PRW10 Peak Current 20A
=1.36V 31.6K_0402_1% 13X8X4 OCP current 30A
@ PRW3
Isat:55A fsw=400kHz
2
VREF_+1.35VS_VGAP 0_0402_5% DCR:1.3mΩ (+/-5%)
1 2 PQW1
<27> FBVDDQ_PSI
4
AOE6930_DFN5X6E8-10 PLW1
Rref1
1
REFIN_+1.35VS_VGAP 0.47UH_MHT-MHDZIR47MEM1-RT_30A_20%
G1
D2/S1_3 S1/D2
D1_1
D1_2
1
SW1_+1.35VS_VGAP-1
Outside@
PRW2 @ PRW5 PRW6
1 2
+1.35VSDGPU
10K_0402_1% 68.1K_0402_1% 10K_0402_1% 9 10
0.1U_0402_25V6
1
D1_3 S2
D2/S1_2
D2/S1_1
2
Outside@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PRW4 1 1 1
2
1
@EMI@ PRW8
PCW7
G2
330U_D1_2VY_R9M
330U_D1_2VY_R9M
330U_D1_2VY_R9M
2.2_0603_5%
1
Inside@ PRW26 2 1 4.7_1206_5% + + +
PCW23
PCW9
PCW10
PCW11
PCW12
PCW13
+3VALW 0_0402_5%
BOOT1_+1..35VS_VGAP_R
2
2
VID_+1.35VS_VGAP_R 1 2
Rref2
2
2 2 2
BOOT1_+1.35VS_VGAP
SNB1_+1.35VS_VGAP
52.3K_0402_1%
0.033U_0402_16V7K
Outside@
UG1_+1.35VS_VGAP
Outside@
VID_+1.35VS_VGAP
PSI_+1.35VS_VGAP
EN_+1.35VS_VGAP
1
1
Outside@ PRW21
Outside@ PCW8
PRW5
PRW7 10K_0402_1% LG1_+1.35VS_VGAP @

35.7K_0402_1% Outside@ PRW27
2
0_0402_5%
2
C C
2
DMN53D0LDW-7 2N SOT363-6
報，最最最最330U 改改
1
@EMI@ PCW16
3
1
PUW1 680P_0402_50V7K
1
@ PRW7
Outside@ PQW2B
Outside@ PQW2A
@0@ PRW9 RT8816BGQW_WQFN20_3X3 PCW14

for cost 22 0U
2
30.9K_0402_1% 0_0402_5% 0.22U_0603_25V7K
UGATE1
BOOT1
VID
PSI
EN
2
5 2 VID_+1.35VS_VGAP_R 1 2
VRAM_VDD_CTL <27>
REFADJ_+1.35VS_VGAP 6 20 SW1_+1.35VS_VGAP
0.1U_0402_16V7K
4
REFADJ PHASE1
@ PCW15
REFIN_+1.35VS_VGAP 7 19 LG1_+1.35VS_VGAP
REFIN LGATE1 PRW11
2
2.2_0603_5%
VREF_+1.35VS_VGAP 8 18 PVCC_+1.35VS_VGAP 1 2
VREF PVCC +5VALW
PRW12 PRW13
2.2_0402_1% 383K_0402_1%
VREF_+1.35VS_VGAP 2 1 2 1 TON_+1.35VS_VGAP 9 17 PCW17
B+_+1.35VS_VGAP TON LGATE2
1
2.2U_0402_6.3V6M
@ PRW22
OCSET/SS
4.7K_0402_1% RGND 10 16
0.1U_0402_25V6
PCW18
2
UGATE2
RGND PHASE2
PGOOD
4.99K_0402_1%
BOOT2
1
2
1TON_+1.35VS_VGAP_R
VSNS
2
Inside@ PCW20
GND
0_0402_5%
@ PRW22
@ PRW14
@ PRW25 0.1U_0402_25V6
REF1
2
42.2K_0402_1%
21
11
1OCset_+1.35VS_VGAP 12
13
14
15
REFADJ
2
1.35VSDGPU_PG
@
Vsense_+1.35VS_VGAP
PRW25
B 33.2K_0402_1% B
REFADJ_+1.35VS_VGAP_R 1 2 REFADJ_+1.35VS_VGAP
Inside@ PCW21
2200P_0402_50V7K
@ PRW23
1
3.92K_0402_1%
3.3K_0402_1%
PRW17 36.5K_0402_1%
@ PRW23
PRW19
RBOOT
2
100_0402_1%
+1.35VSDGPU
1 2
2
2
@
PCW27
REFIN_+1.35VS_VGAP 0.1U_0402_25V6 PRW18
1 2 10K_0402_1%
1 2
Rocset for 75.6A

+3VS
@ PRW24
2200P_0402_50V7K
1
25.5K_0402_1%
28K_0402_1%
@ PRW24
Inside@ PCW22
1
1 2
<30> FB_VDDQ_SENSE
@
PRW20
REF2 1.35VSDGPU_PG <27>
2
0_0402_5%
2
A A

PWR_+1.5VRAM
5 4 3 2 1
SKL_H 42
A B C D E
1 1
@0@ PR1010
0_0402_5%
1VSDGPU_EN_R 1 2
1VSDGPU_EN <27>
1
Current limit = 4.7A(min) PR1008 @ PC1014
0.1U_0402_16V7K
2
PR1009 1M_0402_5%
10K_0402_5%
2
2 1 Choke 1uH SH00000YG00 (Common Part)
+3VALW
(Size:3.8 x 3.8 x 1.9 mm)
(DCR:20m~25m)
PU1002 Choke: SH00000YG00 Size:4x4x2 (Common Part)
<27> 1VSDGPU_PG 9
1 PGND 8 Rdc=27± 20% Taiyo
FB SGND Rdc=20mohm(Typ), 25mohm(Max) Cyntec
@ PJ1001 2
PG EN
7 PL1002 Rdc=27± 20% 3L
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.0VSDGPUP 3 6 LX_1.0VSDGPUP 1 2
Rdc=30± 20% Tai-Tech
+3VALW 1 2 IN LX +1.0VSDGPUP Rdc=32± 20% Chilisin
4 5 Rdc=36mohm(Typ), Xmohm(Max) Maglayers
68P_0402_50V8J
PGND NC
1
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PC1013 EMI@
PC1012
1
SY8003ADFC_DFN8_2X2 PR1007 PR1011
PC1009
PC1010
@ PC1011
22U_0603_6.3V6M 4.7_0603_5% 13.7K_0402_1%
2
2
2
2
FB_1.0VSDGPUP
1
EMI@
2
Rdown 2
1
FB=0.6V PC1008
Note:Iload(max)=3A 680P_0402_50V7K PR1012
20K_0402_1%
2
@ PJ1003
VFB=0.6V
2
JUMP_43X79
Vout=0.6V* (1+Rup/Rdown) +1.0VSDGPUP
1
1 2
2
+1.0VSDGPU
=0.6V* (1+13.7/20)
Vout=1.011V
3 3
4 4

1.05VSDGPU
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1A
A B C D E
5 4 3 2 1
@ PCV1
0.1U_0402_25V6
2 1
PRV1 PRV3
1 2 1 2
0_0402_5% 34K_0402_1%
NVVDD1
NVVDD_B+
TDC 45A
PCV2
0.1U_0402_25V6 +5VCC PRV6 Peak Current 150A
+3VS 1 2 4.3K_0402_1% OCP 200A
2 1
Fsw=300kHz
91K_0402_1%
10K_0402_1%
10K_0402_1%
PRV8
PRV9
1
3.6K_0402_1%
PRV139
PRV140
2 1
D PRV11 D
2
10K_0402_1% PRV2 +5VCC
2 1 4.99K_0402_1%
2
2
VGA_I2CC_SDA_PWR 2 1
VGA_I2CC_SCL_PWR PCV4 @ PCV5 PRV4
0.1U_0402_25V6 0.1U_0402_25V6 3.4K_0402_1%
1
1
0_0402_5%
0_0402_5%
1 2 1 2 2 1
@ PRV142
@ PRV141 2 1 2 1 PRV7
PRV12 PRV13 442_0402_1%
0_0402_5% 0_0402_5% 1 2
2
0_0402_5%
1 2 2 1 PCV3
PRV16
PCV6 PRV15 1U_0402_6.3V6K
0.015U_0402_16V7K 2.4K_0402_1% 1 2
2 1 1 2
2
PRV18 @ PCV7
@0@ PRV20 0_0402_5% 0.1U_0402_25V6 PRV14
<29> NVVDD1_VCC_SENSE 0_0402_5% 2K_0402_1%
0_0402_5%
PRV21
2 1 1 2
1 2 @
FDMF3170_REFIN
+NVVDD1 @0@ PRV145
ADDR/FSW_GPU
PRV22 +5VCC 0_0402_5%
VINMON_GPU
1
10_0402_1% 2 1
FDMF3170_IMON1 <96>
COMP_GPU
IMON_GPU
0.1U_0402_25V6
DAC_GPU
EAP_GPU
LPC_GPU
PCV8
1
100K_0402_1%
@ PRV25 @ PCV11 @ PRV19
1
0_0402_5% 0.1U_0402_25V6 1K_0402_1%
2
+5VCC
@
PRV10
VOUT_S 1 2 1 2
2
0.1U_0402_25V6
@0@ PRV146
24
23
22
21
20
19
18
17
C C
PCV14
2 1 PUV1 0_0402_5%
2
2
100K_0402_1%
PRV31 2 1
REFOUT
COMP
EAP
DAC
VINMON
ADDR
IMON
LPC
FDMF3170_IMON2 <96>
0.1U_0402_25V6
1K_0402_1%
1
PRV29
@
1
1
CSPSUM_GPU
@ PCV13
25 16
FB CSPSUM @ PRV30
@0@ PRV34 NVVDD1_FBRTN 26 15 CSNSUM_GPU 1K_0402_1%
2
<29> NVVDD1_VSS_SENSE 0_0402_5% FBRTN CSNSUM
2
2 1 TSENSE_GPU 27 14 CSP1_GPU
<96> TSENSE_GPU TSENSE CSP1
VGA_I2CC_SDA_PWR CSP2_GPU FDMF3170_REFIN <96>
1 2 28 13
PRV35 <27> VGA_I2CC_SDA_PWR SDA UP9512QQKI_WQFN32_4X4 CSP2
10_0402_1% VGA_I2CC_SCL_PWR 29 12 CSP3_GPU
NVVDD1_FBRTN <27> VGA_I2CC_SCL_PWR SCL CSP3 +5VS
+5VCC
1 2 EN_GPU 30 11
+3VALW EN CSP4
PRV39
1
PSI_GPU
10K_0402_1%
10K_0402_1% 31 10 2 1
PSI 5VCC
4.7U_0402_6.3V6M
PRV40
PRV42
1
NVVDD1_PG
PCV18
32 9 2.2_0603_5%
PGOOD PWM1
6
REFADJ
33
CH_OC
2
2
GND
REFIN
PWM4
PWM3
PWM2
PQV01A
PQV01B
VREF
VID
2 5
<27,37> NVVDD1_EN
8
1
REFADJ_GPU
1 2
PWM4_GPU
PWM3_GPU
VREF_GPU
CH_OC_GPU
+3VS
REFIN_GPU
PWM2_GPU
PWM1_GPU
VID_GPU
@ PRV46
0_0402_5%
PRV50
NVVDD_PSI <27> 0_0402_5%
6.19K_0402_1%
B 2 1 B
1
PRV44
1 2
@ PRV52
R1 @0@ PRV54
0_0402_5% 0_0402_5%
2
2 1 GPU_PWM1 <96>
PRV61
100K_0402_1% 2 1 GPU_PWM2 <96>
+3VS 1 2 2 1
@0@ PRV56
133K_0402_1%
232K_0402_1%
22.6K_0402_1%
63.4K_0402_1%
PRV53 0_0402_5%
PRV63
@0@ PRV70 4.32K_0402_1%
16.5K_0402_1%
0_0402_5%
R3
1
1
+5VS 1 2
1
@ 100K_0402_1%
PRV57
@ PCV9
1U_0402_6.3V6K <27> NVVDD_VID
1 2
R4
PRV71
@ PRV72
PRV73
PRV69
@ PUV8
2
TC7SH08FU_SSOP5~D
R2
2
2
5
1 PRV66
P
+5VS B GPU_DRVON <96>

4 20.5K_0402_1%
EN_GPU 2 O 2 1
A
G
3
4700P_0402_50V7K
1
309_0402_1%
1
PCV26
PRV64
1U_0402_6.3V6K
PRV51
C R5
0_0402_5% PWMVID 的 RC BOM
2
PCV25
2 1
請根據GPU
據GPU 's conf i g 設定
2
A A
NVVDD1_FBRTN

PWR_VGA_UP9512P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F551P
5 4 3 2 1
1 2 3 4 5
GPU_B+ NVVDD_B+
EMI@ PLV11
+19VB PRV74 PRV75
HCB2012KF-121T50_0805
1 2 1 4 1 4
EMI@ PLV12 2 3 2 3
HCB2012KF-121T50_0805
1 2
0.005_1206_1% 0.005_1206_1%
+5VS
A A
2
<36> CSSP_B+ <36> CSSN_B+ CSSP_NVVDD <36><36> CSSN_NVVDD
NCP303150@
PRV77
0_0402_5%
PRV76 NVVDD_B+
1
30K_0402_5%
1 2
Use 0603 size
@0@ PRV82
5> TSENSE_GPU
0_0402_5%
PCV30
PCV31
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
1 1
1 2 TMON1_FDMF3170 BST1_FDMF3170
1 2
33U_25V_M
33U_25V_M
1
1
+ +
PCV32
PCV33
PCV34
PCV35
PCV39
PCV38
PCV249
PCV36
PRV80
2.2_0603_1%
2
1
+5VS 2 2
EMI@
EMI@
16
17
11
10
13
9
@
PCV40
0.1U_0603_25V7K
VIN1
FAULT
BOOT
ZCD_EN
N/C
VIN
2
@0@ PRV85
0_0402_5%
PCV27 +NVVDD1 1 2 VOS1_FDMF3170 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE1_FDMF3170
PVCC PHASE
1 2 VCC1_FDMF3170 3
PRV78 VCC
2_0402_5% 2
AGND
1
PCV37
2.2U_0402_6.3V6M 5 PUV2
PGND QD9619AQR1
2
20
PGND2
PLV2 +NVVDD1
B S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A B
1 2 PWM1_FDMF3170 14 8 LX1_FDMF3170 1 2
GPU_DRVON <95> <95> GPU_PWM1 @0@ PRV79 0_0402_5% PWM SW
1
1 2 EN1_FDMF3170 15
@0@ PRV84 0_0402_5% DISB#
FDMF3170_IMON1 18
10X10X4
EMI@ PRV154
<95> FDMF3170_IMON1 IMON 4.7_1206_5%
Isat:90A
1 2 FDMF3170_REFIN1 19 DCR:0.55mΩ (+/-5%)
PGND1
2
REFIN
@0@ PRV81 0_0402_5% GPU1_SNB1
GL
TP
1
EMI@ PCV255
6
21
7
680P_0402_50V7K
2
+5VS
2
NCP303150@
PRV87
0_0402_5%
PRV88 NVVDD_B+
1
30K_0402_5%
1 2
Use 0603 size
@0@ PRV92
0_0402_5%
PCV47
PCV48
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
1 2 TMON2_FDMF3170 BST2_FDMF3170
1 2
1
PCV49
PCV50
PCV51
PCV52
PCV41
C PRV90 C
2.2_0603_1%
2
1
+5VS
@EMI@
@EMI@
16
17
11
10
13
9
PCV57
0.1U_0603_25V7K
VIN1
FAULT
BOOT
ZCD_EN
N/C
VIN
@0@ PRV95
0_0402_5%
PCV44 +NVVDD1 1 2 VOS2_FDMF3170 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE2_FDMF3170
PVCC PHASE
1 2 VCC2_FDMF3170 3
PRV86 VCC
2_0402_5% 2
1
PCV54 AGND
2.2U_0402_6.3V6M 5
PGND PUV3
2
20 QD9619AQR1
PGND2
PLV3 +NVVDD1
S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A
1 2 PWM2_FDMF3170 14 8 LX2_FDMF3170 1 2
<95> GPU_PWM2 @0@ PRV89 0_0402_5% PWM SW
1
1 2 EN2_FDMF3170 15
@0@ PRV94 0_0402_5% DISB#
FDMF3170_IMON2 18 EMI@ PRV93
<95> FDMF3170_IMON2 IMON 10X10X4
4.7_1206_5%
1 2 FDMF3170_REFIN2 19 Isat:90A
PGND1
DCR:0.55mΩ (+/-5%)
2
REFIN
@0@ PRV91 0_0402_5% GPU1_SNB2
GL
TP
FDMF3170_REFIN <95>
1
EMI@ PCV60
6
21
D 680P_0402_50V7K D
2

PWR_+NVVDD1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F551P
1 2 3 4 5
A
B
C
D
+NVVDD1
2 1 2 1 2 1
2
1
+
@
PCV155 PCV159 PCV251 PCV135
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 560U_D2_2VM_R4.5M
2 1 2 1 2 1
5
5
2
1
+
2 1 2 1 2 1
2
1
+
2 1 2 1 2 1
2
1
+
2 1 2 1 2 1
2
1
PCV162 PCV149 PCV143 +
PCV139
2 1 2 1 2 1
2
1
+

2 1 2 1 2 1
PCV164 PCV151 PCV145

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1
PCV165 PCV152 PCV146

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1
PCV153 PCV147
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1
PCV154 PCV148
1U_0201_6.3V6M 1U_0201_6.3V6M
4
4
+NVVDD1
2 1
+NVVDD
2 1 2 1 2 1
N18P-G0
PCV215
560uF X 6
PCV283 PCV225 PCV235 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV216
1uF_0201 X 28
10uF_0402X 34
PCV280 PCV226 PCV236 10U_0402_6.3V6M

2 1
22uF_0603 X 15
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

2 1 2 1 2 1
PCV217
PCV237 PCV227 PCV279 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1 2 1
PCV218
PCV276 PCV229 PCV282 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV219
3
3
PCV228 PCV287 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV220
PCV230 PCV250 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV221
PCV231 PCV275 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV222
Issued Date
PCV232 PCV281 10U_0402_6.3V6M

10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV223
PCV233 PCV284 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M 2 1
2 1 2 1
PCV224
PCV234 PCV277 10U_0402_6.3V6M
10U_0402_6.3V6M 10U_0402_6.3V6M
2016/01/06
+NVVDD1
2 1 2 1
PCV254 PCV243
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCV253 PCV244
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2
2
PCV252 PCV245
22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data
2 1 2 1
Deciphered Date
PCV257 PCV246
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCV256 PCV247
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
PCV248
22U_0603_6.3V6M
2017/01/06
2 1
PCV358
22U_0603_6.3V6M
2 1
PCV359
22U_0603_6.3V6M
2 1
PCV360
22U_0603_6.3V6M
Size
Title
Date:
2 1
PCV361
22U_0603_6.3V6M
Document Number
LA-F551P
Friday, February 22, 2019
1
1
Sheet
97
PWR_VGA DECOUPLING
of
100
R ev
1A
A
B
C
D
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve Page
B B
A A

N18E-GDDR6_D
1A
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change PG# Modify List Date Phase
change PR1009 from 100K_0402_5% (SD028100380) to 10K_0402_5% (SD028100280)

change PG pull high from +3VS to +3VALW
D change PRW1 from 20K_0402_1% (SD034200280) to 1K_0402_1% (SD034100180) D
01 Design Update For EA Turning and HW 93, 94 Change the PCW27 from pop to un-pop, and . PCW27.2 net name change from +1.35VSDGPU to Vsense_+1.35VS_VGAP.
sequence 95, 97 unpop PCV135
89, 92 Change the PUV8, PCV9 from pop to un-pop. 11/14 A
Add location PRV51 0_0402_5% (SD028000080), and pop.
Change the PCW21, PCW22 From 4700P_0402_50V (SE074472K80) to 2200P_0402_50V(SE074222K80).
Delete PL1111 (HCB2012KF-121T50_0805)
Change the PQB2,PQM2 from AON7506 (SB000010A00) to EMB12N03V (SB00001HV00)

83, 85 update location PRG5 PRA3 to PUG1 PUA1
02 Design Update solution change 90, 91 PLZ1,PLG1,PLZ2,PLZ3,PLZ4 change to common part P/N (SH00001EE00) 11/16 A
pop PQZ2, PQZ4 unpop PQZ1, PQZ3
83, 85 Change PRM10, PRM8, PRV82, PRV85, PRV92, PRV95, PRV79, PRV81, PRV84, PRV89, PRV91, PRV94, PRV54, PRV56, PRV70, PRV145,
03 Design Update 0 ohm to R-short 90, 91 PRV146, PRZ72, PRZ73, PRZ25, PRZ30, PRZ32, PRZ18, PRZ9, PRZ11, PRZ24, PRZ27,PRV20, PRV34 11/16 A
change PRZ12 from 1.78K_0402_1%(SD00000WY80) to 1.62K_0402_1%(SD000003380)

change PRZ14 from 31.6K_0402_1%(SD034316280) to 28K_0402_1%(SD034280280)
change PCZ24 from 470P_0402_50V8J(SE071471J80) to 220P_0402_50V8J(SE082221J80)
C
change PRZ51 from 84.5K_0603_1%(SD014845280) to 100K_0603_1%(SD014100380) C
04 Design Update For CPU transient 89, 92 PRZ61=110k ohm @H82, PRZ61=102k ohm @H62
PRZ35=25.5k ohm @H82, PRZ35=28k ohm @H62 11/19 A
unpop PCZ101, PCZ103, PCG102
pop PCZ176
un pop PCZ120, PCZ104, PCZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124 for H82
un pop PCZ120, PCZ104, CZ105, PCZ118, PCZ111, PCZ108, PCZ126, PCZ124, PCZ123, PCZ127, PCZ107, PCZ113, PCZ116, PCZ114 for H62
Change the PL501 1.5uH to common part

05 Design Update solution change 84 Change the PCZ47, PCZ48, PCZ65, PCV36, PCV249 from 33U_25V_NC_6.3X4.5 (SF000007200) to 33U_25V_M (SF000007700) 12/3 A
Chnage the PRZ43 from 12.1K_0402_1% (SD034121280) to 12K_0402_1% (SD034120280)
06 Design Update solution change 87 unpop PC1811 0.47U_0402_6.3V6K (SE124474K80) 12/12 B
pop PCV149~PCV158, PCV162~PCV165, PCV258 (1U_0201_6.3V6M) 12/18 B

07 Design Update solution change 83, 97 reserve PDB2 for dead battery
12/18 B
08 Design Update solution change 87, Change PR1010, PRW9, PR1801, PR2501 from 0ohm to r-short
93, 94
B B
A A

PIR
5 4 3 2 1
A B C D E
Version change list (P.I.R. List) Page 1 of 2 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
1 6 Chipset 11/14 Update CPU,PCH,GPU PN. DVT 0.2

43,68,
1
2 71,72 Source 11/14 Change material source. 1.Change CS95,CM3,CM20,CS5,CS111 to SGA00003700. DVT 0.2 1
3 58 EC 11/14 Design change. 1.Add CB14 on EC_RST#. DVT 0.2

4 27,37 GPU 11/14 Design change and fine tune sequence. 1.Remove RV397, pop RV335. DVT 0.2
2.Reserve CV400, change RV106 to 100kohm.
3.Change RV105 to 10kohm, CV197 to 0.22uF, depop DV4.
4.Change RV22 to 200kohm.
5.Change UV45,UV48 to SA000070V00.
5 66 Sensor 11/15 Design change. 1.Remove R39,R40,C41,U6. DVT 0.2

6 58 EC 11/16 Board ID. 1.Change RB3 to 12kohm. DVT 0.2
7 43,56 Source 11/16 Change material source. 1.Change CS13 to SE00000X200,0603 size. DVT 0.2
2.Change DS19 to SCA00004500.
3.Change LA4,LA5 to SM01000BW00.
4.Change UF2 to SA000067P00.
2
5.Change QV3,QV4 to SB00001GC00. 2
6.Change UH3 to SA00000OH00.
7.Change UC3 to SA00007WE00.
8 32 VRAM 11/19 For N17P-G0-K1 SKU. 1.Change UV4 related component BOM structure to VRAM4G@. DVT 0.2
9 11/20 Design change. 1.Change RV338,RH94,RH96,RH99,RH101,RH102,RH103,RH105,RX8,RX9 to R-short. DVT 0.2
10 67 HDD 11/20 Follow DVR1012,HDD CONN P11 pull-down. 1.Add RO25, remove T211. DVT 0.2
11 10 ESD 11/21 For ESD request. 1.Add CC101,CC102,CC103, change CD10 to 33pF and pop. DVT 0.2
12 27,51 Crystal 11/21 By Crystal EA result. 1.Add RL14, change CL21,CL22 to 18pF. DVT 0.2
2.Change RV80 to 470ohm, CV1,CV2 to 18pF.
13 43 TYPEC 11/23 Update CONN symbol. 1.Change JTYPEC1 to DC23300RC00. DVT 0.2
14 42,43 TYPEC 12/18 Follow 2018 Type-C spec. 1.Remove RS127, add US14. DVT 0.3
3
,58 2.Remove TYPEC_1P5A net from PCH. 3
3.Add TYPEC_1P5A_EC net from EC.
4.Add RS137.
15 36 GPU 12/18 OVRM issue. 1.Change RV399 power source to +3VLP. DVT 0.3
2.Change RV345~RV348,RV370,RV371,RV372,RV374 power rail to +3V_OVRM.
3.Add QV16,RV400,OVRM_EN net to EC/PCH, reserve RH261.
16 58 EC 12/18 Update board ID. 1.Change RB3 to 15k. DVT 0.3
17 12/27 Design change. 1.Change RA7,RQ1,RQ2,RQ3,RQ4,RQ8,RV352,RV353,RV356,RV358,RV362,RV364,RV365 PVT 1.0
,RV382,RM53 to R-short.
18 63,77 ESD/EMI 01/03 For ESD/EMI request. 1.Reserve DK2,CK6,CK7 for ESD. PVT 1.0
2.Add SPRING1~3 for EMI.
19 58 EC 01/03 Update board ID. 1.Change RB3 to 20k. PVT 1.0
20 66 ESD 01/31 For ESD request. 1.Add C60. PVT 1A
4 4

PIR-HW1
A B C D E

Acer Nitro AN515-54 EH50F EH51F EH5VF EH70F Compal LA-H501P Rev 1A Schematic Diagram

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Acer Nitro AN515-54 EH50F EH51F EH5VF EH70F Compal LA-H501P Rev 1A Schematic Diagram

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A B C D E

Security Classification Compal Secret Data Compal Electronics, Inc.

HDMI Conn. eDP

2 X4 DMI USB 3.0 USB 3.0 CMOS 2

48MHz page 72 page 42,43 page 38 page 71

RJ45 conn. SATA HDD Conn. HDA Codec

page 32. ENE

DC/DC Interface CKT.

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel Power State

EC_SMB_CK1 BQ24780 (Charger IC) 0x12 LAN Switch mode SWR@

Security Classification Compal Secret Data Compal Electronics, Inc.

B UQ2 RQ9 +1.8VS RA3 +1.8VS_VDDA CODEC B

PU1801 PJ1801 +1.8VALW RH100 +1.8VALW _PRIM PCH

US12 +USB_VCCA JUSB1 USB3.0 Conn. +VCC_FAN1

DH5VF_EVT Power Sequence AC mode

Plug in Power On S3 S3 Resume Power Off

PCB EH5VF LA-H501P LS-H501P/H502P PCB EH5VF LA-H501P LS-H501P/H502P

Coffee Lake-H CPU SKU

S IC CL8068403373522 SR3Z0 U0 2.3G ABO! S IC CL8068404121905 QRR5 U0 2.4G FCBGA

S IC CL8068403359524 SR3YY U0 2.2G ABO! S IC CL8068404121817 QRR2 U0 2.6G FCBGA 1440

S IC CL8068403373522 QP89 U0 2.3G BGA

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

<24> DDR_B_D[0..63] DDR CHANNEL B

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG Lane Reversed CFL-H

Security Classification Compal Secret Data Compal Electronics, Inc.

PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

RC14 1 2 499_0402_1% H_PROCHOT#_R

RC15 1 2 60.4_0402_1% EC_VCCST_PG

RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCC_SA CFL-H +1.2V_VDDQ +1.2V_VDDQ

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Max PCIe* Ports (or devices) = 16 - GbE (0 or 1) F26 RSVD USB2P_11 G1

Security Classification Compal Secret Data Compal Electronics, Inc.

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

AW13 BD4 CLK_CNV_PRX_DTX_N

RH29 2 1 100K_0402_5% GPP_H15 STRAP

intel critical net recommend

PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

RH56 2 1 8.2K_0402_5% PM_BATLOW # PM_SLP_S3# RH193 1 2 100K_0201_5%

RH57 1 @ 2 100K_0402_5% AC_PRESENT_R

D_CK_SCLK <23,24> LAN_W AKE# RH212 1 2 10K_0402_5%

PCH_PW ROK RH213 1 2 10K_0402_5%

QH7A EC_RSMRST# RH214 1 2 10K_0402_5%

D_CK_SDATA <23,24> PCH_DPW ROK

RH191 2 1 2.2K_0402_5% D_CK_SCLK XESD@

XESD@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%

2 CPU_ID RH255 1 H82@ 2 1K_0402_5% 2

+3VALW RH256 1 H62@ 2 10K_0402_5%

RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP

RH83 2 @ 1 100K_0402_5% PCH_SPKR ‧‧ GPP_G[7:0]

Security Classification Compal Secret Data Compal Electronics, Inc.

GPIO Group Voltage

1 W20 Short pins AJ22,AJ23,AK22,AK23 together

1 1 AJ22 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71