CMOS Digital Integrated Circuits: Lec 12 Dynamic Logic Circuits

CMOS Digital Integrated Circuits
Lec 12
Dynamic Logic Circuits
1 CMOS Digital Integrated Circuits

Dynamic Logic Circuits
Goals
Understand
Pass transistors circuits
Voltage bootstrapping
Synchronous dynamic circuit techniques
Dynamic CMOS circuit techniques
High-performance dynamic CMOS circuits

Static v.s. Dynamic
Static Logic Gates

Valid logic levels are steady-state operating points
Outputs are generated in response to input voltage levels after a
certain time delay, and it can preserve its output levels as long as
there is power.
All gate output nodes have a conducting path to VDD or GND,
except when input changes are occurring.
Dynamic Logic Gates
The operation depends on temporary storage of charge in parasitic
node capacitances.
The stored charge does not remain indefinitely, so must be
updated or refreshed. This requires establishment of an update or
recharge path to the capacitance frequently enough to preserve
valid voltage levels.

Static v.s. Dynamic (Continued)
Advantages of Dynamic Logic Gates

Allow implementation of simple sequential circuits with memory
functions.
Use of common clock signals throughout the system enables the
synchronization of various circuit blocks.
Implementation of complex circuits requires a smaller silicon area
than static circuits.
Often consumes less dynamic power than static designs, due to
smaller parasitic capacitances.

Pass-Transistor Latch
Circuit and Operation
Soft note
ML Q
D MP Vx Q
X
MD
Cx
CK
Operation
CK = H, D=H or L : CX is charged up or down through MP, and X
becomes H or L (depends on D input) since MP is on D and X
are connected.
CK = L: X is unchanged since MP is off and CX is isolated from D,
and the charge is stored on capacitances CX.
For X = H, Q = L and Q = H
For X = L, Q = H and Q = L
Cost: 3 to 5 devices (very low)
Pass-Transistor Latch
Soft Node Concept
During CK = 1: Let D = 1, i.e. VD = VOH = VDD MP is conducting
and charges CX to a weak 1 (VX = VDD VTD) Q = L (VQ<VTD)
and Q = H(VQ=VDD).
During CK = 0: Logic-level VX is preserved through charge
storage on CX. However, VX starts to drop due to leakage.
What value does VX have to deteriorate to no longer like a stored ?
Example (see p359~359, Kang and Leblebici): For an inverter
with VDD = 5V, VT,n = 0.8V , VOL = 2.9V and VIH = 2.9V, initial VX
=4.2 V. But due to leakage currents, this will decline over time.
When it declines below VIH(2.9V), then a logic 0 out of the
inverter can no longer guaranteed.
Thus, to avoid an erroneous output, the charge stored in CX must
be restored or refreshed to its original level before VX declines
below 2.9 V.

Basic Principles of Pass Transistor Circuits
Logic 1 Transfer
Logic 1 Transfer: VX(t=0)=0V, Vin=VOH=VDD, CK=0 VDD
Soft note
ID

Vx Vin=VDD D S Vx
Vin MP
X MP X
Cx Cx
CK CK
VGS = VDD - VX, VDS = VDD - VX = VGS.

Therefore, VDS> VGS VT,MP MP is in saturation.
dV X k n
V DD V X V T ,MP
2
CX
dt 2
Note that the VT,MP is subject to substrate bias effect and therefore,
depends on the voltage level VX. We will neglect the substrate bias
effect for simplicity.

Logic 1 Transfer (Cont.)
Integrating the above equation with t from 0 t and VX from 0
VX, we have
t VX
2C X dV X
0 dt
k n 0 V DD V X V T ,MP
2
VX
1
2C X
k n V DD V X V T ,MP 0
Therefore,
1 1
t 2C X
kn V DD V X V T ,MP V DD V T ,MP
and,
k n V DD V T ,MP t
V X (t ) V DD V T ,MP
2C X

1 k n V DD V T ,MP t

2C X
VX
Vmax=VDD-VT,MP
Vmax
t
0
VX rises from 0V and approaches a limit value Vmax = VX(t)|t= = VDD-
VT,MP, but it can not exceed this value, since the pass transistor will turn
off at this point (VGS=VT,MP). Therefore, it transfers a weak logic 1.
The actual Vmax by taking the body effect into account is,
V max V DD V T 0,MP 2 F V max 2 F

and tcharge = time to VX = 0.9Vmax,
2C X 1 1
t charge k n
V DD 0.9V max V T ,MP V DD V T ,MP
Body Effect: Reduce VX, and Increase tcharge
Logic 0 Transfer
Logic 0 Transfer: VX(t=0)=Vmax= VDD VT,MP, Vin=VOL=0V,
CK= 0 VDD
Soft note
ID

Vx Vin=0 S D Vx
Vin MP
X MP X
Cx Cx
CK CK
VGS = VDD, VDS = Vmax = VDD VT,MP.

Therefore, VDSVGS VT,MP MP is in linear region.
dV X k n
CX 2 V DD V T ,MP V X V 2X
dt 2
Note that the VSB=0. Hence, there is no body effect for MP (VT,MP=
VT0,MP). But the initial condition VX(t=0)=VDD VT,MP contains the
threshold voltage with body effect. To simplify the expressions,
we will use VT,MP in the following.
Integrating the above equation with t from 0 t and VX from VT,MP
VX, we have
t VX
2C X dV X
0 dt
k n V DD V T , MP 2V DD V T ,MP V X V X
2
2V DD V T ,MP V X
VX
CX
ln
k n V DD V T ,MP VX V DD V T , MP
Therefore,
CX 2V DD V T ,MP V X
t ln
k n V DD V T ,MP VX
and,
2V DD V T ,MP
V X (t ) tk n V DD V T , MP / C X
1 e
VX drops from Vmax = VDD-VT,MP, to 0V. Hence, unlike the charge-
up case, it transfers a strong logic 0.
fall = time of VX drops from 0.9Vmax to 0.1Vmax,
fall t 90% t10%
CX ln(19) ln(1.22) VX
k n V DD V T ,MP Vmax=VDD-VT,MP
Vmax
CX
2.74
k n V DD V T ,MP
where,
CX 2 0.9 V DD V T ,MP
t 90% ln t
k n V DD V T ,MP 0.9 V DD V T ,MP 0
CX
ln 1.22
k n V DD V T ,MP
CX 1.9
t10% ln
k n V DD V T ,MP 0.1

Charge Storage and Charge Leakage
At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX will
gradually leak away, primarily due to the leakage currents
associated with the pass transistor. The gate current of the inverter
driver transistor is negligible.
Ileakage Vx Igate=0
Vin =0 MP
Cx
CK=0
VCK=0
Ileakage VX
Vin=0
CX
n+ Isubthreshold n+
p-type Si Ireverse

Charge Storage and Charge Leakage (Cont.)
VCK=0 Ileakage VX
Vin=0
n+ n+ CX
Isubthreshold
p-type Si Ireverse
Ileakage= Isubthreshold + Ireverse

Ileakage Vx
Cin= Cgb + Cpoly + Cmetal

Cj(VX) Cin
Isubthreshold Ireverse
CX= Cin + Cj
Drain-substrate pn-junction
Isubthreshold is the subthreshold current for the pass transistor with CK=0.
Ireverse is the reverse current for the source/drain pn junction at node X
Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX
Cin: due to oxide-related parasitics, can be considered constants.
Ileakage= Isubthreshold + Ireverse
Ileakage Vx
Cin= Cgb + Cpoly + Cmetal

Isubthreshold Cj Cin
Ireverse
CX= Cin + Cj
Drain-substrate pn-junction
The total charge stored in the soft node can be expressed as,
Q = Qj (VX) + Qin where Qin = CinVX
The total leakage current can be expressed as the time derivative
of the total soft-node charge Q
dQ
I leakage
dt
dQ j (V X ) dQin

dt dt
dQ j (V X ) dV X
C in dV X
dV X dt dt

Where
dQ j (V X )
C j (V X )
dV X
AC j 0 AC j 0 SW

1 V X 1 V X
0 0 SW
kT N D N A kT N D N ASW
0 ln 0 SW ln 2

q ni2 q ni
Therefore,

AC j 0 PC j 0 SW dV X
I leakage C in
dt

1 V X 1 V X

0 0 SW
We have to solve the above differential equation to estimate the

actual charge leakage time from the soft node.

A quick estimate of the worst-case leakage behavior

Assume that the minimum combined soft-node capacitance is
CX,min = Cgb + Cpoly + Cmental + Cdb,min
Cdb,min is the minimum junction capacitance, obtained when VX=Vmax
The worst-case holding time (thold) is the shortest time for VX to drop
from its initial logic-high value to the logic threshold voltage due to
leakage.
thold = Qcritical,min/Ileakage,max
where Vth
Qcritical,min =CX,min (Vmax-VDD/2)

Example 9.2: Consider the soft-node structure shown below, which
consists of the drain (or source, depending on current direction) terminal of
the pass transistor, connected to the polysilicon gate of an nMOS driver
transistor via a metal interconnect.
Question: is to estimate thold if VDD=5V and the soft-node is initially
charged to Vmax.
Vx
MP M1
Cx
CK
soft node
3 6 5 6
1 2
MP 4 5 M1 2
1 2
4 1
3
CK
diffusion metal polysilicon

Material parameters:
VTO = 0.8V COX = 0.065 fF/ m2
= 0.4V1/2 Cmetal = 0.036 fF/ m2
|2 F| = 0.6V Cpoly = 0.055 fF/ m2
0 = 0.88V Cj0 = 0.095 fF/ m2
0SW = 0.95V Cj0SW = 0.2 fF/ m
Ileakage,max = 0.85 pA 3 6 5 6
1 2
MP 4 5 M1 2
1 2
diffusion metal polysilicon 4 1
3
Soft-node Capacitance Calculation CK
Oxide-related (constant) parasitic capacitances
Cgb = COXWLmask = 0.065 fF/ m2 (4 m 2 m) = 0.52 fF
Cmetal = CmetalWLmetal = 0.036 fF/ m2 (5 m 5 m) = 0.90 fF
Cploy = CpolyWLpoly = 0.055 fF/ m2 (36+6+2 m2) = 2.42 fF

Parasitic junction capacitance
By zero-bias unit capacitance values in the previous slide, we have
Cbottom = AbottomCj0 = 0.095 fF/ m2 (36 m2 + 12 m2 ) = 4.56 fF
Csidewall = Cj0SWPsidewall = 0.2 fF/ m2 (30 m) = 6.00 fF
Therefore
Cdb,max = Cbottom + Csidewall = 4.56 fF + 6.00 fF = 10.56 fF
The minimum drain junction capacitance is achieved as the junction is
biased with Vmax. We need to find Vmax to determine Cdb,min
Vmax = 5.0 - 8.0 - 0.4 ( 0.6+ Vmax - 0.6 )
Vmax = 3.68 V
C bottom C sidewall
Therefore, C db,min
1 V X ,max 1 V X ,max
0 0 SW
4.56 6.0
4.71 fF
3.68 3.68
1 1
0.88 0.95
Combining the Oxide-related (constant) parasitic capacitances with the
parasitic junction capacitance, CX,min can be got as
CX,min = Cgb + Cpoly + Cmental + Cdb,min
= 0.52 + 2.42 + 0.90 +4.71 = 8.55 fF
The amount of the critical charge drop is
Qcritical = CX,min(VX,min-VDD/2)=8.55 (3.68-2.5)=10.09 fC
Finally,
thold = Qcritical /Ileakage,max=11.87ms
The worst-case hold time for this structure is relatively long, even with
a very small soft-node capacitance of 8.55fF. It means that the logic
gate can be preserved in a soft node for a long time period when the
leakage current is small.

Voltage Bootstrapping
The Voltage bootstrapping is a technique to overcome the threshold
voltage drops of the output voltage levels in pass transistor gates or
enhancement-load inverters and logic gates.
Consider the following circuit with VXVDD M2 is in saturation. If
Vin is low, the maximum output voltage is limited as
Vout(max) = VX VT2(Vout)
VDD
Vx M2
Vout
Vin M1
Cout

Voltage Bootstrapping (Cont.)
To overcome the voltage drop, the voltage VX must be increased. This
can be achieved by adding a third transistor M3 into the circuit.
CS and Cboot represent the capacitances which dynamically couple
VX to the ground and to the output.
The goal of the above circuit is to provide a high enough voltage VX
to let Vout go to VDD instead of VDD-VT2(Vout).
VDD
M3
Vx
M2
CS Cboot Vout
Vin M1 Cout
Initially, let Vin=H M1 and M2 are on, and Vout=L.

Now Vin goes to L M1 turns off, and Vout starts to rise. This change
will be coupled to VX through the bootstrap capacitor, Cboot.
Let iCboot be the transient current through Cboot during the charge-up event,
and let iCS be the current through CS. Assume iCS iCboot, we have
iCS iCboot CSdVX/dt Cbootd(Vout-VX)/dt
(CS+Cboot)dVX/dt CbootdVout/dt
dVX/dt Cboot /(CS+Cboot) dVout/dt
This expression can be integrated to give VX such that Vout will rise to VDD.
VX C boot V DD
V DD V T 3 dV X C S C boot V OL dV out
C boot
. V X V DD V T 3 V DD V OL
C S C boot
If Cboot >> CS, then for Vout rising to VDD,
VX(max) 2VDD VT3 VOL > VDD VT2.
for realistic values of the voltages. Thus, it is feasible to use the circuit to
obtain Vout =VDD.

To overcome the threshold voltage drop at Vout, the minimum VX is

VX(min) = VDD + VT2|Vout = VDD
= [VDD-VT3(VX)]+Cboot /(CS+Cboot) (VDD-VOL)
Therefore, the required capacitance ratio Cboot /(CS+Cboot) is
C boot V T 2 Vout VDD V T 3 VX

C S C boot V DD V OL
C boot V T 2 Vout VDD V T 3 VX
.
C S V DD V OL V T 2 Vout VDD V T 3 VX
CS is the sum of the parasitic source-to-substrate capacitance of M3 and the
gate-to-substrate capacitance of M2.

Cboot can be specifically constructed to control its value by using a
transistor with the source and drain connected together at Vout and the gate
attached to VX. Since its drain and source tied together, it simply acts as an
MOS capacitor between VX and Vout.
VDD
M3
Vx
M2
Cboot
Vout
Vin M1
See Kang and Leblebici at pp. 373 for a SPICE example.

Synchronous Dynamic Circuit Techniques
Dynamic Pass Transistor Circuits
The multi-stage synchronous circuit is shown below. The circuit consists of
cascaded combinational logic stages interconnected through nMOS
pass transistors. Its operation depends on temporary charge storage in the
parasitic input capacitances.
Comb. Comb. Comb. F1

A Logic Logic Logic
B 1 2 3 F2
1 C 2 D 1
1
t
2 phase1 phase2
t
1, 2 non-overlapping clocks
Logic levels are stored on input capacitances during the inactive clock
phase.
Two-Phase Clock Dynamic Shift Register
Depletion-Load Dynamic Shift Register
The max clock frequency is determined by signal propagation delay
through one inverter stage.
One half-period of the clock signal must be long enough to allow Cin to
charge up or down, and Cout to charge to the new value.
The logic-high input value is one VT0 lower than VDD.
VDD VDD VDD
1 2 1
Vout
Vin
Cin1 Cout1 Cin2 Cout2 Cin3 Cout3

Enhancement-Load Dynamic Shift Register
Enhancement-Load Dynamic Shift Register 1
Instead of biasing load transistors with a constant gate voltage, a clock
signal is applied to the gate of the load transistor power dissipation
and silicon area are reduced.
The power supply current flows only when the load devices are activated
by the clock signal, the power consumption is lower than the depletion-
load nMOS logic.
VDD VDD VDD

1 2 1
2
Vout
Vin

Enhancement-Load Dynamic Shift Register 1 (Cont.)
General Structure
VDD VDD
2 1
1
Z
A
nMOS nMOS
B Logic Logic
Stage 1 Stage 2
C D
General Circuit Structure of Ratioed Synchronous Dynamic Circuit

VDD VDD VDD
1=H 2 1
1 2
Vout1 Vout2
Vout3
Vin
Vout2VOL
VDD VDD VDD
2=H 2 1
1 2
Vout1 Vout2
Vout3
Vin
Vout1VOL Vout3VOL
VOL kdriver/kload Ratioed Dynamic Logic.

Cout1, Cin2 & Cout2, Cin3 interact Charge Sharing

The input pass transistor and the load transistor are driven by the same
clock phase.
The valid low-output voltage level VOL=0V can be achieved regardless of
the driver-to-load ratio, this circuit is a ratioless dynamic logic.
VDD VDD VDD

1 2 1
Vout
Vin

Enhancement-Load Dynamic Shift Register 2(Cont.)
General Structure
VDD VDD
1 2
Z
A
nMOS nMOS
B Logic Logic
Stage 1 Stage 2
C D
General Circuit Structure of Ratioless Synchronous Dynamic Circuit

1=H VDD VDD VDD
1 2 1
Vout1 Vout2
Vout3
Vin
Vout1VOL Vout2 0V Vout3VOL

2=H VDD VDD VDD
1 2 1
Vout1 Vout2
Vout3
Vin
Vout10V Vout2VOL Vout30V

VOL 0V Ratioless Dynamic Logic.
Cini << Couti-1 for i=2,3 Minimum Charge Sharing

Charge Sharing
2
Vb Va
Cout1 Cin2
Charge Sharing
2 = 0: Qout1 = Cout1Vb and Qin2 = Cin2Va

2 = 1: Qtotal = Cout1Vb + Cin2Va and Ctotal = Cout1 + Cin2
The resulting voltage across Ctotal is
VR = Qtotal / Ctotal = (Cout1Vb + Cin2Va )/ (Cout1 + Cin2)
If Vb = VDD and Va << Vb VR Cout1VDD /(Cout1 + Cin2)
VR VDD if Cin2 << Cout1

Dynamic CMOS Transmission Gate Logic
Each transmission gate is controlled by the clock signal and its
complement. Therefore, the two-phase clocking need four clock signals.
As in the nMOS structures, the CMOS dynamic circuit relies on charge
storage in parasitic input capacitances during the inactive clock cycles.
1 2
1
B
F1
Stage 1
C Stage 2
D
1
1 2
Shift Register
The basic building block of the shift register consists of a CMOS
inverter, which is driven by a TG.
CK=1Vin is transferred onto the parasitic input capacitance CX.
The low on-resistance of TG results in
A smaller transfer time compared to nMOS-only switches.
No threshold voltage drop across TG
VDD
soft node
CK
Vin VX Vout
CK CX Cy

Shift Register (Cont.)
The single-phase CMOS shift register is built by
Cascading identical inverter units
Driving each stage alternately with the CK and CK.
Ideally: The odd-numbered stages are on as CK=1, while the even-
numbered stages are off the cascaded inverter stages are
alternately isolated.
Practically:
The CK and CK are not a truly nonoverlapping signal pair,
since their waveforms have finite rise and fall times.
One of the signals is generated by inverting the other the
clock skew is unavoidable.
True two-phase clocking is preferred over single-phase
clocking.
CK CK CK
V1 V2 V3 V4
CK CK CK
Dynamic CMOS Precharge-Evaluate Logic
Reduced Transistor Count
VDD
Mp
Vout
=0 C precharges to
C VDD (output is not available
nMOS Internal during precharge)
inputs Logic capacitance =1 C selectively
discharges to 0 (output is
only available after
Me discharge is complete)
evaluate
t
precharge precharge
Vout
t
An Example
VDD
Mp
Vout
A1
B1
A2
B2
A3
Me
Z is high when =0
Z=(A1 A2A3 +B1B2)
Advantages/Disadvantages
Advantages
Need only N+2 transistors to implement a N-input gate.
Low static power dissipation
No DC current paths to place constraints on device sizing
Input capacitance is same as pseudo nMOS gate.
Pull-up time is improved by active switch to VDD.
Disadvantages
The available time of output is less than 50 % of the time.
Pull-down time is degraded due to series active switch to 0.
Logic output value can be degraded due to charge sharing with other gate
capacitances connected to the output.
Minimum clock rate determined by leakage on C.
Maximum clock rate determined by circuit delays.
Input can only change during the precharge phase. Inputs must be stable
during evaluation; otherwise an incorrect value on an input could
erroneously discharge the output node. (single phase P-E logic gates can
not be cascaded)
Outputs must be stored during precharge, if they are required during the
next evaluate phase.

Cascading Problem
VDD VDD
Mp1 precharge evaluate
Mp2
Vout1 Vout2
t
1st stage 2nd Vout1 does not switch from
nMOS Vout
inputs 1 1 to 0 fast enough
Logic t
Vout correct state
Me2 erroneous state
Me1 t
Evaluate:
Me1, Me2 ON
Mp1, Me2 OFF
Problem: All stages must evaluate simultaneously one clock does
not permit pipelining of stages.
High Performance Dynamic CMOS Circuits
Domino CMOS Logic
Static inverter serves to buffer the
logic part of the circuit from its
VDD VDD
output load

X Vout
nMOS
inputs Logic =0
X precharges to VDD, and Vout = 0.
=1
X remains high, and Vout remains
low.
precharge evaluate X discharges to 0, and Vout
1
changes from 0 to 1.
t

Domino CMOS Logic
VDD VDD VDD

X1 X2 X3
nMOS nMOS nMOS

inputs Logic Logic Logic
evaluate evaluate

precharge teval t
X1
t Max number gates limited:
X2
total propagation delay < teval
X3 t
t
Domino CMOS Logic (Cont.)
VDD VDD VDD

X1 X2 X3
nMOS nMOS nMOS

inputs Logic Logic Logic
The problem in cascading conventional dynamic CMOS occurs

when one or more inputs make a 1 to 0 transition during evaluation.
Domino circuits can fix the above problem
During the evaluation, each buffer output can make at most one
transition (from 0 to 1), and thus each input of all subsequent
logic stages can also make at most one (0 to 1) transition.

Domino CMOS Logic
The Limitations
The static CMOS and domino gates can be used together, see Fig.
9.31. in Kang and Leblebici. The limitation: the number of
inverting static logic stages in cascade must be even, to let the
inputs of next domino stage can have only 0 to 1 transitions during
the evaluation.
Can implement only non-inverting logic
Due to precharge use, can suffer from charge sharing during the
evaluation which may cause erroneous outputs.
The problem will be described in the next slide, and several
solutions will be presented later.

Domino CMOS Logic
Charge Sharing
VDD VDD

VX
Vout
C1
N
C2
VX = VDDC1/(C1+C2)
Keep C2 << C1
Assume that all inputs are low initially, and the voltage across C2=0V
During the precharge, C1 is charged to VDD
If transistor N switches from 0 to 1 during the evaluation phase, the
charge initially stored in C1 will be shared by C2. Therefore, the value of
VX will reduced.

Domino CMOS Logic
Reduce Charge Sharing Degradation of VX
VDD
weak pull-up pMOS

VX Vout
nMOS
inputs Logic Push VX to VDD unless there
is a strong pull-down path
between Vout and ground

Domino CMOS Logic
Reduce Charge Sharing Degradation of VX (Cont.)
VDD
Use separate pMOS transistors to
precharge all intermediate nodes in
VX1 Vout1
nMOS pull-down tree which have a
large parasitic capacitance.
nMOS C1 Effectively eliminate all charge
Logic sharing problems during evaluation
VX2 Vout2 Allow implementation of multiple-
output domino structures.
C2
Can cause additional delay since the
nMOS nMOS tree need to drain a larger
Logic charge to pull down VX
Another Way: Use a smaller threshold voltage

the final stage output is not affected by
lowering of VX trade off the pull-up speed (weaker
pMOS transistor)
Domino CMOS Logic
An Example of Using Separate pMOS Transistor
VDD VDD VDD
VX1
Vout
VA C1
VX2
VB C2
Let C1 = C2 = 0.05pF. VX1 = 0, and VX2 = 0 at t=0
Without this extra pMOS transistor
Precharge: VX1 VX2
Evaluation: VX1 = VDDC1/(C1+C2) = VDD/2
With this extra pMOS transistor
Presharge: VX1 = VX2
Evaluation: VX1 = VDD
See pp.392~393 for the HSPICE simulation result
Note that there is a speed penalty for adding this
extra pMOS precharge transistor.
Domino CMOS Logic
An Example of Multiple-Output Domino Circuits
VDD

C4
P4 G4
C3
P3 G3
C2
P2 G2
C1
P1 G1
C0
Reduce transistor count
C1=G1+P1C0 Gi = Ai Bi
C2=G2+P2G1+P2P1C0
Pi = Ai Bi
C3=G3+P3G2+P3P2G1+P3P2P1C0
C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C0
FET Scaling in Domino CMOS Gates
The transient performance can be improved by adjusting
the nMOS transistor sizes in the pull-down path to reduce
the discharge time.
VDD
D C B A
Mp
Vout CL
A
C
R0 0 R1 1
D
C0 C1 CL
Me

The nMOS Scaling in Domino CMOS Gates
R0 0 R1 1
V1=V0=VDD VDDe-1 after time T1 C0 C1 CL
T1 =R0(C0+C1+CL)+R1(C1+CL)
Let the last nMOS is increased by a fraction of k then
C1 C1(1+k); R1 R1/(1+k)
T1 =R0(C0+C1+CL)+R1(C1+CL)+(C1-R1CL/R0)k
If
CL<(R0/R1)C1
T1 decreases by decreasing the size of the last nMOS.
R0/R1 is the number of series-connected nMOS minus one, times a factor
that takes the many effects that makes a real nMOS different from a
linear resistor, into account. Using the approximation =1/2, we conclude
If CL<C1(N-1)/2 is satisfied, the overall delay can be reduced by
decreasing the size of last nMOS.
The above result can be iteratively applied to the other transistors, which
leads to graded sizing of all nMOS devices.

NORA CMOS Logic (NP-Domino Logic)
VDD VDD VDD
nMOS pMOS nMOS

Logic Logic Logic
to nMOS stage to pMOS stage
nMOS stage all stages nMOS stage all stages

precharge evaluate precharge evaluate
pMOS stage pMOS stage
pre-discharge pre-discharge
Advantages
An Inverter is not required at the output of stages
Allow pipelined system architecture
Disadvantages: Also suffer from charge sharing and leakage

Examples
VDD VDD VDD
=L: nMOS precharges to H, and pMOS pre-discharges to L.

=LH: All cascaded nMOS and pMOS logic stages evaluate
one after the other.

Examples (Cont.)
Pipelined System Architecture: See Fig. 9.39 Use of CMOS2

latches (three state latches storing on logic inputs.)
Zipper Logic: See Fig. 9.40 Identical to NORA except for
weird clock signals that keep precharge devices weakly on to
handle charge leakage and charge sharing

Pipelined True Single-Phase Clock (TSPC) Dynamic CMOS
VDD VDD VDD VDD

nMOS pMOS
Logic Logic to next N-block
N-block P-block
Using tristate inverters between stages decouples the stages and enables pipelined operation
=L: nMOS blocks precharge to VDD
pMOS blocks evaluate by selective pull-up to VDD
=H: pMOS blocks pre-discharge to VDD
nMOS blocks evaluate by selective pull-down to 0V
is not used, no clock skew problem can arise.
Provide similar performance to NORA structure
TSPC-Based Rising Edge-triggered D-type Flip-Flop
VDD VDD VDD VDD
Need only 11 transistors.

Static Edge Triggered D Flip-flop (see Fig. 8.30) need 16 transistors.
Common Advantages of dynamic Logic Styles
Smaller area than fully static gates.
higher speed: smaller parasitic capacitances.
Glitch free operation if design carefully

Summary
Full complementary static logic is best option in the majority of

CMOS circuits.
Noise-immunity is not sensitive to kn/kp
Does not involve precharge of nodes
Dissipate no DC power
Layout can be automated
Large fan-in gates lead to complex circuit structures (2N
transistors)
Larger parasitics
Slower and higher dynamic power dissipation than alternatives
No clock

Summary (Cont.)
Pseudo-nMOS static logic finds widest utility in large fan-in

NOR gates.
Require only N+1 transistors for N fan-in
Smaller parasitics
Faster and lower dynamic power dissipation than full CMOS
Noise immunity sensitive to kn/kp
Dissipate DC power when pulled down
Not well suited for automated layout
No clock

Summary (Cont.)
CMOS domino logic should be used for low-power, high speed

applications
Require only N+k transistors for N fan-in, size advantages of
pseudo-nMOS.
Dissipate no DC power
Noise immunity is not sensitive to kn/kp
Use of clocks enables synchronous operation
Rely on storage on soft node
Require exhaustive simulation at all the process corners to
insure proper operation
Some of the speed advantage over static gates is diminished by
the required per-charge (pre-discharge) time.

CMOS Digital Integrated Circuits: Lec 12 Dynamic Logic Circuits

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CMOS Digital Integrated Circuits: Lec 12 Dynamic Logic Circuits

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CMOS Digital Integrated Circuits

1 CMOS Digital Integrated Circuits

2 CMOS Digital Integrated Circuits

Static Logic Gates

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Advantages of Dynamic Logic Gates

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6 CMOS Digital Integrated Circuits

VGS = VDD - VX, VDS = VDD - VX = VGS.

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V max V DD V T 0,MP 2 F V max 2 F

VGS = VDD, VDS = Vmax = VDD VT,MP.

1 CMOS Digital Integrated Circuits

1 CMOS Digital Integrated Circuits

Ileakage= Isubthreshold + Ireverse

Cin= Cgb + Cpoly + Cmetal

Cin= Cgb + Cpoly + Cmetal

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We have to solve the above differential equation to estimate the

1 CMOS Digital Integrated Circuits

A quick estimate of the worst-case leakage behavior

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1 CMOS Digital Integrated Circuits

1 CMOS Digital Integrated Circuits

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2 CMOS Digital Integrated Circuits

Initially, let Vin=H M1 and M2 are on, and Vout=L.

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To overcome the threshold voltage drop at Vout, the minimum VX is

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See Kang and Leblebici at pp. 373 for a SPICE example.

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Comb. Comb. Comb. F1

VDD VDD VDD

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VDD VDD VDD

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General Circuit Structure of Ratioed Synchronous Dynamic Circuit

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VOL kdriver/kload Ratioed Dynamic Logic.

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VDD VDD VDD

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General Circuit Structure of Ratioless Synchronous Dynamic Circuit

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Vout1VOL Vout2 0V Vout3VOL

Vout10V Vout2VOL Vout30V

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2 = 0: Qout1 = Cout1Vb and Qin2 = Cin2Va

3 CMOS Digital Integrated Circuits

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nMOS nMOS nMOS

nMOS nMOS nMOS

The problem in cascading conventional dynamic CMOS occurs

4 CMOS Digital Integrated Circuits

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4 CMOS Digital Integrated Circuits

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Another Way: Use a smaller threshold voltage

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