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Introduction To Metal-Oxide-Semiconductor Field Effect Transistors (Mosfets)
Introduction To Metal-Oxide-Semiconductor Field Effect Transistors (Mosfets)
Introduction To Metal-Oxide-Semiconductor Field Effect Transistors (Mosfets)
Metal-Oxide-Semiconductor
Field Effect Transistors
(MOSFETs)
metal
oxide
n+ n+
p
x
W
L
MOSFET Future (One Part of)
• International Technology Roadmap for
Semiconductors, 2008 update.
• Look at size, manufacturing technique.
From Intel
Structure: n-channel MOSFET
(NMOS)
gate: metal or heavily doped poly-Si
G
(bulk or body source IG=0 drain
substrate) B S D
ID=IS
y IS
metal
oxide
n+ n+
p
x
W
L
MOSFET Scaling
ECE G201
Gate
Fin (30nm)
BOX
Circuit Symbol (NMOS)
enhancement-type: no channel at zero gate voltage
D
ID= IS
IS G-Gate
D-Drain
S S-Source
B-Substrate or Body
Structure: n-channel MOSFET
(NMOS)
gate: metal or heavily doped poly-Si
G
(bulk or body source IG=0 drain
substrate) B S D
ID=IS
y IS
metal
oxide
n+ n+
p
x
W
L
Energy bands
(“flat band” condition; not equilibrium) (equilibrium)
Flatbands! For this choice of materials, VGS<0
n+pn+ structure ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs
n++
oxide
n+ n+
p
W
L
Flatbands < VGS < VT (Includes VGS=0 here).
n+-depletion-n+ structure ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs
+++
n++
oxide
n+ n+
p
W
L
VGS > VT
n+-n-n+ structure inversion
gate
G
body source drain
B S - + D
VD=Vs
+++
+++
+++
n++
oxide
n+ ----- n+
p
W
L
Channel Charge (Qch)
VGS>VT
Depletion region
charge (QB) is due
to uncovered acceptor ions
Qch
n++
n+ n+
p
W
L
(x)
EB
EF ~ EC
y
0 L
Triode Region
A voltage-controlled resistor @small VDS
B S D
- +
ID
+++
+++ VGS1>Vt
increasing
metal
- oxide
- - -
VGS
n+ n+
p
B S -+ D
+++ VGS2>VGS1
+++
+++
metal G
- -oxide
- - --
n+ n+
p
cut-off VDS
B S -+ D
0.1 v
+++ VGS3>VGS2
+++ +++
+++
metal
Increasing VGS puts more
n+
- - -oxide
------
p
n+ charge in the channel, allowing
more drain current to flow
Saturation Region
occurs at large VDS
As the drain voltage increases, the difference in
voltage between the drain and the gate becomes
smaller. At some point, the difference is too small
to maintain the channel near the drain pinch-off
gate
G
body source drain
+
B S - D
n+ n+
p
Saturation Region
occurs at large VDS
The saturation region is when the MOSFET
experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.
gate
G
body source drain
+
B S - D
n+ n+
p
Saturation Region
occurs at large VDS
VGS - VDS < VT or VGD < VT
VDS > VGS - VT
gate
G
body source drain
+
B S - D
+++ VD>>Vs
+++
+++
metal
oxide
n+ n+
p
Saturation Region
once pinch-off occurs, there is no further increase in
drain current
ID saturation
triode
VDS>VGS-VT
increasing
VDS<VGS-VT
VGS
VDS
0.1 v
Band diagram of triode and saturation
Simplified MOSFET I-V Equations
Cut-off: VGS< VT
ID = I S = 0
Triode: VGS>VT and VDS < VGS-VT
ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS2]
Saturation: VGS>VT and VDS > VGS-VT
ID = 1/2kn’(W/L)(VGS-VT)2
VGS>VT
Depletion region
charge (QB) is due
to uncovered acceptor ions
Qch
Threshold Voltage Definition