eGaN® FET DATASHEET EPC2020

EPC2020 – Enhancement Mode Power Transistor

VDS , 60 V D

RDS(on) , 2.2 mΩ G EFFICIENT POWER CONVERSION

ID , 90 A HAL
S

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
EPC2020 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Maximum Ratings
Die Size: 6.05 mm x 2.3 mm
PARAMETER VALUE UNIT
• High Speed DC-DC Conversion
Drain-to-Source Voltage (Continuous) 60
VDS V • Motor Drive
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 72
• Industrial Automation
Continuous (TA = 25˚C, RθJA = 7°C/W) 90 • Synchronous Rectification
ID A
Pulsed (25°C, TPULSE = 300 µs) 470 • Inrush Protection
Gate-to-Source Voltage 6 • Class-D Audio
VGS V
Gate-to-Source Voltage -4
TJ Operating Temperature -40 to 150
°C
TSTG Storage Temperature -40 to 150

Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 0.4
RθJB Thermal Resistance, Junction-to-Board 1.1 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 1.1mA 60 V
IDSS Drain-Source Leakage VGS = 48 V, VDS = 0 V 0.1 0.8 mA
Gate-to-Source Forward Leakage VGS = 5 V 1 9 mA
IGSS
Gate-to-Source Reverse Leakage VGS = -4 V 0.1 0.8 mA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 16 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 31 A 1.5 2.2 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.6 V
All measurements were done with substrate connected to source.

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eGaN® FET DATASHEET EPC2020

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance 1780 2140
COSS Output Capacitance VDS = 30 V, VGS = 0 V 1020 1530
CRSS Reverse Transfer Capacitance 24 pF
COSS(ER) Effective Output Capacitance, Energy Related (Note 2) 1410
VDS = 0 to 30 V, VGS = 0 V
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 1660
RG Gate Resistance 0.3 Ω
QG Total Gate Charge VDS = 30 V, VGS = 5 V, ID = 31 A 16 20
QGS Gate-to-Source Charge 3.9
QGD Gate-to-Drain Charge VDS = 30 V, ID = 31 A 2.3
nC
QG(TH) Gate Charge at Threshold 2.8
QOSS Output Charge VDS = 30 V, VGS = 0 V 50 75
QRR Source-Drain Recovery Charge 0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

400 400 25˚C

125˚C
VVDSDS==33VV
ID – Drain Current (A)
ID – Drain Current (A)

300 300

200 200
VGS = 5 V
VGS = 4 V
100 VGS = 3 V 100
VGS = 2 V

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDS – Drain-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)

Figure 3: RDS(on) vs. VGS for Various Drain Currents Figure 4: RDS(on) vs. VGS for Various Temperatures
6 6

ID = 30 A
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)

5 5 25˚C
ID = 60 A
ID = 120 A 125˚C
4 ID = 180 A 4 IVDDS==313 AV

3 3

2 2

1 1

0 0
2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VGS – Gate-to-Source Voltage (V) VGS – Gate-to-Source Voltage (V)
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eGaN® FET DATASHEET EPC2020

Figure 5a: Capacitance (Linear Scale) Figure 5b: Capacitance (Log Scale)
3000

2500 COSS = CGD + CSD 1000

CISS = CGD + CGS
CRSS = CGD
2000

Capacitance (pF)
Capacitance (pF)

COSS = CGD + CSD

1500 CISS = CGD + CGS
CRSS = CGD
100
1000

500

0 10
0 10 20 30 40 50 60 0 10 20 30 40 50 60
VDS – Drain-to-Source Voltage (V) VDS – Drain-to-Source Voltage (V)

Figure 6: Gate Charge Figure 7: Reverse Drain-Source Characteristics

5

ID = 31 A 400
4
VGS – Gate-to-Source Voltage (V)

VDS = 30 V 25˚C
ISD – Source-to-Drain Current (A)
125˚C
300
3

200
2

100
1

0 0
0 2 4 6 8 10 12 14 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
QG – Gate Charge (nC) VSD – Source-to-Drain Voltage (V)

Figure 8: Normalized On-State Resistance vs. Temperature Figure 9: Normalized Threshold Voltage vs. Temperature
2.0 1.40

ID = 31 A 1.30 ID = 16 mA
Normalized On-State Resistance RDS(on)

1.8 VGS = 5 V
Normalized Threshold Voltage

1.20
1.6
1.10

1.4 1.00

0.90
1.2
0.80
1.0
0.70

0.8 0.60
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TJ – Junction Temperature (°C) TJ – Junction Temperature (°C)

All measurements were done with substrate shortened to source.

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eGaN® FET DATASHEET EPC2020

Figure 10: Gate Leakage Current Figure 11: Safe Operating Area
80 1000

25˚C
100

I D – Drain Current (A)

60
125˚C
IG – Gate Current (mA)

Limited by RDS(on)
40 10
Pulse Width
100 ms
10 ms
20 1 1 ms
100 µs

0 0.1
0 1 2 3 4 5 6 0.1 1 10 100
VGS – Gate-to-Source Voltage (V) VDS - Drain-Source Voltage (V)
TJ = Max Rated, TC = +25°C, Single Pulse

Figure 12: Transient Thermal Response Curves

Junction-to-Board
1
Duty Cycle:
ZθJB, Normalized Thermal Impedance

0.5
0.2
0.1
0.1
0.05 PDM
0.02
0.01 0.01
t1
t2
0.001 Single Pulse
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
0.0001
10-5 10-4 10-3 10-2 10-1 1 10+1
tp, Rectangular Pulse Duration, seconds

Junction-to-Case
1 Duty Cycle:
ZθJC, Normalized Thermal Impedance

0.5
0.2
0.1
0.1
0.05
0.02
PDM
0.01
0.01
t1
t2
0.001
Single Pulse Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
0.0001
10-6 10-5 10-4 10-3 10-2 10-1 1
tp, Rectangular Pulse Duration, seconds

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eGaN® FET DATASHEET EPC2020

TAPE AND REEL CONFIGURATION

8 mm pitch, 12 mm wide tape on 7” reel e Loaded Tape Feed Direction
g
d f
7” inch reel Die
orientation
dot
ZZZZ
a b c Gate
YYYY solder bump is
under this
corner
2020

h Die is placed into pocket

solder bump side down
DIM Dimension (mm) (face side down)
EPC2020 (Note 1) Target MIN MAX
a 12.00 11.90 12.30
b 1.75 1.65 1.85
c (Note 2) 5.50 5.45 5.55
d 4.00 3.90 4.10
e 8.00 7.90 8.10 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
f (Note 2) 2.00 1.95 2.05 JEDEC industry standard.
g 1.50 1.50 1.60 Note 2: Pocket position is relative to the sprocket hole measured as
h 1.50 1.50 1.75 true position of the pocket, not the pocket hole.

DIE MARKINGS

2020

YYYY Laser Markings

Part
Die orientation dot Number Part # Lot_Date Code Lot_Date Code
ZZZZ Marking Line 1 Marking Line 2 Marking Line 3
Gate Pad bump is
EPC2020 2020 YYYY ZZZZ
under this corner

DIE OUTLINE
Solder Bump View Micrometers
DIM MIN Nominal MAX
A
f
A 6020 6050 6080
X30 B 2270 2300 2330
c 2047 2050 2053
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
X30

d 717 720 723

d

e 210 225 240

f 195 200 205
c

g 400 400 400

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

Pad 1 is Gate;
e g Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22,
X4 X28
25, 26, 29 are Source;
Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
Side View
(685)
(785)

24, 27, 28 are Drain;

Pad 30 is Substrate.*
100 ± 20

Seating plane

*Substrate pin should be connected to Source

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eGaN® FET DATASHEET EPC2020

RECOMMENDED Land pattern is solder mask defined

LAND PATTERN Solder mask opening is 180 µm
(units in µm) It is recommended to have on-Cu trace PCB vias
6050
180
X30 Pad 1 is Gate;
Pads 2, 5, 6, 9,10,13,14, 17, 18, 21, 22,
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
X30
700

25, 26, 29 are Source;

Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23,
2030

2300
24, 27, 28 are Drain;

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
Pad 30 is Substrate.*

*Substrate pin should be connected to Source

400
X28

RECOMMENDED Recommended stencil should be 4 mil

STENCIL DRAWING (100 µm) thick, must be laser cut, openings
(units in µm)
per drawing.
6050

Intended for use with SAC305 Type 3 solder,

reference 88.5% metals content.
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
720

R60 Additional assembly resources available at

https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx

2300
2050

1330

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

400 200
X34 X35

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit Information subject to
described herein; neither does it convey any license under its patent rights, nor the rights of others. change without notice.
eGaN® is a registered trademark of Efficient Power Conversion Corporation. Revised June, 2020
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

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