90 Chapter 2 MOS Transistor Theory

2.5.2 Beta Ratio Effects

We have seen that for Gp = Gn, the inverter threshold voltage Vinv is VDD /2. This may be
desirable because it maximizes noise margins (see Section 2.5.3) and allows a capacitive
load to charge and discharge in equal times by providing equal current source and sink
capabilities (see Section 4.2). Inverters with different beta ratios r = Gp /Gn are called
skewed inverters [Sutherland99]. If r > 1, the inverter is HI-skewed. If r < 1,
the inverter is LO-skewed. If r = 1, the inverter has normal skew or is
unskewed.
VDD
A HI-skew inverter has a stronger pMOS transistor. Therefore, if the
`p
`n = 10
input is VDD /2, we would expect the output will be greater than VDD /2. In
other words, the input threshold must be higher than for an unskewed
2
Vout inverter. Similarly, a LO-skew inverter has a weaker pMOS transistor and
1
0.5 thus a lower switching threshold.
`p
= 0.1 Figure 2.28 explores the impact of skewing the beta ratio on the DC
`n
transfer characteristics. As the beta ratio is changed, the switching thresh-
0 old moves. However, the output voltage transition remains sharp. Gates are
VDD
usually skewed by adjusting the widths of transistors while maintaining
Vin
minimum length for speed.
FIGURE 2.28 Transfer characteristics of
skewed inverters The inverter threshold can also be computed analytically. If the long-
channel models of EQ (2.10) for saturated transistors are valid:
Gn
(V inv  Vtn )
2
I dn =
2
(2.54)

( )
Gp 2
I dp = V  V DD  Vtp
2 inv
By setting the currents to be equal and opposite, we can solve for Vinv as a function of r :

1
VDD + Vtp + Vtn
V inv = r
(2.55)
1
1+
r
In the limit that the transistors are fully velocity saturated, EQ (2.29) shows
I dn = WnC ox vsat n (V inv  Vtn )
(2.56)
I dp = W pC ox vsat  p (V inv  V DD  Vtp )

Redefining r = Wpvsat-p / Wnvsat-n, we can again find the inverter threshold

1
V DD + Vtp + Vtn
V inv = r (2.57)
1
1+
r
In either case, if Vtn = –Vtp and r = 1, Vinv = VDD /2 as expected. However, velocity sat-
urated inverters are more sensitive to skewing because their DC transfer characteristics are
not as sharp.
DC transfer characteristics of other static CMOS gates can be understood by collaps-
ing the gates into an equivalent inverter. Series transistors can be viewed as a single tran-
sistor of greater length. If only one of several parallel transistors is ON, the other