5 4 3 2 1

)+%/2&.',$*5$0 01
IV@ For UMA
GPU CORE PWR CHARGER
EV@ For Pure Dis. RT8204 P45 ISL88731 P53

SP@ For special setting

GPU IO PWR 3/5V SYS PWR
SPI@ For Optimus & UMA special setting UP6111AQDD P46 RT8206 P52
Fan Driver
SPE@ For Pure Dis.special setting (PWM Type) Discharger/+3V_M
D CPU CORE PWR D

VA@ For Audio version A setting P42 P54 ISL95831 P43~P44

VB@ For Audio version B setting intel +1.8V CPU +1.05V_VTT

@3G For 3G setting <MCH Processor> ALS (SM/BUS) UP61111AQDD P51 UP61111AQDD P47

PIV@ For UMA Power

DDR SYSTEM MEMORY

CPU iGPU_CORE PCH +1.05V
PEV@ For Pure Dis. Power SandyBridge 0.61 RT8204 P45 UP61111AQDD P49

+0.85V DDR3 PWR

ISL62871 P48 RT8207A P50
Dual Channel rPGA 988 X'TAL
DDR III (37.5mm X 37.5mm) 27.0MHz
1066/1333 MHz PCI-E
SO-DIMM 0 PCIE
SO-DIMM 1
FDI DMI
X16
5GT/s
nVIDIA GPU
P14, 15 P4~P7 N12P Fermi CRT R-SW
Package GB2-128 P24 CRT P24
C C
Optimus (Muxless) P16~P22
FDI interface X4 DMI interface
2.7GT/s 5GT/s LVDS
INT_CRT Switchable P24 LVDS P24

iGFX Interfaces
FDI DMI
HDD (SATA)
P25 SATA0 SATA Gen3 intel INT_LVDS
HDMI R-SW HDMI
SATA3 INT_HDMI P24
ODD (SATA) SATA Gen2 <PCH> P24
P25

RTC
X'TAL USB8
P9 32.768KHz
PCIE4 NewCard
USB
USB 2.0 CougarPoint 0.7 USB8 P33
USB CNNs PCI-Express Gen2
PCI-E
USB0,1,2 P27 Azalia 5GT/s
HDA
PCIE6 PCIE1 PCIE2
Bluetooth
B
mBGA 989 B
USB9 P27 (25mm X 25mm)
Realtek Mini Card Mini Card
RTL8111E-GR
CCD P8~P13 WiFi 3G
P26 USB3 P28 USB4 P28
USB6 P24
SPI LPC X'TAL USB3 USB4
25MHz
X'TAL
CardReader 25MHz
Transformer SIM Card Conn
RTS5138 P26
USB5 P23
DB P28

Audio CODEC Dual SPI ROM WPCE791/FLASH

4MB x1 (Basic ME+Braidwood) RJ45
P9 P26
RTL ALC269VB P31
P30
PECI3.0

A A

P31
HP Jack MIC Jack SPK DMIC SPI ROM Touch Pad Keyboard Light Sensor Button on
P30 P30 P30 P24 P31 P29 P29 P33 mechanical key Quanta Computer Inc.
1RWH
PROJECT : FH5
Size Document Number Rev
+0GRHVQRWVXSSRUW86%  1A
Block Diagram
+0GRHVQRWVXSSRUW6$7$ 
Date: Monday, September 27, 2010 Sheet 1 of 41
5 4 3 2 1
 1 2 3 4 5 6 7 8

02
N12P-GE Power Up Sequence MS15-UMA Power-ON Sequence
ACIN
MAINON +3VPCU/+5VPCU
A NBSWON# A

DGPU_VRON

S5_ON
T1
RSMRST#
+3V_GPU(VDD3) T2
EC_PWRBTN#

+1.05V_GPU(PEX_VDD)
SLP_S5#,SLP_S4#,SLP_S3#
tNVVDD
SUSON
+VGPU_CORE(NVVDD)
tNV-IFPAB_IOVDD MAINON T3
T5
MAINON2
+1.8V_GPU(IFPAB_IOVDD)
+1.5VSUS/+3VSUS/+5VSUS
tNV-FBVDDQ
+1.5V/+1.8V/+3V/+5V
B B
+1.5V_GPU(FBVDDQ)
+1.05V_PCH/+1.05V_VTT/+0.75V_DDR_VTT

N12P-GE Power up Sequence

tNVVDD>0 HWPG
tNV-IFPAB_IOVDD>0
VRON
tNV-FBVDDQ>0 T10
CPU SVID BUS

+VCC_CORE
+VCC_GFX
T9

Deep S4/S5 off-on Sequence IMVP_PWRGD

+3V_DSW T4
EC_PWROK
DWPROK

SYS_PWROK T8
SUSWARN#

C C
SUS_ACK# DRAMPWROK T6
UNCOREPWRGOOD
SLP_SUS#
SUS_STAT# T7
PLTRST#
RSMRST#
T1
System Power Sequence
S5_ON T1: S5_ON TO RSMRST# = 30ms (spec:mini 10ms)
T2: RSMRST# TO EC_PWRBTN# = 110ms (spec:mini 100ms)
+3V_S5/+5V_S5 T3: MAINON2 TO VRON = 110ms (spec:mini 99ms)
T4: VRON TO EC_PWROK = 10ms (HWPG NEED TO BE HIGH at that time)
T5: MAINON to MAINON2 =500us
Deep S4/S5 Sequence
T6: EC_PWROK to UNCOREPWRGOOD =2ms(Min)
T1: S5_ON TO RSMRST# = 30ms (spec:mini 10ms)
T7: SUS_STAT# to PLTRST# =60us(Min)
T8: SYS_PWROK to SUS_STAT# =1ms(Min)
T9: +VCC_CORE to IMVP_PWRGD =5ms(Max)
T10: VRON to accept SVID command. =5ms(Max)

D D

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
Frontpage
Date: Monday, September 27, 2010 Sheet 2 of 41
1 2 3 4 5 6 7 8
 5 4 3 2 1

03

D D

+3V_S5 +3V_S5
+3V_GPU +3V_GPU
+3V_GPU
2.2Kȍ 2.2Kȍ
N12P-GE
2.2Kȍ 2.2Kȍ
SMB_ME0_CLK
G
D S I2CS_SCL
NMOS
SMB_ME0_DAT
G
D S I2CS_SDA
NMOS
+3V_S5 +3V_S5 +3VPCU +3VPCU
+3V_S5

C C

intel 2.2Kȍ 2.2Kȍ 6.8Kȍ 6.8Kȍ

<PCH> G
SMB_ME1_CLK S NMOS
D MBCLK EC
G
ITE 8518
SMB_ME1_DAT S D MBDATA
CougarPoint 0.7 NMOS

mBGA 989
+3V_S5 +3V_S5 +3V +3V
(25mm X
25mm) +3V_S5
Slave ADDRESS :A0H Slave ADDRESS :A4H
DDR3 DIMM-0-STD VREF DQ0 DDR3 DIMM-1-STD VREF DQ1
(5.2H) M2 Solution (9.2H) M2 Solution
2.2Kȍ 2.2Kȍ 4.7Kȍ 4.7Kȍ
B B
G
SMB_PCH_CLK D S SMB_RUN_CLK
NMOS

G
SMB_PCH_DAT D S SMB_RUN_DAT
NMOS

A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
SMBus Address
Date: Monday, September 27, 2010 Sheet 3 of 41
5 4 3 2 1
 5 4 3 2 1

04
Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG)
U28B
U28A
J22 PEG_COMP R413
PEG_ICOMPI 0X2
J21
D PEG_ICOMPO CLK_CPU_BCLKP_R D
8 DMI_TXN0 B27
DMI_RX#[0] PEG_RCOMPO
H22 SNB_IVB# N.A at SNB EDS #27637 0.7v1 BCLK
A28 3 4 CLK_CPU_BCLKP 10

MISC

CLOCKS
B25 PEG_RXN[0..15] 16 9 H_SNB_IVB# C26 A27 CLK_CPU_BCLKN_R 1 2 CLK_CPU_BCLKN 10
8 DMI_TXN1 DMI_RX#[1] PROC_SELECT# BCLK#
8 DMI_TXN2 A25 DMI_RX#[2]
B24 K33 PEG_RXN0 R415
8 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] PEG_RXN1 SKTOCC#
M35 AN34 SPI@0X2
PEG_RX#[1] TP12 SKTOCC#
B28 L34 PEG_RXN2 A16 CLK_DPLL_SSCLKP_R 3 4
8 DMI_TXP0 DMI_RX[0] PEG_RX#[2] DPLL_REF_CLK CLK_DPLL_SSCLKP 10
B26 J35 PEG_RXN3 A15 CLK_DPLL_SSCLKN_R 1 2 CLK_DPLL_SSCLKN 10
8 DMI_TXP1 DMI_RX[1] PEG_RX#[3] DPLL_REF_CLK#

DMI
A24 J32 PEG_RXN4
8 DMI_TXP2
B23
DMI_RX[2] PEG_RX#[4]
H34 PEG_RXN5 ZĂ
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
H31 PEG_RXN6 TP_CATERR# AL33 R414 Zď *SPE@1K/J_4 EV UMA
PEG_RX#[6] TP9 CATERR#
G21 G33 PEG_RXN7 R417 *SPE@1K/J_4
8 DMI_RXN0
E22
DMI_TX#[0] PEG_RX#[7]
G30 PEG_RXN8
+1.05V_VTT ZĂ E ϬŽŚŵ
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] ZĐ

THERMAL
F21 F35 PEG_RXN9
8 DMI_RXN2
D21
DMI_TX#[2] PEG_RX#[9]
E34 PEG_RXN10 11,31 EC_PECI AN33 R8 CPU_DRAMRST# 5
Zď ϭ<ͲŽŚŵ E
8 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] PEG_RXN11 PECI SM_DRAMRST#
E32
PEG_RX#[11] ZĐ ϭ<ŽŚŵ E

DDR3
MISC
G22 D33 PEG_RXN12
8 DMI_RXP0 DMI_TX[0] PEG_RX#[12]
D22 D31 PEG_RXN13
8 DMI_RXP1 DMI_TX[1] PEG_RX#[13]

PCI EXPRESS* - GRAPHICS

F20 B33 PEG_RXN14 H_PROCHOT# R152 56/J_4 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R427 140/F_4 Terminate DPLL_REF_SSCLK to GND and DPLL_REF_SSCLK# to
8 DMI_RXP2 DMI_TX[2] PEG_RX#[14] 31,36 H_PROCHOT# PROCHOT# SM_RCOMP[0]
C21 C32 PEG_RXN15 PEG_RXP[0..15] 16 A5 SM_RCOMP_1 R180 25.5/F_4 VCCP on Processor if motherboard only supports external
8 DMI_RXP3 DMI_TX[3] PEG_RX#[15] SM_RCOMP[1] SM_RCOMP_2 R181 graphics.
A4 200/F_4
PEG_RXP0 SM_RCOMP[2]
PEG_RX[0] J33
L35 PEG_RXP1 11 PM_THRMTRIP# AN32
PEG_RX[1] PEG_RXP2 THERMTRIP#
PEG_RX[2] K34 DG 1.0 : SM_RCOMP[1] value to 25.5
A21 H35 PEG_RXP3 (CS02552FB16)from 26 due to
8 FDI_TXN0 FDI0_TX#[0] PEG_RX[3] PEG_RXP4
8 FDI_TXN1 H19 FDI0_TX#[1] PEG_RX[4] H32 component selection issue
E19 G34 PEG_RXP5
8 FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_RXP6 AP29 XDP_PRDY# CRB 1.0 change R480 to 25.5/F
Intel(R) FDI

8 FDI_TXN3 FDI0_TX#[3] PEG_RX[6] PRDY# TP14

B21 F33 PEG_RXP7 AP27 XDP_PREQ#
8 FDI_TXN4 FDI1_TX#[0] PEG_RX[7] PREQ# TP20
C20 F30 PEG_RXP8
8 FDI_TXN5 FDI1_TX#[1] PEG_RX[8] PEG_RXP9 XDP_TCLK
8 FDI_TXN6 D18 FDI1_TX#[2] PEG_RX[9] E35 TCK
AR26 TP24

PWR MANAGEMENT
E17 E33 PEG_RXP10 AR27 XDP_TMS

JTAG & BPM

8 FDI_TXN7 FDI1_TX#[3] PEG_RX[10] TMS TP17
F32 PEG_RXP11 8 PM_SYNC R159 0/J_4 PM_SYNC_R AM34 AP30 XDP_TRST# TP3
PEG_RX[11] PEG_RXP12 PM_SYNC TRST#
PEG_RX[12] D34
A22 E31 PEG_RXP13 C692 *0.1U/10V_4 AR28 XDP_TDI_R TP6
8 FDI_TXP0 FDI0_TX[0] PEG_RX[13] PEG_RXP14 TDI XDP_TDO
8 FDI_TXP1 G19 C33 AP26 TP21
FDI0_TX[1] PEG_RX[14] PEG_RXP15 R132 0/J_4 H_PWRGOOD_R AP33 TDO
8 FDI_TXP2 E20 B32 PEG_TXN[0..15] 16 11 H_PWRGOOD
FDI0_TX[2] PEG_RX[15] UNCOREPWRGOOD
8 FDI_TXP3 G18 FDI0_TX[3]
B20 M29 PEG_TXN0_C C207 EV@0.1U/10V_4 PEG_TXN0 R154 10K/J_4
8 FDI_TXP4 FDI1_TX[0] PEG_TX#[0]
C C19 M32 PEG_TXN1_C C231 EV@0.1U/10V_4 PEG_TXN1 AL35 XDP_DBRST# XDP_DBRST# 8 C
8 FDI_TXP5 FDI1_TX[1] PEG_TX#[1] PEG_TXN2_C PEG_TXN2 PM_DRAM_PWRGD_Q_R DBR#
D19 M31 C206 EV@0.1U/10V_4 V8
8 FDI_TXP6 FDI1_TX[2] PEG_TX#[2] SM_DRAMPWROK
F17 L32 PEG_TXN3_C C229 EV@0.1U/10V_4 PEG_TXN3
8 FDI_TXP7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_TXN4_C C204 EV@0.1U/10V_4 PEG_TXN4 +1.05V_VTT R122 75/J_4 AT28 XDP_BPM0 TP16
FDI_FSYNC0 PEG_TX#[4] PEG_TXN5_C C227 EV@0.1U/10V_4 PEG_TXN5 R155 BPM#[0] XDP_BPM1
8 FDI_FSYNC0 J18 K31 AR29 TP19
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PEG_TXN6_C C201 EV@0.1U/10V_4 PEG_TXN6 74LVC1G07GW 43/J_4 BPM#[1] XDP_BPM2
8 FDI_FSYNC1 J17 K28 AR30 TP15
FDI1_FSYNC PEG_TX#[6] PEG_TXN7_C C225 EV@0.1U/10V_4 PEG_TXN7 CPU_PLTRST# BPM#[2] XDP_BPM3
PEG_TX#[7] J30 3
GND OUT 4 AR33 RESET# BPM#[3] AT30 TP13
FDI_INT H20 J28 PEG_TXN8_C C200 EV@0.1U/10V_4 PEG_TXN8 AP32 XDP_BPM4
8 FDI_INT FDI_INT PEG_TX#[8] +3V_S5 BPM#[4] TP11
H29 PEG_TXN9_C C223 EV@0.1U/10V_4 PEG_TXN9 2 C209 AR31 XDP_BPM5 TP10
FDI_LSYNC0 PEG_TX#[9] PEG_TXN10_C C198 EV@0.1U/10V_4 PEG_TXN10 IN 0.1U/10V_4 BPM#[5] XDP_BPM6
8 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#[10] G27 BPM#[6] AT31 TP7
FDI_LSYNC1 H17 E29 PEG_TXN11_C C221 EV@0.1U/10V_4 PEG_TXN11 1 5 AR32 XDP_BPM7 TP8
8 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] PEG_TXN12_C PEG_TXN12 NC VCC BPM#[7]
F27 C195 EV@0.1U/10V_4 R156
PEG_TX#[12] PEG_TXN13_C C219 EV@0.1U/10V_4 PEG_TXN13 U8 *750/F_4
D28
PEG_TX#[13] PEG_TXN14_C C194 EV@0.1U/10V_4 PEG_TXN14 R157 *1.5K/F_4 CPU_PLTRST#_R
F26
PEG_TX#[14] PEG_TXN15_C C217 EV@0.1U/10V_4 PEG_TXN15
PEG_TX#[15] E25 PEG_TXP[0..15] 16
A18 CPU-989P-rPGA
eDP_COMP eDP_COMPIO PEG_TXP0_C C208 EV@0.1U/10V_4 PEG_TXP0
A17 M28 PLTRST# 10,16,26,28,31,32
INT_eDP_HPD_Q eDP_ICOMPO PEG_TX[0] PEG_TXP1_C C230 EV@0.1U/10V_4 PEG_TXP1
B16 eDP_HPD PEG_TX[1] M33
M30 PEG_TXP2_C C205 EV@0.1U/10V_4 PEG_TXP2
PEG_TX[2] PEG_TXP3_C C228 EV@0.1U/10V_4 PEG_TXP3
PEG_TX[3] L31
C15 L28 PEG_TXP4_C C203 EV@0.1U/10V_4 PEG_TXP4
eDP_AUX PEG_TX[4] PEG_TXP5_C C226 EV@0.1U/10V_4 PEG_TXP5
D15 eDP_AUX# PEG_TX[5] K30
eDP

K27 PEG_TXP6_C C202 EV@0.1U/10V_4 PEG_TXP6

PEG_TX[6] PEG_TXP7_C C224 EV@0.1U/10V_4 PEG_TXP7
PEG_TX[7] J29
C17 J27 PEG_TXP8_C C199 EV@0.1U/10V_4 PEG_TXP8
eDP_TX[0] PEG_TX[8] PEG_TXP9_C C222 EV@0.1U/10V_4 PEG_TXP9 +3V_S5
F16 eDP_TX[1] PEG_TX[9] H28
C16 G28 PEG_TXP10_C C197 EV@0.1U/10V_4 PEG_TXP10
eDP_TX[2] PEG_TX[10] PEG_TXP11_C C220 EV@0.1U/10V_4 PEG_TXP11
G15 eDP_TX[3] PEG_TX[11] E28
F28 PEG_TXP12_C C196 EV@0.1U/10V_4 PEG_TXP12
PEG_TX[12] PEG_TXP13_C C218 EV@0.1U/10V_4 PEG_TXP13 +1.5V_CPU
C18 eDP_TX#[0] PEG_TX[13] D27
E16 E26 PEG_TXP14_C C193 EV@0.1U/10V_4 PEG_TXP14 C297
eDP_TX#[1] PEG_TX[14] PEG_TXP15_C C216 EV@0.1U/10V_4 PEG_TXP15 0.1U/10V_4
D16 D25
eDP_TX#[2] PEG_TX[15]
F15
eDP_TX#[3]
0.22uF AC coupling Caps for PCIE GEN1/2/3
R183

5
CPU-989P-rPGA U11 200/F_4
8,31 SYS_PWROK 2
4 PM_DRAM_PWRGD_Q R179 130/F_4 PM_DRAM_PWRGD_Q_R
B 8 PM_DRAM_PWRGD PM_DRAM_PWRGD_R 1 B

R182 TC7SH08

3
+1.05V_VTT 0/J_4 R177 R186 *39/J_4 3 1
*3K/F_4
3

Q7 *2N7002K

2
MAINON_ON_G 6,41
2 Q4
8,36 IMVP_PWRGD
FDV301N
1

R162
1K_4
2

Q3
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# 35

FDI Disabling (Discrete Only) DP & PEG Compensation eDP Hot-plug Processor pull-up(CPU)
+1.05V_VTT +1.05V_VTT
FDI_INT

R421 *EV@0/J_4 FDI_FSYNC0 +1.05V_VTT

R422 *EV@0/J_4 FDI_FSYNC1
R420 *EV@0/J_4 FDI_LSYNC0 CAD Note: Place PU resistor within 2 inches of CPU
FDI_LSYNC1 H_PROCHOT# R130 62/J_4
A eDP_COMP PEG_COMP XDP_TDO A
FDI_FSYNC can gang R173 24.9/F_4 R171 24.9/F_4 HPD disable R165 51/J_4
R418 +1.05V_VTT XDP_TMS R163 51/J_4
R419 all these 4 eDP_COMPIO and ICOMPO signals should PEG_ICOMPI and RCOMPO signals should XDP_TDI_R R160 51/J_4
*EV@1K/F_4 *EV@1K/F_4 signals together XDP_PREQ# R164 *51/J_4
be shorted near balls and routed with be routed within 500 mils XDP_TCLK R166 51/J_4
and tie them with typical impedance <25 mohms typical impedance = 43 mohms R172 XDP_TRST# R133 51/J_4
only one 1K 10K/J_4
resistor to GND PEG_ICOMPO signals should
(DG V0.5 Ch2.2.9). be routed within 500 mils INT_eDP_HPD_Q
typical impedance = 14.5 mohms Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
Sandy Bridge 1/4 1A

Date: Monday, September 27, 2010 Sheet 4 of 41

5 4 3 2 1
 5 4 3 2 1

Sandy Bridge Processor (DDR3)

U28C
05
U28D

14 M_A_DQ[63:0] SA_CLK[0] AB6 M_A_CLKP0 14

AA6 M_A_CLKN0 14 15 M_B_DQ[63:0] AE2 M_B_CLKP0 15
D M_A_DQ0 SA_CLK#[0] SB_CLK[0] D
C5 SA_DQ[0] SA_CKE[0] V9 M_A_CKE0 14 SB_CLK#[0] AD2 M_B_CLKN0 15
M_A_DQ1 D5 M_B_DQ0 C9 R9
SA_DQ[1] SB_DQ[0] SB_CKE[0] M_B_CKE0 15
M_A_DQ2 D3 M_B_DQ1 A7
M_A_DQ3 SA_DQ[2] M_B_DQ2 SB_DQ[1]
D2 D10
M_A_DQ4 SA_DQ[3] M_B_DQ3 SB_DQ[2]
D6 AA5 M_A_CLKP1 14 C8
M_A_DQ5 SA_DQ[4] SA_CLK[1] M_B_DQ4 SB_DQ[3]
C6 SA_DQ[5] SA_CLK#[1] AB5 M_A_CLKN1 14 A9 SB_DQ[4] SB_CLK[1] AE1 M_B_CLKP1 15
M_A_DQ6 C2 V10 M_B_DQ5 A8 AD1
SA_DQ[6] SA_CKE[1] M_A_CKE1 14 SB_DQ[5] SB_CLK#[1] M_B_CLKN1 15
M_A_DQ7 C3 M_B_DQ6 D9 R10
SA_DQ[7] SB_DQ[6] SB_CKE[1] M_B_CKE1 15
M_A_DQ8 F10 M_B_DQ7 D8
M_A_DQ9 SA_DQ[8] M_B_DQ8 SB_DQ[7]
F8 G4
M_A_DQ10 SA_DQ[9] M_B_DQ9 SB_DQ[8]
G10 SA_DQ[10] RSVD_TP[1] AB4 F4 SB_DQ[9]
M_A_DQ11 G9 AA4 M_B_DQ10 F1 AB2
M_A_DQ12 SA_DQ[11] RSVD_TP[2] M_B_DQ11 SB_DQ[10] RSVD_TP[11]
F9 W9 G1 AA2
M_A_DQ13 SA_DQ[12] RSVD_TP[3] M_B_DQ12 SB_DQ[11] RSVD_TP[12]
F7 G5 T9
M_A_DQ14 SA_DQ[13] M_B_DQ13 SB_DQ[12] RSVD_TP[13]
G8 SA_DQ[14] F5 SB_DQ[13]
M_A_DQ15 G7 M_B_DQ14 F2
M_A_DQ16 SA_DQ[15] M_B_DQ15 SB_DQ[14]
K4 SA_DQ[16] RSVD_TP[4] AB3 G2 SB_DQ[15]
M_A_DQ17 K5 AA3 M_B_DQ16 J7 AA1
M_A_DQ18 SA_DQ[17] RSVD_TP[5] M_B_DQ17 SB_DQ[16] RSVD_TP[14]
K1 W10 J8 AB1
M_A_DQ19 SA_DQ[18] RSVD_TP[6] M_B_DQ18 SB_DQ[17] RSVD_TP[15]
J1 SA_DQ[19] K10 SB_DQ[18] RSVD_TP[16] T10
M_A_DQ20 J5 M_B_DQ19 K9
M_A_DQ21 SA_DQ[20] M_B_DQ20 SB_DQ[19]
J4 J9
M_A_DQ22 SA_DQ[21] M_B_DQ21 SB_DQ[20]
J2 AK3 M_A_CS#0 14 J10
M_A_DQ23 SA_DQ[22] SA_CS#[0] M_B_DQ22 SB_DQ[21]
K2 SA_DQ[23] SA_CS#[1] AL3 M_A_CS#1 14 K8 SB_DQ[22] SB_CS#[0] AD3 M_B_CS#0 15
M_A_DQ24 M8 AG1 M_B_DQ23 K7 AE3
SA_DQ[24] RSVD_TP[7] SB_DQ[23] SB_CS#[1] M_B_CS#1 15
M_A_DQ25 N10 AH1 M_B_DQ24 M5 AD6
M_A_DQ26 SA_DQ[25] RSVD_TP[8] M_B_DQ25 SB_DQ[24] RSVD_TP[17]
N8 N4 AE6
M_A_DQ27 SA_DQ[26] M_B_DQ26 SB_DQ[25] RSVD_TP[18]
N7 N2
M_A_DQ28 SA_DQ[27] M_B_DQ27 SB_DQ[26]
M10 SA_DQ[28] N1 SB_DQ[27]
M_A_DQ29 M9 AH3 M_A_ODT0 14 M_B_DQ28 M4
M_A_DQ30 SA_DQ[29] SA_ODT[0] M_B_DQ29 SB_DQ[28]
N9 AG3 N5 AE4
DDR SYSTEM MEMORY A

SA_DQ[30] SA_ODT[1] M_A_ODT1 14 SB_DQ[29] SB_ODT[0] M_B_ODT0 15

DDR SYSTEM MEMORY B

M_A_DQ31 M7 AG2 M_B_DQ30 M2 AD4
C SA_DQ[31] RSVD_TP[9] SB_DQ[30] SB_ODT[1] M_B_ODT1 15 C
M_A_DQ32 AG6 AH2 M_B_DQ31 M1 AD5
M_A_DQ33 SA_DQ[32] RSVD_TP[10] M_B_DQ32 SB_DQ[31] RSVD_TP[19]
AG5 AM5 AE5
M_A_DQ34 SA_DQ[33] M_B_DQ33 SB_DQ[32] RSVD_TP[20]
AK6 AM6
M_A_DQ35 SA_DQ[34] M_B_DQ34 SB_DQ[33]
AK5 SA_DQ[35] M_A_DQSN[7:0] 14 AR3 SB_DQ[34]
M_A_DQ36 AH5 M_B_DQ35 AP3
M_A_DQ37 SA_DQ[36] M_A_DQSN0 M_B_DQ36 SB_DQ[35] M_B_DQSN[7:0] 15
AH6 SA_DQ[37] SA_DQS#[0] C4 AN3 SB_DQ[36]
M_A_DQ38 AJ5 G6 M_A_DQSN1 M_B_DQ37 AN2 D7 M_B_DQSN0
M_A_DQ39 SA_DQ[38] SA_DQS#[1] M_A_DQSN2 M_B_DQ38 SB_DQ[37] SB_DQS#[0] M_B_DQSN1
AJ6 SA_DQ[39] SA_DQS#[2] J3 AN1 SB_DQ[38] SB_DQS#[1] F3
M_A_DQ40 AJ8 M6 M_A_DQSN3 M_B_DQ39 AP2 K6 M_B_DQSN2
M_A_DQ41 SA_DQ[40] SA_DQS#[3] M_A_DQSN4 M_B_DQ40 SB_DQ[39] SB_DQS#[2] M_B_DQSN3
AK8 SA_DQ[41] SA_DQS#[4] AL6 AP5 SB_DQ[40] SB_DQS#[3] N3
M_A_DQ42 AJ9 AM8 M_A_DQSN5 M_B_DQ41 AN9 AN5 M_B_DQSN4
M_A_DQ43 SA_DQ[42] SA_DQS#[5] M_A_DQSN6 M_B_DQ42 SB_DQ[41] SB_DQS#[4] M_B_DQSN5
AK9 AR12 AT5 AP9
M_A_DQ44 SA_DQ[43] SA_DQS#[6] M_A_DQSN7 M_B_DQ43 SB_DQ[42] SB_DQS#[5] M_B_DQSN6
AH8 SA_DQ[44] SA_DQS#[7] AM15 AT6 SB_DQ[43] SB_DQS#[6] AK12
M_A_DQ45 AH9 M_B_DQ44 AP6 AP15 M_B_DQSN7
M_A_DQ46 SA_DQ[45] M_B_DQ45 SB_DQ[44] SB_DQS#[7]
AL9 SA_DQ[46] AN8 SB_DQ[45]
M_A_DQ47 AL8 M_B_DQ46 AR6
SA_DQ[47] M_A_DQSP[7:0] 14 SB_DQ[46]
M_A_DQ48 AP11 M_B_DQ47 AR5
SA_DQ[48] SB_DQ[47] M_B_DQSP[7:0] 15
M_A_DQ49 AN11 D4 M_A_DQSP0 M_B_DQ48 AR9
M_A_DQ50 SA_DQ[49] SA_DQS[0] M_A_DQSP1 M_B_DQ49 SB_DQ[48] M_B_DQSP0
AL12 F6 AJ11 C7
M_A_DQ51 SA_DQ[50] SA_DQS[1] M_A_DQSP2 M_B_DQ50 SB_DQ[49] SB_DQS[0] M_B_DQSP1
AM12 K3 AT8 G3
M_A_DQ52 SA_DQ[51] SA_DQS[2] M_A_DQSP3 M_B_DQ51 SB_DQ[50] SB_DQS[1] M_B_DQSP2
AM11 N6 AT9 J6
M_A_DQ53 SA_DQ[52] SA_DQS[3] M_A_DQSP4 M_B_DQ52 SB_DQ[51] SB_DQS[2] M_B_DQSP3
AL11 SA_DQ[53] SA_DQS[4] AL5 AH11 SB_DQ[52] SB_DQS[3] M3
M_A_DQ54 AP12 AM9 M_A_DQSP5 M_B_DQ53 AR8 AN6 M_B_DQSP4
M_A_DQ55 SA_DQ[54] SA_DQS[5] M_A_DQSP6 M_B_DQ54 SB_DQ[53] SB_DQS[4] M_B_DQSP5
AN12 SA_DQ[55] SA_DQS[6] AR11 AJ12 SB_DQ[54] SB_DQS[5] AP8
M_A_DQ56 AJ14 AM14 M_A_DQSP7 M_B_DQ55 AH12 AK11 M_B_DQSP6
M_A_DQ57 SA_DQ[56] SA_DQS[7] M_B_DQ56 SB_DQ[55] SB_DQS[6] M_B_DQSP7
AH14 SA_DQ[57] AT11 SB_DQ[56] SB_DQS[7] AP14
M_A_DQ58 AL15 M_B_DQ57 AN14
M_A_DQ59 SA_DQ[58] M_B_DQ58 SB_DQ[57]
AK15 M_A_A[15:0] 14 AR14
M_A_DQ60 SA_DQ[59] M_B_DQ59 SB_DQ[58]
AL14 SA_DQ[60] AT14 SB_DQ[59] M_B_A[15:0] 15
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ60 AT12
M_A_DQ62 SA_DQ[61] SA_MA[0] M_A_A1 M_B_DQ61 SB_DQ[60] M_B_A0
AJ15 SA_DQ[62] SA_MA[1] W1 AN15 SB_DQ[61] SB_MA[0] AA8
M_A_DQ63 AH15 W2 M_A_A2 M_B_DQ62 AR15 T7 M_B_A1
B SA_DQ[63] SA_MA[2] M_A_A3 M_B_DQ63 SB_DQ[62] SB_MA[1] M_B_A2 B
SA_MA[3] W7 AT15 SB_DQ[63] SB_MA[2] R7
V3 M_A_A4 T6 M_B_A3
SA_MA[4] M_A_A5 SB_MA[3] M_B_A4
SA_MA[5] V2 SB_MA[4] T2
W3 M_A_A6 T4 M_B_A5
SA_MA[6] M_A_A7 SB_MA[5] M_B_A6
14 M_A_BS#0 AE10 W6 T3
SA_BS[0] SA_MA[7] M_A_A8 SB_MA[6] M_B_A7
14 M_A_BS#1 AF10 SA_BS[1] SA_MA[8] V1 15 M_B_BS#0 AA9 SB_BS[0] SB_MA[7] R2
V6 W5 M_A_A9 AA7 T5 M_B_A8
14 M_A_BS#2 SA_BS[2] SA_MA[9] 15 M_B_BS#1 SB_BS[1] SB_MA[8]
AD8 M_A_A10 R6 R3 M_B_A9
SA_MA[10] 15 M_B_BS#2 SB_BS[2] SB_MA[9]
V4 M_A_A11 AB7 M_B_A10
SA_MA[11] M_A_A12 SB_MA[10] M_B_A11
SA_MA[12] W4 SB_MA[11] R1
14 AE8 AF8 M_A_A13 T1 M_B_A12
M_A_CAS# SA_CAS# SA_MA[13] SB_MA[12]
AD9 V5 M_A_A14 AA10 AB10 M_B_A13
14 M_A_RAS# SA_RAS# SA_MA[14] 15 M_B_CAS# SB_CAS# SB_MA[13]
AF9 V7 M_A_A15 AB8 R5 M_B_A14
14 M_A_WE# SA_WE# SA_MA[15] 15 M_B_RAS# SB_RAS# SB_MA[14]
AB9 R4 M_B_A15
15 M_B_WE# SB_WE# SB_MA[15]

CPU-989P-rPGA
CPU-989P-rPGA

+1.5V_SUS

02/25 Add 1K ohm

#PGU 0.71 440484 R298 R303 *0/J_4
1K/F_4
A A
R300 1K/F_4
14,15 DDR3_DRAMRST# 3 1 CPU_DRAMRST# 4
Q11
2N7002K
2

10 DRAMRST_CNTRL_PCH R312 0/J_4

R311 Quanta Computer Inc.

C427 4.99K/F_4
0.047U/10V_4
PROJECT : FH5
Size Document Number Rev
Sandy Bridge 2/4 1A

Date: Monday, September 27, 2010 Sheet 5 of 41

5 4 3 2 1
 5 4 3 2 1

22uF_8 x7 Socket TOP cavity

22uF_8 x5 Socket BOT cavity
22uF_8 x2 Socket TOP cavity (no stuff)
22uF_8 x5 Socket BOT cavity (no stuff)
330uF_7343 x2
SPI@ For Optimus & UMA
SPE@ For Pure Dis. 06
SP@ For special setting
Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER)
CPU VGT
+1.05V_VTT
SNB 45W:22A

SNB: 55A
+VCC_CORE

U28F POWER 470uF/4mohm x 2

U28G
POWER
D
TP4 D
22uF x 12
R150 R128 100/J_4 +VCC_GFX

SENSE
LINES
+ C634 + C635 0/J_4

SPI@330U/2V_7343

SPI@330U/2V_7343

*SPI@330U/2V_7343
+VCC_GFX AT24 AK35 VCC_AXG_SENSE 36
+ C247 + C620 + C616 *330U/2V_7343 330u/2V_7343 VAXG1 VAXG_SENSE 0/J_4
AT23 AK34 VSS_AXG_SENSE 36
470u/2V_7343 470u/2V_7343 470u/2V_7343 VAXG2 VSSAXG_SENSE R129 100/J_4
AT21
+ C288 + C300 + C307 VAXG3 R151
AT20
VAXG4
SNB: 8.5A AT18
VAXG5 TP5
AG35 AT17
VCC1 VAXG6
AG34 AH13 AR24
VCC2 VCCIO1 VAXG7
AG33 AH10 AR23
VCC3 VCCIO2 VAXG8
AG32 AG10 AR21
C265 C257 C256 VCC4 VCCIO3 C281 C619 VAXG9
AG31 AC10 AR20
VCC5 VCCIO4 VAXG10

VREF
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8

SPI@22U/6.3V_8

SPI@10U/6.3V_6

SPI@22U/6.3V_8

SPI@10U/6.3V_6
AG30 Y10 AR18
AG29
VCC6 VCCIO5
U10 AR17
VAXG11 10 mil
VCC7 VCCIO6 VAXG12 +VDDR_REF_CPU
AG28 P10 AP24 AL1 +VDDR_REF_CPU
VCC8 VCCIO7 VAXG13 SM_VREF
AG27 L10 AP23
VCC9 VCCIO8 VAXG14
AG26
VCC10 VCCIO9
J14 C260 C617 C254 C615 AP21
VAXG15
CAD Note: +VDDR_REF_CPU should
AF35 VCC11 VCCIO10 J13 AP20
VAXG16 have 10 mil trace width
AF34 J12 C629 C280 C563 AP18
C623 C612 C258 VCC12 VCCIO11 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VAXG17
AF33 J11 AP17
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AF32
VCC13 VCCIO12
H14 AN24
VAXG18 CPU MCH
VCC14 VCCIO13 VAXG19

SPI@22U/6.3V_8

SPI@22U/6.3V_8

SPI@22U/6.3V_8

SPI@22U/6.3V_8
AF31 VCC15 VCCIO14 H12 AN23
VAXG20 SNB 45W: 5A
AF30 VCC16 VCCIO15 H11 AN21
VAXG21
AF29
VCC17 VCCIO16
G14 AN20
VAXG22 330uF/6mohm x 1

DDR3 -1.5V RAILS

AF28 G13 C283 C277 C253 C278 AN18
VCC18 VCCIO17 VAXG23

PEG AND DDR

AF27 G12 C618 C628 C627 AN17 10uF x 6
VCC19 VCCIO18 VAXG24

GRAPHICS
AF26 F14 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 AM24 AF7 +1.5V_CPU
C263 C622 C250 VCC20 VCCIO19 VAXG25 VDDQ1
AD35 F13 AM23 AF4
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC21 VCCIO20 VAXG26 VDDQ2
AD34 VCC22 VCCIO21 F12 AM21
VAXG27 VDDQ3 AF1
AD33 F11 AM20 AC7 C292 C298 C293 C294
VCC23 VCCIO22 VAXG28 VDDQ4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
AD32 VCC24 VCCIO23 E14 AM18
VAXG29 VDDQ5 AC4

SPI@22U/6.3V_8

SPI@10U/6.3V_6

SPI@10U/6.3V_6

SPI@22U/6.3V_8
AD31 E12 AM17 AC1
VCC25 VCCIO24 C47 C27 C562 C261 C271 C259 C262 VAXG30 VDDQ6
AD30 VCC26
AL24
VAXG31 VDDQ7 Y7
AD29 E11 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 AL23 Y4
VCC27 VCCIO25 VAXG32 VDDQ8
AD28 D14 AL21 Y1
C272 C268 C613 VCC28 VCCIO26 VAXG33 VDDQ9
AD27 D13 AL20 U7
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC29 VCCIO27 VAXG34 VDDQ10 + C299
AD26 VCC30 VCCIO28 D12 AL18
VAXG35 VDDQ11 U4
AC35 D11 AL17 U1 C295 C306 *330U/2V_7343 C304 C305
VCC31 VCCIO29 VAXG36 VDDQ12 10U/6.3V_6 10U/6.3V_6 22U/6.3V_8 22U/6.3V_8
C AC34 VCC32 VCCIO30 C14 AK24
VAXG37 VDDQ13 P7 C
AC33 C13 C26 AK23 P4
VCC33 VCCIO31 22U/6.3VS_8 VAXG38 VDDQ14
AC32 VCC34 VCCIO32 C12 22uF (Reserved) AK21
VAXG39 VDDQ15 P1 22uF (Reserved)
AC31 VCC35 VCCIO33 C11 AK20
VAXG40
AC30 B14 AK18
C252 C274 C264 VCC36 VCCIO34 VAXG41

*SPI@10U/6.3V_6

*SPI@22U/6.3V_8

*SPI@22U/6.3V_8

*SPI@22U/6.3V_8
AC29 B12 AK17
22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 VCC37 VCCIO35 VAXG42
AC28 VCC38 VCCIO36 A14 AJ24
VAXG43
AC27 VCC39 VCCIO37 A13 AJ23
VAXG44
AC26 A12 C625 C626 C267 C275 C255 C284 AJ21
VCC40 VCCIO38 *22U/6.3VS_8 22U/6.3VS_8 VAXG45
AA35 VCC41 VCCIO39 A11 AJ20
VAXG46
AA34 VCC42
AJ18
VAXG47
AA33 VCC43 VCCIO40 J23 AJ17
VAXG48
AA32 AH24

SA RAIL
C582 C269 C273 VCC44 VAXG49
AA31 AH23
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC45 VAXG50
AA30 VCC46
AH21
VAXG51 VCCSA1 M27 VCCSA
AA29 C282 C286 C285 AH20 M26
VCC47 *22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VAXG52 VCCSA2 + C565
AA28 AH18 L26
AA27
VCC48 R174 ZĂ *SPE@0/J_4 AH17
VAXG53 VCCSA3
J26 C248 C249 C614 *330U/2V_7343
VCC49 VAXG54 VCCSA4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
AA26 VCC50 VCCSA5 J25
CORE SUPPLY

Y35 J24
Y34
VCC51 s hD VCCSA6
H26
CPU SA
C266 C585 C251 VCC52 VCCSA7
Y33 VCC53 +1.05V_VTT ZĂ ϬŽŚŵ E VCCSA8 H25 SNB 45W: 6A
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 Y32 VCC54

1.8V RAIL
Y31 VCC55 +1.05V_VTT_40
330uF/7mohm x 1
Y30 R416 *0_short
VCC56
Y29 VCC57 10uF x 3
Y28 VCC58
Y27 +1.8V B6 H23 R169 0/J_4 VCCSA_SENSE 40
VCC59 VCCPLL1 VCCSA_SENSE

MISC
Y26 A6
C583 C232 C624 V35
VCC60 CPU VCCPL A2
VCCPLL2
VCC61 VCCPLL3
SVID

*22U/6.3VS_8 *22U/6.3VS_8 22U/6.3VS_8 V34 AJ29 H_CPU_SVIDALRT# SNB 45W:3A + C654

VCC62 VIDALERT# H_CPU_SVIDCLK
V33 AJ30 C303 C301 C302 *330U/2V_7343 C22 H_FC_C22 R170 10K/J_4
VCC63 VIDSCLK H_CPU_SVIDDAT 10U/6.3V_6 1U/6.3V_4 1U/6.3V_4 FC_C22
V32
VCC64 VIDSOUT
AJ28 330uF/7mohm x 1 VCCSA_VID1
C24 VCCSA_SEL 40
V31
VCC65
V30
VCC66 10uF x 1
V29 VCC67
V28 1uF x 2 CPU-989P-rPGA
C233 C621 C234 VCC68
V27
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VCC69
B V26 B
VCC70
U35 VCC71
U34 VR_SVID_CLK
U33
VCC72 VR_SVID_DATA Layout note: need routing 4.5A
VCC73 VR_SVID_ALERT# SVID CLK JP5
U32
U31
VCC74 together and ALERT need +1.5V_SUS *SHORT PAD +1.5V_CPU
VCC75 +1.05V_VTT
C584 C581 C270
U30
U29
VCC76 between CLK and DATA 2 1
22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 VCC77
U28
U27
VCC78 C698 C699 C697 Close to VR
VCC79 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4
U26
VCC80 R127
R35 8 1
VCC81 54.9/F_4
R34 7 2
VCC82
22uF_8 x8 Socket TOP cavity R33
VCC83
6 3
R32 H_CPU_SVIDCLK R149 0/J_4 5
22uF_8 x10 Socket BOT cavity VCC84 VR_SVID_CLK 36
R31
22uF_8 x8 Socket TOP edge VCC85 Q5
R30

4
470uF_7343 x3 VCC86 MAIND AO4496
R29 VCC87
SENSE LINES

R28 R124 100/J_4 +VCC_CORE

VCC88 R146 0/J_4
3/26 DB change 10U FP to 0805. R27
VCC89 VCC_SENSE
AJ35 VCCSENSE 36 Place PU resistor close to CPU SVID DATA
R26 AJ34 R145 0/J_4 VSSSENSE 36 C296 R187
VCC90 VSS_SENSE R123 100/J_4 *470P/50V_4 220/J_8
P35
VCC91 +1.05V_VTT +1.05V_VTT
P34
VCC92
P33
VCC93

3
P32 B10 R409 0/J_4
P31
VCC94 VCCIO_SENSE
A10 R410 0/J_4
VCCP_SENSE 37 Close to VR
VCC95 VSSIO_SENSE VSSP_SENSE 37
P30 R119 R125
VCC96 130/F_4 130/F_4
P29 4,41 MAINON_ON_G 2
VCC97
P28 VCC98
P27 H_CPU_SVIDDAT R147 0/J_4 Q6
VCC99 VR_SVID_DATA 36
P26 DMN601K-7
VCC100 +SMDDR_VREF +VDDR_REF_CPU

1
R428 *0/J_8
Place PU resistor close to CPU SVID ALERT
+VDDR_REF_CPU
+1.05V_VTT
3 1
A A
CPU-989P-rPGA Q25
2N7002K
2

MAIND R429 R120

35,38,41 MAIND
100K/J_4 75/J_4

H_CPU_SVIDALRT# R148 43/J_4 R126 0/J_4 VR_SVID_ALERT# 36

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
Sandy Bridge 3/4 1A

Date: Monday, September 27, 2010 Sheet 6 of 41

5 4 3 2 1
 5 4 3 2 1

Sandy Bridge Processor (GND)

AT35
AT32
AT29
U28H

VSS1
VSS2
VSS3
VSS81
VSS82
VSS83
AJ22
AJ19
AJ16 T35
U28I

VSS161 VSS234 F22

Sandy Bridge Processor (RESERVED, CFG)
3/26 Remove XDP
U28E 07
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19 RSVD28 L7
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30 RSVD29 AG7
AT22 AJ7 T32 E27 CFG0 AK28 AE7
VSS6 VSS86 VSS164 VSS237 TP22 CFG[0] RSVD30
AT19 AJ4 T31 E24 CFG1 AK29 AK2
VSS7 VSS87 VSS165 VSS238 TP18 CFG[1] RSVD31
AT16 AJ3 T30 E21 CFG2 AL26 W8
VSS8 VSS88 VSS166 VSS239 CFG3 CFG[2] RSVD32
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18 TP23 AL27 CFG[3]
AT10 AJ1 T28 E15 CFG4 AK26
D VSS10 VSS90 VSS168 VSS241 CFG5 CFG[4] D
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13 AL29 CFG[5] RSVD33 AT26
AT4 AH34 T26 E10 CFG6 AL30 AM33
VSS12 VSS92 VSS170 VSS243 CFG7 CFG[6] RSVD34
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9 AM31 CFG[7] RSVD35 AJ27
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8 AM32 CFG[8]
AR22 VSS15 VSS95 AH29 P6 VSS173 VSS246 E7 AM30 CFG[9]
AR19 VSS16 VSS96 AH28 P5 VSS174 VSS247 E6 AM28 CFG[10]
AR16 VSS17 VSS97 AH26 P3 VSS175 VSS248 E5 AM26 CFG[11]
AR13 VSS18 VSS98 AH25 P2 VSS176 VSS249 E4 AN28 CFG[12]
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3 AN31 CFG[13] RSVD37 T8
AR7 VSS20 VSS100 AH19 N34 VSS178 VSS251 E2 AN26 CFG[14] RSVD38 J16
AR4 VSS21 VSS101 AH16 N33 VSS179 VSS252 E1 AM27 CFG[15] RSVD39 H16
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35 AK31 CFG[16] RSVD40 G16
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32 AN29 CFG[17]
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP28 VSS25 VSS105 AG8 N29 VSS183 VSS256 D26
AP25 VSS26 VSS106 AG4 N28 VSS184 VSS257 D20
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17 RSVD41 AR35
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34 AJ31 VAXG_VAL_SENSE RSVD42 AT34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31 AH31 VSSAXG_VAL_SENSE RSVD43 AT33
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28 AJ33 VCC_VAL_SENSE RSVD44 AP35
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27 AH33 VSS_VAL_SENSE RSVD45 AR34
AP7 VSS32 VSS112 AE34 L27 VSS190 VSS263 C25
AP4 VSS33 VSS113 AE33 L9 VSS191 VSS264 C23
AP1 VSS34 VSS114 AE32 L8 VSS192 VSS265 C10 AJ26 RSVD5

RESERVED
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
AN25 AE29 L4 B19 B34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
14 SMDDR_VREF_DQ0_M3
15 SMDDR_VREF_DQ1_M3
B4
D1
RSVD6
RSVD7
RSVD46
RSVD47
RSVD48
A33
A34
C AN16 VSS40 VSS120 AE26 L1 VSS198 VSS271 B13 RSVD49 B35 C
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11 RSVD50 C35
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9
AN7 AC9 K29 B8 R176 R178 F25
VSS43 VSS123 VSS201 VSS274 *1K/J_4 *1K/J_4 RSVD8
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7 F24 RSVD9
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5 F23 RSVD10
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3 D24 RSVD11 RSVD51 AJ32
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2 G25 RSVD12 RSVD52 AK32
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35 G24 RSVD13
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32 E23 RSVD14
AM13 VSS50 VSS130 AB34 H24 VSS208 VSS281 A29 D23 RSVD15
AM10 VSS51 VSS131 AB33 H21 VSS209 VSS282 A26 C30 RSVD16 VCC_DIE_SENSE AH27
AM7 VSS52 VSS132 AB32 H18 VSS210 VSS283 A23 A31 RSVD17
AM4 VSS53 VSS133 AB31 H15 VSS211 VSS284 A20 02/20 Add for Pre-ES1 B30 RSVD18
AM3 VSS54 VSS134 AB30 H13 VSS212 VSS285 A3 B29 RSVD19
AM2 VSS55 VSS135 AB29 H10 VSS213 D30 RSVD20 RSVD54 AN35
AM1 VSS56 VSS136 AB28 H9 VSS214 B31 RSVD21 RSVD55 AM35
AL34 VSS57 VSS137 AB27 H8 VSS215 A30 RSVD22
AL31 VSS58 VSS138 AB26 H7 VSS216 C29 RSVD23
AL28 VSS59 VSS139 Y9 H6 VSS217
AL25 VSS60 VSS140 Y8 H5 VSS218
AL22 VSS61 VSS141 Y6 H4 VSS219 J20 RSVD24
AL19 VSS62 VSS142 Y5 H3 VSS220 B18 RSVD25 RSVD56 AT2
AL16 VSS63 VSS143 Y3 H2 VSS221 TP25 A19 VCCIO_SEL RSVD57 AT1
AL13 VSS64 VSS144 Y2 H1 VSS222 RSVD58 AR1
AL10 VSS65 VSS145 W 35 G35 VSS223
AL7 VSS66 VSS146 W 34 G32 VSS224 J15 RSVD27
AL4 VSS67 VSS147 W 33 G29 VSS225
Voltage selection for VCCIO:
AL2 VSS68 VSS148 W 32 G26 VSS226 this pin must be pulled high
B
AK33 VSS69 VSS149 W 31 G23 VSS227 on the motherboard KEY B1 For rPGA socket, RSVD59 pin should be left NC B
AK30 VSS70 VSS150 W 30 G20 VSS228
AK27 VSS71 VSS151 W 29 G17 VSS229
AK25 VSS72 VSS152 W 28 G11 VSS230
On CRB
AK22 VSS73 VSS153 W 27 F34 VSS231 H_SNB_IVB#_PWRCTRL = low, 1.0V
AK19 VSS74 VSS154 W 26 F31 VSS232
AK16 U9 F29
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
VSS75 VSS155 VSS233 CPU-989P-rPGA
AK13 VSS76 VSS156 U8
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 VSS80 VSS160 U2

CPU-989P-rPGA CPU-989P-rPGA

Processor Strapping The CFG signals have a default value of '1' if not terminated on the board. CFG[6:5] (PCIE Port Bifurcation Straps)
CFG2 R168 1K/F_4 CFG5 R158 *1K/F_4 11: (Default) x16 - Device 1 functions 1 and 2 disabled
1 0 CFG6 R153 *1K/F_4 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG4 R167 *1K/F_4
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
CFG2 CFG7 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Normal Operation Lane Reversed R131 *1K/F_4
A (PEG Static Lane Reversal) A
CFG3
PEG Static x4 Lane Normal Operation Lane Reversed
CFG4
(DP Presence Strap) Disable; No physical DP attached to eDP Enable; An ext DP device is connected to eDP
CFG7 PEG train immediately following Quanta Computer Inc.
(PEG Defer Training) xxRESETB de assertion PEG wait for BIOS training
PROJECT : FH5
Size Document Number Rev
1A
Sandy Bridge 4/4
Date: Monday, September 27, 2010 Sheet 7 of 41
5 4 3 2 1
 5 4 3 2 1

Cougar Point (DMI,FDI,PM)

U30C
Cougar Point (LVDS,DDI)
U30D
08
4 DMI_RXN0 BC24 BJ14 FDI_TXN0 4 33 INT_LVDS_BLON J47 AP43
DMI0RXN FDI_RXN0 L_BKLTEN SDVO_TVCLKINN
4 DMI_RXN1 BE20 AY14 FDI_TXN1 4 33 INT_LVDS_VDDEN M45 AP45
DMI1RXN FDI_RXN1 L_VDD_EN SDVO_TVCLKINP
4 DMI_RXN2 BG18 BE14 FDI_TXN2 4
DMI2RXN FDI_RXN2
4 DMI_RXN3 BG20 BH13 FDI_TXN3 4 33 INT_LVDS_BRIGHT P45 AM42
DMI3RXN FDI_RXN3 L_BKLTCTL SDVO_STALLN
BC12 FDI_TXN4 4 AM40
FDI_RXN4 INT_EDIDCLK SDVO_STALLP
4 DMI_RXP0 BE24 BJ12 FDI_TXN5 4 33 INT_EDIDCLK T40
DMI0RXP FDI_RXN5 INT_EDIDDAT L_DDC_CLK
4 DMI_RXP1 BC20 BG10 FDI_TXN6 4 33 INT_EDIDDAT K47 AP39
DMI1RXP FDI_RXN6 L_DDC_DATA SDVO_INTN
D 4 DMI_RXP2 BJ18 BG9 FDI_TXN7 4 AP40 D
DMI2RXP FDI_RXN7 R263 2.2K/J_4 SDVO_INTP
4 DMI_RXP3 BJ20 +3V T45
DMI3RXP R262 2.2K/J_4 L_CTRL_CLK
BG14 FDI_TXP0 4 P39
FDI_RXP0 L_CTRL_DATA
4 DMI_TXN0 AW24 BB14 FDI_TXP1 4
DMI0TXN FDI_RXP1 R285 2.37K/F_4
4 DMI_TXN1 AW20 BF14 FDI_TXP2 4 AF37 P38 INT_HDMI_SCL 24
DMI1TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK
4 DMI_TXN2 BB18 BG13 FDI_TXP3 4 T16 AF36 M39 INT_HDMI_SDA 24
DMI2TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA
4 DMI_TXN3 AV18 BE12

DMI
FDI
DMI3TXN FDI_RXP4 FDI_TXP4 4
BG12 FDI_TXP5 4 AE48
FDI_RXP5 LVD_VREFH

INT. HDMI
4 DMI_TXP0 AY24 BJ10 FDI_TXP6 4 AE47 AT49
DMI0TXP FDI_RXP6 LVD_VREFL DDPB_AUXN
4 DMI_TXP1 AY20 BH9 FDI_TXP7 4 AT47
DMI1TXP FDI_RXP7 DDPB_AUXP INT_HDMI_HPD_Q
4 DMI_TXP2 AY18 AT40
DMI2TXP INT_TXLCLKOUTN DDPB_HPD
4 DMI_TXP3 AU18 33 INT_TXLCLKOUTN AK39

LVDS
DMI3TXP INT_TXLCLKOUTP LVDSA_CLK#
AW16 FDI_INT 4 33 INT_TXLCLKOUTP AK40 AV42 INT_HDMI_TXDN2 INT_HDMI_TXDN2 24
FDI_INT LVDSA_CLK DDPB_0N
AV40 INT_HDMI_TXDP2 INT_HDMI_TXDP2 24
INT_TXLOUTN0 DDPB_0P
BJ24 AV12 FDI_FSYNC0 4 33 INT_TXLOUTN0 AN48 AV45 INT_HDMI_TXDN1 INT_HDMI_TXDN1 24
DMI_ZCOMP FDI_FSYNC0 INT_TXLOUTN1 LVDSA_DATA#0 DDPB_1N
33 INT_TXLOUTN1 AM47 AV46 INT_HDMI_TXDP1 INT_HDMI_TXDP1 24

Digital Display Interface

49.9/F_4 DMI_COMP INT_TXLOUTN2 LVDSA_DATA#1 DDPB_1P
+1.05V_PCH R535 BG25 BC10 FDI_FSYNC1 4 33 INT_TXLOUTN2 AK47 AU48 INT_HDMI_TXDN0 INT_HDMI_TXDN0 24
DMI_IRCOMP FDI_FSYNC1 LVDSA_DATA#2 DDPB_2N
AJ48 AU47 INT_HDMI_TXDP0 INT_HDMI_TXDP0 24
LVDSA_DATA#3 DDPB_2P
R538 750/F_4 BH21 AV14 FDI_LSYNC0 4 AV47 INT_HDMI_TXCN INT_HDMI_TXCN 24
DMI2RBIAS FDI_LSYNC0 INT_TXLOUTP0 DDPB_3N
33 INT_TXLOUTP0 AN47 AV49 INT_HDMI_TXCP INT_HDMI_TXCP 24
INT_TXLOUTP1 LVDSA_DATA0 DDPB_3P
BB10 FDI_LSYNC1 4 33 INT_TXLOUTP1 AM49
FDI_LSYNC1 INT_TXLOUTP2 LVDSA_DATA1
33 INT_TXLOUTP2 AK49
LVDSA_DATA2
AJ47 P46
DSWVREN LVDSA_DATA3 DDPC_CTRLCLK
P42
DDPC_CTRLDATA
A18
DSWVRMEN R217 0/J_4 RSMRST# AF40
LVDSB_CLK#

System Power Management

AF39 AP47
SUS_PWR_ACK R207 *0/J_4 SUSACK#_R C12
SUSACK# DPWROK
E22 DPWROK R place close to PCH LVDSB_CLK DDPC_AUXN
DDPC_AUXP
AP49
AH45 AT38
LVDSB_DATA#0 DDPC_HPD
AH47
XDP_DBRST# PCIE_WAKE# R481 150/F_4 INT_CRT_BLU LVDSB_DATA#1
4 XDP_DBRST# K3 B9 PCIE_WAKE# 26,32 AF49 AY47
SYS_RESET# WAKE# LVDSB_DATA#2 DDPC_0N
AF45 AY49
R485 150/F_4 INT_CRT_GRE LVDSB_DATA#3 DDPC_0P
AY43
SYS_PWROK R205 0/J_4 SYS_PWROK_R P12 CLKRUN# DDPC_1N
SYS_PWROK +3V CLKRUN# / GPIO32
N3 CLKRUN# 31 AH43
LVDSB_DATA0 DDPC_1P
AY45
R201 *0/J_4 R490 150/F_4 INT_CRT_RED AH49 BA47
C LVDSB_DATA1 DDPC_2N C
AF47 BA48
EC_PWROK R202 0/J_4 EC_PWROK_R LVDSB_DATA2 DDPC_2P
31,33 EC_PWROK L22
PWROK +3V_S5 SUS_STAT# / GPIO61
G8 SUS_STAT# AF43
LVDSB_DATA3 DDPC_3N
BB47
BB49
DDPC_3P
R200 0/J_4 APWROK_R L10 +3V_S5 N14 PCH_SUSCLK 31
APWROK SUSCLK / GPIO62 INT_CRT_BLU
24 INT_CRT_BLU N48 M43
INT_CRT_GRE CRT_BLUE DDPD_CTRLCLK
24 INT_CRT_GRE P49 M36
PM_DRAM_PWRGD INT_CRT_RED CRT_GREEN DDPD_CTRLDATA
4 PM_DRAM_PWRGD B13
DRAMPWROK +3V_S5 SLP_S5# / GPIO63
D10 T15 24 INT_CRT_RED T49
CRT_RED
T14 AT45

CRT
RSMRST# DDPD_AUXN
31 RSMRST# C21 H4 SLP_S4# 31,32 24 INT_DDCCLK T39 AT43
RSMRST# SLP_S4# CRT_DDC_CLK DDPD_AUXP
24 INT_DDCDAT M40 BH41
CRT_DDC_DATA DDPD_HPD
T40
SUS_PWR_ACK K16 +3V_S5 F4 SLP_S3# 31,32 BB43
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# R473 33/F_4 INT_CRT_HSYNC_R DDPD_0N
24 INT_CRT_HSYNC M47 BB45
R478 33/F_4 INT_CRT_VSYNC_R CRT_HSYNC DDPD_0P
24 INT_CRT_VSYNC M49 BF44
R533 0/J_4 EC_PWRBTN#_R CRT_VSYNC DDPD_1N R316 0/J_4
31 EC_PWRBTN# E20 G10 T13 BE44
PWRBTN# SLP_A# DDPD_1P
BF42
DAC_IREF DDPD_2N
T11 SYNC RS T43
DAC_IREF DDPD_2P
BE42
AC_PRESENT H20 DSW G16 SLP_SUS# T12 33ohm for Direct Connect T42 BJ42
ACPRESENT / GPIO31 SLP_SUS# CRT_IRTN DDPD_3N +3V
20ohm for Dock Support BG42
R264 DDPD_3P
PM_BATLOW# 20ohm for Switchable Graphics Device Down Topology 1K/F_4 CougarPoint_R1P0
BATLOW# / GPIO72 +3V_S5
E10 AP14 PM_SYNC 4
PMSYNCH
10ohm for Switchable Graphics Dock Support
PM_RI# A10 +3V_S5 K14 SLP_LAN# R314
RI# SLP_LAN# / GPIO29 *1M/F_4

2
CougarPoint_R1P0
INT_HDMI_HPD_Q 1 3 INT_HDMI_HPD 24
Q12
*2N7002K
R290 R317
B *100K/J_4 *20K/J_4 B

PCH Pull-high/low(CLG) System PWR_OK(CLG)

+3V_S5
DPWROK FOR DSW (Deep Sx Well )
+3V +3V_S5 +3VPCU +3VPCU
+3V_RTC

CLKRUN# R484 8.2K/J_4 PM_RI# R450 10K/J_4

C291 PR175
XDP_DBRST# R476 10K/J_4 PM_BATLOW# R221 8.2K/J_4 *0.1U/10V_4 R197 *10K/J_4 PR176
330K/J_4 +3V_DSW *30.1K/J_4
R471 *1K/J_4 PCIE_WAKE# R449 10K/J_4
5

U10 +3VPCU R425 *0/J_4 DPWROK

RSMRST# R214 10K/J_4 SLP_LAN# R211 *10K/J_4 2 DSWVREN
IMVP_PWRGD 4,36

3
4,31 SYS_PWROK SYS_PWROK 4 PR174 *0/J_6
SYS_PWROK R196 10K/J_4 SUS_PWR_ACK R208 10K/J_4 1 EC_PWROK PC130
R455 *0.22U/6.3V_4
AC_PRESENT R216 10K/J_4 TC7SH08 *330K/J_4 2 PQ44
3

*2N7002K

3
R185 +3V_S5
100K/J_4 PD8
2

1
PM_DRAM_PWRGD R454 200/F_4
A A
*RB500V-40
DG 0.9 PU 200ohm to +3V_S5 DEEP S4/S5 well PQ43

1
On Die DSW VR Enable *DTC144EUA
DG 1.0 without DDR Power Gating add cap to timing tune
dno't PU to +3V_S5
High = Enable (Default)
Low = Disable
Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
Cougar Point 1/6
Date: Monday, September 27, 2010 Sheet 8 of 41
5 4 3 2 1
 5 4 3 2 1

PCH2(CLG)
RTC Circuitry(RTC)
20mils
+3V_DSW R557 *0/J_6 +3V_RTC C640
Change SIZE 8/24

15p/50V_4
Cougar Point (HDA,JTAG,SATA) 09
D16

1
R558 0/J_6
+3VPCU U30A
R560 20K/J_4 RTC_RST# Y3
+3V_RTC_1 32.768KHz R464
10M/J_4 RTC_X1 A20 C38 LAD0 28,31

4
BAT54C C684 RTCX1 FWH0 / LAD0
20MIL A38

LPC
FWH1 / LAD1 LAD1 28,31 +3V
1U/6.3V_4 C639 15p/50V_4 RTC_X2 C20 B37 LAD2 28,31
RTCX2 FWH2 / LAD2
30mils FWH3 / LAD3
C37 LAD3 28,31
RTC_RST# D20 SERIRQ R279 8.2K/J_4
R553 RTCRST#
D36 LFRAME# 28,31
1K/J_4 SRTC_RST# FWH4 / LFRAME# GPIO21 R266 *10K/J_4
G22
D
SRTC_RST# SRTCRST# D
R559 20K/J_4 E36 PCH_DRQ#0 TP28

RTC
SM_INTRUDER#K22 LDRQ0#
+3V_RTC R228 1M/J_4 +3V K36 PCH_DRQ#1 TP30
INTRUDER# LDRQ1# / GPIO23
20MIL
C683 C682 PCH_INVRMEN C17 V5 SERIRQ
1U/6.3V_4 1U/6.3V_4 Add MOSFET to separate CODEC SYNC signal INTVRMEN SERIRQ SERIRQ 31
CON9 +5V R446 10K/J_4
1 AM3 SATA_RXN0 25
1 SATA0RXN

2
2 ACZ_BITCLK_R N34 AM1
2 HDA_BCLK SATA0RXP SATA_RXP0 25

SATA 6G
AP7 SATA_TXN0_C C431 0.01U/25V_4
SATA_TXN0 25 SATA HDD
AAA-BAT-054-K01 ACZ_SYNC_R ACZ_SYNC_Q SATA0TXN
1 3 L34 AP5 SATA_TXP0_C C434 0.01U/25V_4
SATA_TXP0 25
bat-23_2-4_2 HDA_SYNC SATA0TXP
2N7002K Q26 SPKR T10 AM10
30 SPKR SPKR SATA1RXN
AM8
ACZ_RST#_R SATA1RXP
K34 AP11
HDA_RST# SATA1TXN
AP10
SATA1TXP

30 ACZ_SDIN0 E34 AD7

HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
G34 AH5
HDA_SDIN1 SATA2TXN
AH4
SATA2TXP
Flash Descriptor Security Override C34

IHDA
HDA_SDIN2
AB8 SATA_RXN3 25
SATA3RXN
A34 AB10 SATA_RXP3 25
HDA_SDIN3 SATA3RXP
AF3 SATA_TXN3_C C649 0.01U/25V_4
SATA_TXN3 25 SATA ODD
SATA3TXN
Low = Enabled AF1 SATA_TXP3_C C650 0.01U/25V_4
SATA_TXP3 25
ACZ_SDOUT_R SATA3TXP
GPIO33 High = Disabled A36

SATA
HDA_SDO
Y7
SATA4RXN
RESET JUMP (Near ROOM DOOR) (Internal 20K/F pull high to +3V) C36 +3V
SATA4RXP
Y5
AD3
TP47 HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
SATA4TXP
N32
HDA_DOCK_RST# / GPIO13 +3V_S5
3/26 Remove XDP Y3
RTC_RST# SATA5RXN
Note : GPIO33 is a signal used for Flash SATA5RXP
Y1
Descriptor Security Override/ME Debug AB3
SATA5TXN
2 CL1

PCH_JTAG_TCK_R J3 AB1
CL1_CL1 Mode.This signal should be only asserted JTAG_TCK SATA5TXP
*PAD lowthrough an external pull-down in PCH_JTAG_TMS_R H7 Y11

JTAG
JTAG_TMS SATAICOMPO
C manufacturing or debug environments C
PCH_JTAG_TDI_R SATA_COMP R283 37.4/F_4
B-01 ONLY. K5
JTAG_TDI SATAICOMPI
Y10 +1.05V_PCH
1 CL2

PCH_JTAG_TDO_R H1
TP52 JTAG_TDO
AB12
SRTC_RST# SATA3RCOMPO
AB13 SATA3_COMP R281 49.9/F_4
G1 SATA3COMPI

*SHORT_ PAD PCH_SPI_CLK T3 AH1 SATA3_RBIAS R512 750/F_4

SPI_CLK SATA3RBIAS
PCH_SPI_CS0# Y14 R491 10K +3V
SPI_CS0#
R492 *10K/J_4 PCH_SPI_CS1# T1

SPI
+3VPCU SPI_CS1#
P3 SATA_ACT# 29
SATALED#
PCH_SPI_SI V4 +3V V14 GPIO21
SPI_MOSI SATA0GP / GPIO21
PCH_SPI_SO U3 +3V P1 BBS_BIT0
SPI_MISO SATA1GP / GPIO19

HDA Bus(CLG) CougarPoint_R1P0

30 ACZ_BITCLK R230 33/J_4 ACZ_BITCLK_R

30 ACZ_SYNC R440 33/J_4 ACZ_SYNC_R

30 ACZ_RST# R247 33/J_4 ACZ_RST#_R

30 ACZ_SDOUT R457 33/J_4 ACZ_SDOUT_R

PCH Strap Table

PCH JTAG Debug (CLG)
Pin Name Strap description Sampled Configuration Default weak pull-up on GNT0/1#
B +3V_S5 Modify for B test. [Need external pull-down for LPC BIOS] B
No reboot mode setting 0 = Default (weak pull-down 20K) R508 *1K/J_4 SPKR
SPKR internal PD PWROK +3V
1 = Setting to No-Reboot mode
Top-Block Swap Override 0 = "top-block swap" mode
GNT3# / GPIO55 PWROK R237 *1K/J_4 GNT[3:0]# functionality is not available on Mobile.
internal PU PCI_GNT3# 10
R246 R242 1 = Default (weak pull-up 20K) Used as GPIO only.
210/F_4 210/F_4

PCH_JTAG_TMS_R INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +3V_RTC R195 330K/J_4 PCH_INVRMEN
PCH_JTAG_TDI_R
PCH_JTAG_TCK_R
Boot BIOS Selection 1 [bit-1]
GNT1# / GPIO51 PWROK +3V R465 1K/J_4
internal PU GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1#
R472 R251 R243 R475 1K/J_4
51/J_4 100/F_4 100/F_4 1 1 SPI * [Need external pull-down for LPC BIOS]
Boot BIOS Selection 0 [bit-0] R468 *1K/J_4
BBS_BIT1 10
GPIO19 PWROK 0 0 LPC
internal PU R489 *1K/J_4 BBS_BIT0

Flash Descriptor Security 0 = Default (weak pull-up 20K) R441 *1K/J_4 ACZ_SDOUT_R
HDA_SDO internal PD RSMRST +3V
R436 0_4
1 = Override 31 ME_WR#

DMI/FDI Termination voltage 0 = Set to Vss R522 2.2K/J_4 +1.8V R8361 change to 1K ohm follow DG1.0 and chklist 1.0
DF_TVS PWROK R523 1K/J_4 It needs to be connected to PROC_SELECT with a
PCH SPI ROM(CLG) internal PD 1 = Set to Vcc (weak pull-up 20K) DF_TVS 11
H_SNB_IVB# 4 1K±5% pull-up resistor to PCH VCCPNAND rail and a
+3V 4.7K±5% series resistor.
On-die PLL Voltage Regulator 0 = Disable
U13 GPIO28 RSMRST# R270 *1K/J_4
internal PU PLL_ODVR_EN 11
PCH_SPI_CS0# 1 8 1 = Enable (Default)
PCH_SPI_CLK R319 0_4 PCH_SPI1_CLK_R CE# VDD
6
PCH_SPI_SI R318 0_4 PCH_SPI1_SI_R SCK
PCH_SPI_SO R323 0_4 PCH_SPI1_SO_R
5
SI R322 3.3K_4
0 = Support by 1.8V (weak pull-down) R434 1K/J_4 ACZ_SYNC_Q
New Add in CPT EDS Rev1.0 at 0316
2
SO HOLD#
7 HDA_SYNC On-Die PLL VR Voltage Select RSMRST 1 = Support by 1.5V +3V_S5
internal PD , Needs to be pulled High for
3 4
C443 WP# VSS C442 Huron River platform.
A
*22P/50V_4 SPI Flash Socket 0.1U/10V_4
Need check schematic A

Intel ME Crypto Transport Layer 0 = Intel ME TLS with no confidentiality

GPIO15 Security (TLS) cipher suite RSMRST R241 1K_4
R320 3.3K_4
1 = Intel ME TLS with confidentiality +3V_S5 PCH_GPIO15 11
+3V internal PD

Vender Size P/N

EON 4MB AKE39FN0Q00 (EN25F32-100HIP)
Quanta Computer Inc.
Winbond 4MB AKE391P0N00 (W25Q32BVSSIG)
Socket DG008000031
PROJECT : FH5
Size Document Number Rev
1A
Cougar Point 2/6
Date: Monday, September 27, 2010 Sheet 9 of 41
5 4 3 2 1
 5 4 3 2 1

Cougar Point-M (PCI,USB,NVRAM)

Cougar Point-M (PCI-E,SMBUS,CLK)
U30B
10
28 PCIE_RXN1 BG34
U30E PERN1 SMBALERT#
28 PCIE_RXP1 BJ34
PERP1 +3V_S5 SMBALERT# / GPIO11
E12
AY7 WLAN 28 PCIE_TXN1 C430 0.1U/10V_4 PCIE_TXN1_C AV32
RSVD1 C429 0.1U/10V_4 PCIE_TXP1_C PETN1 SMB_PCH_CLK
AV7 28 PCIE_TXP1 AU32 H14
RSVD2 PETP1 SMBCLK
BG26 AU3
TP1 RSVD3 SMB_PCH_DAT
BJ26 BG4 28 PCIE_RXN2 BE34 C9
TP2 RSVD4 PERN2 SMBDATA
BH25 28 PCIE_RXP2 BF34
TP3 C438 0.1U/10V_4 PCIE_TXN2_C PERP2
BJ16
TP4 RSVD5
AT10 WWAN 28 PCIE_TXN2 BB32
PETN2
BG16 BC8 28 PCIE_TXP2 C437 0.1U/10V_4 PCIE_TXP2_C AY32

SMBUS
TP5 RSVD6 PETP2 DRAMRST_CNTRL_PCH
AH38
TP6 +3V_S5 SML0ALERT# / GPIO60
A12 DRAMRST_CNTRL_PCH 5
AH37 AU2 TP63 BG36
D TP7 RSVD7 PERN3 SMB_ME0_CLK D
AK43 AT4 TP64 BJ36 C8
TP8 RSVD8 PERP3 SML0CLK
AK45 AT3 TP41 AV34
TP9 RSVD9 PETN3 SMB_ME0_DAT
C18 AT1 TP40 AU34 G12
TP10 RSVD10 PETP3 SML0DATA
N30 AY3
TP11 RSVD11
H3 AT5 32 PCIE_RXN4 BF36
TP12 RSVD12 PERN4
AH12 AV3 32 PCIE_RXP4 BE36
TP13 RSVD13 C445 0.1U/10V_4 PCIE_TXN4_C PERP4 SML1ALERT#_R R451 *0_4
AM4
TP14 RSVD14
AV1 New Card 32 PCIE_TXN4 AY34
PETN4 +3V_S5 SML1ALERT# / PCHHOT# / GPIO74
C13 SML1ALERT# 11,31
AM5 BB1 32 PCIE_TXP4 C444 0.1U/10V_4 PCIE_TXP4_C BB34
TP15 RSVD15 PETP4 SMB_ME1_CLK
Y13 BA3 +3V_S5 E14

PCI-E*
TP16 RSVD16 SML1CLK / GPIO58
K24
L24
TP17 RSVD17
BB5
BB3
BG37
BH37
PERN5
+3V_S5 M16 SMB_ME1_DAT For EC
TP18 RSVD18 TP65 PERP5 SML1DATA / GPIO75
AB46 BB7 TP43 AY36
TP19 RSVD19 PETN5
AB45 BE8 BB36

RSVD
TP20 RSVD20 TP45 PETP5
BD4
RSVD21
BF6 26 PCIE_RXN6_LAN BJ38
RSVD22 PERN6
26 PCIE_RXP6_LAN BG38

Controller
NV_ALE C441 0.1U/10V_4 PCIE_TXN6_LAN_C PERP6
B21
TP21 RSVD23
AV5 TP37 GLAN 26 PCIE_TXN6_LAN AU36
PETN6 CL_CLK1
M7 CL_CLK1 28
M20 AV10 26 PCIE_TXP6_LAN C440 0.1U/10V_4 PCIE_TXP6_LAN_C AV36
TP22 RSVD24 PETP6
AY16

Link
TP23
BG46 AT8 BG40 T11 CL_DATA1 28
TP24 RSVD25 PERN7 CL_DATA1
BJ40
PERP7
AY5 TP44 AY40
RSVD26 PETN7
BA2 TP42 BB40 P10 CL_RST1# 28
RSVD27 PETP7 CL_RST1#
BE28
TP25
BC30 AT12 BE38
TP26 RSVD28 PERN8
BE32 BF3 BC38
TP27 RSVD29 PERP8
BJ32 TP38 AW38
TP28 PETN8
BC28 TP39 AY38
TP29 PETP8
BE30
TP30 PCIE_CLKREQ_PEG#
BF32
TP31 +3V_S5 PEG_A_CLKRQ# / GPIO47
M10 PCIE_CLKREQ_PEG# 16
BG32 C24 USBP0- 28 CLK_PCIE_WLANN CLK_PCIE_WLANN Y40
TP32 USBP0N USBP0- 27 CLKOUT_PCIE0N
AV26 A24 USBP0+ USB CNN (Charge) 28 CLK_PCIE_WLANP CLK_PCIE_WLANP Y39
TP33 USBP0P USBP0+ 27 CLKOUT_PCIE0P
BB26 C25 USBP1- WLAN AB37 CLK_PCIE_VGAN CLK_PCIE_VGAN 16
USBP1- 27

CLOCKS
TP34 USBP1N USBP1+ PCIE_CLKREQ_WLAN# CLKOUT_PEG_A_N
AU28 B25 USBP1+ 27 USB CNN 28 PCIE_CLKREQ_WLAN# J2 +3V_S5 AB38 CLK_PCIE_VGAP CLK_PCIE_VGAP 16
TP35 USBP1P USBP2- PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
AY30 C26 USBP2- 27
TP36 USBP2N USBP2+
AU26
TP37 USBP2P
A26 USBP2+ 27 USB CNN
AY26 K28 USBP3- 28 CLK_PCIE_WWANN CLK_PCIE_WWANN AB49 AV22 CLK_CPU_BCLKN 4
TP38 USBP3N USBP3- 28 CLKOUT_PCIE1N CLKOUT_DMI_N
AV28 H28 USBP3+ WLAN 28 CLK_PCIE_WWANP CLK_PCIE_WWANP AB47 AU22 CLK_CPU_BCLKP 4
TP39 USBP3P USBP3+ 28 CLKOUT_PCIE1P CLKOUT_DMI_P
AW30 E28 USBP4- EHCI1 WWAN
TP40 USBP4N USBP4- 28
C D28 USBP4+ WWAN 28 PCIE_CLKREQ_WWAN# PCIE_CLKREQ_WWAN# M1 +3V C
USBP4P USBP4+ 28 PCIECLKRQ1# / GPIO18
C28 USBP5- AM12 CLK_DPLL_SSCLKN 4
USBP5N USBP5- 23 CLKOUT_DP_N
A28 USBP5+ Card Reader AM13 CLK_DPLL_SSCLKP 4
USBP5P USBP5+ 23 CLKOUT_DP_P
C29 TP56 AA48
USBP6N CLKOUT_PCIE2N
B29 TP55 AA47
PCI_PIRQA# USBP6P CLKOUT_PCIE2P CLK_BUF_PCIE_3GPLLN
K40 N28 BF18
PCI_PIRQB# PIRQA# USBP7N PCIE_CLKREQ_USB3# CLKIN_DMI_N CLK_BUF_PCIE_3GPLLP
K38 M28 V10 +3V BE18
PCI

PCI_PIRQC# PIRQB# USBP7P USBP8- PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

H38 L30 USBP8- 32
PCI_PIRQD# PIRQC# USBP8N USBP8+
G38
PIRQD# USBP8P
K30 USBP8+ 32 New Card
G30 USBP9- 32 CLK_PCIE_NEWN CLK_PCIE_NEWN Y37 BJ30 CLK_BUF_BCLKN
USBP9N USBP9- 27 CLKOUT_PCIE3N CLKIN_GND1_N
DGPU_EDIDSEL# USBP9+ CLK_PCIE_NEWP CLK_BUF_BCLKP CLK_PCI_FB
REQ1# / GPIO50 +3V BlueTooth
C46 E30 Y36 BG30
USB

USBP9P USBP9+ 27 32 CLK_PCIE_NEWP CLKOUT_PCIE3P CLKIN_GND1_P

DGPU_SELECT# USBP6-
REQ2# / GPIO52 +3V New Card
C44 C30 USBP6- 33
GPIO54 USBP10N USBP6+ PCIE_CLKREQ_NEW#
REQ3# / GPIO54 +3V CCD on LVDS +3V_S5
E40 A30 USBP6+ 33 32 PCIE_CLKREQ_NEW# A8
USBP10P PCIECLKRQ3# / GPIO25 CLK_BUF_DREFCLKN
L32 G24
USBP11N CLKIN_DOT_96N CLK_BUF_DREFCLKP C353
GNT1# / GPIO51 +3V EHCI2
9 BBS_BIT1 D47 K32 E24
GPIO53 USBP11P CLKIN_DOT_96P
GNT2# / GPIO53 +3V
E42 G32 TP31 Y43 *10P/50V_4
USBP12N CLKOUT_PCIE4N
GNT3# / GPIO55 +3V
9 PCI_GNT3# F46 E32 TP34 Y45
USBP12P CLKOUT_PCIE4P CLK_BUF_DREFSSCLKN
C32 TP46 AK7
USBP13N PCIE_CLKREQ_REV1# CLKIN_SATA_N CLK_BUF_DREFSSCLKP
USBP13P
A32 TP49 L12
PCIECLKRQ4# / GPIO26 +3V_S5 CLKIN_SATA_P
AK5
MPC_PWR_CTRL#
PIRQE# / GPIO2 +3V
G42
GPIO03
PIRQF# / GPIO3 +3V
G40
EXTTS_SNI_DRV0_PCH USB_BIAS R456 22.6/F_4 CLK_PCIE_LANN CLK_PCH_14M
PIRQG# / GPIO4 +3V
C42 C33 26 CLK_PCIE_LANN V45 K45
EXTTS_SNI_DRV1_PCH USBRBIAS# CLK_PCIE_LANP CLKOUT_PCIE5N REFCLK14IN
PIRQH# / GPIO5 +3V
D44 26 CLK_PCIE_LANP V46
CLKOUT_PCIE5P
LAN
B33 26 PCIE_CLKREQ_LAN# PCIE_CLKREQ_LAN# L14 +3V_S5 H45 CLK_PCI_FB C648 18P/50V_4
TP29 PCI_PME# USBRBIAS PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
K10

2
PME#
PCI_PLTRST# C6 +3V_S5 A14 USB_OC0# USB_OC0# 27 AB42 V47 XTAL25_IN Y4
PLTRST# OC0# / GPIO59 TP32 CLKOUT_PEG_B_N XTAL25_IN
+3V_S5 K20 USB_OC1# AB40 V49 XTAL25_OUT R507 25MHz
OC1# / GPIO40 TP33 CLKOUT_PEG_B_P XTAL25_OUT
+3V_S5 B17 USB_OC2# 1M/J_4

1
OC2# / GPIO41 USB_OC3# GPIO56
H49
CLKOUT_PCI0 +3V_S5 OC3# / GPIO42
C16 E6
PEG_B_CLKRQ# / GPIO56+3V_S5
H43 +3V_S5 L16 USB_OC4# C647 18P/50V_4
CLK_PCI_FB R256 22/J_4 CLK_PCI_FB_R CLKOUT_PCI1 OC4# / GPIO43 USB_OC5#
J48 +3V_S5 A16 Y47 XCLK_RCOMP R511 90.9/F_4 +1.05V_PCH
R226 22/J_4 CLK_PCI_LPC_R CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# XCLK_RCOMP
28 CLK_PCI_LPC K42
CLKOUT_PCI3 +3V_S5 OC6# / GPIO10
D14 V40
CLKOUT_PCIE6N
31 CLK_PCI_EC R224 22/J_4 CLK_PCI_EC_R H40 +3V_S5 C14 USB_OC7# V42
CLKOUT_PCI4 OC7# / GPIO14 CLKOUT_PCIE6P
CLK_PCIE_REQ6# T13 +3V_S5
C316 C319 CougarPoint_R1P0 PCIECLKRQ6# / GPIO45
*10P/50V_4 *10P/50V_4 V38 +3V K43 CLK_FLEX0 R236 *22/J_4

FLEX CLOCKS
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_27M_VGA 18
V37
B CLKOUT_PCIE7P B
+3V F47 CLK_FLEX1 R238 22/J_4
CLK_48M_CARD 23
GPIO46 CLKOUTFLEX1 / GPIO65
K12
PCIECLKRQ7# / GPIO46 +3V_S5
+3V H47 CLK_FLEX2 R469 22/J_4
CLK_25M_LAN 26
CLKOUTFLEX2 / GPIO66
TP36 AK14
CLKOUT_ITPXDP_N
TP35 AK13
CLKOUT_ITPXDP_P +3V CLKOUTFLEX3 / GPIO67
K49
C641 C321 C326
*10P/50V_4 *10P/50V_4 *10P/50V_4
CougarPoint_R1P0

+3V CLK_REQ/Strap Pin(CLG) SMBus/Pull-up(CLG)

PCI_PIRQA# R432 8.2K/J_4
PCI/USBOC# Pull-up(CLG) PCI_PIRQB# R443 8.2K/J_4 +3V_S5
PCI_PIRQC# R437 8.2K/J_4 Check
PLTRST#(CLG) PCI_PIRQD# R442 8.2K/J_4 R477 10K/J_4 PCIE_CLKREQ_WLAN#
R445 10K/J_4 PCIE_CLKREQ_NEW#
R219 10K/J_4 PCIE_CLKREQ_REV1#
GPIO53 R444 *10K/J_4 R223 10K/J_4 PCIE_CLKREQ_LAN#
R267 10K/J_4 CLK_PCIE_REQ6# Q28
+3V_S5 2N7002K 2N7002K
+3V_S5 R240 10K/J_4 GPIO56 Q34
R426 R220 10K/J_4 GPIO46 SMB_ME1_CLK 1 3 MBCLK2 31 SMB_PCH_DAT 3 1 SMB_RUN_DAT 14,15,28
10 1 USB_OC6# +3V
USB_OC4# 9 2 USB_OC0# R439 +3V
C638 USB_OC1# 8 3 USB_OC7# 10 1 EXTTS_SNI_DRV0_PCH

2
0.1U/10V_4 USB_OC2# USB_OC5# MPC_PWR_CTRL# EXTTS_SNI_DRV1_PCH R479 10K/J_4 PCIE_CLKREQ_WWAN# 2.2K/J_4 4.7K/J_4
7 4 9 2
USB_OC3# 6 5 8 3 DGPU_EDIDSEL# R278 10K/J_4 PCIE_CLKREQ_USB3# R493 R550
5

GPIO03 7 4 DGPU_SELECT#
PCI_PLTRST# 2 10KX8 GPIO54 6 5 +3V_S5
4 PLTRST# PLTRST# 4,16,26,28,31,32 +3V_S5 +3V
1 10KX8 R261 10K/J_4 PCIE_CLKREQ_PEG#
R260 *10K/J_4
U29 R474 R544
3

TC7SH08FU R447 2.2K/J_4 4.7K/J_4

2
100K/J_4
A A
CLK_BUF_BCLKN R536 10K/J_4 SMB_ME1_DAT 1 3 MBDATA2 31 SMB_PCH_CLK 3 1 SMB_RUN_CLK 14,15,28
CLK_BUF_BCLKP R537 10K/J_4
Q33
Q27 2N7002K
CLK_BUF_PCIE_3GPLLN R310 10K/J_4 2N7002K
MPC Switch Control CLK_BUF_PCIE_3GPLLP R309 10K/J_4 +3V_S5
CLK_BUF_DREFCLKN R234 10K/J_4
Low = MPC ON CLK_BUF_DREFCLKP R235 10K/J_4 R453 1K/J_4 DRAMRST_CNTRL_PCH
MPC_PWR_CTRL# High = MPC OFF (Default) CLK_BUF_DREFSSCLKN R286 10K/J_4 R452 10K/J_4 SML1ALERT#_R
CLK_BUF_DREFSSCLKP R287 10K/J_4 R210 10K/J_4 SMBALERT#
CLK_PCH_14M R249 10K/J_4
MPC_PWR_CTRL# R184 *1K/J_4
C333 *10P/50V_4
R206
R218
2.2K/J_4 SMB_PCH_CLK
2.2K/J_4 SMB_PCH_DAT
Quanta Computer Inc.
R209 2.2K/J_4 SMB_ME0_CLK
R222 2.2K/J_4 SMB_ME0_DAT PROJECT : FH5
Size Document Number Rev
CLOCK TERMINATION for FCIM 1A
Cougar Point 3/6
Date: Monday, September 27, 2010 Sheet 10 of 41
5 4 3 2 1
 5 4 3 2 1

SGPIO

S_GPIO R509
R510
1K/J_4
*1K/J_4
+3V
S_GPIO

EC_EXT_SMI#
Cougar Point (GPIO,VSS_NCTF,RSVD)
T7
U30F

BMBUSY# / GPIO0 +3V +3V TACH4 / GPIO68 C40

B41 R461
BOARD_ID2

1.5K/F_4
11
31 EC_EXT_SMI# A42 TACH1 / GPIO1 +3V +3V TACH5 / GPIO69
BOARD_ID1 H36 +3V +3V C41 R462 1.5K/F_4 +3V
Muxed with STP_PCI# GPIO Pull-up/Pull-down(CLG)
TACH2 / GPIO6 TACH6 / GPIO70 If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3S.
31 EC_EXT_SCI# EC_EXT_SCI# E38 +3V +3V A40 R460 1.5K/F_4
TACH3 / GPIO7 TACH7 / GPIO71 +3V_S5
D ICC_EN# C10 +3V_S5 D
TP48 GPIO8 LAN_DISABLE# R229 10K/J_4
LAN_DISABLE# C4 +3V_S5 PLL_ODVR_EN R496 10K/J_4
TP27 LAN_PHY_PWR_CTRL / GPIO12 ICC_EN# R448 *10K/J_4
EC_A20GATE
9 PCH_GPIO15 G2 GPIO15 +3V_S5 A20GATE P4 EC_A20GATE 31
AU16 R294 *0_4 +3V
PECI EC_PECI 4,31
16 DGPU_HOLD_RST# U2 SATA4GP / GPIO16 +3V
EC_RCIN# EC_EXT_SMI# R463 10K/J_4
GPIO15 RCIN# P5 EC_RCIN# 31
EC_EXT_SCI# R433 10K/J_4

GPIO
Intel ME Crypto Transport Layer 16,31 GFXPG GFXPG D40 +3V AY11 H_PW RGOOD 4

CPU/MISC
TACH0 / GPIO17 PROCPWRGD STP_PCI# R480 10K/J_4
Security (TLS) cipher suite internal PD BIOS_REC T5 +3V AY10 PCH_THRMTRIP# R292 390/J_4 PM_THRMTRIP# 4 EC_A20GATE R259 10K/J_4
R239 1K/F_4 SCLOCK / GPIO22 THRMTRIP# EC_RCIN# R258 10K/J_4
+3V_S5
0 = Intel ME TLS with no confidentiality GFXPG R431 *10K/J_4
31 BIOS_W P# E8 GPIO24 / MEM_LED +3V_S5 INIT3_3V# T14
CRIT_TEMP_REP# R497 10K/J_4
1 = Intel ME TLS with confidentiality GPIO27 E16 DSW AY1 DF_TVS 9 dGPU_PW R_EN R280 10K/J_4
GPIO27 DF_TVS
9 PLL_ODVR_EN P8 GPIO28 +3V_S5
AH8 GPIO27 R225 10K/J_4
STP_PCI# TS_VSS1
K1 STP_PCI# / GPIO34 +3V
TS_VSS2 AK11
GPUCORE_ON 31,39,41 dGPU_VRON K4 GPIO35 +3V
TS_VSS3 AH10
GPU_PWR_ON dGPU_PW R_EN R274 EV@0_4 DMI_OVRVLTG V8 +3V Un-multiplexed. Can be configured as wake input to allow wakes from Deep Sleep.
41 dGPU_PW R_EN SATA2GP / GPIO36 If not used then use 8.2-kȍ to 10-kȍ pull-down to GND.
TS_VSS4 AK10
dGPU_PRSNT# R501 EV@0_4 FDI_OVRVLTG M5 +3V
SATA3GP / GPIO37
C MFG_MODE N2 +3V P37 C
SLOAD / GPIO38 NC_1
BOARD_ID0 M3 +3V
SDATAOUT0 / GPIO39
TEST_SET_UP V13 +3V BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15

10,31 SML1ALERT# R498 0_4 CRIT_TEMP_REP# V3 +3V BG48

SATA5GP / GPIO49 VSS_NCTF_16
SV_DET D6 GPIO57 +3V_S5 VSS_NCTF_17 BH3

VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

A45 VSS_NCTF_3 VSS_NCTF_21 BJ45

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 C48 +3V_S5

VSS_NCTF_8 VSS_NCTF_26
SV_SET_UP
BD1 D1 R231 *10K/J_4 SV_DET R233 100K/J_4
B VSS_NCTF_9 VSS_NCTF_27 B

BD49 D49 High = Strong (Default)

VSS_NCTF_10 VSS_NCTF_28
BE1 E1 +3V
VSS_NCTF_11 VSS_NCTF_29
BE49 VSS_NCTF_12 VSS_NCTF_30 E49
TEST_SET_UP R430 10K/J_4
BF1 F1 R435 *1K/J_4
VSS_NCTF_13 VSS_NCTF_31
[ID0:D1] 0:0 0:1 1:0 1:1
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
Fuction UMA Optimus Optimus Rev.
(Hynix) (Samsung)
CougarPoint_R1P0
Board ID2 reserve PD +3V

SATA[3:2]GP/GPIO[37:36] internal Pull-down 20K R250 *SP@10K/J_4 BOARD_ID0 R245 SP@10K/J_4

R190 SP@10K/J_4 BOARD_ID1 R189 *SP@10K/J_4
SATA2GP/GPIO36 (FDI_OVRVLTG) & SATA3GP/GPIO37 (DMI_OVRVLTG) MFG-TEST R458 SP@10K/J_4 BOARD_ID2 R459 *SP@10K/J_4
Sampled at Rising edge of PWROK.
Weak internal pull-down. (weak internal pull-down is disabled after PLTRST# de-asserts)
NOTE: This signal should NOT be pulled high when strap is sampled
EV UMA
+3V Stuff Ra Rb
+3V +3V +3V +3V
MFG_MODE R482 10K/J_4
R506 *100K/J_4 FDI_OVRVLTG R500 *1K/J_4 DMI_OVRVLTG R282 *200K/F_4 BIOS_REC R272 10K/J_4 R488 *1K/J_4 R504 DGPU_PRSNT# R505
A R271 *1K/J_4 SPE@10K/J_4 *SPI@100K/J_4 A

Ra Rb
Low = Tx, Rx terminated to
FDI TERMINATION LOW - Tx, Rx terminated DMI TERMINATION same voltage (DC Coupling Mode) High = Disable (Default)
VOLTAGE OVERRIDE to same voltage VOLTAGE OVERRIDE BIOS RECOVERY
(DEFAULT)
Low = Enable Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
Cougar Point 4/6
Date: Monday, September 27, 2010 Sheet 11 of 41
5 4 3 2 1
 5 4 3 2 1

12
PCH5(CLG)
COUGAR POINT (POWER)
+VCCA_DAC_1_2 +3V
VccADAC =1mA(8mils)
U30G POWER L26 180ohm/5A Cougar Point-M (POWER)
+1.05V_PCH +1.05V_PCH_VCC R524 *0/J_8 +1.05V_VCCUSBCORE +1.05V_PCH
+1.05V_PCH
VccCORE =1.3 A(60mils) R486 C646 C645 C643
D
R546 0.002/F_1206 AA23
VCCCORE[1] VCCADAC
U48 *0/J_6 0.01U/25V_4 0.1U/10V_4 10U/6.3V_6 U30J POWER R438 0/J_8
D

AC23
VCCCORE[2]

CRT
AD21 +VCCACLK AD49 N26
C368 C373 C381 C382 VCCCORE[3] +VCCALVDS +3V R499 0/J_4 VCCACLK VCCIO[29] C346
AD23 U47 +3V_S5
VCCCORE[4] VSSADAC

VCC CORE
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6 AF21 VccALVDS=1mA(8mils) VCCDSW3_3= 3mA P26 1U/6.3V_4 VCCSUS3_3 = 119mA(15mils)
VCCCORE[5] R529 SPI@0/J_4 R503 *0/J_4 +VCCPDSW VCCIO[30]
AF23 +3V_DSW T16
VCCCORE[6] VCCDSW3_3 +3V_S5
AG21
AG23
VCCCORE[7] R284 ZĂ *SPE@0/J_4 VCCIO[31]
P28
VCCCORE[8] C348 PCH_VCCDSW R487 0/J_6
AG24 AK36 V12 T27
+1.05V_PCH +1.05V_PCH_VCCDPLL_EXP VCCCORE[9] VCCALVDS 0.1U/10V_4 DCPSUSBYP VCCIO[32]
AG26
VCCCORE[10]
AG27 AK37 T29
R540 0/J_6 VCCCORE[11] VSSALVDS +VCC_TX_LVDS +1.8V C357 +3V_SUS_CLKF33 VCCIO[33] C334
AG29 T38
VCCCORE[12] +1.05V_PCH +VCCAPLL_CPY_PCH *0.1U/10V_4 VCC3_3[5] 0.1U/10V_4
AJ23 VccTX_LVDS=60mA(10mils)

LVDS
VCCCORE[13] L13 SPI@0.1uH_8 +3V_VCCPUSB
AJ26 AM37 T23
+1.05V_PCH +1.05V_VCCAPLL_EXP VCCCORE[14] VCCTX_LVDS[1] L31 *10uH/100mA_8 VCCSUS3_3[7]
AJ27
AJ29
VCCCORE[15]
AM38 R289 Zď *SPE@0/J_4
BH23
VCCAPLLDMI2
T24
L30 *1uH/25mA_6 VCCCORE[16] VCCTX_LVDS[2] C396 C428 R548 0/J_6 +VCCDPLL_CPY VCCSUS3_3[8] R204 0/J_6
AJ31 +1.05V_PCH AL29
VCCCORE[17] SPI@0.01U/25V_4 SPI@22U/6.3V_8 C672 VCCIO[14]
AP36 V23

USB
VCCTX_LVDS[3] C400 *10U/6.3V_6 VCCSUS3_3[9]
C665 AP37 SPI@0.01U/25V_4 +VCCSUS1 C335
*10U/6.3V_6 AN19
VCCTX_LVDS[4] s hD AL24
DCPSUS[3] VCCSUS3_3[10]
V24
0.1U/10V_4
VCCIO[28] +3V_VCCAUBG
ZĂ ϬŽŚŵ E VCCME(+1.05V) = ??A(??mils) C392 VCCSUS3_3[6]
P24

BJ22 +3V_VCC_GIO +3V *1U/6.3V_4

+1.05V_PCH +1.05V_VCCIO VCCAPLLEXP Zď ϬŽŚŵ E AA19
VCCASW[1]
T26 +VCCAUPLL R495 0/J_6 +1.05V_PCH
R483 0/J_6 +1.05V_PCH +1.05V_VCCEPW VCCIO[34]
VccIO =2.925 A(140mils) V33 AA21 VCC5REFSUS=1mA

HVCMOS
R321 0.002/F_1206 VCC3_3[6] VCCASW[2]
AN16
VCCIO[15] VccASW =1.01 A(60mils)
VCCDMI = 42mA(10mils) R530 0.002/F_1206 AA24 M26 +5V_PCH_VCC5REFSUS R193 10/F_4 +5V_S5
C361 VCCASW[3] V5REF_SUS
AN17
VCCIO[16]

Clock and Miscellaneous

C393 C401 C394 V34 0.1U/10V_4 +1.1V_VCC_DMI +1.05V_VTT AA26 D2 RB500V-40
VCC3_3[7] VCCASW[4] +3V_S5
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 C367 C356 C341 AN23 +VCCA_USBSUS C309
R291 0/J_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 DCPSUS[4] 0.1U/10V_4
AN21 AA27
VCCIO[17] VCCASW[5] +3V_VCCPSUS
AN24
VCCSUS3_3[1] C398
AN26 AA29
VCCIO[18] C399 VCCASW[6] *1U/6.3V_4
AN27 AT16 +VCCAFDI_VRM +VCCAFDI_VRM 1U/6.3V_4 AA31 V5REF= 1mA
VCCIO[19] VCCVRM[3] VCCASW[7]
C391 C395 AP21 AC26 P34 +5V_PCH_VCC5REF R467 10/F_4 +5V
1U/6.3V_4 10U/6.3V_6 VCCIO[20] C655 C656 VCCASW[8] V5REF
AP23 AT20 VCCCLKDMI = 20mA(8mils) 22U/6.3V_8 22U/6.3V_8 AC27 D15 RB500V-40 +3V
VCCIO[21] VCCDMI[1] VCCASW[9] C338
N20

DMI

PCI/GPIO/LPC
+1.1V_VCC_DMI_CCI +VCC_DMI_CCI +1.05V_PCH VCCSUS3_3[2] 1U/6.3V_4
AP24 AC29
VCCIO
VCCIO[22] VCCASW[10]
N22
C L28 R515 *1/F_4 VCCSUS3_3[3] C
AP26 AB36 AC31
VCCIO[23] VCCCLKDMI *10uH/100mA_8 VCCASW[11] +3V_VCCPSUS R203 0/J_6
P20 +3V_S5
R516 0/J_4 VCCSUS3_3[4]
AT24 AD29
+3V +3V_VCC_EXP VCCIO[24] C374 C366 VCCASW[12]
VCCSUS3_3[5]
P22 VCCSUS3_3 = 119mA(15mils)
1U/6.3V_4 *10U/6.3V_6 AD31 C336
R547 0/J_8 VCCASW[13] 1U/10V_4
AN33
VCCIO[25]
W21 AA16
VCCASW[14] VCC3_3[1]
AN34 AG16
C667 VCCIO[26] VCCDFTERM[1] +VCCP_NAND +1.8V +3V_VCCPCORE R525 0/J_6
VCCPNAND = 190 mA(15mils) W23
VCCASW[15] VCC3_3[8]
W16 +3V
0.1U/10V_4
BH29 AG17 R531 0/J_8 W24 T34 VCCPCORE = 28mA(10mils)
DFT / SPI

VCC3_3[3] VCCDFTERM[2] VCCASW[16] VCC3_3[4] +3V

C363
W26 0.1U/10V_4
C386 VCCASW[17] C347
AJ16
VCCDFTERM[3] 0.1U/10V_4 0.1U/10V_4
W29
+VCCAFDI_VRM VCCASW[18]
+VCCAFDI_VRM AP16
VCCVRM[2] +1.05V_PCH
AJ17 W31 AJ2 +3V
VCCDFTERM[4] VCCASW[19] VCC3_3[2]
+1.05V_PCH R313 *0/J_8 +1.05V_VCCAPLL_FDI BG6 R518 0/J_6 W33
VccAFDIPLL VCCASW[20] C388
AF13
+3V_VCCME_SPI +3V VCCIO[5] 0.1U/10V_4
VCCSPI = 20mA(8mils)
R539 0/J_8 +1.05V_VCCDPLL_FDI AP17 C652 C332 0.1U/10V_4 +VCCRTCEXT N16
VCCIO[27] DCPRTC
FDI

V1 R494 0/J_6 1U/6.3V_4 AH13 +V1.05S_SATA3 R528 0/J_8 +1.05V_PCH

VCCSPI VCCIO[12]

+1.05V_VTT AU20 +VCCAFDI_VRM +VCCAFDI_VRM Y49 AH14

VCCDMI[2] C644 R288 0/J_6 VCCVRM[4] VCCIO[13] C387
1U/6.3V_4 1U/10V_4
CougarPoint_R1P0 AF14
C379 +1.05V_VCCA_A_DPL VCCIO[6]
65mA(10mils) BD47 ??mA(??mils)

SATA
1U/6.3V_4 VCCADPLLA +V1.1LAN_VCCAPLL L27 *10uH/100mA_8
AK1 +1.05V_PCH
+1.05V_VCCA_B_DPL VCCAPLLSATA
8mA(8mils) BF47
VCCADPLLB
VCCVRM= 114mA(15mils)
C651
R542 0/J_6 AF11 +VCCAFDI_VRM *10U/6.3V_6
+VCCDIFFCLK VCCVRM[1]
AF17
+VCCDIFFCLKN VCCIO[7]
AF33
C668 VCCDIFFCLKN[1] R526 0/J_6
AF34 AC16 +1.05V_PCH
1U/6.3V_4 VCCDIFFCLKN[2] VCCIO[2]
VCCDIFFCLKN= 55mA(10mils) AG34
VCCDIFFCLKN[3]
+1.05V_PCH AC17
VCCIO[3] C372
VCCSSC= 95mA(10mils)
R520 *0/J_6 +V1.05V_SSCVCC AG33 AD17 1U/6.3V_4
+VCCAFDI_VRM VCCSSC VCCIO[4]

C344 C355 0.1U/10V_4 +VCCSST V16 +1.05V_VCCEPW VCCME = 1.01A(60mils)

B R517 0/J_6 +VCCAFDI_VRM *1U/6.3V_4 DCPSST B
+1.5V
VCCVRM: 1.8V (Destop) 02/20 del for Pre-ES1
+1.05V_PCH R514 *0/J_6 1.5V (Mobile) T17 T21
+1.05V_VTT +V1.05M_VCCSUS DCPSUS[1] VCCASW[22]
V19

MISC
DCPSUS[2]
1mA(8mils)
R315 0/J_4 +VTT_VCCPCPU V21
VCCASW[23]

CPU
BJ8
C664 C425 C426 V_PROC_IO
T19
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 VCCASW[21]
VCCRTC<1mA(8mils) +3V_RTC

+3V

RTC
A22 P32 +V3.3A_1.5A_HDA_IO R188 0/J_4 VCCSUSHDA= 10mA(8mils)

HDA
VCCRTC VCCSUSHDA +3V_S5

C317 C314 C315 CougarPoint_R1P0 C337 C339

1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 *1U/6.3V_4 0.1U/10V_4

C693 C694 C695 C696

*0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4

+1.05V_PCH L33 10uH/100mA +1.05V_VCCA_A_DPL

+ C670 C420
220U/2.5V_3528 1U/6.3V_4
+3V

R470 *0/J_6
L32 10uH/100mA +1.05V_VCCA_B_DPL
R466 1/F_4 L25 10uH/100mA_8 +3V_SUS_CLKF33

+ C669 C423
C642 C349 220U/2.5V_3528 1U/6.3V_4
10U/6.3V_6 1U/10V_4

A A

Quanta Computer Inc.

PROJECT :FH5
Size Document Number Rev
1A
Cougar Point 5/6
Date: Monday, September 27, 2010 Sheet 12 of 41
5 4 3 2 1
 5 4 3 2 1

PCH6(CLG)
13
U30I

AY4 H46
IBEX PEAK-M (GND) AY42
AY46
VSS[159]
VSS[160]
VSS[259]
VSS[260] K18
K26
VSS[161] VSS[261]
D AY8 VSS[162] VSS[262] K39 D
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
B27 VSS[167] VSS[267] L20
B31 VSS[168] VSS[268] L26
B35 VSS[169] VSS[269] L28
B39 VSS[170] VSS[270] L36
B7 VSS[171] VSS[271] L48
U30H F45 M12
VSS[172] VSS[272]
H5 VSS[0] BB12 VSS[173] VSS[273] P16
BB16 VSS[174] VSS[274] M18
AA17 VSS[1] VSS[80] AK38 BB20 VSS[175] VSS[275] M22
AA2 VSS[2] VSS[81] AK4 BB22 VSS[176] VSS[276] M24
AA3 VSS[3] VSS[82] AK42 BB24 VSS[177] VSS[277] M30
AA33 VSS[4] VSS[83] AK46 BB28 VSS[178] VSS[278] M32
AA34 VSS[5] VSS[84] AK8 BB30 VSS[179] VSS[279] M34
AB11 VSS[6] VSS[85] AL16 BB38 VSS[180] VSS[280] M38
AB14 VSS[7] VSS[86] AL17 BB4 VSS[181] VSS[281] M4
AB39 VSS[8] VSS[87] AL19 BB46 VSS[182] VSS[282] M42
AB4 VSS[9] VSS[88] AL2 BC14 VSS[183] VSS[283] M46
AB43 VSS[10] VSS[89] AL21 BC18 VSS[184] VSS[284] M8
AB5 VSS[11] VSS[90] AL23 BC2 VSS[185] VSS[285] N18
AB7 VSS[12] VSS[91] AL26 BC22 VSS[186] VSS[286] P30
AC19 VSS[13] VSS[92] AL27 BC26 VSS[187] VSS[287] N47
AC2 VSS[14] VSS[93] AL31 BC32 VSS[188] VSS[288] P11
AC21 VSS[15] VSS[94] AL33 BC34 VSS[189] VSS[289] P18
AC24 VSS[16] VSS[95] AL34 BC36 VSS[190] VSS[290] T33
AC33 VSS[17] VSS[96] AL48 BC40 VSS[191] VSS[291] P40
AC34 VSS[18] VSS[97] AM11 BC42 VSS[192] VSS[292] P43
AC48 VSS[19] VSS[98] AM14 BC48 VSS[193] VSS[293] P47
C C
AD10 VSS[20] VSS[99] AM36 BD46 VSS[194] VSS[294] P7
AD11 VSS[21] VSS[100] AM39 BD5 VSS[195] VSS[295] R2
AD12 VSS[22] VSS[101] AM43 BE22 VSS[196] VSS[296] R48
AD13 VSS[23] VSS[102] AM45 BE26 VSS[197] VSS[297] T12
AD19 VSS[24] VSS[103] AM46 BE40 VSS[198] VSS[298] T31
AD24 VSS[25] VSS[104] AM7 BF10 VSS[199] VSS[299] T37
AD26 VSS[26] VSS[105] AN2 BF12 VSS[200] VSS[300] T4
AD27 VSS[27] VSS[106] AN29 BF16 VSS[201] VSS[301] W34
AD33 VSS[28] VSS[107] AN3 BF20 VSS[202] VSS[302] T46
AD34 VSS[29] VSS[108] AN31 BF22 VSS[203] VSS[303] T47
AD36 VSS[30] VSS[109] AP12 BF24 VSS[204] VSS[304] T8
AD37 VSS[31] VSS[110] AP19 BF26 VSS[205] VSS[305] V11
AD38 VSS[32] VSS[111] AP28 BF28 VSS[206] VSS[306] V17
AD39 VSS[33] VSS[112] AP30 BD3 VSS[207] VSS[307] V26
AD4 VSS[34] VSS[113] AP32 BF30 VSS[208] VSS[308] V27
AD40 VSS[35] VSS[114] AP38 BF38 VSS[209] VSS[309] V29
AD42 VSS[36] VSS[115] AP4 BF40 VSS[210] VSS[310] V31
AD43 VSS[37] VSS[116] AP42 BF8 VSS[211] VSS[311] V36
AD45 VSS[38] VSS[117] AP46 BG17 VSS[212] VSS[312] V39
AD46 VSS[39] VSS[118] AP8 BG21 VSS[213] VSS[313] V43
AD8 VSS[40] VSS[119] AR2 BG33 VSS[214] VSS[314] V7
AE2 VSS[41] VSS[120] AR48 BG44 VSS[215] VSS[315] W17
AE3 VSS[42] VSS[121] AT11 BG8 VSS[216] VSS[316] W19
AF10 VSS[43] VSS[122] AT13 BH11 VSS[217] VSS[317] W2
AF12 VSS[44] VSS[123] AT18 BH15 VSS[218] VSS[318] W27
AD14 VSS[45] VSS[124] AT22 BH17 VSS[219] VSS[319] W48
AD16 VSS[46] VSS[125] AT26 BH19 VSS[220] VSS[320] Y12
AF16 VSS[47] VSS[126] AT28 H10 VSS[221] VSS[321] Y38
AF19 VSS[48] VSS[127] AT30 BH27 VSS[222] VSS[322] Y4
AF24 VSS[49] VSS[128] AT32 BH31 VSS[223] VSS[323] Y42
AF26 VSS[50] VSS[129] AT34 BH33 VSS[224] VSS[324] Y46
B AF27 AT39 BH35 Y8 B
VSS[51] VSS[130] VSS[225] VSS[325]
AF29 VSS[52] VSS[131] AT42 BH39 VSS[226] VSS[328] BG29
AF31 VSS[53] VSS[132] AT46 BH43 VSS[227] VSS[329] N24
AF38 VSS[54] VSS[133] AT7 BH7 VSS[228] VSS[330] AJ3
AF4 VSS[55] VSS[134] AU24 D3 VSS[229] VSS[331] AD47
AF42 VSS[56] VSS[135] AU30 D12 VSS[230] VSS[333] B43
AF46 VSS[57] VSS[136] AV16 D16 VSS[231] VSS[334] BE10
AF5 VSS[58] VSS[137] AV20 D18 VSS[232] VSS[335] BG41
AF7 VSS[59] VSS[138] AV24 D22 VSS[233] VSS[337] G14
AF8 VSS[60] VSS[139] AV30 D24 VSS[234] VSS[338] H16
AG19 VSS[61] VSS[140] AV38 D26 VSS[235] VSS[340] T36
AG2 VSS[62] VSS[141] AV4 D30 VSS[236] VSS[342] BG22
AG31 VSS[63] VSS[142] AV43 D32 VSS[237] VSS[343] BG24
AG48 VSS[64] VSS[143] AV8 D34 VSS[238] VSS[344] C22
AH11 VSS[65] VSS[144] AW14 D38 VSS[239] VSS[345] AP13
AH3 VSS[66] VSS[145] AW18 D42 VSS[240] VSS[346] M14
AH36 VSS[67] VSS[146] AW2 D8 VSS[241] VSS[347] AP3
AH39 VSS[68] VSS[147] AW22 E18 VSS[242] VSS[348] AP1
AH40 VSS[69] VSS[148] AW26 E26 VSS[243] VSS[349] BE16
AH42 VSS[70] VSS[149] AW28 G18 VSS[244] VSS[350] BC16
AH46 VSS[71] VSS[150] AW32 G20 VSS[245] VSS[351] BG28
AH7 VSS[72] VSS[151] AW34 G26 VSS[246] VSS[352] BJ28
AJ19 VSS[73] VSS[152] AW36 G28 VSS[247]
AJ21 VSS[74] VSS[153] AW40 G36 VSS[248]
AJ24 VSS[75] VSS[154] AW48 G48 VSS[249]
AJ33 VSS[76] VSS[155] AV11 H12 VSS[250]
AJ34 VSS[77] VSS[156] AY12 H18 VSS[251]
AK12 VSS[78] VSS[157] AY22 H22 VSS[252]
AK3 VSS[79] VSS[158] AY28 H24 VSS[253]
H26 VSS[254]
CougarPoint_R1P0 H30 VSS[255]
A H32 VSS[256] A
H34 VSS[257]
F3 VSS[258]

CougarPoint_R1P0

Quanta Computer Inc.

PROJECT :FH5
Size Document Number Rev
Cougar Point 6/6 1A

Date: Monday, September 27, 2010 Sheet 13 of 41

5 4 3 2 1
 5 4 3 2 1

DDR_STD(DDR)
5 M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
JDIM2A

A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ[63:0] 5

2.48A
+1.5V_SUS

75
76
JDIM2B

VDD1
VDD2
VSS16
VSS17
44
48
14
95 17 81 49
M_A_A4 A3 DQ3 M_A_DQ1 VDD3 VSS18
92 4 82 54
M_A_A5 A4 DQ4 M_A_DQ0 VDD4 VSS19
91 6 87 55
M_A_A6 A5 DQ5 M_A_DQ3 VDD5 VSS20
90 16 88 60
M_A_A7 A6 DQ6 M_A_DQ2 VDD6 VSS21
86 18 93 61
M_A_A8 A7 DQ7 M_A_DQ9 VDD7 VSS22
89 21 94 65
M_A_A9 A8 DQ8 M_A_DQ8 VDD8 VSS23
85 23 99 66
M_A_A10 A9 DQ9 M_A_DQ15 VDD9 VSS24
107 A10/AP DQ10 33 100 VDD10 VSS25
71
M_A_A11 84 35 M_A_DQ10 105 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26
D 83 22 106 127 D

PC2100 DDR3 SDRAM SO-DIMM

M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD12 VSS27
119 24 111 128
M_A_A14 A13 DQ13 M_A_DQ11 VDD13 VSS28
80 34 112 133
M_A_A15 A14 DQ14 M_A_DQ14 VDD14 VSS29
78 36 117 134
A15 DQ15 VDD15 VSS30

PC2100 DDR3 SDRAM SO-DIMM

39 M_A_DQ21 118 138
DQ16 M_A_DQ16 VDD16 VSS31
5 M_A_BS#0 109 41 123 139
BA0 DQ17 M_A_DQ19 VDD17 VSS32
5 M_A_BS#1 108 51 124 144
BA1 DQ18 M_A_DQ18 VDD18 VSS33
5 M_A_BS#2 79 53 145
BA2 DQ19 M_A_DQ20 VSS34
5 M_A_CS#0 114 40 +3V 199 150
S0# DQ20 M_A_DQ17 VDDSPD VSS35
5 M_A_CS#1 121 42 151
S1# DQ21 M_A_DQ22 VSS36
5 M_A_CLKP0 101 50 77 155
CK0 DQ22 M_A_DQ23 NC1 VSS37
5 M_A_CLKN0 103 CK0# DQ23 52 122
NC2 VSS38
156
102 57 M_A_DQ25 R273 *10K/J_4 125 161
5 M_A_CLKP1 CK1 DQ24 +3V NCTEST VSS39
104 59 M_A_DQ24 162
5 M_A_CLKN1 CK1# DQ25 VSS40
73 67 M_A_DQ30 198 167
5 M_A_CKE0 CKE0 DQ26 EVENT# VSS41
74 69 M_A_DQ26 5,15 DDR3_DRAMRST# DDR3_DRAMRST# 30 168
5 M_A_CKE1 CKE1 DQ27 RESET# VSS42
115 56 M_A_DQ28 172
5 M_A_CAS# CAS# DQ28 VSS43
110 58 M_A_DQ29 173
5 M_A_RAS# RAS# DQ29 VSS44
113 68 M_A_DQ31 SMDDR_VREF_DQ0_M1 R304 0/J_6 +SMDDR_VREF_DQ0 1 178
5 M_A_WE# WE# DQ30 VREF_DQ VSS45
R302 10K/J_4 DIMM0_SA0 197 70 M_A_DQ27 +SMDDR_VREF_DIMM 126 179
R297 10K/J_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 SMDDR_VREF_DQ0_M3 R305 *0/J_6 VREF_CA VSS46
201 SA1 DQ32
129 7 SMDDR_VREF_DQ0_M3 VSS47 184
10,15,28 SMB_RUN_CLK SMB_RUN_CLK 202 131 M_A_DQ37 185
SMB_RUN_DAT SCL DQ33 M_A_DQ34 VSS48
10,15,28 SMB_RUN_DAT 200 SDA DQ34
141 CAD Note: All VREF traces should 2 VSS1 VSS49 189
143 M_A_DQ38 3 190
116
DQ35
130 M_A_DQ32 have 10 mil trace width 8
VSS2 VSS50
195

(204P)
5 M_A_ODT0 ODT0 DQ36 VSS3 VSS51
120 132 M_A_DQ33 9 196
5 M_A_ODT1 ODT1 DQ37 VSS4 VSS52
140 M_A_DQ35 13
DQ38 M_A_DQ39 VSS5
11 DM0 DQ39
142 14 VSS6
28 147 M_A_DQ41 19
02/23 Remove 0ohm to GND 46
DM1 DQ40
149 M_A_DQ45 DDR3_DRAMRST# 20
VSS7
63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ47 25
VSS8
VSS9
136 159 M_A_DQ46 C691 26 203 +0.75V_DDR_VTT
DM4 DQ43 M_A_DQ40 VSS10 VTT1
153 DM5 DQ44 146 31 VSS11 VTT2 204
170 148 M_A_DQ44 0.1u/10V_4 32
DM6 DQ45 M_A_DQ42 VSS12
C 5 M_A_DQSP[7:0] 187 DM7 DQ46
158 37 VSS13 GND 205 C
160 M_A_DQ43 38 206
M_A_DQSP0 DQ47 M_A_DQ49 VSS14 GND
12 163 43
M_A_DQSP1 DQS0 DQ48 M_A_DQ48 VSS15
29 DQS1 DQ49 165
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ55 DDR3-DIMM0_H=5.2_RVS_LTS
64 DQS3 DQ51 177
M_A_DQSP4 137 164 M_A_DQ53
M_A_DQSP5 DQS4 DQ52 M_A_DQ52
154 166
M_A_DQSP6 DQS5 DQ53 M_A_DQ51
171 174
M_A_DQSP7 DQS6 DQ54 M_A_DQ50
188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ61
M_A_DQSN1 DQS#0 DQ56 M_A_DQ60
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ62
M_A_DQSN3 DQS#2 DQ58 M_A_DQ63
62 193
M_A_DQSN4 DQS#3 DQ59 M_A_DQ56
135 180
M_A_DQSN5 DQS#4 DQ60 M_A_DQ57
152 182
M_A_DQSN6 DQS#5 DQ61 M_A_DQ59
169 DQS#6 DQ62 192
M_A_DQSN7 186 194 M_A_DQ58
5 M_A_DQSN[7:0] DQS#7 DQ63

DDR3-DIMM0_H=5.2_RVS_LTS

Place these Caps near So-Dimm0. +SMDDR_VREF_DQ0

+1.5V_SUS C403 C407

C415 C413 C371 C377 C370 0.1u/10V_4 2.2U/6.3V_6

10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 1U/10V_4 1U/10V_4

C412 + C421
*330U/2V_7343 C411 C369
B 10U/6.3V_6 10U/6.3V_8 10U/6.3V_8 B

C414 C380 C416 C410 C418

10U/6.3V_6 10U/6.3V_6 *10U/6.3V_6 1U/10V_4 1U/10V_4

+SMDDR_VREF_DIMM

+3V +0.75V_DDR_VTT +SMDDR_VREF_DIMM

C397 C422

C383 C390 C404 C402 C330 C375 0.1u/10V_4 2.2U/6.3V_6

C406 C405 1U/6.3V_4 1U/6.3V_4 1u/6.3V_4 1U/6.3V_4
2.2U/6.3V_6 0.1u/10V_4 10U/6.3V_6 *10U/6.3V_6

+1.5V_SUS

R307
10K/J_4

+SMDDR_VREF R308 *0/J_6 +SMDDR_VREF_DIMM

R301 C409
VREF DQ0 M1 Solution +1.5V_SUS 10K/J_4 470P/50V_4
A A

R306
1K/F_4

+SMDDR_VREF R299 *0/J_6 SMDDR_VREF_DQ0_M1

R296
1K/F_4
Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
DDRIII SO-DIMM-0
Date: Monday, September 27, 2010 Sheet 14 of 41
5 4 3 2 1
 5 4 3 2 1

DDR_RVS(DDR)
5 M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
98
97
96
A0
A1
A2
JDIM1A

DQ0
DQ1
DQ2
5
7
15
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ[63:0] 5

+1.5V_SUS
JDIM1B
15
95 A3 DQ3 17 75 VDD1 VSS16 44
M_B_A4 92 4 M_B_DQ0 76 48
M_B_A5 A4 DQ4 M_B_DQ1 VDD2 VSS17
91 A5 DQ5 6 81 VDD3 VSS18 49
M_B_A6 90 16 M_B_DQ6 82 54
M_B_A7 A6 DQ6 M_B_DQ7 VDD4 VSS19
86 A7 DQ7 18 87 VDD5 VSS20 55
M_B_A8 89 21 M_B_DQ12 88 60
M_B_A9 A8 DQ8 M_B_DQ13 VDD6 VSS21
85 A9 DQ9 23 93 VDD7 VSS22 61
D M_B_A10 107 33 M_B_DQ14 94 65 D
M_B_A11 A10/AP DQ10 M_B_DQ10 VDD8 VSS23
84 35 2.48A 99 66
M_B_A12 A11 DQ11 M_B_DQ8 VDD9 VSS24
83 22 100 71
M_B_A13 A12/BC# DQ12 M_B_DQ9 VDD10 VSS25
119 A13 DQ13 24 105 VDD11 VSS26 72
M_B_A14 80 34 M_B_DQ11 106 127

PC2100 DDR3 SDRAM SO-DIMM

M_B_A15 A14 DQ14 M_B_DQ15 VDD12 VSS27
78 A15 DQ15 36 111 VDD13 VSS28 128

PC2100 DDR3 SDRAM SO-DIMM

39 M_B_DQ20 112 133
DQ16 M_B_DQ21 VDD14 VSS29
5 M_B_BS#0 109 41 117 134
BA0 DQ17 M_B_DQ18 VDD15 VSS30
5 M_B_BS#1 108 BA1 DQ18 51 118 VDD16 VSS31 138
79 53 M_B_DQ22 123 139
5 M_B_BS#2 BA2 DQ19 VDD17 VSS32
114 40 M_B_DQ17 124 144
5 M_B_CS#0 S0# DQ20 VDD18 VSS33
121 42 M_B_DQ16 145
5 M_B_CS#1 S1# DQ21 VSS34
101 50 M_B_DQ19 +3V 199 150
5 M_B_CLKP0 CK0 DQ22 VDDSPD VSS35
103 52 M_B_DQ23 151
5 M_B_CLKN0 CK0# DQ23 VSS36
102 57 M_B_DQ25 77 155
5 M_B_CLKP1 CK1 DQ24 NC1 VSS37
104 59 M_B_DQ29 122 156
5 M_B_CLKN1 CK1# DQ25 NC2 VSS38
73 67 M_B_DQ27 125 161
5 M_B_CKE0 CKE0 DQ26 NCTEST VSS39
74 69 M_B_DQ26 R254 *10K/J_4 162
5 M_B_CKE1 CKE1 DQ27 +3V VSS40
115 56 M_B_DQ28 198 167
5 M_B_CAS# CAS# DQ28 EVENT# VSS41
110 58 M_B_DQ24 5,14 DDR3_DRAMRST# 30 168
5 M_B_RAS# RAS# DQ29 RESET# VSS42
113 68 M_B_DQ31 172
5 M_B_W E# WE# DQ30 VSS43
R255 10K/J_4 DIMM1_SA0 197 70 M_B_DQ30 173
R265 10K/J_4 DIMM1_SA1 SA0 DQ31 M_B_DQ36 SMDDR_VREF_DQ1_M1 R268 0/J_6 +SMDDR_VREF_DQ1 VSS44
+3V 201 129 1 178
SMB_RUN_CLK SA1 DQ32 M_B_DQ37 VREF_DQ VSS45
10,14,28 SMB_RUN_CLK 202 SCL DQ33 131 +SMDDR_VREF_DIMM 126 VREF_CA VSS46 179
10,14,28 SMB_RUN_DAT SMB_RUN_DAT 200 141 M_B_DQ35 7 SMDDR_VREF_DQ1_M3 SMDDR_VREF_DQ1_M3 R257 *0/J_6 184
SDA DQ34 M_B_DQ34 VSS47
DQ35 143 VSS48 185
5 M_B_ODT0 116 130 M_B_DQ33 CAD Note: All VREF traces should 2 189
ODT0 DQ36 M_B_DQ32 VSS1 VSS49
5 M_B_ODT1 120 132 3 190
ODT1 DQ37
140 M_B_DQ39 have 10 mil trace width 8
VSS2 VSS50
195

(204P)
DQ38 M_B_DQ38 VSS3 VSS51
11 DM0 DQ39 142 9 VSS4 VSS52 196
28 147 M_B_DQ44 13
C DM1 DQ40 M_B_DQ40 VSS5 C
46 149 14
02/23 Remove 0ohm to GND

(204P)
DM2 DQ41 M_B_DQ42 VSS6
63 157 19
DM3 DQ42 M_B_DQ43 VSS7
136 DM4 DQ43 159 20 VSS8
153 146 M_B_DQ45 25
DM5 DQ44 M_B_DQ41 VSS9
170 DM6 DQ45 148 26 VSS10 VTT1 203 +0.75V_DDR_VTT
187 158 M_B_DQ46 31 204
5 M_B_DQSP[7:0] DM7 DQ46 VSS11 VTT2
160 M_B_DQ47 32
M_B_DQSP0 DQ47 M_B_DQ49 VSS12
12 163 37 205
M_B_DQSP1 DQS0 DQ48 M_B_DQ48 VSS13 GND
29 165 38 206
M_B_DQSP2 DQS1 DQ49 M_B_DQ54 VSS14 GND
47 175 43
M_B_DQSP3 DQS2 DQ50 M_B_DQ55 VSS15
64 177
M_B_DQSP4 DQS3 DQ51 M_B_DQ52
137 164
M_B_DQSP5 DQS4 DQ52 M_B_DQ53 DDR3-DIMM1_H=9.2_RVS_MLX
154 166
M_B_DQSP6 DQS5 DQ53 M_B_DQ51
171 174
M_B_DQSP7 DQS6 DQ54 M_B_DQ50
188 176
M_B_DQSN0 DQS7 DQ55 M_B_DQ61
10 181
M_B_DQSN1 DQS#0 DQ56 M_B_DQ60
27 183
M_B_DQSN2 DQS#1 DQ57 M_B_DQ62
45 191
M_B_DQSN3 DQS#2 DQ58 M_B_DQ63
62 193
M_B_DQSN4 DQS#3 DQ59 M_B_DQ57
135 180
M_B_DQSN5 DQS#4 DQ60 M_B_DQ56
152 182
M_B_DQSN6 DQS#5 DQ61 M_B_DQ59
169 192
M_B_DQSN7 DQS#6 DQ62 M_B_DQ58
5 M_B_DQSN[7:0] 186 194
DQS#7 DQ63

DDR3-DIMM1_H=9.2_RVS_MLX

B +1.5V_SUS Place these Caps near So-Dimm1. B

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C359 C364 C378 C352 C417
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 1U/10V_4 1U/10V_4

C358 C322 C350 C342 C340

C354 C331
10U/6.3V_6 10U/6.3V_8 10U/6.3V_8 0.1u/10V_4 2.2U/6.3V_6 0.1u/10V_4 2.2U/6.3V_6

C362 C389 C384 C345 C324

10U/6.3V_6 10U/6.3V_6 *10U/6.3V_6 1U/10V_4 1U/10V_4

+3V +0.75V_DDR_VTT

C328 C351 C360 C325 C376 C385

C365 C343 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2.2U/6.3V_6 0.1u/10V_4 10U/6.3V_6 *10U/6.3V_6

VREF DQ1 M1 Solution STD 4H STD 8H

+1.5V_SUS

A FOX A

R276
1K/F_4 LTK DGMK4000004 DGMK4000097

R277 *0/J_6 SMDDR_VREF_DQ1_M1 SUY

+SMDDR_VREF

R275
Quanta Computer Inc.
MLX DGMK4000011 DGMK4000080
1K/F_4
PROJECT : FH5
Standard 8H type:DDR-C-2013310-204p-1 Size Document Number Rev
1A
DDRIII SO-DIMM-1
Date: Monday, September 27, 2010 Sheet 15 of 41
5 4 3 2 1
 1 2 3 4 5 6 7 8

PEX_IOVDD+PEX_IOVDDQ+PEX_PLLVDD >2.2A
16
2000mA U23A
+1.05V_GPU fcbga973-nvidia-n12p-ge
COMMON
A A
C97 *EV@0.1U/10V_4 AK16 AP17 PEG_TXP15 4
C73 EV@0.1U/10V_4 PEX_IOVDD_1 PEX_RX0
PLACE NEAR BALLS AK17 PEX_IOVDD_2 PEX_RX0* AN17 PEG_TXN15 4
C114 EV@0.1U/10V_4 AK21 AN19
C122 EV@1U/6.3V_4 AK24
PEX_IOVDD_3 PEX_RX1
AP19
PEG_TXP14 4
PEG_TXN14 4
GPU RST# +3V
C28 EV@1U/6.3V_4 PEX_IOVDD_4 PEX_RX1*
AK27 PEX_IOVDD_5 PEX_RX2 AR19 PEG_TXP13 4
PLACE NEAR BGA C24 EV@4.7U/6.3V_6 AR20 PEG_TXN13 4
C516 EV@10U/6.3V_8 PEX_RX2*
PEX_RX3 AP20 PEG_TXP12 4
C17 EV@22U/6.3V_8 AN20 PEG_TXN12 4
PEX_RX3* C59
PEX_RX4 AN22 PEG_TXP11 4
AP22 PEG_TXN11 4 EV@0.1U/10V_4
PEX_RX4*
+1.05V_GPU AG11 PEX_IOVDDQ_1 PEX_RX5 AR22 PEG_TXP10 4

5
AG12 PEX_IOVDDQ_2 PEX_RX5* AR23 PEG_TXN10 4
C84 *EV@0.1U/10V_4 AG13 AP23 PEG_TXP9 4 2
PEX_IOVDDQ_3 PEX_RX6 4,10,26,28,31,32 PLTRST#
PLACE NEAR BALLS C23 EV@0.1U/10V_4 AG15 AN23 PEG_TXN9 4 4 GPU_RST#
C125 EV@0.1U/10V_4 PEX_IOVDDQ_4 PEX_RX6*
AG16 PEX_IOVDDQ_5 PEX_RX7 AN25 PEG_TXP8 4 11 DGPU_HOLD_RST# 1
C131 EV@1U/6.3V_4 AG17 AP25 PEG_TXN8 4
C134 EV@1U/6.3V_4 PEX_IOVDDQ_6 PEX_RX7* U3
AG18 AR25 PEG_TXP7 4

3
C71 EV@4.7U/6.3V_6 PEX_IOVDDQ_7 PEX_RX8 EV@TC7SH08FU
PLACE NEAR BGA AG22 PEX_IOVDDQ_8 PEX_RX8* AR26 PEG_TXN7 4
C18 EV@10U/6.3V_8 AG23 AP26 PEG_TXP6 4 R55
C517 EV@22U/6.3V_8 PEX_IOVDDQ_9 PEX_RX9 EV@100K/J_4
AG24 PEX_IOVDDQ_10 PEX_RX9* AN26 PEG_TXN6 4
AG25 PEX_IOVDDQ_11 PEX_RX10 AN28 PEG_TXP5 4
AG26 PEX_IOVDDQ_12 PEX_RX10* AP28 PEG_TXN5 4
AJ14 PEX_IOVDDQ_13 PEX_RX11 AR28 PEG_TXP4 4
AJ15 PEX_IOVDDQ_14 PEX_RX11* AR29 PEG_TXN4 4
AJ19 PEX_IOVDDQ_15 PEX_RX12 AP29 PEG_TXP3 4
AJ21 PEX_IOVDDQ_16 PEX_RX12* AN29 PEG_TXN3 4
AJ22 PEX_IOVDDQ_17 PEX_RX13 AN31 PEG_TXP2 4
AJ24 PEX_IOVDDQ_18 PEX_RX13* AP31 PEG_TXN2 4
AJ25 AR31 +3V +3V_GPU
B AJ27
PEX_IOVDDQ_19 PEX_RX14
AR32
PEG_TXP1 4
PEG_TXN1 4
GPU all PWROK B
PEX_IOVDDQ_20 PEX_RX14*
AK18 PEX_IOVDDQ_21 PEX_RX15 AR34 PEG_TXP0 4
AK20 PEX_IOVDDQ_22 PEX_RX15* AP34 PEG_TXN0 4
AK23 R396
PEX_IOVDDQ_23 EV@10K_4
AK26 PEX_IOVDDQ_24
120mA AL16 AL17 PEG_RXP15_C C80 EV@0.1U/10V_4 PEG_RXP15 4
PEX_IOVDDQ_25 PEX_TX0 PEG_RXN15_C C89 EV@0.1U/10V_4 R397
+3V_GPU PEX_TX0* AM17 PEG_RXN15 4
PEG_RXP14_C C109 EV@0.1U/10V_4 EV@10K_4 GFXPG
PLACE NEAR BGA C95 EV@4.7U/6.3V_6 PCI EXPRESS PEX_TX1 AM18
AM19 PEG_RXN14_C C102 EV@0.1U/10V_4
PEG_RXP14 4
PEG_RXN14 4
GFXPG 11,31
PEX_TX1*

3
C81 EV@1U/6.3V_4 J10 AL19 PEG_RXP13_C C113 EV@0.1U/10V_4 PEG_RXP13 4
C79 EV@0.1U/10V_4 VDD33_1 PEX_TX2 PEG_RXN13_C C108 EV@0.1U/10V_4 Q24
J11 VDD33_2 PEX_TX2* AK19 PEG_RXN13 4 2
PLACE NEAR BALLS C76 EV@0.1U/10V_4 J12 AL20 PEG_RXP12_C C106 EV@0.1U/10V_4 PEG_RXP12 4 EV@MMBT3904
C98 EV@0.1U/10V_4 VDD33_3 PEX_TX3 PEG_RXN12_C C112 EV@0.1U/10V_4
J13 AM20 PEG_RXN12 4

1
VDD33_4 PEX_TX3* PEG_RXP11_C C120 EV@0.1U/10V_4
J9 VDD33_5 PEX_TX4 AM21 PEG_RXP11 4
AM22 PEG_RXN11_C C123 EV@0.1U/10V_4 PEG_RXN11 4
PEX_TX4* PEG_RXP10_C C124 EV@0.1U/10V_4
AD20 VDD_SENSE PEX_TX5 AL22 PEG_RXP10 4
39 VGPU_VCC_SENSE D35 AK22 PEG_RXN10_C C127 EV@0.1U/10V_4 PEG_RXN10 4
NC_9/ VDD_SENSE PEX_TX5* PEG_RXP9_C C129 EV@0.1U/10V_4
P7 NC_16/ VDD_SENSE PEX_TX6 AL23 PEG_RXP9 4
AM23 PEG_RXN9_C C137 EV@0.1U/10V_4 PEG_RXN9 4
39 VGPU_VSS_SENSE PEX_TX6*

3
AM24 PEG_RXP8_C C128 EV@0.1U/10V_4 PEG_RXP8 4
PEX_TX7 PEG_RXN8_C C136 EV@0.1U/10V_4
120mAL9 120-ohm / ESR=0.18
EV@BLM18AG121SN1D
AD19 GND_SENSE PEX_TX7* AM25
PEG_RXP7_C C130 EV@0.1U/10V_4
PEG_RXN8 4
R386 EV@10K_4 Q23
+1.05V_GPU E35 NC_10/ GND_SENSE PEX_TX8 AL25 PEG_RXP7 4 +1.5V_GPU 2
R7 AK25 PEG_RXN7_C C138 EV@0.1U/10V_4 PEG_RXN7 4 EV@PDTC143TT
C61 EV@4.7U/6.3V/X7R_6 NC_17/ GND_SENSE PEX_TX8* PEG_RXP6_C C143 EV@0.1U/10V_4
PEX_TX9 AL26 PEG_RXP6 4
PLACE NEAR BGA C68 EV@1U/6.3V/X7R_4 AM26 PEG_RXN6_C C145 EV@0.1U/10V_4 PEG_RXN6 4 *EV@1000P/50V/X7R_4@NC C515

1
PEX_TX9* PEG_RXP5_C C144 EV@0.1U/10V_4
PEX_TX10 AM27 PEG_RXP5 4
C75 *EV@1U/6.3V_4 +PEX_PLLVDD AG14 AM28 PEG_RXN5_C C147 EV@0.1U/10V_4 PEG_RXN5 4
C78 *EV@1U/6.3V_4 PEX_PLLVDD PEX_TX10* PEG_RXP4_C C160 EV@0.1U/10V_4
PEX_TX11 AL28 PEG_RXP4 4
AK28 PEG_RXN4_C C153 EV@0.1U/10V_4 PEG_RXN4 4
C55 EV@0.1U/10V/X7R_4 PEX_TX11* PEG_RXP3_C C162 EV@0.1U/10V_4
C PEX_TX12 AK29 PEG_RXP3 4 C
PLACE NEAR BALLS AL29 PEG_RXN3_C C157 EV@0.1U/10V_4 PEG_RXN3 4 R385 *EV@10K/J_4
PEX_TX12* PEG_RXP2_C C165 EV@0.1U/10V_4 +3V_GPU
PEX_TX13 AM29 PEG_RXP2 4 +3V
120mA AM30 PEG_RXN2_C C168 EV@0.1U/10V_4 PEG_RXN2 4
L6 EV@0_6 +PEX_SVDD_3V3 PEX_TX13* PEG_RXP1_C C167 EV@0.1U/10V_4
+3V_GPU AG19 PEX_CAL_PD_VDDQ/ PEX_SVDD_3V3 PEX_TX14 AM31 PEG_RXP1 4
+1.05V_GPU L10 *EV@0_6 F7 AM32 PEG_RXN1_C C170 EV@0.1U/10V_4 PEG_RXN1 4
NC_12/ PEX_SVDD_3V3 PEX_TX14* PCIE_CLKREQ_PEG# 10
AN32 PEG_RXP0_C C171 EV@0.1U/10V_4 PEG_RXP0 4 R383
PEX_TX15

3
C56 EV@0.1U/10V_4 AP32 PEG_RXN0_C C173 EV@0.1U/10V_4 PEG_RXN0 4 EV@10K/J_4
C42 EV@4.7U/6.3V_6 PEX_TX15*
PLACE NEAR BALLS
GFXPG R384 *EV@10K/F_4 2 Q22
AG20 AR16 CLK_PCIE_VGAP 10 EV@DTC144EUA
PEX_CAL_PU_GND/ NC PEX_REFCLK

3
A2 NC_1 PEX_REFCLK* AR17 CLK_PCIE_VGAN 10
AB7
??

1
NC_2 PEX_CLKREQ# Q21
AD6 NC_3 2
AF6 AJ17 PEX_TSTCLK R89 *EV@200/J_4 R90 1 2 EV@100K/J_4 EV@DTC144EUA
NC_4 PEX_TSTCLK_OUT PEX_TSTCLK#
AG6 NC_5 PEX_TSTCLK_OUT* AJ18
AJ5

1
NC_6
AK15 NC_7
AL7 AM16 VGA_RST# R87 EV@0/J_4 GPU_RST# GPU_RST# 31
R61 EV@10K_4 NC_8 PEX_RST*
E7 NC_11
H32 AR13 PEX_CLKREQ# R401 EV@10K/J_4 +3V_GPU
NC_13 PEX_CLKREQ*
M7 NC_14
R60 EV@40.2K/F_4 P6 AG21 PEX_TERMP R94 EV@2.49K/F_4
NC_15 PEX_TERMP
U7 NC_18
V6 AP35 TESTMODE R110 EV@10K/J_4
NC_19 TESTMODE

Ffor N12P-GE, they can be unstuffed by default

D D

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
N12P-GE (PCIE I/F) 1/5
Date: Monday, September 27, 2010 Sheet 16 of 41
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

17
U23B U23C
fcbga973-nvidia-n12p-ge VMA_DQ[63..0] fcbga973-nvidia-n12p-ge
21 VMA_DQ[63..0]
COMMON COMMON
VMA_CMD3 V32 VMA_DM[7..0] VMC_CMD3 C17 B13 VMC_DQ0
21 VMA_CMD3 FBA_CMD0 21 VMA_DM[7..0] 22 VMC_CMD3 FBC_CMD0 FBC_D00
21 VMA_CMD8 W 31 L32 VMA_DQ0 22 VMC_CMD8 B19 D13 VMC_DQ1
FBA_CMD1 FBA_D00 VMA_DQ1 VMA_WDQS[7..0] VMC_CMD2 FBC_CMD1 FBC_D01 VMC_DQ2
21 VMA_CMD2 U31 FBA_CMD2 FBA_D01 N33 21 VMA_WDQS[7..0] 22 VMC_CMD2 D18 FBC_CMD2 FBC_D02 A13
Y32 L33 VMA_DQ2 F21 A14 VMC_DQ3
21 VMA_CMD21 FBA_CMD3 FBA_D02 22 VMC_CMD21 FBC_CMD3 FBC_D03
AB35 N34 VMA_DQ3 VMA_RDQS[7..0] A23 C16 VMC_DQ4
21 VMA_CMD24 FBA_CMD4 FBA_D03 21 VMA_RDQS[7..0] 22 VMC_CMD24 FBC_CMD4 FBC_D04
21 VMA_CMD23 AB34 N35 VMA_DQ4 22 VMC_CMD23 D21 B16 VMC_DQ5
FBA_CMD5 FBA_D04 VMA_DQ5 VMC_DQ[63..0] FBC_CMD5 FBC_D05 VMC_DQ6
21 VMA_CMD26 W 35 FBA_CMD6 FBA_D05 P35 22 VMC_DQ[63..0] 22 VMC_CMD26 B23 FBC_CMD6 FBC_D06 A17
21 VMA_CMD7 W 33 P33 VMA_DQ6 22 VMC_CMD7 E20 D16 VMC_DQ7
FBA_CMD7 FBA_D06 VMA_DQ7 VMC_DM[7..0] FBC_CMD7 FBC_D07 VMC_DQ8
21 VMA_CMD15 W 30 FBA_CMD8 FBA_D07 P34 22 VMC_DM[7..0] 22 VMC_CMD15 G21 FBC_CMD8 FBC_D08 C13
T34 K35 VMA_DQ8 F20 B11 VMC_DQ9
21 VMA_CMD13 FBA_CMD9 FBA_D08 VMC_WDQS[7..0] 22 VMC_CMD13 FBC_CMD9 FBC_D09
21 VMA_CMD4 T35 K33 VMA_DQ9 22 VMC_WDQS[7..0] 22 VMC_CMD4 F19 C11 VMC_DQ10
FBA_CMD10 FBA_D09 VMA_DQ10 VMC_CMD18 FBC_CMD10 FBC_D10 VMC_DQ11
A 21 VMA_CMD18 AB31 FBA_CMD11 FBA_D10 K34 22 VMC_CMD18 F23 FBC_CMD11 FBC_D11 A11 A
Y30 H33 VMA_DQ11 VMC_RDQS[7..0] A22 C10 VMC_DQ12
21 VMA_CMD29 FBA_CMD12 FBA_D11 22 VMC_RDQS[7..0] 22 VMC_CMD29 FBC_CMD12 FBC_D12
Y34 G34 VMA_DQ12 C22 C8 VMC_DQ13
21 VMA_CMD27 FBA_CMD13 FBA_D12 22 VMC_CMD27 FBC_CMD13 FBC_D13
W 32 G33 VMA_DQ13 B17 B8 VMC_DQ14
21 VMA_CMD6 FBA_CMD14 FBA_D13 22 VMC_CMD6 FBC_CMD14 FBC_D14
VMA_CMD17 AA30 E34 VMA_DQ14 VMC_CMD17 F24 A8 VMC_DQ15
T9 FBA_CMD15 FBA_D14 T7 FBC_CMD15 FBC_D15
21 VMA_CMD19 VMA_CMD19 AA32 E33 VMA_DQ15 VMA_CMD0 R108 EV@10K/F_4 22 VMC_CMD19 VMC_CMD19 C25 E8 VMC_DQ16
FBA_CMD16 FBA_D15 VMA_DQ16 FBC_CMD16 FBC_D16 VMC_DQ17
21 VMA_CMD22 Y33 FBA_CMD17 FBA_D16 G31 22 VMC_CMD22 E22 FBC_CMD17 FBC_D17 F8
U32 F30 VMA_DQ17 VMA_CMD19 R106 EV@10K/F_4 C20 F10 VMC_DQ18
21 VMA_CMD12 FBA_CMD18 FBA_D17 22 VMC_CMD12 FBC_CMD18 FBC_D18
21 Y31 G30 VMA_DQ18 B22 F9 VMC_DQ19
VMA_CMD28 FBA_CMD19 FBA_D18 22 VMC_CMD28 FBC_CMD19 FBC_D19
U34 G32 VMA_DQ19 VMA_CMD3 R107 EV@10K/F_4 A19 F12 VMC_DQ20
21 VMA_CMD10 FBA_CMD20 FBA_D19 22 VMC_CMD10 FBC_CMD20 FBC_D20
21 Y35 K30 VMA_DQ20 D22 D8 VMC_DQ21
VMA_CMD25 FBA_CMD21 FBA_D20 22 VMC_CMD25 FBC_CMD21 FBC_D21
21 W 34 K32 VMA_DQ21 VMA_CMD16 R103 EV@10K/F_4 D20 D11 VMC_DQ22
VMA_CMD9 FBA_CMD22 FBA_D21 22 VMC_CMD9 FBC_CMD22 FBC_D22
VMA_CMD1 V30 H30 VMA_DQ22 VMC_CMD1 E19 E11 VMC_DQ23
T10 FBA_CMD23 FBA_D22 T6 FBC_CMD23 FBC_D23
U35 K31 VMA_DQ23 VMA_CMD20 R109 EV@10K/F_4 D19 D12 VMC_DQ24
21 VMA_CMD11 FBA_CMD24 FBA_D23 22 VMC_CMD11 FBC_CMD24 FBC_D24
VMA_CMD0 U30 L31 VMA_DQ24 VMC_CMD0 F18 E13 VMC_DQ25
21 VMA_CMD0 FBA_CMD25 FBA_D24 22 VMC_CMD0 FBC_CMD25 FBC_D25
21 VMA_CMD5 U33 L30 VMA_DQ25 22 VMC_CMD5 C19 F13 VMC_DQ26
VMA_CMD16 FBA_CMD26 FBA_D25 VMA_DQ26 VMC_CMD0 R93 EV@10K/F_4 VMC_CMD16 FBC_CMD26 FBC_D26 VMC_DQ27
21 VMA_CMD16 AB30 FBA_CMD27 FBA_D26 M32 22 VMC_CMD16 F22 FBC_CMD27 FBC_D27 F14
VMA_CMD20 AB33 N30 VMA_DQ27 VMC_CMD20 C23 F15 VMC_DQ28
21 VMA_CMD20 FBA_CMD28 FBA_D27 22 VMC_CMD20 FBC_CMD28 FBC_D28
21 VMA_CMD14 T33 M30 VMA_DQ28 VMC_CMD19 R101 EV@10K/F_4 22 VMC_CMD14 B20 E16 VMC_DQ29
FBA_CMD29 FBA_D28 VMA_DQ29 FBC_CMD29 FBC_D29 VMC_DQ30
21 VMA_CMD30 W 29 FBA_CMD30 FBA_D29 P31 22 VMC_CMD30 A20 FBC_CMD30 FBC_D30 F16
R32 VMA_DQ30 VMC_CMD3 R85 EV@10K/F_4 F17 VMC_DQ31
VMA_DM0 FBA_D30 VMA_DQ31 VMC_DM0 FBC_D31 VMC_DQ32
P32 FBA_DQM0 FBA_D31 R30 A16 FBC_DQM0 FBC_D32 D29
VMA_DM1 H34 AG30 VMA_DQ32 VMC_CMD16 R96 EV@10K/F_4 VMC_DM1 D10 F27 VMC_DQ33
VMA_DM2 FBA_DQM1 FBA_D32 VMA_DQ33 VMC_DM2 FBC_DQM1 FBC_D33 VMC_DQ34
J30 FBA_DQM2 FBA_D33 AG32 F11 FBC_DQM2 FBC_D34 F28
VMA_DM3 P30 AH31 VMA_DQ34 VMC_CMD20 R97 EV@10K/F_4 VMC_DM3 D15 E28 VMC_DQ35
VMA_DM4 FBA_DQM3 FBA_D34 VMA_DQ35 VMC_DM4 FBC_DQM3 FBC_D35 VMC_DQ36
AF32 FBA_DQM4 FBA_D35 AF31 D27 FBC_DQM4 FBC_D36 D26
VMA_DM5 AL32 AF30 VMA_DQ36 VMC_DM5 D34 F25 VMC_DQ37
VMA_DM6 FBA_DQM5 FBA_D36 VMA_DQ37 VMC_DM6 FBC_DQM5 FBC_D37 VMC_DQ38
AL34 FBA_DQM6 FBA_D37 AE30 A34 FBC_DQM6 FBC_D38 D24
VMA_DM7 AF35 AC32 VMA_DQ38 VMC_DM7 D28 E25 VMC_DQ39
FBA_DQM7 FBA_D38 VMA_DQ39 FBC_DQM7 FBC_D39 VMC_DQ40
FBA_D39 AD30 FBC_D40 E32
VMA_WDQS0 L34 AN33 VMA_DQ40 VMC_WDQS0 C14 F32 VMC_DQ41
B VMA_WDQS1 FBA_DQS_W P0 FBA_D40 VMA_DQ41 VMC_WDQS1 FBC_DQS_W P0 FBC_D41 VMC_DQ42 B
H35 FBA_DQS_W P1 FBA_D41 AL31 A10 FBC_DQS_W P1 FBC_D42 D33
VMA_WDQS2 J32 AM33 VMA_DQ42 VMC_WDQS2 E10 E31 VMC_DQ43
VMA_WDQS3 FBA_DQS_W P2 FBA_D42 VMA_DQ43 VMC_WDQS3 FBC_DQS_W P2 FBC_D43 VMC_DQ44
N31 FBA_DQS_W P3 FBA_D43 AL33 D14 FBC_DQS_W P3 FBC_D44 C33
VMA_WDQS4 AE31 AK30 VMA_DQ44 VMC_WDQS4 E26 F29 VMC_DQ45
VMA_WDQS5 FBA_DQS_W P4 FBA_D44 VMA_DQ45 VMC_WDQS5 FBC_DQS_W P4 FBC_D45 VMC_DQ46
AJ32 FBA_DQS_W P5 FBA_D45 AK32 D32 FBC_DQS_W P5 FBC_D46 D30
VMA_WDQS6 AJ34 AJ30 VMA_DQ46 VMC_WDQS6 A32 E29 VMC_DQ47
VMA_WDQS7 FBA_DQS_W P6 FBA_D46 VMA_DQ47 VMC_WDQS7 FBC_DQS_W P6 FBC_D47 VMC_DQ48
AC33 FBA_DQS_W P7 FBA_D47 AH30 B26 FBC_DQS_W P7 FBC_D48 B29
AH33 VMA_DQ48 C31 VMC_DQ49
VMA_RDQS0 FBA_D48 VMA_DQ49 VMC_RDQS0 FBC_D49 VMC_DQ50
L35 FBA_DQS_RN0 FBA_D49 AH35 B14 FBC_DQS_RN0 FBC_D50 C29
VMA_RDQS1 G35 AH34 VMA_DQ50 VMC_RDQS1 B10 B31 VMC_DQ51
VMA_RDQS2 FBA_DQS_RN1 FBA_D50 VMA_DQ51 VMC_RDQS2 FBC_DQS_RN1 FBC_D51 VMC_DQ52
H31 FBA_DQS_RN2 FBA_D51 AH32 D9 FBC_DQS_RN2 FBC_D52 C32
VMA_RDQS3 N32 AJ33 VMA_DQ52 VMC_RDQS3 E14 B32 VMC_DQ53
VMA_RDQS4 FBA_DQS_RN3 FBA_D52 VMA_DQ53 VMC_RDQS4 FBC_DQS_RN3 FBC_D53 VMC_DQ54
AD32 FBA_DQS_RN4 FBA_D53 AL35 F26 FBC_DQS_RN4 FBC_D54 B35
VMA_RDQS5 AJ31 AM34 VMA_DQ54 VMC_RDQS5 D31 B34 VMC_DQ55
VMA_RDQS6 FBA_DQS_RN5 FBA_D54 VMA_DQ55 VMC_RDQS6 FBC_DQS_RN5 FBC_D55 VMC_DQ56
AJ35 FBA_DQS_RN6 FBA_D55 AM35 A31 FBC_DQS_RN6 FBC_D56 A29
VMA_RDQS7 AC34 AF33 VMA_DQ56 VMC_RDQS7 A26 B28 VMC_DQ57
FBA_DQS_RN7 FBA_D56 VMA_DQ57 FBC_DQS_RN7 FBC_D57 VMC_DQ58
FBA_D57 AE32 FBC_D58 A28
P29 AF34 VMA_DQ58 G14 C28 VMC_DQ59
FBA_W CK0 FBA_D58 VMA_DQ59 FBC_W CK0 FBC_D59 VMC_DQ60
R29 FBA_W CK0_N FBA_D59 AE35 G15 FBC_W CK0_N FBC_D60 C26
L29 AE34 VMA_DQ60 G11 D25 VMC_DQ61
FBA_W CK1 FBA_D60 VMA_DQ61 FBC_W CK1 FBC_D61 VMC_DQ62
M29 FBA_W CK1_N FBA_D61 AE33 G12 FBC_W CK1_N FBC_D62 B25
AG29 AB32 VMA_DQ62 G27 A25 VMC_DQ63
FBA_W CK2 FBA_D62 VMA_DQ63 FBC_W CK2 FBC_D63
AH29 FBA_W CK2_N FBA_D63 AC35 5500mA G28 FBC_W CK2_N
AD29 FBA_W CK3 G24 FBC_W CK3
AE29 T32 +1.5V_GPU G25 E17
FBA_W CK3_N FBA_CLK0 VMA_CLKP0 21 FBC_W CK3_N FBC_CLK0 VMC_CLKP0 22
FBA_CLK0* T31 VMA_CLKN0 21 FBC_CLK0* D17 VMC_CLKN0 22
+1.5V_GPU AC31 D23
FBA_CLK1 VMA_CLKP1 21 FBC_CLK1 VMC_CLKP1 22
5500mA AA27 FBVDDQ_1 FBA_CLK1* AC30 VMA_CLKN1 21 N27 FBVDDQ_28 FBC_CLK1* E23 VMC_CLKN1 22
AA29 FBVDDQ_2 P27 FBVDDQ_29
AA31 FBVDDQ_3 R27 FBVDDQ_30
AB27 FBVDDQ_4 T27 FBVDDQ_31
C C
AB29 FBVDDQ_5 FB_VREF J27 T8 U27 FBVDDQ_32
AC27
AD27
FBVDDQ_6
15mils width
U29
V27
FBVDDQ_33 MEMORY I/F C
FBVDDQ_7 FBVDDQ_34
AE27 FBVDDQ_8 V29 FBVDDQ_35 PLACE NEAR BALLS
AJ28 FBVDDQ_9 V34 FBVDDQ_36
B18 W 27 K27 FB_CAL_PD_VDDQ R99 EV@40.2/F_4 +1.5V_GPU
FBVDDQ_10 FBVDDQ_37 FB_CAL_PD_VDDQ
E21 FBVDDQ_11 Y27 FBVDDQ_38
G17 FBVDDQ_12
G18 L27 FB_CAL_PU_GND R98 EV@40.2/F_4
FBVDDQ_13 FB_CAL_PU_GND
G22 FBVDDQ_14
G8
G9
FBVDDQ_15 MEMORY I/F A POP For Debug only
Check M27 FB_CAL_TERM_GND R105 EV@60.4/F_4
FBVDDQ_16 Place close to ball FB_CAL_TERM_GND
H29 FBVDDQ_17
J14 FBVDDQ_18
J15 T30 FBA_DEBUG0 R104 *EV@10K/F_4 +1.5V_GPU G19 FBC_DEBUG0 R92 EV@60.4/F_4 +1.5V_GPU
FBVDDQ_19 FBA_DEBUG0 FBA_DEBUG1 R102 EV@10K/F_4 FBC_DEBUG0 FBC_DEBUG1 R84 EV@10K/F_4
J16 FBVDDQ_20 FBA_DEBUG1 T29 FBC_DEBUG1 G16
J17 FBVDDQ_21 30-ohm ESR=0.01-ohm 30-ohm ESR=0.01-ohm
EV@BLM18AG331SN1D +1.5V_GPU EV@BLM18AG331SN1D
J20 FBVDDQ_22 +FB_PLLAVDD
100mA +FB_PLLAVDD1
100mA
J21 AG27 L11 +1.05V_GPU J19 L4 +1.05V_GPU
FBVDDQ_23 FB_DLLAVDD0 NC/ FB_DLLAVDD1
J22 FBVDDQ_24
J23 AF27 C158 EV@10U/6.3V_6 PLACE NEAR BALLS C43 EV@0.1U/10V_4 J18 C10 EV@10U/6.3V_6 PLACE NEAR BGA
FBVDDQ_25 FB_PLLAVDD0 C161 EV@1U/6.3V_4 C522 EV@0.1U/10V_4 NC/ FB_PLLAVDD1 C11 EV@1U/6.3V_4
J24 FBVDDQ_26
J29 C111 EV@0.1U/10V_4
+1.5V_GPU FBVDDQ_27
PLACE NEAR BGA
C141 *EV@0.1U/10V_4 C51 *EV@0.1U/10V_4 PLACE NEAR BALLS
C154 EV@0.1U/10V_4 C185 EV@0.01U/25V/X7R_4 C33 EV@0.1U/10V_4
C175 EV@0.1U/10V_4 C146 EV@0.1U/10V_4 C183 EV@0.01U/25V/X7R_4 C12 EV@0.1U/10V_4
C164 EV@0.1U/10V_4 C576 EV@0.01U/25V/X7R_4
PLACE NEAR BGA C103 EV@0.1U/10V_4 PLACE NEAR BGA
C547 EV@0.1U/10V_4 C589 EV@2700p/50V_4
D
C573 EV@0.1U/10V_4 C151 EV@2700p/50V_4 D
C133 EV@0.1U/10V_4 C150 EV@2700p/50V_4

C148 EV@1U/6.3V_4 PLACE NEAR BALLS C572 EV@1U/6.3V_4

PLACE NEAR BALLS C149 EV@1U/6.3V_4 C121 EV@1U/6.3V_4
C152 EV@4.7U/6.3V_6 C155 EV@4.7U/6.3V_6
C45 EV@4.7U/6.3V_6 C159 EV@4.7U/6.3V_6 Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
N12P-GE (MEMORY I/F) 2/5
Date: Monday, September 27, 2010 Sheet 17 of 41
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

R74 EV@10K/J_4 +IFPCAB_PLLVDD AK9

U23D
fcbga973-nvidia-n12p-ge
COMMON
IFPAB_PLLVDD

IFPAB(LVDS)
IFPA_TXC
IFPA_TXC*
IFPA_TXD0
AM11
AM12
AM8
AL8
18
IFPA_TXD0*
IFPA_TXD1 AM10
IFPA_TXD1* AM9
IFPA_TXD2 AK10
IFPA_TXD2* AL10
A AJ11 IFPAB_RSET IFPA_TXD3 AK11 A
IFPA_TXD3* AL11
AG9 IFPA_IOVDD IFPB_TXC AP13
R70 EV@10K/J_4 +IFPAB_IOVDD AG10 AN13
IFPB_IOVDD IFPB_TXC*
IFPB_TXD4 AN8
IFPB_TXD4* AP8
IFPB_TXD5 AP10
IFPB_TXD5* AN10
IFPB_TXD6 AR11
IFPB_TXD6* AR10
IFPB_TXD7 AN11
IFPB_TXD7* AP11

R69 EV@10K/J_4 +IFPCD_PLLVDD AJ9 AN3

IFPCD_PLLVDD/ I2CW _SDA/ IFPC_AUX_N
IFPC_PLLVDD I2CW _SCL/ IFPC_AUX AP2
R63 EV@10K/J_4 DACB_VDD AC6 AR2
DACB_VDD/ IFPC_L3_N
IFPD_PLLVDD IFPC_L3 AP1
IFPC_L2_N AM4
IFPC IFPC_L2 AM3
IFPC_L1_N AM5
IFPC_L1 AL5
IFPC_L0_N AM6
IFPC_L0 AM7
AK7 IFPCD_RSET/ IFPC_RSET I2CX_SDA/ IFPD_AUX_N AN4
AB6 DACB_RSET/ IFPD_RSET I2CX_SCL/ IFPD_AUX AP4
IFPD_L3_N AR4
IFPCD IFPD_L3 AR5
AP5
IFPD_L2_N
R57 EV@10K/J_4 +IFPCD_IOVDD
AJ8 IFPC_IOVDD IFPD IFPD_L2 AN5
B AK8 IFPD_IOVDD IFPD_L1_N AN7 B
IFPD_L1 AP7
IFPD_L0_N AR7
IFPD_L0 AR8

I2CY_SCL/ IFPE_AUX AE4

I2CY_SDA/ IFPE_AUX* AD4
IFPE_L0 AH6
AL1 IFPEF_RSET IFPE_L0* AH5
IFPE_L1 AH4
IFPEF IFPE_L1* AG4
AF4
R65 EV@10K/J_4
+IFPEF_PLLVDD IFPE_L2
AJ6 IFPEF_PLLVDD IFPE_L2* AF5
AE7 IFPE_IOVDD IFPE_L3 AE6
R56 +IFPEF_IOVDD
EV@10K/J_4 AD7 AE5
IFPF_IOVDD IFPE_L3*
I2CZ_SCL/ IFPF_AUX AF3
I2CZ_SDA/ IFPF_AUX* AF2
IFPF_L0 AL2
IFPF_L0* AL3
IFPF_L1 AJ3
IFPF_L1* AJ2
IFPF_L2 AJ1
IFPF_L2* AH1
IFPF_L3 AH2
IFPF_L3* AH3

R82 EV@10K/J_4DACA_VDD AJ12 AM15 +3V_GPU

DACA_VDD DACA_RED
DACA(CRT) AM14
DACA_GREEN
C C
DACA_BLUE AL14
R389 R45
AM13 EV@2.2K/J_4
EV@2.2K/J_4
DACA_HSYNC
DACA_VSYNC AL13
AK12 DACA_VREF
AK13 G1 I2CA_SCL
DACA_RSET I2CA_SCL I2CA_SDA
I2CA_SDA G4

R62 EV@10K/J_4 +DACB_VDD AG7 AK4 +3V_GPU

DACC_VDD/ /DACC_RED
AK6
DACB_VDD DACC(CRT2) DACB_RED
AL4
DACC_VREF/ /DACC_GREEN
DACB_VREF DACB_GREEN
AH7 DACC_RSET/ /DACC_BLUE AJ4
R391 R390 R50
DACB_RSET DACB_BLUE EV@2.2K/J_4
EV@2.2K/J_4
DACB_HSYNC/ DACC_HSYNC AM1 EV@10K/J_4
DACB_VSYNC/ DACC_VSYNC AM2

G3 I2CB_SCL
I2CB_SCL I2CB_SDA
I2CB_SDA G2

NC/ DACB_RED AA4

AC5
DACB(TV)NC/ DACB_GREEN AB4
Y4
DACB_VREF/ NC NC/ DACB_BLUE CEC XTAL_SSIN R393 EV@10K/J_4
CEC/ DACB_CSYNC AB5
P$ RKP(65 RKP
+1.05V_GPU L8 EV@BLM18PG300SN1 +NV_PLLVDD AE9 D2 XTAL_SSIN BXTALOUT R392 EV@10K/J_4
PLLVDD XTAL_SSIN BXTALOUT
XTAL_OUTBUFF D1
8QGHU%*$ C58 EV@0.1U/10V_4 AD9 VID_PLLVDD
D C65 EV@0.1U/10V_4 B1 XTALI_27M R19 *EV@0/J_4 CLK_27M_VGA 10 D
C70 EV@0.1U/10V_4 XTAL_IN
C69 EV@0.1U/10V_4 XTAL_PLL B2 XTALO_27M 2 1
XTAL_OUT
C15 Y1 C14
Close to GPU
1HDU*38 EV@27MHZ
C50 22U/6.3V_8 AF9 EV@18P/50V_4 EV@18P/50V_4
SP_PLLVDD Quanta Computer Inc.
8/24 follow NVDIA Change to 22U/8 .
PROJECT : FH5
Size Document Number Rev
1A
N12P-GE (DISPLAY) 3/5
Date: Monday, September 27, 2010 Sheet 18 of 41
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

P9
R9
T9
U23E
fcbga973-nvidia-n12p-ge
COMMON
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA
MIOA_D0
MIOA_D1
MIOA_D2
N1
P4
P1
19
U9 P2
R76 MIOA_VDDQ_4 MIOA_D3
P3
MIOA_D4
T3
MIOA_D5
EV@10K/J_4
MIOA_D6
T2 /RJLFDO /RJLFDO /RJLFDO /RJLFDO
MIOA_D7
T1 6WUDSSLQJ%LW 6WUDSSLQJ%LW 6WUDSSLQJ%LW 6WUDSSLQJ%LW 38 3'
U4
MIOA_D8
U5
MIOA_CAL_PD_VDDQ MIOA_D9
U1 520B62 XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE  .  
U2
MIOA_D10
MIOA_D11
U3 520B6&/. PCI_DEVIDE[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM  .  
T5 R6
MIOA_CAL_PU_GND MIOA_D12
A MIOA_D13
T6 520B6, RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]  .   A
MIOX_VDDQ should pop MIOA_D14
N6
675$3 USER[3] USER[2] USER[1] USER[0]  .  
3.3V for N11P-GE1,but N5 P5
MIOA_VREF MIOA_CTL3
pull down 10k for N11P-GT MIOA_HSYNC
N3 675$3 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]  .  
L3
MIOA_VSYNC
MIOA_DE
N2 675$3 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]  .  
MIOA_CLKOUT
R4 675$3 SOR_EXPOSED[3] SOR_EXPOSED[2] SOR_EXPOSED[1] SOR_EXPOSED[0] 7%' .  
T4
MIOA_CLKOUT*
MIOA_CLKIN
N4 MIOA_CLKIN 675$3 Reserve Reserve PCI_MAX_SPEED DP_PLL_VDD3 7%' .  
R52 EV@10K/J_4
AA9 Y1
MIOB_VDDQ_1 MIOB_D0
AB9
MIOB_VDDQ_2 MIOB MIOB_D1
Y2
W9 Y3
MIOB_VDDQ_3 MIOB_D2
Y9 AB3
R77 MIOB_VDDQ_4 MIOB_D3
AB2
MIOB_D4
MIOB_D5
AB1 VRAM Configuration Table 4.99K/F_4 ==> CS24992FB26
EV@10K/J_4 AC4
MIOB_D6
MIOB_D7
AC1 RAMCFG 10K/F_4 ==> CS31002FB26
MIOB_D8
AC2 [3:0] DESCRIPTION Quanta PN(Q buy) Quanta PN(W buy) Vendor PN
AA7
MIOB_CAL_PD_VDDQ MIOB_D9
AC3 15K/F_4 ==> CS31502FB24
AE3
MIOB_D10
MIOB_D11
AE2
* 0x3(0011) 900MHz 512MB(64M*16) Samsung AKD5LGHT500 K4W1G1646E-HC11 20K/F_4 ==> CS32002FB29
AA6 U6
MIOB_CAL_PU_GND MIOB_D12
MIOB_D13
W6 0x2(0010) 900MHz 512MB(64M*16) Hynix AKD5LZWTW01 AKD5LZWTW00 H5TQ1G63BFR-11C 30.1K/F_4 ==> CS33012FB18
Y6
MIOB_D14 STRAP0
STRAP0
W5 0x6(0110) 800MHz 1GB(128M*16) Hynix AKD5MGGTW00 AKD5MGGTW01 H5TQ2G63BFR-12C 35.7K/F_4 ==> CS33572FB13
AF1 W7 STRAP1
MIOB_VREF STRAP1 STRAP2
STRAP2
V7 0x7(0111) 800MHz 1GB(128M*16) Samsung AKD5MGGT501 AKD5MGGT502 K4W2G1646B-HC12 45.3K/F_4 ==> CS34532FB18
W3
MIOB_CTL3
MIOB_HSYNC
W1
W2
Check value
MIOB_VSYNC
Y5
MIOB_DE
V4
MIOB_CLKOUT EV@100K/J_4 R41
W4
MIOB_CLKOUT* MIOB_CLKIN
B AE1 2 1 B
MIOB_CLKIN

T1 VGA_THERMDN B4 K1 T36
THERMDN GPIO0 HDMI_HPD_S
K2
GPIO1
K3
VGA_THERMDP GPIO2
T3 B5 H3
THERMDP GPIO3
GPIO4
H2
GPU_VID1
520B6,6WUDS%LWIRU5$00DSSLQJ
H1 GPU_VID1 39
JTAG_TCK GPIO5 GPU_VID2
JTAG_TCK MISC1
AP14 H4 GPU_VID2 39
JTAG_TMS GPIO6 +3V_GPU +3V_GPU +3V_GPU
AR14 H5
JTAG_TDI JTAG_TMS (GPIOS,JTAG,THERM,I2C) GPIO7 dGPU_GPIO8
AN14 H6
JTAG_TDO JTAG_TDI GPIO8 dGPU_GPIO9
T5 AN16 J7
JTAG_TRST# JTAG_TDO GPIO9
AP16 K4 T37
+3V_GPU JTAG_TRST* GPIO10
K5 T4
GPIO11 dGPU_GPIO12
H7
R31 EV@2.2K/J_4 I2CS_SCL GPIO12
E2 J4
R30 EV@2.2K/J_4 I2CS_SDA I2CS_SCL GPIO13 R13 R10
E1 J6
R48 EV@2.2K/J_4 I2CC_SCL I2CS_SDA GPIO14 R46 *EV@10K/F_4 R395 R388 R67 R59 *EV@15K/F_4 R11
E3 L1
R44 EV@2.2K/J_4 I2CC_SDA I2CC_SCL GPIO15 *SPE@20K/F_4 EV@15K/F_4 EV@45.3K/F_4 *EV@35.7K/F_4 *EV@35.7K/F_4 *EV@35.7K/F_4
E4 L2
I2CC_SDA GPIO16 ROM_SI STRAP0
F4 L4
I2CD_SCL/ NC GPIO17 ROM_SO STRAP1 STRAP3
G5 M4
I2CD_SDA/ NC GPIO18 ROM_SCLK STRAP2 STRAP4
D5 L7
I2CE_SCL/ NC GPIO19
E5 L5
I2CE_SDA/ NC GPIO20
K6
GPIO21
L6
GPIO22 R47 R14 R394 R387 R71 R58 R9 R12
GPIO23
M6 Samsung SPE@20K/F_4 EV@10K/F_4 *EV@15K/F_4 *EV@2K/F_4 EV@30.1K/F_4 *EV@20K/F_4 *EV@20K/F_4
J26 C3 ROM_CS# EV@35.7K/F_4
BBIASN_NC ROM_CS* ROM_SI
J25
BBIASP_NC MISC2(ROM) ROM_SI
D3
ROM_SO
C4
STRAP3 ROM_SO ROM_SCLK
D7 D4
HDA_BCLK/ NC ROM_SCLK
D6
STRAP4 HDA_RST*/ NC HDCP_SCL
C7
HDA_SDI/ NC I2CH_SCL
F6 N11P-GE1 DevID is 0x0DFE, so pull up
B7 G6 HDCP_SDA
A7
HDA_SDO/ NC I2CH_SDA ROM_SCLK with 15Kohm and STRAP2
HDA_SYNC/ NC pull up 35Kohm
A5
R75 EV@40.2K/F_4 STRAP_REF_3V3 SPDIF
N9
STRAP_REF_3V3/ MULTI_STRAP_REF0_GND +3.3V_GPU Output
R78 EV@40.2K/F_4 STRAP_REF_MIOB M9 A4
C STRAP_REF_MIOB/ MULTI_STRAP_REF1_GND BUFRST* C
C5
NC
ON EXT_HDMI/DP
AK14
GND +3V_GPU
GND/ NC
K9 OFF INT_HDMI/DP

HDCP_SCL
HDCP_SDA
R8
R7
EV@10K/J_4
EV@10K/J_4
GPIO ASSIGNMENTS
GPU_VID1 R26 *EV@10K/J_4
GPU_VID2 R23 EV@10K/F_4 GPIO I/O ACTIVE USAGE

JTAG_TMS R402 *EV@10K/F_4 0 N/A N/A

+3V_GPU JTAG_TDI R399 *EV@10K/F_4
1 IN N/A Hot plug detect for IFP link C
+3V_GPU Thermal Sensor(VGA)
2 OUT N/A
+3V_GPU 3 OUT N/A
R17 R15 ROM_CS# R49 EV@10K/J_4
4 OUT N/A
2

*EV@10K/J_4 *EV@10K/J_4 dGPU_GPIO8 R43 EV@10K/J_4

Q2 $''5(66+ C21 *EV@0.1U/10V_4 dGPU_GPIO9 R73 EV@10K/J_4
5 OUT N/A NVVDD VID0
31 VGACLK 3 1 *EV@2N7002W-7-F
U1 dGPU_GPIO12 R66 EV@10K/J_4
6 OUT N/A NVVDD VID1
2

I2CS_SCL R27 *EV@0_4 R22 *EV@0_4 VGA_THERMDP

Q1
8
SCLK VCC
1
JTAG_TRST# R88 EV@1K/F_4
Check 7 OUT N/A NVVDD VID2
31 VGADATA 3 1 *EV@2N7002W-7-F I2CS_SDA R20 *EV@0_4 7 2 JTAG_TCK R83 EV@10K/J_4
8 I/O LOW OVERT
SDA DXP C16 HDMI_HPD_S R42 EV@100K/J_4
6 3 *EV@2200P/50V_4
ALERT# DXN R18 *EV@0_4 VGA_THERMDN GPU_VID1 R25 EV@10K/J_4 9 I/O LOW ALERT
4 5 GPU_VID2 R24 *EV@10K/F_4
31 VGA_THERM# OVERT# GND 10 OUT N/A FBVREF SELECT
*EV@G780P81U 11 OUT N/A SLI SYNC0
D
12 IN N/A PWR_LEVEL D
NV VID Table for N12P-GE
13 OUT N/A MEM_VID or power supply control
GPU_VID1 GPU_VID2 +VGPU_CORE 14 OUT N/A PS CONTROL
0 0 0.825V
1 0 0.9V
0 1 0.95V
Quanta Computer Inc.
1 1 TBD
PROJECT : FH5
Modify 8/18 Size Document Number Rev
1A
N12P-GE (GPIO&STRAPS)4/5
Date: Monday, September 27, 2010 Sheet 19 of 41
1 $''5(66+
2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

+VGPU_CORE U23F
fcbga973-nvidia-n12p-ge
+VGPU_CORE
U23G
fcbga973-nvidia-n12p-ge
COMMON
20
COMMON AA11 E15
GND_1 GND_096
AB11 P21 AA12 E18
VDD_001 VDD_057 GND_2 GND_097
AB13 P23 AA13 E24
VDD_002 VDD_058 GND_3 GND_098
AB15
AB17
VDD_003 NVVDD VDD_059
P25
R11
AA14
AA15
GND_4 GROUND GND_099
E27
E30
VDD_004 VDD_060 GND_5 GND_100
AB19 R12 AA16 E6
VDD_005 VDD_061 GND_6 GND_101
AB21 R13 AA17 E9
VDD_006 VDD_062 GND_7 GND_102
A AB23 R14 AA18 F2 A
VDD_007 VDD_063 GND_8 GND_103
AB25 R15 AA19 F31
VDD_008 VDD_064 GND_9 GND_104
AC11 R16 AA2 F34
VDD_009 VDD_065 GND_10 GND_105
AC12 R17 AA20 F5
VDD_010 VDD_066 GND_11 GND_106
AC13 R18 AA21 J2
VDD_011 VDD_067 GND_12 GND_107
AC14 R19 AA22 J31
VDD_012 VDD_068 GND_13 GND_108
AC15 R20 AA23 J34
VDD_013 VDD_069 GND_14 GND_109
AC16 R21 AA24 J5
VDD_014 VDD_070 GND_15 GND_110
AC17 R22 AA25 L9
VDD_015 VDD_071 GND_16 GND_111
AC18 R23 AA34 M11
VDD_016 VDD_072 GND_17 GND_112
AC19 R24 AA5 M13
VDD_017 VDD_073 GND_18 GND_113
AC20 R25 AB12 M15
VDD_018 VDD_074 GND_19 GND_114
AC21 T12 AB14 M17
VDD_019 VDD_075 GND_20 GND_115
AC22 T14 AB16 M19
VDD_020 VDD_076 GND_21 GND_116
AC23 T16 AB18 M2
VDD_021 VDD_077 GND_22 GND_117
AC24 T18 AB20 M21
VDD_022 VDD_078 GND_23 GND_118
AC25 T20 AB22 M23
VDD_023 VDD_079 GND_24 GND_119
AD12 T22 AB24 M25
VDD_024 VDD_080 GND_25 GND_120
AD14 T24 AC9 M31
VDD_025 VDD_081 GND_26 GND_121
AD16 V11 AD11 M34
VDD_026 VDD_082 GND_27 GND_122
AD18 V13 AD13 M5
VDD_027 VDD_083 GND_28 GND_123
AD22 V15 AD15 N11
VDD_028 VDD_084 GND_29 GND_124
AD24 V17 AD17 N12
VDD_029 VDD_085 GND_30 GND_125
L11 V19 AD2 N13
VDD_030 VDD_086 GND_31 GND_126
L12 V21 AD21 N14
VDD_031 VDD_087 GND_32 GND_127
L13 V23 AD23 N15
VDD_032 VDD_088 GND_33 GND_128
L14 V25 AD25 N16
VDD_033 VDD_089 GND_34 GND_129
L15 W11 AD31 N17
VDD_034 VDD_090 GND_35 GND_130
L16 W12 AD34 N18
VDD_035 VDD_091 GND_36 GND_131
L17 W13 AD5 N19
VDD_036 VDD_092 GND_37 GND_132
L18 W14 AE11 N20
VDD_037 VDD_093 GND_38 GND_133
L19 W15 AE12 N21
VDD_038 VDD_094 GND_39 GND_134
L20 W16 AE13 N22
B VDD_039 VDD_095 GND_40 GND_135 B
L21 W17 AE14 N23
VDD_040 VDD_096 GND_41 GND_136
L22 W18 AE15 N24
VDD_041 VDD_097 GND_42 GND_137
L23 W19 AE16 N25
VDD_042 VDD_098 GND_43 GND_138
L24 W20 AE17 P12
VDD_043 VDD_099 GND_44 GND_139
L25 W21 AE18 P14
VDD_044 VDD_100 GND_45 GND_140
M12 W22 AE19 P16
VDD_045 VDD_101 GND_46 GND_141
M14 W23 AE20 P18
VDD_046 VDD_102 GND_47 GND_142
M16 W24 AE21 P20
VDD_047 VDD_103 GND_48 GND_143
M18 W25 AE22 P22
VDD_048 VDD_104 GND_49 GND_144
M20 Y12 AE23 P24
VDD_049 VDD_105 GND_50 GND_145
M22 Y14 AE24 R2
VDD_050 VDD_106 GND_51 GND_146
M24 Y16 AE25 R31
VDD_051 VDD_107 GND_52 GND_147
P11 Y18 AG2 R34
VDD_052 VDD_108 GND_53 GND_148
P13 Y20 AG31 R5
VDD_053 VDD_109 GND_54 GND_149
P15 Y22 AG34 T11
VDD_054 VDD_110 GND_55 GND_150
P17 Y24 AG5 T13
VDD_055 VDD_111 GND_56 GND_151
P19 AK2 T15
VDD_056 GND_57 GND_152
AK31 T17
GND_58 GND_153
AK34 T19
GND_59 GND_154
AK5 T21
GND_60 GND_155
AL12 T23
GND_61 GND_156
AL15 T25
+VGPU_CORE GND_62 GND_157
AL18 U11
GND_63 GND_158
AL21 U12
C140 EV@0.01U/25V_4 GND_64 GND_159
AL24 U13
C139 EV@0.01U/25V_4 GND_65 GND_160
AL27 U14
C119 EV@0.01U/25V_4 GND_66 GND_161
AL30 U15
C67 EV@0.01U/25V_4 GND_67 GND_162
AL6 U16
C104 EV@0.01U/25V_4 GND_68 GND_163
AL9 U17
C85 EV@0.01U/25V_4 GND_69 GND_164
AN2 U18
GND_70 GND_165
PLACE UNDER BALLS C100 EV@0.01U/25V_4 AN34
GND_71 GND_166
U19
C135 EV@0.01U/25V_4 AP12 U20
GND_72 GND_167
C AP15 U21 C
C66 EV@0.022U/16V_4 GND_73 GND_168
AP18 U22
C116 EV@0.022U/16V_4 GND_74 GND_169
AP21 U23
C93 EV@0.022U/16V_4 GND_75 GND_170
AP24 U24
GND_76 GND_171
AP27 U25
C142 EV@0.1U/10V_4 GND_77 GND_172
AP3 V12
C90 EV@0.1U/10V_4 GND_78 GND_173
AP30 V14
GND_79 GND_174
AP33 V16
C91 EV@0.22U/6.3V_4 GND_80 GND_175
AP6 V18
C132 EV@0.22U/6.3V_4 GND_081 GND_176
AP9 V2
GND_082 GND_177
B12 V20
C118 EV@1U/10V_6 GND_083 GND_178
B15 V22
C94 *EV@1U/6.3V_4 GND_084 GND_179
B21 V24
GND_085 GND_180
B24 V31
C543 EV@0.047u/6.3V_4 GND_086 GND_181
B27 V5
C541 EV@0.047u/6.3V_4 GND_087 GND_182
B3 V9
C117 EV@0.047u/6.3V_4 GND_088 GND_183
B30 Y11
GND_089 GND_184
B33 Y13
GND_090 GND_185
B6 Y15
GND_091 GND_186
B9 Y17
GND_092 GND_187
C2 Y19
GND_093 GND_188
C34 Y21
GND_094 GND_189
E12 Y23
GND_095 GND_190
Y25
GND_191
+VGPU_CORE

PLACE NEAR BALLS

C105 EV@4.7U/6.3V_6

C546 EV@10U/6.3V_8
C83 EV@10U/6.3V_8
D D
C99 EV@22U/6.3V_8

C126 EV@47U/6.3V_8

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
N12P-GE(POWER&THM)5/5
Date: Monday, September 27, 2010 Sheet 20 of 41
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

U7
17 VMA_DQ[63..0]
17 VMA_DM[7..0]
17 VMA_WDQS[7..0]
17 VMA_RDQS[7..0] CHANNEL A: 512MB/1024MB DDR3
U27 U6 U26
21
VREFC_VMA1 M8 E3 VMA_DQ16 VREFC_VMA1 M8 E3 VMA_DQ27 VREFC_VMA3 M8 E3 VMA_DQ44 VREFC_VMA3 M8 E3 VMA_DQ60
VREFD_VMA1 VREFCA DQL0 VMA_DQ22 VREFD_VMA1 VREFCA DQL0 VMA_DQ26 VREFD_VMA3 VREFCA DQL0 VMA_DQ43 VREFD_VMA3 VREFCA DQL0 VMA_DQ61
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMA_DQ18 VREFDQ DQL1 VMA_DQ29 VREFDQ DQL1 VMA_DQ45 VREFDQ DQL1 VMA_DQ58
F2 F2 F2 F2
VMA_CMD7 DQL2 VMA_DQ20 VMA_CMD7 DQL2 VMA_DQ28 VMA_CMD9 DQL2 VMA_DQ40 VMA_CMD9 DQL2 VMA_DQ59
17 VMA_CMD7 N3 F8 N3 F8 N3 F8 N3 F8
VMA_CMD10 A0 DQL3 VMA_DQ19 VMA_CMD10 A0 DQL3 VMA_DQ31 VMA_CMD24 A0 DQL3 VMA_DQ47 VMA_CMD24 A0 DQL3 VMA_DQ63
17 VMA_CMD10 P7 H3 P7 H3 P7 H3 P7 H3
VMA_CMD24 A1 DQL4 VMA_DQ23 VMA_CMD24 A1 DQL4 VMA_DQ25 VMA_CMD10 A1 DQL4 VMA_DQ41 VMA_CMD10 A1 DQL4 VMA_DQ62
17 VMA_CMD24 P3 H8 P3 H8 P3 H8 P3 H8
VMA_CMD6 A2 DQL5 VMA_DQ17 VMA_CMD6 A2 DQL5 VMA_DQ30 VMA_CMD13 A2 DQL5 VMA_DQ46 VMA_CMD13 A2 DQL5 VMA_DQ56
17 VMA_CMD6 N2 G2 N2 G2 N2 G2 N2 G2
VMA_CMD22 A3 DQL6 VMA_DQ21 VMA_CMD22 A3 DQL6 VMA_DQ24 VMA_CMD26 A3 DQL6 VMA_DQ42 VMA_CMD26 A3 DQL6 VMA_DQ57
A
17 VMA_CMD22 P8 H7 P8 H7 P8 H7 P8 H7 A
VMA_CMD26 A4 DQL7 VMA_CMD26 A4 DQL7 VMA_CMD22 A4 DQL7 VMA_CMD22 A4 DQL7
17 VMA_CMD26 P2 P2 P2 P2
VMA_CMD5 A5 VMA_CMD5 A5 VMA_CMD21 A5 VMA_CMD21 A5
17 VMA_CMD5 R8 R8 R8 R8
VMA_CMD21 A6 VMA_DQ7 VMA_CMD21 A6 VMA_DQ12 VMA_CMD5 A6 VMA_DQ33 VMA_CMD5 A6 VMA_DQ51
17 VMA_CMD21 R2 D7 R2 D7 R2 D7 R2 D7
VMA_CMD8 A7 DQU0 VMA_DQ2 VMA_CMD8 A7 DQU0 VMA_DQ8 VMA_CMD8 A7 DQU0 VMA_DQ39 VMA_CMD8 A7 DQU0 VMA_DQ53
17 VMA_CMD8 T8 C3 T8 C3 T8 C3 T8 C3
VMA_CMD4 A8 DQU1 VMA_DQ5 VMA_CMD4 A8 DQU1 VMA_DQ15 VMA_CMD23 A8 DQU1 VMA_DQ32 VMA_CMD23 A8 DQU1 VMA_DQ50
17 VMA_CMD4 R3 C8 R3 C8 R3 C8 R3 C8
VMA_CMD25 A9 DQU2 VMA_DQ1 VMA_CMD25 A9 DQU2 VMA_DQ10 VMA_CMD28 A9 DQU2 VMA_DQ38 VMA_CMD28 A9 DQU2 VMA_DQ52
17 VMA_CMD25 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
VMA_CMD23 R7 A7 VMA_DQ6 VMA_CMD23 R7 A7 VMA_DQ13 VMA_CMD4 R7 A7 VMA_DQ36 VMA_CMD4 R7 A7 VMA_DQ48
17 VMA_CMD23 A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
VMA_CMD9 N7 A2 VMA_DQ0 VMA_CMD9 N7 A2 VMA_DQ9 VMA_CMD7 N7 A2 VMA_DQ37 VMA_CMD7 N7 A2 VMA_DQ54
17 VMA_CMD9 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMA_CMD12 T3 B8 VMA_DQ4 VMA_CMD12 T3 B8 VMA_DQ14 VMA_CMD14 T3 B8 VMA_DQ34 VMA_CMD14 T3 B8 VMA_DQ49
17 VMA_CMD12 A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
VMA_CMD14 T7 A3 VMA_DQ3 VMA_CMD14 T7 A3 VMA_DQ11 VMA_CMD12 T7 A3 VMA_DQ35 VMA_CMD12 T7 A3 VMA_DQ55
17 VMA_CMD14 A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
VMA_CMD30 M7 VMA_CMD30 M7 VMA_CMD27 M7 VMA_CMD27 M7
17 VMA_CMD30 A15 A15 A15 A15

VMA_CMD29 M2 B2 VMA_CMD29 M2 B2 VMA_CMD29 M2 B2 VMA_CMD29 M2 B2

17 VMA_CMD29 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMA_CMD13 N8 D9 VMA_CMD13 N8 D9 VMA_CMD6 N8 D9 VMA_CMD6 N8 D9
17 VMA_CMD13 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_CMD27 M3 G7 VMA_CMD27 M3 G7 VMA_CMD30 M3 G7 VMA_CMD30 M3 G7
17 VMA_CMD27 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#K8 K8 VDD#K8 K8 VDD#K8 K8 VDD#K8 K8
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMA_CLKP0 J7 N9 VMA_CLKP0 J7 N9 VMA_CLKP1 J7 N9 VMA_CLKP1 J7 N9
17 VMA_CLKP0 CK VDD#N9 CK VDD#N9 17 VMA_CLKP1 CK VDD#N9 CK VDD#N9
VMA_CLKN0 K7 R1 VMA_CLKN0 K7 R1 VMA_CLKN1 K7 R1 VMA_CLKN1 K7 R1
17 VMA_CLKN0 CK VDD#R1 +1.5V_GPU CK VDD#R1 17 VMA_CLKN1 CK VDD#R1 CK VDD#R1 +1.5V_GPU
VMA_CMD3 K9 R9 VMA_CMD3 K9 R9 VMA_CMD16 K9 R9 VMA_CMD16 K9 R9
17 VMA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GPU 17 VMA_CMD16 CKE VDD#R9 +1.5V_GPU CKE VDD#R9

VMA_CMD0 K1 A1 VMA_CMD0 K1 A1 VMA_CMD19 K1 A1 VMA_CMD19 K1 A1

17 VMA_CMD0 ODT VDDQ#A1 ODT VDDQ#A1 17 VMA_CMD19 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CMD2 L2 A8 VMA_CMD2 L2 A8 VMA_CMD18 L2 A8 VMA_CMD18 L2 A8
17 VMA_CMD2 CS VDDQ#A8 CS VDDQ#A8 17 VMA_CMD18 CS VDDQ#A8 CS VDDQ#A8
VMA_CMD11 J3 C1 VMA_CMD11 J3 C1 VMA_CMD11 J3 C1 VMA_CMD11 J3 C1
17 VMA_CMD11 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
VMA_CMD15 K3 C9 VMA_CMD15 K3 C9 VMA_CMD15 K3 C9 VMA_CMD15 K3 C9
17 VMA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
VMA_CMD28 L3 D2 VMA_CMD28 L3 D2 VMA_CMD25 L3 D2 VMA_CMD25 L3 D2
17 VMA_CMD28 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_WDQS2 F3 H2 VMA_WDQS3 F3 H2 VMA_WDQS5 F3 H2 VMA_WDQS7 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
G3 DQSL VDDQ#H9
H9 G3 DQSL VDDQ#H9
H9 G3 DQSL VDDQ#H9
H9 G3 DQSL VDDQ#H9
H9
B B

VMA_DM2 E7 A9 VMA_DM3 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 DML VSS#A9 VMA_DM1 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM6 DML VSS#A9
D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMA_WDQS0 C7 J2 VMA_WDQS1 C7 J2 VMA_WDQS4 C7 J2 VMA_WDQS6 C7 J2
VMA_RDQS0 DQSU VSS#J2 VMA_RDQS1 DQSU VSS#J2 VMA_RDQS4 DQSU VSS#J2 VMA_RDQS6 DQSU VSS#J2
B7 DQSU VSS#J8
J8 B7 DQSU VSS#J8
J8 B7 DQSU VSS#J8
J8 B7 DQSU VSS#J8
J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M9 M9
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
17 VMA_CMD20 VMA_CMD20 T2 P9 VMA_CMD20 T2 P9 VMA_CMD20 T2 P9 VMA_CMD20 T2 P9
RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
VMA_ZQ1 L8 T9 VMA_ZQ2 L8 T9 VMA_ZQ3 L8 T9 VMA_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1 Ohms +-1% VSSQ#B1 B1
VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9 VSSQ#B9 B9
VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D1 D1
R114 D8 R412 D8 R138 D8 R408 D8
EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SPE@K4W1G1646E-HC11 SPE@K4W1G1646E-HC11 SPE@K4W1G1646E-HC11 SPE@K4W1G1646E-HC11

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU

C C

+1.5V_GPU
R142 R144 R140
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 R136
EV@1.33K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA3

C594 *EV@10U/6.3V_6 VREFD_VMA3

C240 C241 C237

R141 R143 R139 C236
EV@1.33K/F_4 EV@0.01U/25V_4 EV@1.33K/F_4 EV@0.01U/25V_4 EV@1.33K/F_4 EV@0.01U/25V_4 R137
EV@1.33K/F_4 EV@0.01U/25V_4

3/22 Change R1/R2/C values for VREF

Placement has to be close to VRAM
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU

C593 EV@1U/6.3V_4 C599 EV@1U/6.3V_4 C590 EV@1U/6.3V_4 C192 EV@1U/6.3V_4

VMA_CLKP0 C602 EV@1U/6.3V_4 C596 EV@1U/6.3V_4 C246 EV@1U/6.3V_4 C605 EV@1U/6.3V_4
C214 EV@1U/6.3V_4 C595 EV@1U/6.3V_4 C598 EV@1U/6.3V_4 C235 EV@1U/6.3V_4
R135 C523 EV@1U/6.3V_4 C181 EV@1U/6.3V_4 C591 EV@1U/6.3V_4 C579 EV@1U/6.3V_4
EV@162/F_4 C601 EV@1U/6.3V_4 C212 EV@1U/6.3V_4 C239 EV@1U/6.3V_4 C242 EV@1U/6.3V_4
C243 EV@1U/6.3V_4 C588 EV@1U/6.3V_4 C604 EV@1U/6.3V_4 C597 EV@1U/6.3V_4
VMA_CLKN0 C40 EV@1U/6.3V_4 C35 EV@1U/6.3V_4 C188 EV@1U/6.3V_4 C524 EV@1U/6.3V_4
C182 EV@1U/6.3V_4

VMA_CLKP1
D D

R134
EV@162/F_4

VMA_CLKN1 C603 EV@0.1U/10V_4 C606 EV@0.1U/10V_4 C210 EV@0.1U/10V_4 C244 EV@0.1U/10V_4

C610 EV@0.1U/10V_4 C607 EV@0.1U/10V_4 C245 EV@0.1U/10V_4 C577 EV@0.1U/10V_4
C592 EV@0.1U/10V_4 C580 EV@0.1U/10V_4 C600 EV@0.1U/10V_4 C211 EV@0.1U/10V_4
C238 EV@0.1U/10V_4 C609 EV@0.1U/10V_4 C608 EV@0.1U/10V_4 C611 EV@0.1U/10V_4

Quanta Computer Inc.

PROJECT : FH5
GE1 FOR 243 BUT GT/E REQUIRE CHECK FAE Size Document Number Rev
1A
N12P-GE VRAM-1
Date: Monday, September 27, 2010 Sheet 21 of 41
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

22
17 VMC_DQ[63..0]
17 VMC_DM[7..0]
17 VMC_WDQS[7..0]
17 VMC_RDQS[7..0] CHANNEL B: 512MB/1024MB DDR3
U4
U22 U5 U25
VREFC_VMC1 M8 E3 VMC_DQ25
VREFC_VMC1 VMC_DQ18 VREFD_VMC1 VREFCA DQL0 VMC_DQ28 VREFC_VMC3 VMC_DQ36 VREFC_VMC3 VMC_DQ49
M8 VREFCA DQL0 E3 H1 VREFDQ DQL1 F7 M8 VREFCA DQL0 E3 M8 VREFCA DQL0 E3
VREFD_VMC1 H1 F7 VMC_DQ21 F2 VMC_DQ26 VREFD_VMC3 H1 F7 VMC_DQ33 VREFD_VMC3 H1 F7 VMC_DQ48
VREFDQ DQL1 VMC_DQ22 VMC_CMD7 DQL2 VMC_DQ30 VREFDQ DQL1 VMC_DQ39 VREFDQ DQL1 VMC_DQ55
F2 N3 F8 F2 F2
VMC_CMD7 DQL2 VMC_DQ17 VMC_CMD10 A0 DQL3 VMC_DQ27 VMC_CMD9 DQL2 VMC_DQ32 VMC_CMD9 DQL2 VMC_DQ50
17 VMC_CMD7 N3 F8 P7 H3 N3 F8 N3 F8
VMC_CMD10 A0 DQL3 VMC_DQ20 VMC_CMD24 A1 DQL4 VMC_DQ29 VMC_CMD24 A0 DQL3 VMC_DQ38 VMC_CMD24 A0 DQL3 VMC_DQ52
17 VMC_CMD10 P7 H3 P3 H8 P7 H3 P7 H3
VMC_CMD24 A1 DQL4 VMC_DQ19 VMC_CMD6 A2 DQL5 VMC_DQ24 VMC_CMD10 A1 DQL4 VMC_DQ34 VMC_CMD10 A1 DQL4 VMC_DQ51
17 VMC_CMD24 P3 H8 N2 G2 P3 H8 P3 H8
VMC_CMD6 A2 DQL5 VMC_DQ23 VMC_CMD22 A3 DQL6 VMC_DQ31 VMC_CMD13 A2 DQL5 VMC_DQ37 VMC_CMD13 A2 DQL5 VMC_DQ54
17 VMC_CMD6 N2 G2 P8 H7 N2 G2 N2 G2
VMC_CMD22 A3 DQL6 VMC_DQ16 VMC_CMD26 A4 DQL7 VMC_CMD26 A3 DQL6 VMC_DQ35 VMC_CMD26 A3 DQL6 VMC_DQ53
17 VMC_CMD22 P8 H7 P2 P8 H7 P8 H7
VMC_CMD26 A4 DQL7 VMC_CMD5 A5 VMC_CMD22 A4 DQL7 VMC_CMD22 A4 DQL7
A
17 VMC_CMD26 P2 R8 P2 P2 A
VMC_CMD5 A5 VMC_CMD21 A6 VMC_DQ8 VMC_CMD21 A5 VMC_CMD21 A5
17 VMC_CMD5 R8 R2 D7 R8 R8
VMC_CMD21 A6 VMC_DQ3 VMC_CMD8 A7 DQU0 VMC_DQ14 VMC_CMD5 A6 VMC_DQ44 VMC_CMD5 A6 VMC_DQ61
17 VMC_CMD21 R2 D7 T8 C3 R2 D7 R2 D7
VMC_CMD8 A7 DQU0 VMC_DQ6 VMC_CMD4 A8 DQU1 VMC_DQ9 VMC_CMD8 A7 DQU0 VMC_DQ45 VMC_CMD8 A7 DQU0 VMC_DQ58
17 VMC_CMD8 T8 C3 R3 C8 T8 C3 T8 C3
VMC_CMD4 A8 DQU1 VMC_DQ0 VMC_CMD25 A9 DQU2 VMC_DQ12 VMC_CMD23 A8 DQU1 VMC_DQ41 VMC_CMD23 A8 DQU1 VMC_DQ62
17 VMC_CMD4 R3 C8 L7 C2 R3 C8 R3 C8
VMC_CMD25 A9 DQU2 VMC_DQ7 VMC_CMD23 A10/AP DQU3 VMC_DQ11 VMC_CMD28 A9 DQU2 VMC_DQ47 VMC_CMD28 A9 DQU2 VMC_DQ59
17 VMC_CMD25 L7 A10/AP DQU3
C2 R7
A11 DQU4
A7 L7 A10/AP DQU3
C2 L7 A10/AP DQU3
C2
VMC_CMD23 R7 A7 VMC_DQ1 VMC_CMD9 N7 A2 VMC_DQ13 VMC_CMD4 R7 A7 VMC_DQ42 VMC_CMD4 R7 A7 VMC_DQ60
17 VMC_CMD23 A11 DQU4 A12/BC DQU5 A11 DQU4 A11 DQU4
VMC_CMD9 N7 A2 VMC_DQ5 VMC_CMD12 T3 B8 VMC_DQ10 VMC_CMD7 N7 A2 VMC_DQ46 VMC_CMD7 N7 A2 VMC_DQ56
17 VMC_CMD9 A12/BC DQU5 A13 DQU6 A12/BC DQU5 A12/BC DQU5
VMC_CMD12 T3 B8 VMC_DQ2 VMC_CMD14 T7 A3 VMC_DQ15 VMC_CMD14 T3 B8 VMC_DQ40 VMC_CMD14 T3 B8 VMC_DQ63
17 VMC_CMD12 A13 DQU6 A14 DQU7 A13 DQU6 A13 DQU6
VMC_CMD14 T7 A3 VMC_DQ4 VMC_CMD30 M7 VMC_CMD12 T7 A3 VMC_DQ43 VMC_CMD12 T7 A3 VMC_DQ57
17 VMC_CMD14 A14 DQU7 A15 A14 DQU7 A14 DQU7
VMC_CMD30 M7 VMC_CMD27 M7 VMC_CMD27 M7
17 VMC_CMD30 A15 A15 A15
VMC_CMD29 M2 B2
VMC_CMD29 M2 VMC_CMD13 BA0 VDD#B2 VMC_CMD29 VMC_CMD29
17 VMC_CMD29 B2 N8 D9 M2 B2 M2 B2
VMC_CMD13 N8 BA0 VDD#B2 VMC_CMD27 BA1 VDD#D9 VMC_CMD6 BA0 VDD#B2 VMC_CMD6 BA0 VDD#B2
17 VMC_CMD13 D9 M3 G7 N8 D9 N8 D9
VMC_CMD27 M3 BA1 VDD#D9 BA2 VDD#G7 VMC_CMD30 BA1 VDD#D9 VMC_CMD30 BA1 VDD#D9
17 VMC_CMD27 G7 K2 M3 G7 M3 G7
BA2 VDD#G7 VDD#K2 BA2 VDD#G7 BA2 VDD#G7
K2 K8 K2 K2
VDD#K2 VDD#K8 VDD#K2 VDD#K2
VDD#K8 K8 VDD#N1 N1 VDD#K8 K8 VDD#K8 K8
N1 VMC_CLKP0 J7 N9 N1 N1
VMC_CLKP0 VDD#N1 VMC_CLKN0 CK VDD#N9 VMC_CLKP1 VDD#N1 VMC_CLKP1 VDD#N1
17 VMC_CLKP0 J7 CK VDD#N9 N9 K7 CK VDD#R1 R1 17 VMC_CLKP1 J7 CK VDD#N9 N9 J7 CK VDD#N9 N9
VMC_CLKN0 K7 R1 VMC_CMD3 K9 R9 VMC_CLKN1 K7 R1 VMC_CLKN1 K7 R1
17 VMC_CLKN0 CK VDD#R1 +1.5V_GPU CKE VDD#R9 +1.5V_GPU 17 VMC_CLKN1 CK VDD#R1 +1.5V_GPU CK VDD#R1 +1.5V_GPU
VMC_CMD3 K9 R9 VMC_CMD16 K9 R9 VMC_CMD16 K9 R9
17 VMC_CMD3 CKE VDD#R9 17 VMC_CMD16 CKE VDD#R9 CKE VDD#R9
VMC_CMD0 K1 A1
VMC_CMD0 VMC_CMD2 ODT VDDQ#A1 VMC_CMD19 VMC_CMD19
17 VMC_CMD0 K1 ODT VDDQ#A1 A1 L2
CS VDDQ#A8 A8 17 VMC_CMD19 K1 ODT VDDQ#A1 A1 K1 ODT VDDQ#A1 A1
VMC_CMD2 L2 A8 VMC_CMD11 J3 C1 VMC_CMD18 L2 A8 VMC_CMD18 L2 A8
17 VMC_CMD2 CS VDDQ#A8 RAS VDDQ#C1 17 VMC_CMD18 CS VDDQ#A8 CS VDDQ#A8
VMC_CMD11 J3 C1 VMC_CMD15 K3 C9 VMC_CMD11 J3 C1 VMC_CMD11 J3 C1
17 VMC_CMD11 RAS VDDQ#C1 CAS VDDQ#C9 RAS VDDQ#C1 RAS VDDQ#C1
VMC_CMD15 K3 C9 VMC_CMD28 L3 D2 VMC_CMD15 K3 C9 VMC_CMD15 K3 C9
17 VMC_CMD15 CAS VDDQ#C9 WE VDDQ#D2 CAS VDDQ#C9 CAS VDDQ#C9
VMC_CMD28 L3 D2 E9 VMC_CMD25 L3 D2 VMC_CMD25 L3 D2
17 VMC_CMD28 WE VDDQ#D2 VDDQ#E9 WE VDDQ#D2 WE VDDQ#D2
E9 F1 E9 E9
VDDQ#E9 VMC_WDQS3 VDDQ#F1 VDDQ#E9 VDDQ#E9
VDDQ#F1 F1 F3 DQSL VDDQ#H2 H2 VDDQ#F1 F1 VDDQ#F1 F1
VMC_WDQS2 F3 H2 VMC_RDQS3 G3 H9 VMC_WDQS4 F3 H2 VMC_WDQS6 F3 H2
VMC_RDQS2 DQSL VDDQ#H2 DQSL VDDQ#H9 VMC_RDQS4 DQSL VDDQ#H2 VMC_RDQS6 DQSL VDDQ#H2
G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9 G3 DQSL VDDQ#H9 H9

VMC_DM3 E7 A9
B
VMC_DM2 VMC_DM1 DML VSS#A9 VMC_DM4 VMC_DM6 B
E7 DML VSS#A9 A9 D3 DMU VSS#B3 B3 E7 DML VSS#A9 A9 E7 DML VSS#A9 A9
VMC_DM0 D3 B3 E1 VMC_DM5 D3 B3 VMC_DM7 D3 B3
DMU VSS#B3 VSS#E1 DMU VSS#B3 DMU VSS#B3
VSS#E1 E1 VSS#G8 G8 VSS#E1 E1 VSS#E1 E1
G8 VMC_WDQS1 C7 J2 G8 G8
VMC_WDQS0 VSS#G8 VMC_RDQS1 DQSU VSS#J2 VMC_WDQS5 VSS#G8 VMC_WDQS7 VSS#G8
C7 DQSU VSS#J2 J2 B7 DQSU VSS#J8 J8 C7 DQSU VSS#J2 J2 C7 DQSU VSS#J2 J2
VMC_RDQS0 B7 J8 M1 VMC_RDQS5 B7 J8 VMC_RDQS7 B7 J8
DQSU VSS#J8 VSS#M1 DQSU VSS#J8 DQSU VSS#J8
M1 M9 M1 M1
VSS#M1 VSS#M9 VSS#M1 VSS#M1
M9 P1 M9 M9
VSS#M9 VMC_CMD20 VSS#P1 VSS#M9 VSS#M9
P1 T2 P9 P1 P1
VMC_CMD20 T2 VSS#P1 RESET VSS#P9 VMC_CMD20 VSS#P1 VMC_CMD20 VSS#P1
17 VMC_CMD20 P9 T1 T2 P9 T2 P9
RESET VSS#P9 VMC_ZQ2 VSS#T1 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 L8
ZQ VSS#T9 T9 VSS#T1 T1 VSS#T1 T1
VMC_ZQ1 L8 T9 VMC_ZQ3 L8 T9 VMC_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 VSSQ#B1
B1 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B9 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 VSSQ#B9 VSSQ#B1 VSSQ#B1
VSSQ#B9 B9 VSSQ#D1 D1 VSSQ#B9 B9 VSSQ#B9 B9
VSSQ#D1 D1 VSSQ#D8 D8 VSSQ#D1 D1 VSSQ#D1 D1
R398 D8 R91 E2 R115 D8 R100 D8
EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#E2 EV@240/F_4 VSSQ#D8 EV@240/F_4 VSSQ#D8
E2 J1 E8 E2 E2
VSSQ#E2 NC#J1 VSSQ#E8 VSSQ#E2 VSSQ#E2
J1 E8 L1 F9 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#L1 VSSQ#F9 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 J9 G1 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#J9 VSSQ#G1 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 L9 G9 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#L9 VSSQ#G9 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
96-BALL
96-BALL SDRAM DDR3 96-BALL 96-BALL
SDRAM DDR3 SPE@K4W1G1646E-HC11 SDRAM DDR3 SDRAM DDR3
SPE@K4W1G1646E-HC11 SPE@K4W1G1646E-HC11 SPE@K4W1G1646E-HC11

C +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU C

+1.5V_GPU
R39 R36 R113 R117
EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4 EV@1.33K/F_4
15 mil width and <500 mil
VREFC_VMC1 VREFD_VMC1 VREFC_VMC3 VREFD_VMC3
C519 *EV@10U/6.3V_6

C36 C34 C179 C184

R38 R37 R112 R116
EV@1.33K/F_4 EV@0.01U/25V_4 EV@1.33K/F_4 EV@0.01U/25V_4 EV@1.33K/F_4 EV@0.01U/25V_4 EV@1.33K/F_4 EV@0.01U/25V_4

3/22 Change R1/R2/C values for VREF

Placement has to be close to VRAM
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU

VMC_CLKP0 C544 EV@1U/6.3V_4 C542 EV@1U/6.3V_4 C101 EV@1U/6.3V_4 C74 EV@1U/6.3V_4

C107 EV@1U/6.3V_4 C37 EV@1U/6.3V_4 C177 EV@1U/6.3V_4 C536 EV@1U/6.3V_4
R40 C82 EV@1U/6.3V_4 C63 EV@1U/6.3V_4 C39 EV@1U/6.3V_4 C521 EV@1U/6.3V_4
EV@162/F_4 C540 EV@1U/6.3V_4 C548 EV@1U/6.3V_4 C174 EV@1U/6.3V_4 C169 EV@1U/6.3V_4
C545 EV@1U/6.3V_4 C54 EV@1U/6.3V_4 C557 EV@1U/6.3V_4 C178 EV@1U/6.3V_4
VMC_CLKN0 C529 EV@1U/6.3V_4 C163 EV@1U/6.3V_4 C166 EV@1U/6.3V_4 C520 EV@1U/6.3V_4
C187 EV@1U/6.3V_4 C189 EV@1U/6.3V_4 C586 EV@1U/6.3V_4 C190 EV@1U/6.3V_4
D D
C186 EV@1U/6.3V_4 C191 EV@1U/6.3V_4 C587 EV@1U/6.3V_4
VMC_CLKP1

R111
EV@162/F_4
C176 EV@0.1U/10V_4 C92 EV@0.1U/10V_4
VMC_CLKN1 C38 EV@0.1U/10V_4 C531 EV@0.1U/10V_4 C534 EV@0.1U/10V_4 C60 EV@0.1U/10V_4
C172 EV@0.1U/10V_4 C180 EV@0.1U/10V_4 C48 EV@0.1U/10V_4 C52 EV@0.1U/10V_4
C518 EV@0.1U/10V_4 C556 EV@0.1U/10V_4 C527 EV@0.1U/10V_4 C156 EV@0.1U/10V_4
Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
N12P-GE VRAM-2
Date: Monday, September 27, 2010 Sheet 22 of 41
1 2 3 4 5 6 7 8
 5 4 3 2 1

RST5138 SIDO 23
SD/SDHC CARD READER SD/MS CONNDETOR
CARD_3V3 Change Card reader socket 8/11
D 10 CLK_48M_CARD D
CN9
14 SD-VCC
SP4 17
SP3 SD-DAT0
18

SP14
SP13
SP12
SP13 SD-DAT1
19
C470 SP12 SD-DAT2
11
*100pF SP8 SD-DAT3
15 SD-CLK
CARD_3V3 SP10

24
23
22
21
20
19
12
U15 SP6 SD-CMD
20 SD-C/D
R344 SP1 22

CLK_IN
XD_D7
SP14
SP13
SP12
SP11
6.2K 1% SD-WP
13 SD-GND
RREF 1 18 SP10 16
RREF SP10 C450 C454 C472 SD-GND
10 USBP5- 4 3 2 DM GPIO0 17
1 2 3 RTS5138 SP9 16 SP9 1.0uF 1.0uF 1.0uF
10 USBP5+ DP SP8
+3V 4 3V3_IN QFN24 SP8 15
L17 *90ohm,400mA CARD_3V3 5 14 9
VREG CARD_3V3 SP7 SP6 SP9 MS-VCC
6 V18 SP6 13 4 MS-DATA0

XD_CD#
SP12 3
SP8 MS-DATA1
5 MS-DATA2

SP1
SP2
SP3
SP4
SP5
C477 C475 C466 SP5 7
4.7uF 0.1uF 1.0uF GND SP1 MS-DATA3
25 8
MS-SCLK
SP2 6

7
8
9
10
11
12
SP14 MS-INS
IC Bottom Ground 2
MS-BS GND 23
1 21
MS-GND GND
10 MS-GND

CARD_READER_PROCONN

SP1
SP2
SP3
SP4
SP5
DFHD23MS0B6
C 3IN1-SD-47265-001-23P C

SP8
SP1

Share Pin C464

*10P/50V_4
C449
*10P/50V_4

Share Pin XD MS SD

SP1 XDR/B# MS_CLK SD_WP

SP2 XD_RE# MS_INS#

SP3 XD_CE# SD_D1

SP4 XD_CLE MS_D7 SD_D0

SP5 XD_ALE MS_D3 SD_D7

B B
SP6 XD_WE# SD_CD#

SP7 XD_WP MS_D6 SD_D6

SP8 XD_D0 MS_D2 SD_CLK

SP9 XD_D1 MS_D0 SD_D5

SP10 XD_D2 SD_CMD

SP11 XD_D3 MS_D4 SD_D4

SP12 XD_D4 MS_D1 SD_D3

SP13 XD_D5 MS_D5 SD_D2

SP14 XD_D6 MS_BS

A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
3G
Card Reader RST5138
Date: Monday, September 27, 2010 Sheet 23 of 41
5 4 3 2 1
 5 4 3 2 1

CRT CONN/DDC LEVEL SHIFT 24

40mils
C514 0.1U/10V_4
TBD CN5500 FOOTPRINT
F1
5V_CRT2 CN4

16
+5V 2 1 2 3
CH411DPT D1
1.1A/6V_POLY CRT
6
L3 BLM15BA470SS1D_4 CRT_RED_L 1 11 T32
8 INT_CRT_RED
7
L2 BLM15BA470SS1D_4 CRT_GRE_L 2 12
8 INT_CRT_GRE
D 8 D
L1 BLM15BA470SS1D_4 CRT_BLU_L 3 13
8 INT_CRT_BLU
9
4 14
R6 C9 R4 C7 R2 C4 C5 C6 C8 10
5 15
150/F_4 10P/50V_4 150/F_4 10P/50V_4 150/F_4 10P/50V_4 10P/50V_4 10P/50V_4 10P/50V_4

17
DFDS15FR039
DSUB-070546FR015S272-15P-V-SMT
U21
5V_CRT2 1 16 CRT_VSYNC_Q R382 27/F_4 CRT_VSYNC_R L21 BLM18BA220SN1D CRT_VSYNC_L
VCC_SYNC SYNC_OUT2 CRT_HSYNC_Q R381 27/F_4 CRT_HSYNC_R L20 BLM18BA220SN1D CRT_HSYNC_L
14
SYNC_OUT1
+3V 7
C501 0.22U/10V_4 VCC_DDC
8
BYP C513 C509
15 INT_CRT_VSYNC 8
5V_CRT2 SYNC_IN2 5V_CRT2
2 13 INT_CRT_HSYNC 8
VCC_VIDEO SYNC_IN1 10P/50V_4 10P/50V_4
R375 R379
CRT_RED_L 3 10 INT_DDCCLK
CRT_GRE_L VIDEO_1 DDC_IN1 INT_DDCDAT 2.7K/J_4 2.7K/J_4
4 11
CRT_BLU_L VIDEO_2 DDC_IN2
5
VIDEO_3 CRTDCLK
9
DDC_OUT1 CRTDDAT
6 12
GND DDC_OUT2
CM2009
+3V C503 C510
+5V +3V
10P/50V_4 10P/50V_4

C13 C508 8 INT_DDCCLK INT_DDCCLK R1 2.2K/J_4

0.1U/10V_4 0.1U/10V_4 8 INT_DDCDAT INT_DDCDAT R3 2.2K/J_4

C C
TXC_HDMI-

TXC_HDMI+ INT-HDMI
TX0_HDMI- PLACE AC CAP
TX0_HDMI+
CLOSE TO CONNECTOR
INT_HDMI_TXCN C311 0.1U/10V_4 TXC_HDMI-
8 INT_HDMI_TXCN
TX1_HDMI-
INT_HDMI_TXCP C312 0.1U/10V_4 TXC_HDMI+
8 INT_HDMI_TXCP
TX1_HDMI+
INT_HDMI_TXDN0 C327 0.1U/10V_4 TX0_HDMI-
8 INT_HDMI_TXDN0
TX2_HDMI-
INT_HDMI_TXDP0 C329 0.1U/10V_4 TX0_HDMI+
8 INT_HDMI_TXDP0
TX2_HDMI+
INT_HDMI_TXDN1 C313 0.1U/10V_4 TX1_HDMI-
+5V 8 INT_HDMI_TXDN1
619/F_4

619/F_4

619/F_4

619/F_4

619/F_4

619/F_4

619/F_4

619/F_4

R269 INT_HDMI_TXDP1 C318 0.1U/10V_4 TX1_HDMI+

8 INT_HDMI_TXDP1
100K_4 PLACE PULL DOWN RESISTORS CLOSE TO
INT_HDMI_TXDN2 C320 0.1U/10V_4 TX2_HDMI-
DIFFERENTIAL PAIRS CONNECTED TO SOLID 8 INT_HDMI_TXDN2
CS41002JB20 GROUND FLOOD WHICH IS CONTROLLED INT_HDMI_TXDP2 C323 0.1U/10V_4 TX2_HDMI+
8 INT_HDMI_TXDP2
BY THE FET
2

R248

R244

R253

R252

R232

R227

R215

R212

AVOID STUBS TO ALL DIFFERENTIAL TRACES

Q10
1 3
2N7002E

+3V
D5
HDMI CONN
+5V_HDMIC_R 3 2 +5V_HDMIC
R194 CN7
R192 20
B 2.2K/J_4 CH411DPT +5V TX2_HDMI+ SHELL1 B
1 21
Q8 2.2K/J_4 +3V TX2_HDMI- D2+ SHELL2
3 22
2

2N7002E TX1_HDMI+ D2- SHELL3

4 23
*BAV99W TX1_HDMI- D1+ SHELL4
6
1 D1-
8 INT_HDMI_SCL 1 3 R191 33/J_4 HDMI_SCLK TX0_HDMI+ 7
3 R519 TX0_HDMI- D0+
9
10K_4 +3V D0- +5V
2
2 D2 Shield
R521 5
C308 D3 D1 Shield
8
*22P/50V/NPO TXC_HDMI+ D0 Shield
8 INT_HDMI_HPD 10 11
+3V R513 TXC_HDMI- CK+ CK Shield
12 17

1
10K_4 CK- GND
*0/F_4 F8
+5V_HDMIC_R FUSE1A6V_POLY
R213 2 HDMI_SCLK 15 13
+5V HDMI_HPD_EC# 31 DDC CLKCE Remote
R199 HDMI_SDATA 16 14

2
3
2.2K/J_4 DDC DATA NC
Q9 2.2K/J_4 Q30
2

2N7002E 2N7002K
1

*BAV99W 2 HP_DET 18 +5V_HDMIC

HDMI_SDATA 1 +5V
8 INT_HDMI_SDA 1 3 R198 33/J_4
3
Q29
2 2N7002K R502 19
HDMI connector

1
C310 D4 HP DET C637 C636
20K/J_4
*22P/50V/NPO *0.1U/10V_4 *1U_6
HDMI CONN
DFHD19MR109
HDMI-C12825-11908-L-19P-V

A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
CRT CONN/HDMI
Date: Tuesday, September 28, 2010 Sheet 24 of 41
5 4 3 2 1
 5 4 3 2 1

6$7$+'' 6$7$2''
CN8
25
1
GND1
TXP
TXN
2
3
SATA_TXP0 9
SATA_TXN0 9
ODD CONN
D GND2 4 D
5 SATA_RXN0_C C452 0.01U/25V_4 CON7 R175 1K/J_4
RXN SATA_RXN0 9
6 SATA_RXP0_C C448 0.01U/25V_4 1 8
RXP SATA_RXP0 9 GND DP 3A/32VS_1206
F2
GND3 7
2 9 ODD_5V
80 mils 1 2
9 SATA_TXP3 TX VCC5 +5V
3.3V 8 9 SATA_TXN3 3 TX# VCC5 10
9 f3_18x1_52-2_665
3.3V C276 C279 C287
3.3V 10 4 GND MD 11
11 0.1U/10V 0.1U/10V 10U/10V_8
GND 0.01U/25V_4 C290 SATA_RXN3_C
GND 12 9 SATA_RXN3 5 RX# GND 12
13 0.01U/25V_4 C289 SATA_RXP3_C 6 13
GND
5V 14 0.94A(80mils) +5V_SATA
9 SATA_RXP3 RX GND
GND 14
5V 15 7 GND GND 15
5V 16 GND 16
GND 17 GND 17
25 XX RSVD 18
26 XX GND 19
20 +5V_SATA +5V
12V F3 2A/63VS_1206
23 XX 12V 21
24 XX 12V 22 1 2

C435 C432 C439

SATA_HDD SLS-13DD1G
sata-127072fr022g212zr-22p-r *0.1u/10V_4 0.1u/10V_4 10u/10V_8
C DFHS22FR183 DFHS13FR026 C
bat-sls-13dd1g-13p-r-smt

H6 H23 H20 H12 H8 H18

FH1 FH1 FH1 H11 H14 H16 H7 H9 *FH1 *FH1 *FH1
FH1 FH1 FH1 FH1 FH1
1

1
1

1
B H-TC100BC256D59P2 H-BC197D142PB H-BC197D142PB H-C217D118P2 H-C315D126P2 H-C315D126P2 B
H-BC217I95D55PB
H-BC217I95D55PB H-TC217BC248D142P2 H-TC217BC248D142P2 H-TC217BC248D142P2

H24 H26
H27 H3 H13 H29 *HG-C295D126P2 *HG-FH5-MB-1-D126P2
*FH1 *FH1 *FH1 *FH1 2 5 2 5 CPU Socket H5 H10 H22
3 6 3 6 *HG-MS15-3 *HG-MS15-2 *HG-TC315BC350D126P2
4 7 4 7 H17 2 5 2 5 2 5
1 3 3 6 3 6 3 6
2 4 4 7 4 7 4 7
8
1
9

8
1
9
1

8
1
9

8
1
9

8
1
9
H-C98D98N H-C98D98N H-MS15-1 H-O157X98D157X98N H19 H1
*HG-C315D126P2 *HG-C315D126P2
2 5 2 5 H28 H25 H4 H15
3 6 3 6 *HG-C315D126P2 *HG-C315D126P2 *HG-C315D126P2 *HG-MS15-3
4 7 4 7 2 5 2 5 2 5 2 5
3 6 3 6 3 6 3 6
4 7 4 7 4 7 4 7
8
1
9

8
1
9

8
1
9

8
1
9

8
1
9

8
1
9
A A

H21 H2
*HG-C236D126P2 *HG-C315D126P2
2 5 2 5
3 6 3 6 Quanta Computer Inc.
4 7 4 7
PROJECT : FH5
8
1
9

8
1
9

Size Document Number Rev

1A
HDD/ ODD
Date: Monday, September 27, 2010 Sheet 25 of 41
5 4 3 2 1
 5 LAN_XTAL2 4 3 2 1

LAN +1.05V_LAN
1
R28
2
*510

+1.05V_LAN VDD33 VDD33

CLK_25M_LAN 10

VDD33
X'tal 25MHz
LAN_XTAL2
LAN EEPROM(DEL)
26
R21
R35 2.49K/F VDD33 PCIE_CLKREQ_LAN#
1 2 1M/F_4
R80 *10K Y2
D LAN_XTALI 2 1 D

LAN_XTAL2_R
PCIE_WAKE# 1 2
VDD33

LAN_XTALI
R68 *10K 25MHz

R34 C19 C20

1K/J_4
LED1_EESK T39 27P/50_4 27P/50_4
Transformer
R53 75/F_8 TXCT0
L22
TXCT0
MCT0 24
U2 R72 75/F_8 TXCT1

49
48
47
46
45
44
43
42
41
40
39
38
37
1 TCT0
+1.05V_LAN_S R79 75/F_8 TXCT2 23 RJ45-TX0+
R86 75/F_8 TXCT3 MDI0+ TX0+
GND 2

LED1/EESK
RSET

GPO/SMBALERT
AVDD33

AVDD1
CKXTAL2
CKXTAL1

LED0
VDD3
AVDD33(NC)

AVDD3(AVDD1)
VDD1(NC)
VDD33 TD0+ RJ45-TX0-
TX0- 22
VDD33 MDI0- 3
+1.05V_LAN C41 TD0- TXCT1
MCT1 21
R51 1000P 4
MDI0+ 0 3KV TCT1 RJ45-TX1+
1 MDIP0 SROUT1 36 R51 For Enable Switch Regulator. TX1+ 20
MDI0- 2 35 1808 MDI1+ 5
3
MDIN0 VDDSR
34
R403 For Disable Switch Regulator. TD1+
19 RJ45-TX1-
MDI1+ AVDD1(NC) VDDSR Enable +1.05VLAN_S R403 *0 MDI1- TX1-
4 MDIP1 ENSR 33 6 TD1-
MDI1- 5 32 EEDI_SDA 2 1 18 TXCT2
MDIN1 EEDI/SDA LED3_EDO R54 10K C110 *6.8P MDI3+ MCT2
6 AVDD1(NC) LED3/EDO 31 T2 7 TCT2
MDI2+ 7 RTL8111EL 30 EECS_SCL 2 1 C115 *6.8P MDI3- 17 RJ45-TX2+
MDI2- MDIP2(NC) EECS/SCL R64 10K C88 *6.8P MDI2+ MDI2+ TX2+
8 MDIN2(NC) DVDD1 29 +1.05V_LAN 8 TD2+
VDD33 9 28 C96 *6.8P MDI2- 16 RJ45-TX2-
AVDD1(NC) LANWAKEB PCIE_WAKE# 8,32 TX2-
C MDI3+ 10 MDIP3(NC) VDD3 27 VDD33 C62 *6.8P MDI1+ MDI2- 9 TD2-
C
MDI3- 11 26 ISOLATE# C72 *6.8P MDI1- 15 TXCT3
MDIN3(NC) ISOLATEB C53 *6.8P MDI0+ MCT3
SMBDATA(NC)

12 AVDD3(NC) PERSTP 25 PLTRST# 4,10,16,28,31,32 10 TCT3

SMBCLK(NC)

C57 *6.8P MDI0- 14 RJ45-TX3+

REFCLK_M

TX3+
REFCLK_P

C49 MDI3+
CLKREQB

Check point: 0.01U

11 TD3+ RJ45-TX3-
Reserver for EMI 13
GNDTX
DVDD1

EVDD1

1. LOM_CLK_REQ# and PCIE_WAKE# needsto be pull up TX3-

HSON
HSOP

+3V 25 MDI3- 12
HSIN
HSIP

+1.05V_LAN TD3-
by PCH side LFE9276C-R
2. PCIE_TX must have AC cap at PCH side
13
14
15
16
17
18
19
20
21
22
23
24

R405
1K/F
RJ45
+1.05V_LAN VDD33
R404 *100/F
CON6
ISOLATE#
10 PCIE_CLKREQ_LAN# LAN_PCIE_PWR_CTRL# 31
RJ45-TX3-
PCIE_RXN6_R
PCIE_RXP6_R

R406 RJ45-TX3+ 8
15K/F C44 C46 RJ45-TX1- 7
10 PCIE_TXP6_LAN 2 1 6
1

R81 4.7U 0.1U RJ45-TX2-

10 PCIE_TXN6_LAN 5
D14 *RB501V-40 6.3 10 RJ45-TX2+
10K X5R X5R RJ45-TX1+ 4 12
10 CLK_PCIE_LANP 3 11
Isolate# is for power saving. RJ45-TX0-
10 CLK_PCIE_LANN 2 10
C86 0.1U RJ45-TX0+
10 PCIE_RXP6_LAN
2

1 9
B 10 It needs to pull low when system state in S3, S4, and S5. B
C77 0.1U GND_LAN
10 PCIE_RXN6_LAN
10
pull high when system at S0 state RJ45
rj45-c100v5-10806-l-8p-luv
Place Close to LAN chip, DFTJ08FR157

R400 0_6
pin 34 and 35

LAN Power VDD33 +3V_S5

VDD33 R95 0_6

+1.05V_LAN_S
+1.05V_LAN
+1.05V_LAN R32 0_6

IND SMD 4.7UH 30% 1A( LQH32PN4R7NN0L)

R33 0_6

L5
C532 C87 C526 C525 C533 C538 C530 C31 C32 C64 C30 C29 C535
C25 C528 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U C537 C539 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U GND_LAN
4.7U 0.1U 10 10 10 10 10 10 10 1U 0.1U 10 10 10 10 10 10
6.3 10 X7R X7R X7R X7R X7R X7R X7R 6.3 10 X5R X5R X5R X5R X5R X5R
X5R X7R X5R X5R

A A

For L50, C420, C62 need to check layout guild Close to pin 3, 6, 9, 13, 29, 41 and 45 Place connect to Pin21 Place Close to LAN chip, pin 12, 27, 39, 42, 47 48 Quanta Computer Inc.
REQ by layout PROJECT : FH5
Size Document Number Rev
1A
LAN_RTL8111E-GR/RJ45
Date: Monday, September 27, 2010 Sheet 26 of 41
5 4 3 2 1
 5 4 3 2 1

+3V_S5
C484
1

R359
Q18
3

+ C483
VCC3_BT

C482
VCC3_BT

BuleTooth (BTM) 27

2
0.33u/10V_6 47K_4 AO3413
2.2u/6.3V_6 1000p/50V_4
CON4

1
L15 *WCM-2012-900T 2

1
C465 C468 C471 2 2
10 USBP9+ 1 1 3
D 10 USBP9- 3 3 4 4 4 D
R357 4.7K_4 0.1U/10V 10U/6.3V_6 *10U/6.3V_6 5
31 BT_ON#

2
6

2
22_6 Bluetooth CN
87213-0600-6p-l
VCC3_BT 3 1

R356
2N7002E 8/23 Change BT on circuit.
Q17

USB Connector
USB Charge +5VPCU

R555
22.1K/F_4
C677 1 2 10u/6.3V_6 USB_OC0# 10

C680 2 1 0.1u/16V_4

17
16
15
14
13
U34 +5V_USB0
+5V_USB0 CON10

GND
FAULT
PwPd
ILIM0
ILIM1
C C
L34
DLW21HN900SQ2L 60mils 1 4
USBP0_R- USBP0_C- 1 4
1 IN OUT 12 3 3 4 4 2 2 GND 5
2 11 USBP0_R- USBP0_R+ 2 2 USBP0_C+
10 USBP0- DM_OUT DM_IN USBP0_R+ 1 1 3 3 GND 6
10 USBP0+ 3 DP_OUT DP_IN 10 GND 7
R551 2 1 10K/F_4 4 9 8
ILIM_SEL N/C GND
+5VPCU U35 USB

CTL1
CTL2
CTL3
USBP0_C- USBP0_C+ USB-020173MR004XX52ZR-4P-R-V

EN
1 Z1 Z4 6
2 5 +5V_USB0
GND VB

1
TPS2540 3 4

5
6
7
8
Z2 Z3
R556 *IP4220CZ6
CTL1 CTL2 CTL3 NOTE R582 *0/J_4 100K_4
31 USBON Place close to the CONN side

2
ES(PG1.1) 0 1 0 SDP(S3/S5)battery 12%‫א‬Հ +5VPCU R581 1 2 100K_4
+5V
DCP, Auto-detect(S3/S5)battery +5V_USB1 CON8
0 1 1 12%‫א‬Ղ or AC mode

1
R554 0/J_4 L29
31 USB0_WORK
DLW21HN900SQ2L 60mils 1 4
R552 USBP1_R- 1 4
10 USBP1- 3 3 4 4 2 2 GND 5
1 1 0 SDP(S0) 100K_4 2 2 USBP1_R+
10 USBP1+ 1 1 3 3 GND 6
7

2
GND
GND 8
B B
USB
R573 U32 USB-020173MR004XX52ZR-4P-R-V
+5VSUS +5V_USB1 10K/J_4 USBP1_R- 1 6 USBP1_R+
Z1 Z4 +5V_USB1
2 GND VB 5
F9 3 4
MINI_PS-HS1 Z2 Z3
2 1 *IP4220CZ6

USB0_WORK Mode C653 + C657

C658 8/30 Pin Define Mirror
4.7u/10V_6 150U/10V 0.1u/10V_4 +5V_USB2
Low - S5 - 1.8A DCP, Auto-detect L12
60mils 6
DLW21HN900SQ2L 5
High - S0/S3 - 1.5A CDP, BC Spec 1.1 2 1 USBP2_R- 4
10 USBP2- 2 1 USBP2_R+
3 4 3
USB wake up with S3 == PCH HOST 10 USBP2+ 3 4
2
1
+5VSUS +5V_USB2 JP7
DFFC06FR062
F10 88502-06XX-6P-L-SMT
MINI_PS-HS1 U12 88501-0601-6P-L-AQ1
R321 mA USBP2_R- USBP2_R+
2 1 1 Z1 Z4 6
2 5 +5V_USB2
C681 GND VB
OC 100k ohm 480 C674
3 Z2 Z3 4
A A
limitation 4.7u/10V_6 + *IP4220CZ6
22.1k ohm 2171 Applied Now C662 0.1u/10V_4
150U/10V

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
USB/BLUE TOOTH
Date: Tuesday, October 05, 2010 Sheet 27 of 41
5 4 3 2 1
 5 4 3 2 1

MINI CARD (WLAN)

28
8/16 Change Debug Pin define to NB4 use. +1.5V +1.5V_WLAN

R16 *0_8

RF_EN#
PLTRST# R361 0_4
D D
R369 0_4 +3V +3V +3V
10 CLK_PCI_LPC
CON5
51 52
R360 *0_4 CL_RST1#_WLAN Reserved +3.3V
10 CL_RST1# 49 50
R363 *0_4 CL_DATA1_WLAN Reserved GND R370
10 CL_DATA1 47 48
R366 *0_4 CL_CLK1_WLAN Reserved +1.5V
10 CL_CLK1 45 46 *10K_4
Reserved LED_WPAN#
43 44
Reserved LED_WLAN# R367 *0_4
41 42 LED_WLAN# 29,31
Reserved LED_WWAN# L19 *WCM-2012-900T
39 40
Reserved GND
37 38 2 1
Reserved USB_D+ 2 1 USBP3+ 10
35 36 3 4
GND USB_D- 3 4 USBP3- 10
10 PCIE_TXP1 33 34
PETp0 GND SMB_RUN_DAT_R R374 *0_4
10 PCIE_TXN1 31 32
PETn0 SMB_DATA SMB_RUN_CLK_R R377 *0_4 SMB_RUN_DAT 10,14,15
29 30
GND SMB_CLK SMB_RUN_CLK 10,14,15
27 28
GND +1.5V
10 PCIE_RXP1 25 26
PERp0 GND
10 PCIE_RXN1 23 24
PERn0 +3.3Vaux PLTRST#_R R5 *0_short PLTRST#
21 22 PLTRST# 4,10,16,26,31,32
GND PERST#
19 20 RF_EN# 31
Reserved Reserved
T33 17 18
Reserved GND
15 16 LFRAME# 9,31
GND Reserved
10 CLK_PCIE_WLANP 13 14 LAD3 9,31
REFCLK+ Reserved
10 CLK_PCIE_WLANN 11 12 LAD2 9,31
REFCLK- Reserved
9 10 LAD1 9,31
GND Reserved
10 PCIE_CLKREQ_WLAN# 7 8 LAD0 9,31
CLKREQ# Reserved
T34 5 6
Reserved +1.5V
T35 3 4
Reserved GND
T38 1 2
WAKE# +3.3V
67910-0002
DFHD52MS049
MIPCIEXP-AS0B22X-S80N-52P-SMT

C C

+3V

C22 C486 C507 C496 C495

*10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4

Mini Card2-3G(MNC)

+3V
+1.5V_3G
+3V
+3V

1
CN5 C564 C568 C558 C561 C560 C554
51 52 C690
Reserved +3.3V 10u/10V_8@3G 0.1u/10V_4@3G 0.1u/10V_4@3G 0.1u/10V_4@3G 0.47u/6.3V_4@3G *10p/50V_4@3G *56p/4
49 50

2
Reserved GND
47 48
Reserved +1.5V
45 46
Reserved LED_WPAN#
43 44
Reserved LED_WLAN#
41 42
B Reserved LED_WWAN# B
39 40
Reserved GND USBP4+
37 38 USBP4+ 10
Reserved USB_D+ USBP4-
35 36 USBP4- 10
GND USB_D-
10 PCIE_TXP2 33 34
PETp0 GND SMB_RUN_DAT_R +1.5V +1.5V_3G
10 PCIE_TXN2 31 32
PETn0 SMB_DATA SMB_RUN_CLK_R
29 30
GND SMB_CLK R411 *0_8@3G
27 28
GND +1.5V
10 PCIE_RXP2 25 26
PERp0 GND C571 C559 C574
10 PCIE_RXN2 23 24
PERn0 +3.3Vaux 3G_PLTRST_R R118 *0_short PLTRST# C570
21 22
GND PERST# *1n/50V_4@3G *0.1u/10V_4@3G *10u/10V_8@3G *56p/4
19 20 3G_EN 31
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND
15 16 UIM_VPP
GND UIM_VPP UIM_RST
10 CLK_PCIE_WWANP 13 14
REFCLK+ UIM_RST UIM_CLK
10 CLK_PCIE_WWANN 11 12
REFCLK- UIM_CLK UIM_DATA +3V
9 10
GND UIM_DATA UIM_PWR
10 PCIE_CLKREQ_WWAN# 7 8
CLKREQ# UIM_PWR
5 6
Reserved +1.5V C569
3 4
GND

GND

Reserved GND + C575 C578

1 2
WAKE# +3.3V *100u/6.3V_3528@3G
0.1u/10V_4@3G 10u/10V_8@3G
53

54

67910-0002@3G
DFHD52MS049
MIPCIEXP-AS0B22X-S80N-52P-SMT

JSIM1
UIM_CLK 6 1 UIM_PWR C551 *27p/50V_4@3G +3V
CLK(C3) GND(C5) UIM_PWR
7 2
N/A(C8) VCC(C1) UIM_VPP
8 3
N/A(C4) VPP(C6) UIM_RST U24
9 4
CT RST(C2) UIM_DATA UIM_DATA C552 *10p/50V_4@3G UIM_RST UIM_VPP
A 10 5 1 6 A
CD DATA(C7) CH1 CH4
GND
GND

GND
GND

2 5
VN VP UIM_PWR
SIM-Conn-CE015@3G UIM_RST C550 *27p/50V_4@3G UIM_CLK 3 4 UIM_DATA
13
11

12
14

DFHS10FR381 CH2 CH3

2

sim-ce01x-3-14p-smt C553 *CM1293-04SO@3G C555

2

C549
*10p/50V_4@3G *33p/50V_4@3G
1

*1u/10V_6@3G
1

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
MINI CARD(WLAN/3G)
Date: Monday, September 27, 2010 Sheet 28 of 41
5 4 3 2 1
 5 4 3 2 1

Touch Pad
Keyboard(KBC)
+5V_TP 40mils
F7
+5V SWL# 3
4
SW3
sw-tme-532-v-6p
DHP00533B00
1
2
29
5
1 2 6

C632 1.1A/6V_POLY C633

0.1u/10V_4 *0.1u/10V_4

D D
+5V
CON3
SWL#
12
11
CN1 10 DHP00533B00
9 R423 R424 SW2 sw-tme-532-v-6p
27
MY0 8 SWR# SWR#
31 MY0 1 3 1
MY1 7 4.7K_4 4.7K_4
31 MY1 2 4 2
MY2 6
31 MY2 3 5
MY3 5 TPCLK_8 L23 NHCB2012KF-131T10/1A/130ohm_8
31 MY3 4 TPCLK 31 6
MY4 4 TPDATA_8 L24 NHCB2012KF-131T10/1A/130ohm_8
31 MY4 5 TPDATA 31
MY5 3
31 MY5 6
MY6 2
31 MY6 7 +5V_TP
MY7 1 C630 C631
31 MY7 8
MY8 9 TOUCH PAD 12P
31 MY8
MY9 10 10p/50V_4 10p/50V_4
31 MY9
MY10 11
31 MY10
MY11 12
31 MY11
MY12 13
31 MY12
MY13 14
31 MY13
MY14 15
31 MY14
MY15 16
31 MY15
MY16 17
31 MY16
MY17 18
31 MY17
MX0 19
31 MX0
MX1 20
31 MX1
MX2 21
31 MX2
MX3 22
31
31
MX3
MX4
MX4
MX5
23
24
8/23 Change TP to 12 pin conn.
31 MX5
MX6 25
31 MX6
MX7 26
31 MX7
28

KB_CONN
C 88513-2641-26P-L-smt C
DFFC26FR039

For EMI Reserve Caps for debug

+3V

MY3
CP6
7 8
CP1
8 7 MX7
LED
MY2 5 6 6 5 MX6
MY1 3 4 4 3 MX5 R567
MY0 1 2 2 1 MX4 10K_4
*100p_8P4R *100p_8P4R

CP3 CP4 SATA_LED

MY15 7 8 7 8 MY8
MY14 5 6 5 6 MY9
Blue

3
MY13 3 4 3 4 MY10

2
MY12 1 2 1 2 MY11 Q37 LTST-C190TBKT/BLUE
2 DDTC144EUA-7-F LED4
9 SATA_ACT#
*100p_8P4R *100p_8P4R SATA_LED#_D R572 1 220_6
HDD/ODD 1 3 1 2 2 +5V
CP2 CP5 Q38 BEBL0088Z00

1
MX0 8 7 7 8 MY4 2N7002E
MX1 6 5 5 6 MY5
MX2 4 3 3 4 MY6
MX3 2 1 1 2 MY7 Blue
*100p_8P4R *100p_8P4R
R565
CAPSLED# 1N4148WS LTST-C190TBKT/BLUE LED2 1 1 220_6
CAPS LED 31 CAPSLED#
D18 BEBL0088Z00
2 2 +5V

B
Blue B

R566
NUMLED# 1N4148WS LTST-C190TBKT/BLUE LED3 1 1 220_6
NUM LED 31 NUMLED#
D19 BEBL0088Z00
2 2 +5V

Blue
R569
LED_WLAN# 1N4148WS LTST-C190TBKT/BLUE LED6 1 1 220_6
WLAN 28,31 LED_WLAN#
D21 BEBL0088Z00
2 2 +5V

Blue
AMBER
BE0R0025Z00 R570
BAT_LED1# LTST-C191KFKT/AMBER LED1 1 2 2 1 220_6 +3VPCU
31 BAT_LED1#
R571
Battery 31 BAT_LED0#
BAT_LED0# 1N4148WS LTST-C190TBKT/BLUE LED7 1 2 2 1 220_6 +5V
D22 BEBL0088Z00

Blue

Blue
R568 220_6
PWRLED0# 1N4148WS LTST-C190TBKT/BLUE LED5 1 2 PWRLED0_R# 2 1 +5VSUS
31,32 PWRLED0#
D20 BEBL0088Z00
Power Status
A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
KB/TOUCH PAD/LED
Date: Monday, September 27, 2010 Sheet 29 of 41
5 4 3 2 1
 A B C D E

ALG_LI_VR_R

MIC
30
ALG_LI_VR_L
GNDAUD
EMI Codec ALC269-VB
C479 AR10 AR9
Rc Re
*10P/50V_4 2.2K/F_4 2.2K/F_4 ALG_LI_VR_L AR25 VB@0/J_4 AR26 *VA@0/J_4 GNDAUD
ALG_MIC_SENSE
8 5
4 AC6 4.7U/10V/8
Cd
3 MICIN_JACK_R AL1 HCB1608KF-601T10 AR6 1K/F_4 1 2ALG_MAIN_IN_R ALG_LI_VR_L AR24
Rd *VA@0/J_4
AC8 4.7U/10V/8 AC24 VB@10U/6.3V/X5R/0805
6
2 MICIN_JACK_L AL2 HCB1608KF-601T10 AR7 1K/F_4 1 2ALG_MAIN_IN_L
U23 Ra Rb Rc Rd Re Ca Cb Cc Cd Da La Ua
7 1 GND_MIC ALG_LI_VR_R Close to CODEC
GNDAUD
4 ACON2
ALC269Q-VA 4
DFTJ06FR253 ALG_HP_L Close to CODEC
phjk-2sj-s351-015-8p-v AR13
0_6 AC21 AC20
ALC269Q-VB ALG_HP_R AC16 AC7
0603 *100P/50V/NPO *100P/50V/NPO 0.1U/10V_4
GNDAUD 10U/6.3V/X5R/0805
Close to CODEC ALG_VREF
AC14 AC19
GNDAUD GNDAUD GNDAUD AC17 AC39
2.2U/16V/X5R 2.2U/16V/X5R AR8 0.1U/10V_4
PWR_AUD 2.2U/16V/X5R
0_6
Close to CODEC
U36

HP GNDAUD ALC269Q-VA6-GR GNDAUD

36

35

34

33

32

31

30

29

28

27

26

25
EMI AL000269007

HP-OUT-L

MIC1-VREFO-L

AVSS1
CBN

HP-OUT-R

MIC1-VREFO-R

AVDD1
CPVREF

VREF
MIC2-VREFO
CBP

CPVEE
C480 Close to CODEC
*10P/50V_4 GNDAUD
8 5 ALG_HP_SENSE AC18 10U/6.3V/X5R/0805
4 37 24
HPOUTR_CN AL3 HCB1608KF-601T10ALG_HEADPHONE_RPR137 47R/F_4 ALG_HP_R PWR_5VAMP AVSS2 LINE1-R
3
6 GNDAUD AC12 0.1U/10V_4 38 23
HPOUTL_CN AL4 HCB1608KF-601T10ALG_HEADPHONE_LPR138 47R/F_4 ALG_HP_L L36 AVDD2 LINE1-L
2
7 1 GND_HP PVDD2_AC 39 22 ALG_MAIN_IN_R
BLM18PG121SN PVDD1 MIC1-R
AL000269007
ACON3 AC9 AC10 ALG_SPKOUTL+ 40 21 ALG_MAIN_IN_L
DFTJ06FR253 0.1U/10V_4 SPK-L+ MIC1-L
phjk-2sj-s351-015-8p-v 10U/6.3V/X5R/0805 ALG_SPKOUTL- 41 20
AC23 AC22 AR12 AR11 SPK-L- MONO-OUT
AR14 100P/50V/NPO 100P/50V/NPO *1K/F/4 *1K/F/4 42 19 PR225 20K/F/4 GNDAUD
*short PVSS1 JDREF
43
PVSS2 Sense B
18 T41 Close to CODEC
ALG_SPKOUTR- 44 17
GNDAUD GNDAUD GNDAUD GNDAUD GNDAUD PWR_5VAMP SPK-R- MIC2-R
3 3
ALG_SPKOUTR+ 45 16
L35 SPK-R+ MIC2-L
PVDD1_AC 46 15
BLM18PG121SN PVDD2 LINE2-R
AC36 AC37 EAPD#

GPIO0/DMIC-DATA
47 14
SPDIFO2/EAPD LINE2-L

GPIO1/DMIC-CLK
0.1U/10V_4
10U/6.3V/X5R/0805 48 13 SENSE_A AR22 39.2K/F_4 ALG_HP_SENSE
SPDIFO Sense A

SDATA-OUT

SDATA-IN
49 AR23 20K/F_4 ALG_MIC_SENSE

DVDD-IO

PCBEEP
PGND

RESET#
BIT-CLK
DVDD1

DVSS2

SYNC
Close to CODEC

PD#
SPKR AGND

ACZ_SDIN0_R 8

10

11

12
DGND
ACON1
4 SPKOUTL-_CN AR1 0_4 ALG_SPKOUTL- GNDAUD
4 SPKOUTL+_CN AR2 0_4 ALG_SPKOUTL+
5 3 33 DMIC_DAT
5 3 SPKOUTR+_CN AR3 0_4 ALG_SPKOUTR+ AMP_PD# AR5
6 2
6 2 SPKOUTR-_CN AR4 0_4 ALG_SPKOUTR- *short
1 33 DMIC_CLK
1
TUNER-PWR AC3 AR19 +5V PWR_5VAMP
9 ACZ_SDOUT
DFHD04MR088 470P/50V/X7R 33/J_4
88263-040L-4P-L AC1 AR20 22/J_4 ACZ_BITCLK_C AR21
9 ACZ_BITCLK
470P/50V/X7R AC4 *short
9 ACZ_SDIN0
470P/50V/X7R
9 ACZ_SYNC
AC2 ACZ_RST#
9 ACZ_RST#
470P/50V/X7R
AC26 AC33 AC34 ALG_BEEP_IN
10p/50V_4 *22P/50V_4 *22P/50V_4

50 50 +3V AR18 0/J_4

2
BEEP AC27
*10P/50V/NPO
AC32
*22P/50V/NPO
2

+3V
AR16 18K/4 ALG_BEEPIN_B ALG_BEEP_IN AC35 AC30
9 SPKR
AC29 0.1U/10V_4 10U/6.3V/X5R/0805
0.1U/25V/X7R C685
0.1U/25V/X7R

AC28 AR17 AC31

100P/50V/NPO 1K/F_4 *0.01U/50V/X7R

DGND plane AGND plane

VOLMUTE +5V
R562
10K/F_4
AMP_PD#
La L18

VB@BLM18PG121SN
AC15
1000P/50V/X7R
3

AC11
+5V Da D7 PWR_AUD 1000P/50V/X7R
R561 MUTE_C2 2 Q36 *VA@1SS355
10K/F_4 DTC144EUA U17 AC13
Q35 1 4 1000P/50V/X7R
DTC144EUA SHDN VO
1

3 1 2 AC38
GND 1000P/50V/X7R
3
VIN SET
5 Ra PR136
AC5
1 1
AR15 C469 C467 *VA@G913-C *VA@28K/F/4 1000P/50V/X7R
10K/F_4 *VA@10U/6.3V_8 ADJ C476
Ua
2

MUTE_C1 *VA@0.1u/10V_4 *VA@10U/6.3V_8

+3V Ca Cb
EAPD# AD3 1 2 RB501V-40 AC25 PR135 GNDAUD
*0.1U/10V_4
Cc
31 VOLMUTE#
AD1 1 2 RB501V-40 Rb *VA@10K/F/4

ACZ_RST# AD2 1 2 *RB501V-40 Vo=1.25*(1+Ra/Rb)

GNDAUD GNDAUD Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
CODEC (ALC269)
Date: Monday, September 27, 2010 Sheet 30 of 41
A B C D E
 5 4 3 2 1

L14 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU 3G_EN R331 *10K_4

+3V
C460 C457

0.1u/10V_4 10u/6.3V_6
+3VPCU
+3VPCU E775AGND
R563 2.2_6 D17 C688 C689
1 2 +3VPCU_EC
BAS316 4.7u/6.3V_6 0.1u/10V_4 MBCLK R327 10K_4
C686 C473 C478 C451 C474 C446 MBDATA R326 10K_4

115

102
19
46
76
88

4
4.7u/6.3V_6 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 U16 +3V_GPU

AVCC

VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C456 10u/6.3V_8 ICM VGACLK R564 2.2K_4
D CLK_PCI_EC VGADATA R350 2.2K_4 D
C453 0.01u/16V_4
3 97 VGA_THERM# R346 *10K_4
9,28 LFRAME# LFRAME GPIO90/AD0 TEMP_MBAT 34
126 98 IGFX_VR_ICC T20
9,28 LAD0 LAD0 GPIO91/AD1 +3V_S5
R355 127 A/D 99 CPU_VCC T21
9,28 LAD1 LAD1 GPIO92/AD2
128 100 CPU_ICC
9,28 LAD2 LAD2 GPIO93/AD3
*22_4 1 R336 0_4 MBCLK2 R324 10K_4
9,28 LAD3 LAD3 ICM 34
CLK_PCI_EC 2 MBDATA2 R325 10K_4
10 CLK_PCI_EC LCLK
101 POWER_SAVE T22
GPIO94/DA0 R343 0_4
C481
8 CLKRUN# 8 GPIO11/CLKRUN D/A GPI95/DA1
105
ODDLED
CPUFAN# 32
+3V
GPI96/DA2 106 T23
*10p/50V_4 11 EC_A20GATE 121 GPIO85/GA20
122 ODD_EJ R332 *10K_4
11 EC_RCIN# KBRST/GPIO86
64 ACIN 34
GPIO01/TB2 PANEL_COLOR ODD_POWER R348 *10K_4
11 EC_EXT_SCI# 29 ECSCI/GPIO54 LPC GPIO02
79 T19
95 NBSWON# 32
GPIO03
33 DLID# 6 GPIO24/LDRQ GPIO04 96
GPIO05 108
30 VOLMUTE# 124 GPIO10/LPCPD GPIO06/IOX_DOUT/RTS1 93 LID# 33
94 IGFX_VR_VCC T17 R349 0_4 H_PROCHOT# 4,36
GPIO07 ODD_POWER
4,10,16,26,28,32 PLTRST# 7 114 T27
LREST GPIO16

3
109 ACPRN T25
GPIO30 Q15
28 RF_EN# 123 GPIO67/PWUREQ GPIO36/CTS1 15 LED_WLAN# 28,29
GPIO41 80 VRON 36
125 17 HWPG PROCHOT_EC 2
9 SERIRQ SERIRQ GPIO42/SCL3B/TCK
GPIO43/SDA3B/TMS 20 SML1ALERT# 10,11
11 EC_EXT_SMI# 9 GPIO65/SMI GPIO44/TDI
21 SLP_S3# 8,32
GPIO 24 R347 2N7002K
GPO47/SCL4 USB0_WORK 27
25 D/C# 34 AKE35FN0N00

1
GPIO50/PSCLK3/TDO S5_ON 100K_4
29 MX0 54 KBSIN0 GPIO51 26 S5_ON 35 2nd AKE35ZN0800
29 MX1 55 KBSIN1 GPIO52/PSDAT3/RDY 27 HDMI_HPD_EC# 24
56 28 C459 *10P/50V_4
29 MX2 KBSIN2 GPIO53/SDA4 LAN_PCIE_PWR_CTRL# 26
C 29 MX3 57 73 SLP_S4# 8,32 C
KBSIN3 GPIO70 PWROK_EC_uR R328 0_4 C463 *10P/50V_4
29 MX4 58 74 EC_PWROK 8,33
KBSIN4 GPIO71 RSMRST#_uR R329 0_4
29 MX5 59 75 RSMRST# 8
KBSIN5 GPIO72 C458 *10P/50V_4 +3VPCU
29 MX6 60 82 MAINON 37,38,40,41
KBSIN6 GPIO75/SPI_SCK
29 MX7 61 KBSIN7 GPO76/SHBM 83 3G_EN 28
84 ODD_EJ T18 U14
GPIO77 SPI_SDI_uR R339 22_4 SPI_SDI_uR_R
29 MY0 53 KBSOUT0/JENK GPIO81 91 EC_PWRBTN# 8 2 SO VDD 8
52 110 Do not use it T24
29 MY1 KBSOUT1/TCK GPO82/IOX_LDSH/TEST
51 112 R340 100K_4 SPI_SDO_uR 5 7 C462
29 MY2 KBSOUT2/TMS GPO84/IOX_SCLK/XORTR USBON 27 SI HOLD
50 107 VGA_THERM#_R R345 *0_4
29 MY3 KBSOUT3/TDI GPIO97 VGA_THERM# 19
49 KB SPI_SCK_uR 6 3 0.1u/10V_4
29 MY4 KBSOUT4/JEN0 SCK WP
29 MY5 48 KBSOUT5/TDO
47 31 +3VPCU R337 10K_4 SPI_CS0#_uR 1 4
29 MY6 KBSOUT6/RDY GPIO56/TA1 CE VSS
29 MY7 43 KBSOUT7 GPIO20/TA2/IOX_DIN_DIO 117 SUSON 38
42 63 W25X40BVSSIG
29 MY8 KBSOUT8 GPIO14/TB1 FANSIG 32
41 C455
29 MY9 KBSOUT9/SDP_VIS +3VPCU
40 TIMER 32 *56p/4
29 MY10 KBSOUT10/P80_CLK GPIO15/A_PWM CONTRAST 33
29 MY11 39 KBSOUT11/P80_DAT GPIO21/B_PWM 118 NUMLED# 29
29 MY12 38 KBSOUT12/GPIO64 GPIO13/C_PWM 62 PWRLED0# 29,32
29 MY13 37 KBSOUT13/GPIO63 GPIO32/D_PWM 65 BAT_LED0# 29
36 22 PANEL_ENG T31
29 MY14 KBSOUT14/GPIO62 GPIO45/E_PWM
35 16 SUSLED# T30 R335
29 MY15 KBSOUT15/GPIO61/XOR_OUT GPIO40/F_PWM/RI1
34 81 *8.2K R334
29 MY16 GPIO60/KBSOUT16 GPIO66/G_PWM CAPSLED# 29
29 MY17 33 66 BAT_LED1# 29 *10K/J_4
GPIO57/KBSOUT17 GPIO33/H_PWM/SOUT1

34 MBCLK
MBCLK 70 GPIO17/SCL1 BIOS Write Protect

3
MBDATA 69
34 MBDATA GPIO22/SDA1

3
10 MBCLK2 MBCLK2 67 SMB 113 T26 Q14 Q13
MBDATA2 GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR
10 MBDATA2 68 14 T43
VGACLK GPIO74/SDA2 GPIO34/SIN1/CIRRXL
19 VGACLK
VGADATA
119 GPIO23/SCL3 IR GPIO46/CIRRXM/TRST
23
PROCHOT_EC
T29 11 BIOS_WP# 2 2
19 VGADATA 120 GPIO31/SDA3 GPO83/SOUT_CR/TRIST 111

*2N7002E

1
B 72 86 SPI_SDI_uR *DTC144EU B
29 TPCLK

1
GPIO37/PSCLK1 F_SDI/F_SDIO1 SPI_SDO_uR_R R341 22_4 SPI_SDO_uR
29 TPDATA 71 87
GPIO35/PSDAT1 F_SDO/F_SDIO0 SPI_CS0#_uR
9 ME_WR# 10
GPIO26/PSCLK2 PS/2 FIU F_CS0
90
SPI_SCK_uR_R R338 22_4 SPI_SCK_uR
27 BT_ON# 11 GPIO27PSDAT2 F_SCK 92

R330 0_4 E775_32KX1 77 30 ECDB_CLOCK +3V

8 PCH_SUSCLK GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN_DIO T28

85 VCC_POR# R333 47K/F_4 +3VPCU

R354 0_4 +1.05V_VTT_EC VCC_POR
12
VCORF

+1.05V_VTT VTT
AGND
GND1
GND2
GND3
GND4
GND5
GND6

4,11 EC_PECI R353 43_4 EC_PECR_R 13 104 VREF_uR R342 0_4 +A3VPCU R358
PECI VREF
10K/J_4
HWPG
NPCE791L C447 C461
93&893&8
5
18
45
78
89
116

103

VCORF_uR 44

*56p/4 *56p/4 D9 1SS355 HWPG

35 SYS_HWPG HWPG
D10 1SS355
40 HWPG_VCCSA
L16 PBY160808T-250Y-N/3A/25ohm_6 D12 1SS355
40 HWPG_1.8V
C687 D8 1SS355
37,40 HWPG_VTT
1u/6.3V_4 D11 1SS355
38 HWPG_1.5V
E775AGND

Power sequence CN3

J1 *SHORT PAD 2 1
+3VPCU 2 1 +3V_S5 4 3 S5_ON_CN3
EC_PWRBTN#_CN3 6 5
R407 R351 *0_4 EC_PWRBTN#_CN3 SUSON_CN3 8 7 +3VPCU
8 EC_PWRBTN#
10 9 +1.5V_SUS
A *10K_4 SW1 R574 *0_4 SUSON_CN3 +3V 12 11 R352 *795@10K_4 A
38 SUSON MAINON 37,38,40,41 S5_ON
14 13 GFX_PWRGD 36
NBSWON# 1 2 16 15
R575 *0_4 EC_PWROK_CN3 EC_PWROK_CN3 VRON 36
3 4 8,33 EC_PWROK 18 17 HWPG
2

5 PLTRST#_CN3 20 19 SYS_PWROK_CN3
D6 6 R576 *0_4 PLTRST#_CN3 +3V_GPU 22 21 dGPU_VRON_CN3
*VPORT_6 4,10,16,26,28,32 PLTRST#
+1.05V_GPU 24 23 +VGPU_CORE
MSK:NTCQ31-AB1G-A160T R577 *0_4 GPU_RST#_CN3 26 25 +1.5V_GPU
16 GPU_RST# GPU_RST#_CN3
1

28 27

R578 *0_4 S5_ON_CN3

30 29
GFXPG 11,16 Quanta Computer Inc.
35 S5_ON
8/10 modify *Power_sequence_30N PROJECT : FH5
R579 *0_4 SYS_PWROK_CN3 Size Document Number Rev
4,8 SYS_PWROK 1A
R580 *0_4 dGPU_VRON_CN3 WPCE791 & FLASH
11,39,41 dGPU_VRON Date: Monday, September 27, 2010 Sheet 31 of 41
5 4 3 2 1
 5 4 3 2 1

NEW CARD
U33 W83L351YG
PW BOARD CON 32
8,31 SLP_S3# 1 STBY# SHDN# 20 SLP_S4# 8,31

+3V 2 19 R549 2K +3V_S5

3.3VIN OC# CON2 C567 0.1U/10V
D 3 18 TPS2231_CLKEN 88501-0401 D
3.3VOUT RCLKEN
C676 0.1U/10V 4 17 +3V_S5 +3V_S5
3.3VIN AUXIN 1
2 PWRLED0# 29,31
PWR_3.3VPEC 5 16 C666 0.1U/10V NBSWON# 31
3.3VOUT NC 3
4
4,10,16,26,28,31 PLTRST# 6 SYSRST# AUXOUT 15 PWR_3.3VPECAUX
DFFC04FR045
7 14 +1.5V 88502-040n-4p-l-smt C566 0.1U/10V
GND 1.5VIN
EXC_RST# 8 13
PERST# 1.5VOUT
CPUSB# 9 12 C661 0.1U/10V
CPUSB# 1.5VIN
CPPE# 10 11 PWR_1.5VPEC

TML
CPPE# 1.5VOUT

qfn20-4x4-5-21p

CPU FAN CTRL

21
AL083351000

C C

+5V
CN2 130805-1 PWR_3.3VPECAUX
FANPWR = 1.6*VSET
GND_1 1
USB- 2 USBP8- 10
U9
VSET >= 1V, Enable FAN_CONN.
USB+ 3 USBP8+ 10

2
4 CPUSB#_CN R161 2 3 +5V_FAN
CPUSB# Q31 10K_4 VIN VO 1
RSV_0 5 GND 5 2
RSV_1 6 DTC144EUEUA-7-F 1 FON# GND 6 3

1
7 SMB_CLK_EXC RC0402 R293 4.7K 7 C215 C213
SMBCLK SMB_DATA_EXC GND
8 PWR_3.3VPECAUX 1 3 4 8 CN6
SMBDATA RC0402 R295 4.7K 31 CPUFAN# VSET GND 10u/10V_8 0.1U/25V/X7R 53398-0310-3P-L
9

2
+1.5V G995P1U DFHD03MR026
+1.5V 10 PWR_1.5VPEC
11 PWAKE# R527 *10_4 AL000991000
WAKE# PCIE_WAKE# 8,26
+3.3VAUX 12 PWR_3.3VPECAUX
13 EXC_RST#
PERST# PWR_3.3VPEC +3V +3V
+3.3V_1 14 PWR_3.3VPEC
+3.3V_2 15
16 EXC_CLKREQ#
CLKREQ# CPPE#_CN
CPPE# 17
18 CLK_PCIE_NEWN 10 R532 C675 R121
REFCLK- R534 100K/J_4
REFCLK+ 19 CLK_PCIE_NEWP 10
20 100K 0.1U/10V
GND_2 100K
B
PERn0 21 PCIE_RXN4 10 31 FANSIG B

5
22 PCIE_RXP4 10 U31
PERp0 EXC_CLKREQ#
GND_3 23 1
PETn0 24 PCIE_TXN4 10 4 PCIE_CLKREQ_NEW# 10
25 PCIE_TXP4 10 EXC_PLLEN#0 2
NC4
NC3
NC2
NC1

PETp0
GND_4 26
3

NL17SZ32DFT2G
3

Q32
30
29
28
27

ncard-13180151-n-26p-l TPS2231_CLKEN 2
DFHD26MR014

C671 2N7002E-T1-E3
R545 BAM70020001
1

1M_4 0.01U/16V
PWR_1.5VPEC
1

C660 C419 C408

10U/6.3V *10U/6.3V 0.1U/10V
2

CPPE#_CN CPPE#
R541 100_4/J
PWR_3.3VPECAUX PWR_3.3VPEC C663
A A

0.033U
1

C659 C424 C678 C679 C436 C433

*10U/6.3V 0.1U/10V *4.7U/10V *10U/6.3V 10U/6.3V 0.1U/10V CPUSB#_CN CPUSB# Quanta Computer Inc.
R543 100_4/J
2

C673
PROJECT : FH5
0.033U Size Document Number Rev
1A
FAN/SW/NEWCARD
Date: Monday, September 27, 2010 Sheet 32 of 41
5 4 3 2 1
 5 4 3 2 1

BACKLIGHT Control(LVDS) BACKLIGHT POWER LED Panel POWER SWITCH(LVDS) 33

+3V

VIN
80mils V_BLIGHT 80mils
R371 F4 2A/63VS_1206
10K 1 2 LCDVCC_1 LCDVCC
F5 2A/63VS_1206
1 2
D + C487 C492 C491 D
+3V

1
*10U/25V_1206 1000P/50V_4 0.1U/25V/X5R C490 C498 C489 C494

U20 *0.1u/10V_4 0.1u/10V_4 33p/50V_4 4.7U/25V_8

2
5
BAS316 D13 2
31 DLID#
4 DISPON
8 INT_LVDS_BLON 1

3
MC74VHC1G08DFT2G R362 0/J_4
R373 +3V

+3VPCU +3V_S5
100K/J_4
C485 U19 LCDVCC_1

1u/10V_6 6 1
U18 IN OUT

5
1 2 LID# 4 2
LID# 31 IN GND
8 INT_LVDS_VDDEN 2
MR1 4 INT_LVDS_DIGON_U 3 5
C3 C1 APX9132H AI-TRG
C2 ON/OFF GND
8,31 EC_PWROK 1
2.2U/6.3V_6 AL009249000

3
0.1U/10V_4 220p/50V_4 R365 G5243AT11U

3
*MC74VHC1G08DFT2G AL005243001
item19
100K/J_4

LCDVCC
+3VPCU
C C
R368
R364
*100K *22_6

LVDS/CCD

3
+3V

3
V_BLIGHT
2 Q20
CON1 INT_LVDS_DIGON_U 2 Q19 *2N7002E-T1-E3
LCDVCC *DTC144EU
R376 R372 40 39
2.2K_4 38 37 +3V
2.2K_4

1
36 35
34 33
32 31
30 29 DISPON
8 INT_EDIDCLK 28 27 LVDS_VADJ
8 INT_EDIDDAT 26 25
24 C505 C493 C488
23 CCD_POWER
C500 C497 DMIC_CLK *1000p/50V_4 0.1U *56p/4
*12P/50V/NPO *12P/50V/NPO USBP6- 22 21 DMIC_DAT
USBP6+ 20 CCD 19
18 17

16 15
14 13
8 INT_TXLOUTN0 12 11 INT_TXLOUTN1 8
8 INT_TXLOUTP0 10 9 INT_TXLOUTP1 8
8 7
8 INT_TXLOUTN2 6 5 INT_TXLCLKOUTN 8
8 INT_TXLOUTP2 4 3 INT_TXLCLKOUTP 8
42

41

2 1

B B

LCD_CON40P
87241-4001-40P-LUV
DFWF40MR006

L7 +3V F6 CCD_POWER
*WCM-2012-900T MINI_PS-HS1
USBP6- C499 10u/10V_8
+

10 USBP6- 2 2 1 1 2 1
3 4 USBP6+
10 USBP6+ 3 4 C506 1000p/50V_4

C504 0.1u/10V_4

DMIC_CLK
30 DMIC_CLK
C512 8 INT_LVDS_BRIGHT R380 *0/J_4

*1000p/50V_4 31 CONTRAST R378 0/J_4 LVDS_VADJ

DMIC_DAT
30 DMIC_DAT
C502
C511 0.1U/10V_4
A A
*1000p/50V_4

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
LCD/CCD
Date: Monday, September 27, 2010 Sheet 33 of 41
5 4 3 2 1
 5 4 3 2 1

PR56
VA1 PD5 0.01/F_3720
PL1 SBR1045SP5-13 PQ9 VIN PQ26
HI0805R800R-00_8 1 FDD6685 FDD6685
VA 3 VA2 3 4 1 2 3 4
PJ2 2
PR143

1
1 0_4

1
2 PC95 PC8 PC99 PR29 24707_ACN PC98 PC97 PR28
3 2200p/50V_4 PL2 0.1u/50V_6 0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_4 33K/F_4
4 HI0805R800R-00_8 PD7
SMAJ20A 24707_ACP

2
D DFHS04FR349 D
87501-0400-4P-L PC96 PR142
0.1u/50V_6 1 6 0_4
PD4 PR27
1N4148WS PR21 2 5 10K_4
D/C# 31
220K_4
recommend 200mA at least. 3 4 PR140

3
0_4
PQ28
IMD2AT108
2

PQ6
24707_ACP DMN601K-7

1
24707_ACN

PC23 PC21 PC24

0.1u/50V_6 0.1u/25V_4 0.1u/50V_6

PR20
63.4K/F_4

1
VIN
PR19 PC12

ACP

ACN
+3VPCU 10K/F_4 1u/10V_4
C 24707_ACDET 6 16 24707_REGN C
ACDET REGN

PD3
PR25 24707_VCC 20 RB500V-40 PC15
10K_4 VCC PR18 2200p/50V_4 PC14
PR26 PC22 0_6 4.7u/25V_8
10_1206 1u/25V_6 17 24707_BST
PR22 BTST
31 ACIN

5
6
7
8
100K/F_4
3

PC19
0.1u/50V_6
18 24707_DH 4
HIDRV
2 5
ACOK#
PQ5 19 24707_LX
DMN601K-7 PHASE PQ27 PR139
AO4468 0.01/F_3720
1

8 PU1 PL3
31 MBDATA

3
2
1
SDA BQ24707 6.8uH
15 24707_DL 1 2 BAT-V
LCDRV

5
6
7
8
9
31 MBCLK SCL
+3VPCU
PR12 14 4 PR16
10K_4 PGND *4.7_6 PR14 PR11
PC6 24707_IFAULT# 11 0_4 0_4
IFAULT#
B B
PR24 PC11 PQ25
PJ1 0.1u/25V_4 *10K_4 24707_CMPOUT 3 0.1u/25V_4 AO4468
CMPOUT 24707_SRP 24707_SRP PC10 PC16 PC17
13

3
2
1
BAT-V SRP PC13 2200p/50V_4 10u/25V_1206 10u/25V_1206
1
BATT 24707_ILIM PC9 *680p/50V_6 24707_SRN
10
ILIM 0.1u/25V_4
2
VS PR15
3 316K/F_4 24707_CMPIN 4 12 24707_SRN
SWT+ CMPIN SRN

IOUT
4

GND
GND
GND
GND
GND
POWER TEMP_MBAT 31
PC7
5 0.1u/25V_4
CLOCK PR23 7

21
22
23
24
25
6 100K/F_4
DATA
7
SC#T-
8 PC4 PC5 +3VPCU REGN MAX voltage 6.5V
GND 47p/50V_4 47p/50V_4
PR17 PC18
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
100K/F_4 0.01u/25V_4
DFAD08MR001
PR9 PR7 =0.793V for 3.965A current limit
100_4 100K/F_4
BAT-1746498-2-8P-L
PR8
100_4
MBCLK 31 ICM ICM
MBCLK 31
MBDATA
A MBDATA 31 A
1

PD2 PD1 PR3 PC20

ZD5.6V ZD5.6V 100K/F_4 PC1 100P/50V_4
0.01u/25V_4 Quanta Computer Inc.
2

PROJECT : FH5
Size Document Number Rev
1A
Charger(BQ24703)
Date: Monday, September 27, 2010 Sheet 34 of 41
5 4 3 2 1
 5 4 3 2 1

MAIND
MAIND 6,38,41

TP62 TP60 VL TP61 TP58

4 SYS_SHDN#
JP16 JP15
0.001/F_3720 PR210 0.001/F_3720
0_4 +3VPCU
1 2 +5VPCU_VIN +3VPCU_VIN 1 2
3.3 Volt +/- 5%
D VIN VIN D
PR211
39K/F_4 VL
TDC : 7A
PEAK : 8.8A
OCP : 10A
1

PC138
+ PC158 3V5V_EN 4.7u/6.3V_6 PC159
2200p/50V_4 PR200 2200p/50V_4 Width : 352mil
PC162 PC155 0_4 PC156
2

100u/25V_6X5.8 4.7u/25V_8 PR193 4.7u/25V_8

PR208 PR209 0_4
0_4 0_4
PR191 PC139 PC141
390K/F_4 0.1u/50V_6 1u/10V_4 +3VPCU

5V_EN

3V_EN
TP70

5
6
7
8
PC140 PC142
0.01u/25V_4 0.1u/25V_4
+5VPCU

1
+5VPCU 5 Volt +/- 5% 8206_ONLDO REF 4
TP67 3V_DH

8
7
6
5
TDC : 4.5A
PEAK : 5.7A TP69
1

8
7
6
5
4
3
2
1
4 5V_DH PR192 JP19
OCP : 7A

2
JP18 150K/F_4 PQ58 PL13 0.001/F_3720

LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF

3
2
1
0.001/F_3720 AO4468 2.2uH
Width : 230mil PQ55 +3VPCU_SRC
AO4468 PR203 3V_LX
TP68

5
6
7
8
+5VPCU_SRC 9 32 REFIN2 255K/F_4
2

PL12 BYP REFIN2

10 31

1
2
3
2.2uH OUT1 ILIM2 PR217
C 11 FB1 OUT2 30 C
+5VPCU_SRC 5V_LX 12 PU7 29 SKIP 4 *4.7_6
PR202 DDPWRGD_R 13 ILIM1 RT8206M SKIP# DDPWRGD_R
PGOOD1 PGOOD2 28

8
7
6
5
162K/F_4 5V_EN 14 27 3V_EN PC169 +
PR198 EN1 EN2 0.1u/25V_4
15 DH1 DH2 26
*0_4 PR220 16 25 PC152 PC167
*4.7_6 5V_DL LX1 LX2 *680p/50V_6 330u/6.3V_6X5.7
4 37 PAD
+ PC168 36

3
2
1
PAD

PGND
PVCC
0.1u/25V_4 PQ57

BST1

BST2
GND
PAD
PAD
PAD

DL1

DL2
PC166 PC145 PC149 AO4710

NC
330u/6.3V_6X5.7 PC161 0.1u/50V_6 0.1u/50V_6
*680p/50V_6 PQ56 PR216

35
34
33

17
18
19
20
21
22
23
24
AO4710 PR212 1/F_6
1
2
3

PR197 1/F_6
0_4 3V_DL
PR207
*0_4
PR214 VL SKIP REF
+5VPCU_FB *0_6 PR194
PC147 0_4
2 0.1u/50V_6 PC148
PD9 1u/10V_4 PR195
CHN217 3 0_4
PR205
1 0_4 +3VPCU
PR215
0_6
PC146 2
1u/25V_6 PD10
B
OCP:7A CHN217 3 OCP:10A PR204
B
L(ripple current) PC151 L(ripple current) *100K/F_4
1 0.1u/50V_6
=(9-5)*5/(2.2u*0.4M*9) =(9-3.3)*3.3/(2.2u*0.5M*19)
+15V_ALWP
~2.525A +15V ~1.9A DDPWRGD_R
SYS_HWPG 31
Iocp=7-(2.525/2)=5.74 PR218 PR219 Iocp=10-(1.9/2)=9.05A
22_8 *200K/F_4 PR213 PR206
Vth=5.74*14.2mohm=0.081V PC154 *39K/F_4 Vth=9.05*14.2mohm=0.12851V 0_4
R(ILM)=0.8147*10/5uA=162.941K 1u/25V_6 R(ILM)=0.12851*10/5uA=257.02K

+5VPCU +5VPCU
VIN +3V_S5 +5V_S5 +15V VIN +3VPCU +3VPCU

PR179 PR181 PR184 PR182 PR186

3
1M_4 22_8 22_8 1M_4 *1M_6
3

5
6
7
8

5
6
7
8
S5D 2
S5D 2 MAIND 4 MAIND 4
3

PQ62
A PQ61 PQ64 PQ60 AO3404 A

1
2 AO3404 AO4468 AO4468
31 S5_ON
1

2 2 2 +3V_S5
3
2
1

3
2
1

PR180 PQ49 PQ52

+5V_S5 0.36A
1

PQ48 1M_4 DMN601K-7 DMN601K-7

DTC144EUA PQ51 PC136 20mil Quanta Computer Inc.
1

DMN601K-7 *2200p/50V_4
0.75A
+5V +3V
30mil PROJECT : FH5
2.6A 5A Size Document Number Rev
100mil 200mil 1A
SYSTEM 5V/3V (RT8206)
Date: Monday, September 27, 2010 Sheet 35 of 41
5 4 3 2 1
 5 4 3 2 1
JP11
0.001/F_3720

1 2 VIN
17511_VCC +5V_S5
PR171 PC123
2.2_6 0.1u/50V_6

2200p/50V_4

0.1u/50V_6

1
17511_VCC

PC73

PC69
17511_BSTA1 + PC111

5
PR84 100u/25V_6X5.8
PC64 10_6 PC120 PC124

2
1u/10V_4 2.2u/10V_6 1u/10V_4

2
17511_DHA1 4
PQ42 +VCC_CORE
AOL1448 PC70 PC71 PL8

24

1
2
3
VIN 4.7u/25V_8 4.7u/25V_8 0.36uH
17511_LXA1
DCR=1.1mOhm
PR89 1 2

VDDA
D 17511_EN D
31 VRON 40
VCC PR90 PQ40 PQ41
15 PR1003 :

4
VDDB

5
0_4 SP@200K/F_4 IV@ 100K/F_4 AOL1718 AOL1718 17511_LXA1-1
2 EV@ 200K/F_4
PR168 TON PC67 PR97 +
100K/F_4 17511_DLA1 3300p/50V_6 4 4 2.2_6
20 17511_BSTA1 PR106 PR105
BSTA1 1.74K/F_4 1/F_4 PC108

1
2
3

1
2
3
39 22 17511_DHA1 330u/2V_7343
CSPA3 DHA1 PC61 PC68
21 17511_LXA1 *0.1u/50V_6 1000p/50V_6
LXA1
31
DRVPWMA3 17511_DLA1 PR111
23
+3V DLA1 17511_CSPA1 11K/F_4

36 17511_CSPA1
CSPA1 PC65
17511_CSNA 0.22u/25V_6
PR109
PIV@10K/F_4 JP9
PR108 35 17511_CSPAAVE 0.001/F_3720
1.91K/F_4 CSPAAVE PC62 1 2 VIN
4,8 IMVP_PWRGD 19 37 17511_CSNA 0.1u/50V_6
POKA CSNA

2200p/50V_4

4.7u/25V_8

4.7u/25V_8
*4.7u/25V_8

*4.7u/25V_8

1
10 4 17511_FBA
31 GFX_PWRGD POKB FBA

PC55

PC57

PC58

PC171

PC170
17511_BSTA2 + PC109

0.1u/50V_6
5

PC56
4,31 H_PROCHOT# 5 100u/25V_6X5.8
VRHOT# 17511_CSPA2 PR169 PC117
38

2
17511_EN CSPA2 2.2_6 0.1u/50V_6
Pull up resister to 1.05V 1
EN +VCC_CORE
28 17511_BSTA2 17511_DHA2 4
BSTA2 PQ35
16 26 17511_DHA2 AOL1448 PL6

1
2
3
6 VR_SVID_DATA VDIO DHA2 0.36uH DCR=1.1mOhm
18 27 17511_LXA2 17511_LXA2 1 2
6 VR_SVID_CLK CLK LXA2
PR1018 : 17 25 17511_DLA2 PQ39 PQ38
C C

4
6 VR_SVID_ALERT# ALERT# DLA2

5
17511_VCC AOL1718 AOL1718 17511_LXA2-1
IV@ 5.62K/F_4
EV@ 1K/F_4 17511_GNDSA PC60 PR73 +
3
GNDSA 17511_DLA2 3300p/50V_6 2.2_6
PU4 4 4
PR71 PR70
MAX17511GTL+ 1.74K/F_4 1/F_4 PC66

1
2
3

1
2
3
PC59 330u/2V_7343
PR82 PR83 PR81 PR163 PR77 11 17511_BSTB PC63 1000p/50V_6
5.62K/F_4 SP@1K/F_4 1K/F_4 150K/F_4 PIV@130K/F_4 BSTB +5V_S5 *0.1u/50V_6
13 17511_DHB
DHB PR69
17511_THERMA 33 12 17511_LXB 17511_CSPA2 11K/F_4
THERMA LXB
14 17511_DLB
17511_THERMB DLB PR104 PC113
34
THERMB PEV@1K/F_4 17511_CSNA 0.22u/25V_6 Load line 1.9mV/A
PC112
17511_SR 32 8 17511_CSPB 0.1u/50V_6 PC116 PR170 OCP 60A
SR CSPB 0.1u/50V_6 *10_4
9 17511_CSNB
17511_IMAXA CSNB
29
IMAXA 17511_FBB 17511_GNDSA
6 VSSSENSE 6
FBB
17511_IMAXB 30 7 17511_GNDSB PR94
PAD

IMAXB GNDSB PC118 10_4

*1000p/50V_4
PR76 17511_FBA VCCSENSE 6
41

PIV@158K/F_4
PR96 PR95 +VCC_CORE
6.65K/F_4 10_4
PC119 PR92
PR78 0_4 0.1u/50V_6 *10_4 JP12
PIV@0.001/F_3720
PR165 PR164 PR160 0_4
*200K/F_4 200K/F_4
B PR178 1 2 B
VIN
PR157 PIV@100K/F_4_4250KNTC
100K/F_4_4250KNTC PR173 PC126

PIV@2200p/50V_4

PIV@4.7u/25V_8

PIV@4.7u/25V_8

PIV@4.7u/25V_8
IV@ for Internal VGA (+VCC_GFX enable) PIV@2.2_6 PIV@0.1u/50V_6

PIV@0.1u/50V_6
PC78

PC79

PC81

PC82

PC80
17511_BSTB
EV@ for External VGA (+VCC_GFX disable discrete only) Load line 3.9mV/A

5
SP@ for IV@ or EV@ selection Peak 24A
17511_DHB 4
PQ45 +VCC_GFX
PIV@AOL1448 PL9

1
2
3
PR159 PIV@0.36uH DCR=1.1mOhm
10K/F_4_3435KNTC 17511_LXA1-1 17511_LXB 1 2

PR167 PQ47 PQ46

4
5

5
PR161 3.4K/F_4 PIV@AOL1718 PIV@AOL1718
2.49K/F_4
17511_LXA2-1 PC84 PR119 +
17511_DLB PIV@3300p/50V_6 4 4 PIV@2.2_6 PR117
PR162 PR158 PIV@1.69K/F_4
45.3K/F_4 3.4K/F_4 PC129

1
2
3

1
2
3
17511_CSPAAVE PR177 PIV@330u/2V_7343
PC72 PC83 PIV@10K/F_4_3435KNTC
PC114 PR166 * PIV@0.1u/50V_6 PIV@1000p/50V_6
0.22u/25V_6 1/F_4

17511_CSPB

PC115 PR107 PIV@1/F_4 PR115 PR116

*0.22u/25V_6 PC75 PIV@2.49K/F_4 PIV@45.3K/F_4
17511_CSNA 17511_CSNB PIV@0.22u/25V_6
PC74
PIV@0.1u/50V_6

A PC125 PR172 A
PIV@0.1u/50V_6 *PIV@10_4

17511_GNDSB
VSS_AXG_SENSE 6
PR101
PC121 PIV@10_4
*PIV@1000p/50V_4
17511_FBB
VCC_AXG_SENSE 6
Quanta Computer Inc.
PR99 PR98 +VCC_GFX
PIV@6.81K/F_4 PIV@10_4
PC122 PR102
PROJECT : FH5
PIV@0.1u/50V_6 *PIV@10_4 Size Document Number Rev
1A
+VCC_CORE (MAX17511))
Date: Monday, September 27, 2010 Sheet 36 of 41
5 4 3 2 1
 5 4 3 2 1

JP4 VIN
0.001_3720
PR67 +1.05V_PCH
+3V +5V_S5
8238_TON
360K_4
1 2
1.05 Volt +/- 5%
D
TDC : 13.58A D

PEAK : 18.2A
PR64
*100K/F_4 OCP : 23A
PR153 PC110 PC52 PC54
10_6 PR68 2200p/50V_4 4.7u/25V_8 4.7u/25V_8 Width : 730mil
8238_VCC 2_6
8238_BST1
8238_BST

5
PC50
1u/10V_4 +1.05V_PCH

PC51

11
4

4
0.1u/50V_6 +1.05V_VTT

BOOST
TON
VCC

1
2
3
PQ36
AOL1448
JP10
9 3 8238_DH PL7
31,40 HWPG_VTT PGOOD UGATE 0.56uH
8238_EN 8 2 8238_LX 2 1
31,38,40,41 MAINON EN PHASE
PR66 0_4 PU3
C RT8238A LGATE 1 8238_DL PQ34 PQ37 C
AOL1718 AOL1718
0.001/F_7520

5
13 10 8238_CS
PAD CS

MODE
PR72 + + PC127

GND
*4.7_6 0.1u/25V_4

FB
4 4
PC107

12

6
*0.1u/10V_4 PR154

1
2
3

1
2
3
0_4 PC53
PR152 *680p/50V_6
43.2K/F_4 PC128
560u/2.5V_6X5.7 PC131
560u/2.5V_6X5.7
RDSon 4.3mOhm/2
PR156
0_4
Close to output cap

6 VCCP_SENSE
PR149 *0_4
B B

PR151 PC49
8238_MODE 11K/F_4 *100P/50V_4
6 VSSP_SENSE
PR150 *0_4
8238_FB

+5V_S5
PR65 0_4
PR155
10K/F_4

Current limit =10uA*Rth/RDSon VOUT=(1+R1/R2)*0.5

A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
+PCH&VTT (RT8238A)
Date: Monday, September 27, 2010 Sheet 37 of 41
5 4 3 2 1
 5 4 3 2 1

[PWM]

+0.75V_DDR_VTT
0.75 Volt +/- 5%
TDC : 0.75A PC85
10u/10V_8
PEAK : 1A TP53 TP2 +1.5V_SUS
JP6
Width : 40mil PR185 PC135 0.001_3720 1.5 Volt +/- 5%
D 0_6 0.1u/50V_6 D

+0.75V_DDR_VTT
8207A_VBST
8207A_VIN
TDC : 10.36A
1 2 VIN
8207A_DH PEAK : 13.81A
PC133 PC134
10u/10V_8 *10u/10V_8 8207A_LX OCP : 15A
Width : 550mil

5
8207A_DL

4
TP54 TP57

25

24

23

22

21

20

19
PC132 PC87 JP13

1
2
3
PQ50 2200p/50V_4 4.7u/25V_8 0.001/F_7520

LL

DRVL
VTT

VBST
GND

VLDOIN

DRVH
AOL1448

1 18 +1.5VSUS_SRC 1 2 +1.5V_SUS
VTTGND PGND
SMDDR_VREF PL10
0.75 Volt +/- 5% 2 VTTSNS CS_GND 17 1.5uH

TDC : 0.015A

5
3 16 PR199
PEAK : 0.02A GND RT8207L CS 7.32K/F_4
PU6 PR123
Width : 10mil +1.5VSUS_SRC 4
MODE V5IN
15 +5V_S5 4 *4.7_6 +
PC153
PQ53 0.1u/25V_4

1
2
3
5 14 AOL1718
+SMDDR_VREF VTTREF V5FILT
PR201
VDDQSNS

VDDQSET
PC86 +5V_S5 6 13 PC143 5.1/F_6 PC144 PC88
C 33n/25V_4 COMP PGOOD 1u/10V_4 1u/10V_4 *680p/50V_6 PC150 C
560u/2.5V_6X5.7
NC

NC
S3

S5
PR196 +3V
100K/F_4
7

10

11

12
FOR DDR III
HWPG_1.5V 31

PR190
VIN (For RT8207A 400KHZ ) close to pc2008
750K/F_4

PR124 S5_1.8V PR189

SUSON 31
0_4 0_4

S3_1.8V PR187
MAINON 31,37,40,41
0_4

PR120 +5V_S5
PR122 *0_4
0_4

L(ripple current)
PC137 PR183
*22p/50V_4 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75 =(9-1.5)*1.5/(2.2u*400k*9)
~1.42A
8207A_SET
Vtrip= (15-0.71)*4.3mohm=0.06145V
RILIM=Vtrip/10u=6.144K
B PR121 S5_1.8V PR188 S3_1.8V B
10K/F_4 *0_4
+1.5V_SUS
+1.5V S3 S5 +1.5V_SUS REF VTT
1.5 Volt +/- 5%

3
S0 1 1 ON ON ON
TDC : 0.5A
6,35,41 MAIND
MAIND 2 PEAK : 0.65A S3 (mainon off) 0 1 ON ON OFF
Width : 25mil
PQ54 S4/S5 0 0 OFF OFF OFF
AO3404
1

+1.5V

VIN +SMDDR_VREF +5VSUS +15V +5VPCU

PR134 PR129 PR130 PR132

3

1M_4 *22_8 22_8 1M_4

SUS_ON_G SUSD 2
3

3
3

PQ59
A PR131 AO3404 A
1

2 PQ21 1M_4 2 2 2
31 SUSON DTC144EU PC94
PQ22 PQ23 PQ24 *2200p/50V_4
*DMN601K-7 DMN601K-7 DMN601K-7
TDC : 1.125A
1

PR133
1

+5VSUS
*100K/F_6 PEAK : 1.5A
Width : 60mil Quanta Computer Inc.
PROJECT : FH5
Size Document Number Rev
1A
DDR 1.5V(TPS51116)
Date: Monday, September 27, 2010 Sheet 38 of 41
5 4 3 2 1
 5 4 3 2 1

JP1
PEV@0.001_3720

GPU_CORE_VIN 1 2 VIN +VGPU_CORE

1 Volt +/- 5%
+5V_S5
D PC100
TDC : 24A D
PEV@2200p/50V_4 PC25 PC29 PC28 PEAK : 31.5A
8117_VDDA 8117_VDDP PEV@4.7u/25V_8PEV@4.7u/25V_8 PEV@4.7u/25V_8
OCP : 35.8A
PR43
PC39 PEV@22_6 PC30 PD6 Width : 1320mil
PR41 PEV@1u/10V_4 PEV@1u/10V_4 PEV@RB500V-40 PQ30 PQ31
PEV@100K/F_4 PEV@AOL1448 PEV@AOL1448 +VGPU_CORE

5
+3V
8117_BST1
8117_VIN
4 4
PR45 PC32
PR40 PEV@0_6 PEV@0.1u/50V_6

18

12

1
2
3

1
2
3

1
PEV@10K_4 PC26
PEV@0.01u/25V_4 JP2

VDDA

VDDP
5 15 8117_BST PEV@0.001/F_7520
VIN BST
Close to Phase 1 Inductor
11 16 8117_DH PL4
41 PG_GPUIO_EN

2
PG HDR PEV@0.68uH_13X13X5

8117_EN 3 17 8117_LX +VCC_GFX_CORE_SRC

11,31,41 dGPU_VRON ON/SKIP LX
PR46
C C
*PEV@0_4 8117_VSET1 7 13 8117_DL
VSET1 LDR

5
PR47 PR30
+3V *PEV@100K/F_4 PU2 PR54 PEV@20K/F_4
8117_VSET2 8 PEV@OZ8117 14 PEV@2.2_6 PR141
PR48 VSET2 GNDP PEV@10K_6_NTC + + +
4 4
PEV@0_4 9
19 GPU_VID1 G0 PC42

1
2
3

1
2
3
10 19 8117_CSP PR31 PEV@0.1u/25V_4
19 GPU_VID2 G1 CSP PEV@20K/F_4 PC43
VREF=2.75V 8117_VREF 4 20 8117_CSN PC40 PEV@330u/2V_7343
VREF CSN PEV@1000p/50V_6
8117_TEST 6 PR57
TSET 8117_RSP PC37 PEV@51.1/F_6 PC36
RSP 1
PR34 PEV@33n/25V_4 PEV@330u/2V_7343
PR44 PC31 PEV@0_4 21 2 8117_RSN PQ32 PC33
PEV@160K/F_4 PEV@0.1u/25V_4 GNDA RSN PEV@AOL1718 PQ33 PEV@330u/2V_7343
PEV@AOL1718

8117_VSET2 PR52
PEV@825/F_4
PR35 PR39 PC35 PC34 PC41
Modify 8/18 PEV@200K/F_4PC27 PEV@0_4 PEV@0.01u/50V_4 PEV@0.01u/50V_4 8117_CSP PEV@1000p/50V_4
PR36 PEV@1000p/50V_4
PEV@11.3K/F_4 8117_CSN
B PR38 B
8117_VSET1 PEV@0_4
PC38
PEV@22p/50V_4
PR58
PR37 *PEV@10_4
PEV@76.8K/F_4
PR55
PEV@51.1/F_6
8117_RSP
VIN +VGPU_CORE VGPU_VCC_SENSE 16
PR53
PEV@0_4
8117_RSN
VGPU_VSS_SENSE 16
PR32 PR42 PR49 PR50
PEV@1M_4 PEV@22_8 PEV@51.1/F_6 PEV@0_4

PR51
NV VID Table for N12P-GE *PEV@10_4

3
GPU_VID1 GPU_VID2 +VGPU_CORE
3

0 0 0.85V 8117_EN
2
A
2 A
PQ8
PR33 PEV@DMN601K-7
PQ7 PEV@1M_4
0 1 0.95V(Boot)
1

PEV@DTC144EUA
1 1 0.975 Quanta Computer Inc.
Modify 8/18 PROJECT : FH5
Size Document Number Rev
1A
GPU CORE(OZ8117)
Date: Monday, September 27, 2010 Sheet 39 of 41
5 4 3 2 1
 5 4 3 2 1

VID0
0
0
VID1
0
1
VCCSA
0.9V
0.8V 1
JP3
0.001/F_3720

2
+3V

VCCSA
40
1 0 0.725V 0.9 Volt +/- 5%
1 1 0.675V TDC : 4.2A
PC44 PEAK : 6A
0.1u/25V_4 PC101 PC102
D
10u/10V_8 10u/10V_8 Width : 240mil D

+5V_S5 VCCSA

PC103
2.2u/10V_6

2
+3V 51461_DRV

24

23

22

21

20

19
PC48 JP8
0.1u/50V_6 0.001/F_3720

VIN

VIN

VIN

PGND

PGND

PGND
PR59
0_6 18 12 51461_BST
PC104 V5DRV BST PL5

1
PR144 1u/10V_4 1uH_7X7X3
100K/F_4 51461_FILT 17 11
V5FILT SW

31 HWPG_VCCSA 16 10 51461_SW
PGOOD TPS51461 SW +
PU5 PC106
51461_EN 13 9 0.1u/25V_4 PR148
31,37 HWPG_VTT EN SW
PR147 100_4
0_4 PC46 14 8
VID0 SW
*0.1u/25V_4
PC105
15 7 560u/2.5V_6X5.7
6 VCCSA_SEL VID1 SW

MODE

COMP

SLEW

VOUT
VREF
C C

GND
Pad 25

5
PR145
51461_MODE

51461_COMP

51461_SLEW
51461_VREF
1K_4

PR60 0_4 VCCSA_SEL VCCSA

1 0.8V
PR61 0_4 51461_VOUT VCCSA_SENSE 6
0 0.9V PR63
*0_4 PC47 PR146
0.01u/25V_4 0_4
default 0.9V

PC45
0.22u/25V_6
PR62
7.15K/F_4

TP1 TP66 +1.8V

+3VPCU
1.8 Volt +/- 5%
+1.8V
1 2 TDC : 1.34A
B
PEAK : 1.78A B
TP26
JP17 Width : 71mil

1
0.001_3720 PC165 PC93
10u/10V_8 0.1u/10V_4 PU8 TPS51117RGYR-GP_4 JP14
16 835_PH
VIN PH 10 0.001_3720

1 11 PL11
VIN PH 1uH_7X7X3

2
PR224 2 12 TP59
0_4 VIN PH
MAINON 835_EN 15 13 PR221 0_6
EN BOOT
54418-1.8_VFB 6 14 PC163 R1
VSNS PW RGD 0.1u/50V_6 PR126
835_COMP 7 3 100K/F_4
COMP GND PC160 PC89 PC157
PR127 PC91 835_RTCLK 8 4 0.1u/10V_4 10u/10V_8 10u/10V_8
*100K/F_4 1000p/50V_4 RT/CLK GND
HWPG_1.8V 31
PAD
PAD
PAD
PAD
PAD
PAD

835_SS 9 5 PR223
PR222 PR125 SS AGND
100K/F_4
8.06K/F_4 182K/F_4 +3V 54418-1.8_VFB
22
21
20
19
18
17

PC92
*100P/50V_4 PC90 R2 PR128
0.01u/25V_4 78.7K/F_4
V0=0.8*(R1+R2)/R2
PC164
2700p/50V_4
A A
MAINON
MAINON 31,37,38,41

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
VCCSA(TPS51461)/+1.8V(HPA00835)
Date: Monday, September 27, 2010 Sheet 40 of 41
5 4 3 2 1
 5 4 3 2 1

VIN +1.5V_GPU +15V +1.5V_SUS +1.05V_VTT

PR10 PR4 PR6 PQ29

5
6
7
8
PR5 PEV@1M_4 PEV@22_8 PEV@1M_4 PEV@AOL1718
D PEV@0_4 D

39 PG_GPUIO_EN dGPU_D1 4
6.645A dGPU_D1 4
266mil 2.87A

1
2
3
3
PR1 PQ4
*PEV@0_4 PR13 +1.5V_GPU PEV@AO4468
120mil
2 PEV@1M_4 2 2
11,31,39 dGPU_VRON PQ3 PC3 +1.05V_GPU

3
2
1
PEV@PDTC143TT PQ2 PQ1 *PEV@2.2n/50V_4
PEV@DMN601K-7 PEV@DMN601K-7

1
PC2 PR2

1
PEV@1u/10V_4 PEV@100K/F_4

+3VPCU
VIN +3V_GPU +1.05V_GPU +15V

C C
PR87 PR93 PR103 PR112

3
PEV@1M_4 PEV@22_8 *PEV@22_8 PEV@1M_4
PR79
PEV@0_4 dGPU_D 2
1.04A
11 dGPU_PWR_EN

3
40mil
3

PR80 PQ63
*PEV@0_4 PR88 PEV@AO3404

1
2 PEV@1M_4 2 2 2 +3V_GPU
11,31,39 dGPU_VRON PC76
PQ13 PQ15 PQ17 *PEV@2.2n/50V_4
1

PQ11 PEV@DMN601K-7 *PEV@DMN601K-7 PEV@DMN601K-7

1

PR75 PEV@DTC144EUA

1
*PEV@100K/F_4
2

B B

VIN +3V +5V +0.75V_DDR_VTT +1.5V +1.8V +15V

PR85 PR91 PR100 PR110 PR113 PR114 PR118

4,6 MAINON_ON_G
1M_4 22_8 22_8 22_8 22_8 *22_8 1M_4

MAINON_ON_G MAIND
MAIND 6,35,38
3

3
3

PR86
2 PQ10 1M_4 2 2 2 2 2 2
31,37,38,40 MAINON DTC144EUA PC77
PQ12 PQ14 PQ16 PQ18 PQ19 PQ20 *2200p/50V_4
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 *DMN601K-7 DMN601K-7
1

PR74
1

1
*100K/F_4

A A

Quanta Computer Inc.

PROJECT : FH5
Size Document Number Rev
1A
Discharger
Date: Monday, September 27, 2010 Sheet 41 of 41
5 4 3 2 1
 5 4 3 2 1

REV CHANGE LIST

Model
page 33: Change +VIN to VIN.

2010/09/20 page 30 : Del Q16 ,R351.

FH5 MB
page 10 : Add Q27 and Q28.

page 26 : Change CON6 RJ45 Conn to DFTJ08FR157.

B
2010/09/22
D
page 10: Change USB port6 ot port10. D

2010/09/22 page 31 : Del CN3 Netname ,NBSWON#, SLP_S3# ,+VCC_GFX,+VCC_CORE,H_PWRGOOD, RSMRST#, SLP_S4# ,SUS_STAT#.

page 31 : Reserve R351 ,R574~R580 for Power sequence resistor.

page 31 : Reserve C692 for H_PWRGOOD.

page 9: Change JTAG VCC +3VPCU to +3V_S5.

2010/09/23 page 31 : Change CON2 VCC from +3V to +3V_S5.

page 12 : Reserve C693,C694,C695,C696 for ESD.

Κ PC61Ε
Page36Κ Ε PC63 change value from *1000p/50V_4 (CH21006JB10) to *0.1u/50V_6 (CH41006K911)
Κ PC62Ε
Page36Κ Ε PC112Ε
Ε PC116Ε
Ε PC119 change value from 1000p/50V_4 (CH21006JB10) to 0.1u/50V_6 (CH41006K911)

Κ PC72 change value from *PIV@1000p/50V_4 (CH21006JB10) to * PIV@0.1u/50V_6 (CH41006K911)

Page36Κ

Κ PC74Ε
Page36Κ Ε PC122Ε
Ε PC125 change value from PIV@1000p/50V_4 (CH21006JB10) to PIV@0.1u/50V_6 (CH41006K911)

Κ PR190 changes value from 620K/F_4 (CS46202FB00) to 750K/F_4 (CS47502FB14)

Page38Κ

Κ PR44 changes value from PEV@169K/F_4 (CS41692FB12) to PEV@160K/F_4 (CS41602FB00)

Page39Κ

Κ PR36 changes value from PEV@21.5K/F_4 (CS32152FB17) to PEV@11.3K/F_4 (CS31132FB07)

Page39Κ

Κ PR37 changes value from PEV@82K/F_4 (CS38202FB14) to PEV@76.8K/F_4 (CS37682FB00)

Page39Κ

C
Ε PL8Ε
page36 :PL6Ε Ε PL9 change footprint from CHOKE-ETQP4LR36WFC-4P-SMT to CHOKE-PCMB104T-R45MN-4P-SMT C
page06 Reserve C697,C698,C699 for VID.

2010/09/24 page06 Del R28 , add R21,C19,C20,Y2 , use cystal to provide 25M CLK.

page36 Del PC57,PC58 ,ADD PC170,171,PC78,PC73,PC55 for C state issue.

page38 CHange PR199 to 7.32K_4(CS27322FB12), change 1.5V_SUS OCP value.

Κ PL4 change P/B from CV+68^0MZ00 to DC+68Z0M001

2010/09/27 Page39Κ

Κ C4,C5,C6,C7,C8,C9 change from2.2P/50V_4 to 10P/50V_4(CH01006JB08).

Page24Κ

page 27 : Change U34 Ctrl 1 ~3 behavior,add R554 , R581,del R582.

B B

A A

3C

Quanta Computer Inc.

PROJECT : FH5 DOC NO. PROJECT MODEL : FH5 APPROVED BY: DATE: 2010/09/20
Size Document Number Rev
1A
Change list PART NUMBER: DRAWING BY: REVISON: 1A
Date: Monday, September 27, 2010 Sheet 49 of 49

5 4 3 2 1