A DETAILED LESSON PLAN OF Flip Flop

(JK Flip Flop)

I. Objectives
At the end of the lesson the students should be able to:
 Familiarize the JK Flip Flop
 Discuss the JK Flip Flop
 Shows self-realization when working independently
II. Subject Matter
Topic: JK Flip Flop
Instructional Materials: whiteboard, PowerPoint presentation, Laptop

III. Methodologies
TEACHER’S ACTIVITY STUDENT’S ACTIVITY
I. PRELIMINARY ACTIVITIES
A. Pre-assessment Activity
1. Greetings “Good morning ma’am”
“Good morning class!”

2. Prayer (One Mr. Alvero will lead the prayer)

“Let us pray, Please lead the prayer, Mr.
Alvero?”

3. Checking of attendance “Yes ma’am”

“Say present if your name is called”

4. Recall  D flip-flop or Data flip flop is a type

 Our previous topic was all about
the D Flip Flop. What is the D Flip
Flop?
5. orientation
Today we are going to discuss about JK
flip flop?
B. Motivation
 Before we start let's have an
individual activity. Every student
will pick one logic gates and
explain.
C. Presentation
of flip Flop that has only one data
input that is ‘D’ and one clock
pulse input with two outputs Q and
Q bar..
(The learners pay attention and listen to
the teacher)
(The learners will pick a logic gate)
 The learners individually choose 1
logic gate.
Now I am going to present to you the JK
flip flop through PowerPoint presentation.
So, what is JK flip flop…….
II. LESSON PROPER
1. Activity
 Prepare 1/2 crosswise. Each learner
will share their ideas about the JK
flip flop.
(The students pay attention and listen to
the teacher)
 The learner will write their ideas
about JK flip flop on a piece of
paper

 Ms Alcansado: what is your idea  The JK flip flop is called a jack

about the JK flip flop? kilby.

2. Abstract
 Mr. Capongha, what is the JK flip  JK flip flop is one of main types of
flop? flip flop also have an additional
input pin for clock signal usually
 The JK flip flop one of main types label the clock or clock pulse..
of flip flop also have an additional
input pin for clock signal usually
label the clock or clock pulse.

The JK flip flop is made to solve

the problem of the SR flip flop if
the reset and set is going active at
the same time the flip flop enters
and invalid state-input Q and not Q
which should ideally be inverse
can become both high or both low
this causes the flip flop lose control
of the output and their future state
become unpredictable.

This is the JK latches

In JK flip flop the two two input and

gates are swapped out for two
three input NAND gates, having
the third input of each NAND gates
 Mr. Capongha to solve the invalid
connected to the opposing output
state of RS flip flop.
eliminates the invalid.
  Mr. Capongha. Why JK flip flop is
made?
 Ms. Tasic What is the two logic
gates and two input added?
 The two NAND gates and the input
is connecting the together the
NAND gates that is clock signal
and connect the opposite output of
NOR gates.

 To occur the potential problem of

SR flip flop that is when the set
3. Abstraction and reset is both 1.
 Why SR flip flop need a JK flip flop?

 The JK flip flop has an 8

combination because of the clock
signal. This truth table of JK flip flop
in the 1st 4 batch clock cycle is good
and the 2nd 4 batch cycle is
something wrong but the next cycle
of the clock is back to the result of
the 1st 4 batch.

This is the square wave of JK flip

flop this is still behave like set and
reset setting Q and setting not Q but
if the J and K go active high the
input simply toggle boom no invalid
stated problem.

This circuit are considered

 sequential logic because the logic
happens in a certain sequence.

 Mr. Capongha can you draw the JK

latch?

 The JK flip flop is add a two-input

and gates to avoid invalid states.
 Ms. Guiamal how JK flip flop solve the
potential problem of SR flip flop

4. Application
 Prepare 1/2 crosswise then draw
the JK wave and discuss.

IV. EVALUATION
1. it may perform the function of an R-S, T, or D flip-flop.
a) Flip flop

b) JK flip flop

c) RS flip flop

d) D flip flop

2. it is the two input and gates add in JK flip flop except.

a) NAND gates

b) Clock signal

c) D flip flop

d) Connected in opposing output.

3. What is the Q output and not Q if the J is 1?

a) 0 and 1

b) 1 and 0
 c) 1 and 1

d) 0 and 0

4-5. if a JK flip flop has a missing logic gate, is it still considered as a JK flip flop. Why

or why not?

.