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    14 views56 pages

    Acer Aspire 3100

    Uploaded by

    ady putra

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 56

    A B C D E

    1 1

    2
    Compal Confidential 2

    HCW50 Schematics Document


    AMD/Sempron/ATI RX485/SB460 W/s M52/54/56P

    2006 / 02 / 28 Rev:0.3 (For PVT)


    3 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/05/09 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 1 of 55
    A B C D E
    5 4 3 2 1

    Compal confidential
    Project Code: HCW50
    Thermal Sensor Clock Generator AMD Turion/Sempron CPU DDRII DDRII-SO-DIMM X2
    File Name : LA-3151P
    ADM1032ARM ICS951462 Socket S1 638P page 9,10
    page 5,6,7,8
    page 7 page 15 Dual Channel DDR-II
    D D

    H_A#(3..31) H_D#(0..63)
    HT 16x16 800MHZ

    DVI-D Conn. LCD CONN CRT & TV-OUT ATI-RX485M


    page 30 page 29 page 28

    465 BGA
    page 11,12,13,14

    A-Link Express
    2 x PCIE
    PCI-Express
    ATI M52PG/M54P/M56P
    with 64/128/256MB VRAM USB 2.0 USB conn x 2 / New card
    C
    page 39 C
    page 16,17,18,19,20,21

    ATI-SB460 USB 2.0 BT Conn


    page 34
    PCI BUS 549 BGA
    Audio CKT
    AC-LINK AMP & Audio Jack
    ALC883 page 45
    page 22,23,24,25,26 page 44
    Mini PCI Socket Realtek 1394 Controller
    RTL8100CL ENE Controller MDC Conn.
    Mini card / CAM RTL8110SCL CB714 VT6311S page 34
    page 36 page 31 page 40
    page 37
    SATA SATA HDD Conn.
    page 27
    6in1 CardReader LPC BUS
    RJ45 CONN Slot 0 1394
    B page 32 Slot page 38 Conn. B
    page 38 page 40
    PATA One Channel HDD Conn.
    CDROM Conn.
    page 27

    Power On/Off CKT / LID switch / Power OK CKT


    page 42
    SMsC LPC47N207 ENE KB910
    page 41 page 33
    DC/DC Interface CKT. CIR/LED RTC CKT.
    page 46 page 43 page 22

    Int. KBD
    Power Circuit DC/DC FIR module page 34
    page 46~ page 41
    Touch Pad
    CONN.page 34 BIOS
    A
    page 35 A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 2 of 55
    5 4 3 2 1
    5 4 3 2 1

    SIGNAL
    STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
    Voltage Rails
    Full ON HIGH HIGH HIGH HIGH ON ON ON ON

    Power Plane Description S0 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

    VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
    D D
    B+ AC or battery power rail for power circuit. N/A N/A N/A
    S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
    +CPU_CORE Core voltage for CPU ON OFF OFF
    +0.9V 0.9V switched power rail for DDRII terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
    +1.2V_HT 1.2V switched power rail ON OFF OFF
    +1.5VS 1.5V switched power rail ON OFF OFF
    +1.8V 1.8V power rail for DDRII ON ON OFF Board ID / SKU ID Table for AD channel
    +1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
    +2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
    +3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
    +3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
    +5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
    +5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
    +VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
    +RTCVCC RTC power ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
    +1.2VS 1.2V switched power rail for PCIE ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
    C C
    +0.9VS 0.9V switched power rail for VRAM terminator ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
    +1.8VALW 1.8V switched power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
    +VDD_CORE 1.0~1.2V switched power rail for VGA ON OFF OFF

    BOARD ID Table BTO Option Table


    Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

    External PCI Devices Board ID PCB Revision BTO Item BOM Structure
    Device IDSEL# REQ#/GNT# Interrupts
    0 0.1 VGA
    Ca rdBus(SD) AD20 2 PIRQE/PIRQH
    1 UMA
    1 394 AD16 0 PIRQE
    2 UMA's DVI
    LAN(10/100) AD17 3 PIRQF
    3 LAN(10/100)
    Mini-PCI(WLAN/TV-Tuner) AD18 1 PIRQG/PORQH
    4 LAN(GIGA)
    5 MINI CARD1
    6 MINI CARD2
    7 SATA-to-IDE
    B PATA B

    SKU ID Table GRAPEVINE


    EC SM Bus1 address EC SM Bus2 address G72MV Only
    Device Address Device Address
    SKU ID SKU G73 Only
    Smart Battery 0001 011X b Fintek F75383M 1001 100X b
    0 PM VRAM
    EEPROM(24C16/02) 1010 000X b
    1 GM VRAM 64M
    GMT G781-1 1001 101X b
    2 VRAM 128M
    3 VRAM 256M
    4 MEDIA/B
    5 CIR
    6 FIR
    SB460 SM Bus address 7 GENEVA
    Device Address
    LCM
    Sub-woofer
    Clock Generator 1101 001Xb
    (ICS9LPRS325AKLFT_MLF72)
    A DDR DIMM0 A
    1001 000Xb
    DDR DIMM2 1001 010Xb

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 3 of 55
    5 4 3 2 1
    5 4 3 2 1

    +5V 1.5V SW CPU_VDDA_RUN (S0, S1)


    +3.3VALW_NTB REGULATOR AMD CPU

    +3.3VSUS_NTB +VIN VCCA 2.5V


    BATTERY
    CPU_VDD_RUN (S0, S1)

    CHARGER
    BATTERY
    +VDC MAIN PWR SW +5V SW REGULATOR VDDCORE
    REGULATOR
    +5VALW_NTB 0.375-1.500V 30A
    +5VSUS_NTB +VIN
    VLDT 1.2V SW VLDT_RUN (S0, S1) VLDT 1.2V 3A
    D +5V NB RS485 D
    REGULATOR
    +3.3V_NTB
    HT VLDT 1.2V 1A
    SWITCH
    +3.3VALW

    POWER SWITCH
    SWITCH
    +VIN
    PWR

    +/-5%

    VCC_NB (S0, S1)


    CPU

    NB CORE SW
    12V

    +5V_NTB NB CORE 10A


    +5V REGULATOR
    PCI-E CORE
    +3.3VSUS +VIN &PCI-E IO 3.5A
    +VIN_MEM PCIE&SB SW VDDA_1V2(S0, S1)
    SW +5V HTPLL (1.8V) 200mA
    +/-5%

    REGULATOR
    12V

    PLL & DAC-Q(1.8V)


    +5VSUS +3.3V 200mA
    +5V 1.8V SW +1.8V(S0, S1) TRANSFORMER
    ATX POWER SUPPLY

    REGULATOR 400mA
    +5VALW_ATX
    5VSB
    +/-5%

    +3.3V AVDD (S0, S1) DAC 300mA


    +5VALW
    +5VDUAL_ATX
    SW
    +5V_ATX
    +/-5%

    +5VSUS
    DDRII SODIMMX2
    5V

    +3.3VALW LDO +3.3VALW_ATX +VIN CPU_VDDIO_SUS (S0, S1, S3)


    1.8V VDD&VTT VDD MEM 4A
    REGULATOR
    +5V +5VSUS SW REGULATOR CPU_VTT_SUS (S0, S1,S3)
    +3.3VDUAL_ATX
    +/-5%
    3.3V

    C
    SW VTT_MEM 0.5A C

    VCC_SB (S0, S1)


    +3.3V_ATX

    SB SB600
    +/-5%
    -12V

    X4 PCI-E 0.8A
    ATA I/O 0.2A
    ATA PLL 0.01A
    PCI-E PVDD 80mA
    SB CORE 0.6A
    CONTROL SIGNAL: +3.3VALW 1.2V LDO +1.2VALW 1.2V S5 PW 0.22A
    MOBILE: BATTERY REGULATOR
    +3.3V 3.3V I/O 0.45A
    DESKTOP: ATX +3.3VALW 3.3V S5 PW 0.01A
    +5V USB CORE I/O 0.2A

    MINI PCI SLOT GBIT ENTHENET


    +3.3V 3.3V(S0, S1)1.5A 3.3V 0.5A
    B +5V 5V (S0, S1) 0.1A (S0, S1, S3, S4, S5) B

    +3.3VALW 3.3V(S3, S5) 0.2A


    +VIN PCI-E CARD
    1.5V (S0, S1) 0.7A
    3.3V (S3, S5) 0.3A
    +3.3V 3.3V (S0, S1) 1.3A
    +5V

    +5VALW SUPER I/O


    PCI Slot (per slot) X1 PCIE per X16 PCIE CNR CONNECTOR
    +3.3VDUAL (S3) 0.01A
    5V 5.0A 3.3V 3.0A 3.3V 3.0A 5V 1.0A +3.3V (S0, S1) 0.01A
    USB X7 FR USB X2 RL 2XPS/2
    3.3V 7.6A 3.3V 1.0A +5V (S0, S1) 0.1A
    12V 0.5A 12V 5.5A
    12V 0.5A 12V 0.5A VDD VDD 5VDual
    3.3Vaux 0.1A
    3.3Vaux 0.375A 3.3Vaux 1.0A 5VDual 5VDual HD CODEC
    1.0A
    -12V 0.1A -12V 0.1A 3.5A 1.0A 3.3V CORE 0.3A
    5VDual 0.5A 5V ANALOG 0.1A
    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 4 of 55
    5 4 3 2 1
    5 4 3 2 1

    H_CADIP[0..15] H_CADOP[0..15]
    <11> H_CADIP[0..15] H_CADIN[0..15] H_CADON[0..15] H_CADOP[0..15] <11>
    <11> H_CADIN[0..15] H_CADON[0..15] <11>

    PROCESSOR HYPERTRANSPORT INTERFACE


    D D
    VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
    SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
    ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

    +1.2V_HT
    JP72A
    FAN1 Conn
    D4 VLDT_A3 VLDT_B3 AE5 1 2 C1
    D3 AE4 4.7U_0805_10V4Z +5VS
    VLDT_A2 VLDT_B2 C2 10U_0805_10V4Z +5VS
    D2 VLDT_A1 VLDT_B1 AE3
    D1 VLDT_A0 VLDT_B0 AE2 1 2

    1
    H_CADIP15 N5 T4 H_CADOP15 U2 D1
    H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15 1SS355_SOD323
    P5 L0_CADIN_L15 L0_CADOUT_L15 T3 1 VEN GND 8
    H_CADIP14 M3 V5 H_CADOP14 2 7
    H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14 +VCC_FAN1 VIN GND D2
    M4 U5 3 6

    2
    H_CADIP13 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP13 EN_DFAN1 VO GND 1N4148_SOT23
    L5 L0_CADIN_H13 L0_CADOUT_H13 V4 <33> EN_DFAN1 4 VSET GND 5
    H_CADIN13 M5 V3 H_CADON13 1 2
    H_CADIP12 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP12 G993P1UF_SOP8
    K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
    H_CADIN12 K4 W5 H_CADON12
    H_CADIP11 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP11 C3
    H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
    H_CADIN11 H4 AA5 H_CADON11 10U_0805_10V4Z
    H_CADIP10 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP10
    G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 1 2
    H_CADIN10 H5 AB3 H_CADON10
    H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9 +3VS C4
    F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
    H_CADIN9 F4 AC5 H_CADON9 1000P_0402_50V7K
    H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8
    E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 1 2

    1
    H_CADIN8 F5 AD3 H_CADON8
    C H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 C
    HTT Interfa ce

    N3 T1 H_CADOP7 R1
    H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7 10K_0402_5%
    N2 L0_CADIN_L7 L0_CADOUT_L7 R1
    H_CADIP6 L1 U2 H_CADOP6 40mil
    H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6 JP73
    M1 U3

    2
    H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5 +VCC_FAN1
    L3 L0_CADIN_H5 L0_CADOUT_H5 V1 1
    H_CADIN5 L2 U1 H_CADON5
    L0_CADIN_L5 L0_CADOUT_L5 <33> FAN_SPEED1 2
    H_CADIP4 J1 W2 H_CADOP4
    H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4 3
    K1 L0_CADIN_L4 L0_CADOUT_L4 W3 1
    H_CADIP3 G1 AA2 H_CADOP3 C5 ACES_85205-03001
    H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3 1000P_0402_50V7K
    H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
    H_CADIP2 G3 AB1 H_CADOP2
    H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2 2
    G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
    H_CADIP1 E1 AC2 H_CADOP1
    H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
    F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
    H_CADIP0 E3 AD1 H_CADOP0
    H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
    E2 L0_CADIN_L0 L0_CADOUT_L0 AC1

    <11> H_CLKIP1 H_CLKIP1 J5 Y4 H_CLKOP1 H_CLKOP1 <11>


    H_CLKIN1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKON1
    <11> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <11>
    <11> H_CLKIP0 H_CLKIP0 J3 Y1 H_CLKOP0 H_CLKOP0 <11>
    +1.2V_HT H_CLKIN0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKON0
    <11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>

    R2 1 2 51_0402_1% H_CTLIP1 P3 T5
    R3 1 H_CTLIN1 L0_CTLIN_H1 L0_CTLOUT_H1
    2 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5

    <11> H_CTLIP0 H_CTLIP0 N1 R2 H_CTLOP0 H_CTLOP0 <11>


    H_CTLIN0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLON0
    <11> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <11>

    B Athlon 64 S1 B
    Processor Socket

    +1.2V_HT

    1 1 1 1 1
    C6 C8 C9 C10 C11

    10U_0805_10V4Z 180P_0402_50V8J
    2 2 2 2 2
    0.22U_0603_10V7K 180P_0402_50V8J
    0.22U_0603_10V7K

    LAYOUT: Place bypass cap on topside of board


    NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
    TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
    A A
    TO OTHER HT POWER PINS
    PLACE CLOSE TO VLDT0 POWER PINS

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 5 of 55
    5 4 3 2 1
    A B C D E

    DDR_A_MA[0..15] DDR_A_DQS[0..7]
    <9> DDR_A_MA[0..15]
    DDR_B_DQS[0..7]
    Processor DDR2 Memory Interface <9> DDR_A_DQS[0..7]
    DDR_A_DQS#[0..7]
    <10> DDR_B_DQS[0..7] <9> DDR_A_DQS#[0..7]
    VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
    SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED DDR_B_DQS#[0..7]
    <10> DDR_B_DQS#[0..7] <10> DDR_B_D[0..63]
    ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE JP72C DDR_A_D[0..63] <9>
    DDR_B_D63 AD11 AA12 DDR_A_D63
    DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62
    AF11 MB_DATA62 MA_DATA62 AB12
    DDR_B_D61 AF14 AA14 DDR_A_D61
    DDR_B_D60 MB_DATA61 MA_DATA61 DDR_A_D60
    AE14 MB_DATA60 MA_DATA60 AB14
    DDR_B_D59 Y11 W11 DDR_A_D59
    DDR_B_D58 MB_DATA59 MA_DATA59 DDR_A_D58
    AB11 MB_DATA58 MA_DATA58 Y12
    DDR_B_D57 AC12 AD13 DDR_A_D57
    +1.8V DDR_B_D56 MB_DATA57 MA_DATA57 DDR_A_D56
    AF13 MB_DATA56 MA_DATA56 AB13
    +0.9VREF_CPU DDR_B_D55 AF15 AD15 DDR_A_D55
    4 JP72B +0.9V DDR_B_D54 MB_DATA55 MA_DATA55 DDR_A_D54 4
    AF16 MB_DATA54 MA_DATA54 AB15
    DDR_B_D53 AC18 AB17 DDR_A_D53
    MB_DATA53 MA_DATA53
    1

    W17 D10 DDR_B_D52 AF19 Y17 DDR_A_D52


    R4 M_VREF VTT1 DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
    VTT2 C10 AD14 MB_DATA51 MA_DATA51 Y14
    39.2_0402_1%~D Y10 B10 DDR_B_D50 AC14 W14 DDR_A_D50
    VTT_SENSE VTT3 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
    VTT4 AD10 AE18 MB_DATA49 MA_DATA49 W16
    W10 DDR_B_D48 AD18 AD17 DDR_A_D48
    2

    M_ZN VTT5 DDR_B_D47 MB_DATA48 MA_DATA48 DDR_A_D47


    AE10 M_ZN VTT6 AC10 AD20 MB_DATA47 MA_DATA47 Y18
    M_ZP AF10 AB10 DDR_B_D46 AC20 AD19 DDR_A_D46
    M_ZP VTT7 DDR_B_D45 MB_DATA46 MA_DATA46 DDR_A_D45
    VTT8 AA10 AF23 MB_DATA45 MA_DATA45 AD21
    R5 A10 DDR_B_D44 AF24 AB21 DDR_A_D44

    DDRII Cmd/Ctrl//Clk
    VTT9 MB_DATA44 MA_DATA44
    1

    39.2_0402_1%~D DDR_B_D43 AF20 AB18 DDR_A_D43


    DDR_CS3_DIMMA# DDR_A_CLK2 DDR_B_D42 MB_DATA43 MA_DATA43 DDR_A_D42
    <9> DDR_CS3_DIMMA# V19 MA0_CS_L3 MA0_CLK_H2 Y16 DDR_A_CLK2 <9> AE20 MB_DATA42 MA_DATA42 AA18
    <9> DDR_CS2_DIMMA# DDR_CS2_DIMMA# J22 AA16 DDR_A_CLK#2 DDR_A_CLK#2 <9> DDR_B_D41 AD22 AA20 DDR_A_D41
    DDR_CS1_DIMMA# MA0_CS_L2 MA0_CLK_L2 DDR_A_CLK1 DDR_B_D40 MB_DATA41 MA_DATA41 DDR_A_D40
    <9> DDR_CS1_DIMMA# V22 MA0_CS_L1 MA0_CLK_H1 E16 DDR_A_CLK1 <9> AC22 MB_DATA40 MA_DATA40 Y20
    <9> DDR_CS0_DIMMA# DDR_CS0_DIMMA# T19 F16 DDR_A_CLK#1 DDR_A_CLK#1 <9> DDR_B_D39 AE25 AA22 DDR_A_D39
    2

    MA0_CS_L0 MA0_CLK_L1 DDR_B_D38 MB_DATA39 MA_DATA39 DDR_A_D38


    AD26 MB_DATA38 MA_DATA38 Y22
    <10> DDR_CS3_DIMMB# DDR_CS3_DIMMB# Y26 AF18 DDR_B_CLK2 DDR_B_CLK2 <10> DDR_B_D37 AA25 W21 DDR_A_D37
    DDR_CS2_DIMMB# J24 MB0_CS_L3 MB0_CLK_H2 MB_DATA37 MA_DATA37
    <10> DDR_CS2_DIMMB# MB0_CS_L2 MB0_CLK_L2 AF17 DDR_B_CLK#2 DDR_B_CLK#2 <10> DDR_B_D36 AA26 MB_DATA36 MA_DATA36 W22 DDR_A_D36
    <10> DDR_CS1_DIMMB# DDR_CS1_DIMMB# W24 A17 DDR_B_CLK1 DDR_B_CLK1 <10> DDR_B_D35 AE24 AA21 DDR_A_D35
    DDR_CS0_DIMMB# U23 MB0_CS_L1 MB0_CLK_H1 MB_DATA35 MA_DATA35
    PLACE THEM CLOSE TO <10> DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L1 A18 DDR_B_CLK#1 DDR_B_CLK#1 <10> DDR_B_D34 AD24 MB_DATA34 MA_DATA34 AB22 DDR_A_D34
    DDR_B_D33 AA23 AB24 DDR_A_D33
    CPU WITHIN 1" DDR_CKE1_DIMMB DDR_B_ODT1 DDR_B_D32 MB_DATA33 MA_DATA33 DDR_A_D32
    <10> DDR_CKE1_DIMMB H26 MB_CKE1 MB0_ODT1 W23 DDR_B_ODT1 <10> AA24 MB_DATA32 MA_DATA32 Y24
    <10> DDR_CKE0_DIMMB DDR_CKE0_DIMMB J23 W26 DDR_B_ODT0 DDR_B_ODT0 <10> DDR_B_D31 G24 H22 DDR_A_D31
    DDR_CKE1_DIMMA MB_CKE0 MB0_ODT0 DDR_A_ODT1 DDR_B_D30 MB_DATA31 MA_DATA31 DDR_A_D30
    <9> DDR_CKE1_DIMMA J20 MA_CKE1 MA0_ODT1 V20 DDR_A_ODT1 <9> G23 MB_DATA30 MA_DATA30 H20
    <9> DDR_CKE0_DIMMA DDR_CKE0_DIMMA J21 U19 DDR_A_ODT0 DDR_A_ODT0 <9> DDR_B_D29 D26 E22 DDR_A_D29
    MA_CKE0 MA0_ODT0 DDR_B_D28 MB_DATA29 MA_DATA29 DDR_A_D28
    DDR_B_MA[0..15] <10> C26 MB_DATA28 MA_DATA28 E21
    DDR_A_MA15 K19 J25 DDR_B_MA15 DDR_B_D27 G26 J19 DDR_A_D27
    DDR_A_MA14 MA_ADD15 MB_ADD15 DDR_B_MA14 DDR_B_D26 MB_DATA27 MA_DATA27 DDR_A_D26
    K20 MA_ADD14 MB_ADD14 J26 G25 MB_DATA26 MA_DATA26 H24
    DDR_A_MA13 V24 W25 DDR_B_MA13 DDR_B_D25 E24 F22 DDR_A_D25

    To reverse SODIMM socket

    To normal SODIMM socket


    DD RII Data
    DDR_A_MA12 MA_ADD13 MB_ADD13 DDR_B_MA12 DDR_B_D24 MB_DATA25 MA_DATA25 DDR_A_D24
    K24 MA_ADD12 MB_ADD12 L23 E23 MB_DATA24 MA_DATA24 F20
    DDR_A_MA11 L20 L25 DDR_B_MA11 DDR_B_D23 C24 C23 DDR_A_D23
    DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D22 MB_DATA23 MA_DATA23 DDR_A_D22
    R19 MA_ADD10 MB_ADD10 U25 B24 MB_DATA22 MA_DATA22 B22
    DDR_A_MA9 L19 L24 DDR_B_MA9 DDR_B_D21 C20 F18 DDR_A_D21
    DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D20 MB_DATA21 MA_DATA21 DDR_A_D20
    L22 MA_ADD8 MB_ADD8 M26 B20 MB_DATA20 MA_DATA20 E18
    DDR_A_MA7 L21 L26 DDR_B_MA7 DDR_B_D19 C25 E20 DDR_A_D19
    DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D18 MB_DATA19 MA_DATA19 DDR_A_D18
    M19 MA_ADD6 MB_ADD6 N23 D24 MB_DATA18 MA_DATA18 D22
    DDR_A_MA5 M20 N24 DDR_B_MA5 DDR_B_D17 A21 C19 DDR_A_D17
    3 DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D16 MB_DATA17 MA_DATA17 DDR_A_D16 3
    M24 MA_ADD4 MB_ADD4 N25 D20 MB_DATA16 MA_DATA16 G18
    DDR_A_MA3 M22 N26 DDR_B_MA3 DDR_B_D15 D18 G17 DDR_A_D15
    DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D14 MB_DATA15 MA_DATA15 DDR_A_D14
    N22 MA_ADD2 MB_ADD2 P24 C18 MB_DATA14 MA_DATA14 C17
    DDR_A_MA1 N21 P26 DDR_B_MA1 DDR_B_D13 D14 F14 DDR_A_D13
    DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 DDR_B_D12 MB_DATA13 MA_DATA13 DDR_A_D12
    R21 MA_ADD0 MB_ADD0 T24 C14 MB_DATA12 MA_DATA12 E14
    DDR_B_D11 A20 H17 DDR_A_D11
    DDR_A_BS#2 MB_DATA11 MA_DATA11
    <9> DDR_A_BS#2 K22 MA_BANK2 MB_BANK2 K26 DDR_B_BS#2 DDR_B_BS#2 <10> DDR_B_D10 A19 MB_DATA10 MA_DATA10 E17 DDR_A_D10
    <9> DDR_A_BS#1 DDR_A_BS#1 R20 T26 DDR_B_BS#1 DDR_B_BS#1 <10> DDR_B_D9 A16 E15 DDR_A_D9
    DDR_A_BS#0 MA_BANK1 MB_BANK1 MB_DATA9 MA_DATA9
    <9> DDR_A_BS#0 T22 MA_BANK0 MB_BANK0 U26 DDR_B_BS#0 DDR_B_BS#0 <10> DDR_B_D8 A15 MB_DATA8 MA_DATA8 H15 DDR_A_D8
    DDR_B_D7 A13 E13 DDR_A_D7
    DDR_A_RAS# MB_DATA7 MA_DATA7
    <9> DDR_A_RAS# T20 MA_RAS_L MB_RAS_L U24 DDR_B_RAS# DDR_B_RAS# <10> DDR_B_D6 D12 MB_DATA6 MA_DATA6 C13 DDR_A_D6
    <9> DDR_A_CAS# DDR_A_CAS# U20 V26 DDR_B_CAS# DDR_B_CAS# <10> DDR_B_D5 E11 H12 DDR_A_D5
    DDR_A_WE# MA_CAS_L MB_CAS_L MB_DATA5 MA_DATA5
    <9> DDR_A_WE# U21 MA_WE_L MB_WE_L U22 DDR_B_WE# DDR_B_WE# <10> DDR_B_D4 G11 MB_DATA4 MA_DATA4 H11 DDR_A_D4
    DDR_B_D3 B14 G14 DDR_A_D3
    DDR_B_D2 MB_DATA3 MA_DATA3 DDR_A_D2
    A14 MB_DATA2 MA_DATA2 H14
    Athlon 64 S1 DDR_B_D1 A11 F12 DDR_A_D1
    Processor DDR_B_D0 MB_DATA1 MA_DATA1 DDR_A_D0
    C11 MB_DATA0 MA_DATA0 G12
    Socket
    <10> DDR_B_DM[0..7] DDR_A_DM[0..7] <9>
    DDR_B_DM7 AD12 Y13 DDR_A_DM7
    DDR_B_DM6 MB_DM7 MA_DM7 DDR_A_DM6
    AC16 MB_DM6 MA_DM6 AB16
    DDR_B_DM5 AE22 Y19 DDR_A_DM5
    DDR_B_DM4 MB_DM5 MA_DM5 DDR_A_DM4
    AB26 MB_DM4 MA_DM4 AC24
    DDR_A_CLK2 DDR_B_CLK2 DDR_B_DM3 E25 F24 DDR_A_DM3
    DDR_B_DM2 MB_DM3 MA_DM3 DDR_A_DM2
    1 1 A22 MB_DM2 MA_DM2 E19
    DDR_B_DM1 B16 C15 DDR_A_DM1
    C12 C13 DDR_B_DM0 MB_DM1 MA_DM1 DDR_A_DM0
    A12 MB_DM0 MA_DM0 E12
    1.5P_0402_50V8C 1.5P_0402_50V8C
    DDR_A_CLK#2 2 DDR_B_CLK#2 2 DDR_B_DQS7 DDR_A_DQS7
    AF12 MB_DQS_H7 MA_DQS_H7 W12
    DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
    DDR_A_CLK1 DDR_B_CLK1 DDR_B_DQS6 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS6
    AE16 MB_DQS_H6 MA_DQS_H6 Y15
    1 1 DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
    DDR_B_DQS5 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS5
    AF21 MB_DQS_H5 MA_DQS_H5 AB19
    C14 C15 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
    1.5P_0402_50V8C 1.5P_0402_50V8C DDR_B_DQS4 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS4
    AC25 MB_DQS_H4 MA_DQS_H4 AD23
    DDR_A_CLK#1 2 DDR_B_CLK#1 2 DDR_B_DQS#4 DDR_A_DQS#4
    AC26 MB_DQS_L4 MA_DQS_L4 AC23
    DDR_B_DQS3 F26 G22 DDR_A_DQS3
    DDR_B_DQS#3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS#3
    E26 MB_DQS_L3 MA_DQS_L3 G21
    PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR DDR_B_DQS2 A24 C22 DDR_A_DQS2
    2 DDR_B_DQS#2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS#2 2
    WITHIN 1.5 INCH WITHIN 1.5 INCH A23 MB_DQS_L2 MA_DQS_L2 C21
    DDR_B_DQS1 D16 G16 DDR_A_DQS1
    DDR_B_DQS#1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS#1
    C16 MB_DQS_L1 MA_DQS_L1 G15
    DDR_B_DQS0 C12 G13 DDR_A_DQS0
    DDR_B_DQS#0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS#0
    B12 MB_DQS_L0 MA_DQS_L0 H13

    DDR: DATA
    Athlon 64 S1
    Processor Socket

    ATI check ,Use +0.9V PWR , can delete or not

    A1 A26
    +1.8V

    Athlon 64 S1g1
    1

    R6
    uPGA638
    1K_0402_1% +0.9VREF_CPU
    Top View
    2

    +0.9VREF_CPU

    1 1 1 1
    1

    C16 C18 C19 C20


    1 R7 AF1 1
    0.1U_0402_16V4Z 1U_0402_6.3V4Z
    1K_0402_1% 2 2 2 2
    1000P_0402_50V7K
    2

    1000P_0402_50V7K
    VDD_VREF_SUS_CPU

    LAYOUT:PLACE CLOSE TO CPU Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 6 of 55
    A B C D E
    5 4 3 2 1

    ATHLON Control and Debug +1.8V

    LAYOUT: ROUTE VDDA TRACE APPROX.

    1
    50 mils WIDE (USE 2x25 mil TRACES TO
    EXIT BALL FIELD) AND 500 mils LONG. R8 R9

    +2.5VS 300_0402_5% 300_0402_5%


    L1 50mil width(600mA) JP72D

    2
    2 1 +VDDA_25V F8 AF6 H_THERMTRIP_S#
    VDDA2 THERMTRIP_L
    1 1 1 F9 VDDA1 PROCHOT_L AC7 CPU_PROCHOT#_1.8
    FBM-L11-321611-260-LMT_1206 C22 C23
    C24 CPU_HT_RESET# B7
    3300P_0402_50V7K CPU_ALL_PWROK RESET_L
    A7 PWROK
    2 2 2 CPU_LDTSTOP# F10 LDTSTOP_L
    D 4.7U_0805_10V4Z 0.22U_0603_10V7K VID5 D
    VID5 A5 VID5 <54>
    R10 1 2 300_0402_5% CPU_SIC_R AF4 C6 VID4 VID4 <54>
    SIC VID4 VID3
    AF5 SID VID3 A6 VID3 <54>
    A4 VID2 VID2 <54>
    R12 CPU_HTREF1 VID2 VID1
    SB460 ONLY +1.2V_HT 1 2 44.2_0603_1% P6 HTREF1 VID1 C5 VID1 <54>
    R13 1 2 44.2_0603_1% CPU_HTREF0 R6 B5 VID0 VID0 <54>
    HTREF0 VID0
    AC6 CPU_PRESENT#
    CPU_VCC_SENSE CPU_PRESENT_L
    <54> CPU_VCC_SENSE F6 VDD_FB_H
    place them to CPU within 1" CPU_VSS_SENSE E6 A3 PSI# PSI# <54>
    <54> CPU_VSS_SENSE VDD_FB_L PSI_L
    +3VS +1.8V PAD T1 VDDIOFB_H W9
    PAD T2 VDDIOFB_L VDDIO_FB_H
    Y9 VDDIO_FB_L
    +1.8VS

    1
    R15 C25 1 2 CPU_CLKIN_SC_P A9
    <15> CPUCLK CLKIN_H
    C26 CPU_CLKIN_SC_N A8 CLKIN_L
    1

    1
    1 2 3900P_0402_50V7K
    R14 4.7K_0402_5% R16 C PU_DBRDY G10 E10 CPU_DBREQ#
    DBRDY DBREQ_L

    5
    300_0402_5% @ U49 0.1U_0402_16V4Z 169_0402_1%

    2
    2 B CPU_TMS AA9

    P
    CPU_ALL_PWROK CPU_TCK TMS CPU_TDO
    4 AC9 AE9
    2

    2
    Y C27 1 CPU_TRST# TCK TDO Place within 0.5" from CPU
    <23> CPU_PWRGD 1 A <15> CPUCLK# 2 AD9 TRST_L

    G
    CPU_TDI AF9 25mil/6mil/6mil/6mil/25mil
    NC7SZ08P5X_NL_SC70-5 3900P_0402_50V7K TDI R17

    3
    CPU_TEST25_H_BYPASSCLK_H E9 C9 CPU_TEST29_H_FBCLKOUT_P 1 2
    CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H CPU_TEST29_L_FBCLKOUT_N 80.6_0402_1%
    E8 TEST25_L TEST29_L C8 ROUTE AS 80 Ohm DIFFERENTIAL PAIR
    CPU_TEST19_PLLTEST0 G9 PLACE IT CLOSE TO CPU WITHIN 1"
    R806 1 CPU_TEST18_PLLTEST1 TEST19
    2 @ 0_0402_5% H10

    MISC
    TEST18
    AA7 TEST13
    +1.8VS C2
    +1.8V PAD T13 TEST9
    D7 TEST17 TEST24 AE7 T14 PAD
    C28 PAD T15 E7 AD7 T16 PAD
    TEST16 TEST23
    1

    1 2 PAD T17 F7 AE8 T18 PAD


    R18 PAD T19 TEST15 TEST22 CPU_TEST21_SCANEN
    C7 TEST14 TEST21 AB8
    5

    300_0402_5% U50 0.1U_0402_16V4Z PAD T20 AC8 AF7 T21 PAD


    TEST12 TEST20
    2
    P

    B CPU_LDTSTOP# PAD T23


    4 C3 J7 T24 PAD
    2

    Y PAD T25 TEST7 TEST28_H


    <13,23> LDT_STOP# 1 A AA6 TEST6 TEST28_L H8 T26 PAD
    G

    C CPU_THERMDC C
    W7 THERMDC TEST27 AF8 T27 PAD
    NC7SZ08P5X_NL_SC70-5 CPU_THERMDA W8 AE6 CPU_TEST26_BURNIN#
    3

    PAD T28 THERMDA TEST26


    Y6 TEST3 TEST10 K8 T29 PAD
    PAD T30 AB6 C4 T31 PAD
    TEST2 TEST8
    Modify 11/22 P20 RSVD0 RSVD8 H16
    R807 1 2 @ 0_0402_5% P19 B18
    RSVD1 RSVD9
    N20 RSVD2
    N19 RSVD3 RSVD10 B3
    +1.8VS +1.8VS C1
    RSVD11

    RSVD12 H6
    1

    +1.8V +3VS G6
    RSVD13

    1
    R19 C29 D5
    300_0402_5% R844 RSVD14
    1 2

    1
    RSVD15 R24
    5

    U51 0.1U_0402_16V4Z @ 10K_0402_5% R845 W18


    2

    R8041 0_0402_5% SB_PWROK_R @ 4.7K_0402_5% RSVD16


    2 2 R26 R23
    P

    <23,42> SB_PWRGD

    2
    B CPU_HT_RESET# RSVD4 RSVD17
    Y 4 R25 RSVD5 RSVD18 AA8
    <22> LDT_RST# 1 P22 H18

    2
    A RSVD6 RSVD19

    2
    G

    B
    Q47 R22 H19
    NC7SZ08P5X_NL_SC70-5 RSVD7 RSVD20
    3

    E
    LDT_RST# 3 1 3V_LDT_RST#

    C
    @ MMBT3904_SOT23

    AMD NPT S1 SOCKET


    R808 1 2 @ 0_0402_5% Processor Socket

    +1.8V

    +1.8V
    R24 1@ 220_0402_5%

    R25 1@ 220_0402_5%

    R26 1@ 220_0402_5%

    R27 1@ 220_0402_5%

    R28 1@ 220_0402_5%

    +3VALW

    HDT Connector

    1
    +1.8V +3VALW

    1
    R20
    1 R21

    1
    1K_0402_5% @ 1K_0402_5%
    B +1.8V R22 R23 B

    2
    JP74

    2 2
    300_0402_5% 10K_0402_5%
    1 2

    2
    Q2
    2

    2
    3 4 Q1 @ MMBT3904_SOT23 +1.8V
    2

    CPU_DBREQ# 5 6 H_THERMTRIP_S#
    7 8 3 1H_THERMTRIP# 3 1 MAINPWON <47,48,50>
    C PU_DBRDY MMBT3904_SOT23
    9 10

    1
    CPU_TCK
    11 12 H_THERMTRIP# <23>
    CPU_TMS R29
    CPU_TDI 13 14
    CPU_TRST# 15 16 10K_0402_5%
    CPU_TDO 17 18 +3VS

    CPU_PH_G 2
    19 20
    21 22 3V_LDT_RST#
    23 24

    1
    26 R30
    NOTE: HDT TERMINATION IS REQUIRED
    4.7K_0402_5%
    FOR REV. Ax SILICON ONLY. @ SAMTEC_ASP-68200-07
    +1.8V

    2
    2
    B
    Q3

    E
    CPU_TEST26_BURNIN# R32 1 2 300_0402_5% CPU_PROCHOT#_1.8 3 1 EC_THERM# <23,33>

    C
    MMBT3904_SOT23
    CPU_PRESENT# R33 1 2 1K_0402_5%
    CPU_TEST25_H_BYPASSCLK_H R34 1 2 510_0402_5%

    +3VS
    C30
    0.1U_0402_16V4Z
    1 2

    1 U4 CPU_TEST25_L_BYPASSCLK_L R42 1 2 510_0402_5%


    C31 1 8 CPU_TEST19_PLLTEST0 R43 1 2 300_0402_5%
    VDD SCLK EC_SMB_CK2 <33>
    CPU_TEST18_PLLTEST1 R44 1 2 300_0402_5%
    2200P_0402_50V7K CPU_THERMDA 2 7 CPU_TEST21_SCANEN R35 1 2 300_0402_5%
    A 2 D+ SDATA EC_SMB_DA2 <33> A
    CPU_THERMDC 3 6
    D- ALERT#
    4 THERM# GND 5

    ADM1032ARMZ-2REEL_MSOP8

    F75383M_MSOP8

    SMBus Address: 1001110X (b) Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 7 of 55
    5 4 3 2 1
    5 4 3 2 1

    D D

    BOTTOMSIDE DECOUPLING
    +CPU_CORE

    1 1 1 1 1 1 1 1 1
    C32 C33 C34 C35 C36 C37 C38 C39 C40

    JP72F 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
    2 2 2 2 2 2 2 2 2
    AA4 VSS1 VSS66 J6
    AA11 VSS2 VSS67 J8
    +CPU_CORE +CPU_CORE AA13 J10
    JP72E VSS3 VSS68
    AA15 VSS4 VSS69 J12
    AC4 VDD1 VDD43 V12 AA17 VSS5 VSS70 J14
    AD2 VDD2 VDD44 V14 AA19 VSS6 VSS71 J16
    G4 VDD3 VDD45 W4 AB2 VSS7 VSS72 J18
    H2 VDD4 Y2 AB7 K2 +CPU_CORE +1.8V
    VDD46 VSS8 VSS73
    J9 VDD5 VDD47 J15 AB9 VSS9 VSS74 K7
    J11 VDD6 VDD48 K16 AB23 VSS10 VSS75 K9
    J13 VDD7 VDD49 L15 AB25 VSS11 VSS76 K11 1 1 1 1 1 1 1 1
    K6 VDD8 M16 AC11 K13 C41 C42 C43 C44 C47 C48
    VDD50 VSS12 VSS77 C45 C46
    K10 VDD9 VDD51 P16 AC13 VSS13 VSS78 K15
    K12 VDD10 T16 AC15 K17 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_10V7K 0.22U_0603_10V7K
    VDD52 VSS14 VSS79 2 2 2 2 2 2 2 2
    K14 VDD11 VDD53 U15 AC17 VSS15 VSS80 L6
    L4 VDD12 VDD54 V16 AC19 VSS16 VSS81 L8
    L7 VDD13 +1.8V AC21 L10
    VSS17 VSS82
    L9 VDD14 AD6 VSS18 VSS83 L12 1 1
    L11 VDD15 H25 AD8 L14 C923 C924
    VDDIO1 VSS19 VSS84
    L13 VDD16 VDDIO2 J17 AD25 VSS20 VSS85 L16
    M2 VDD17 K18 AE11 L18 0.01U_0402_16V7K 180P_0402_50V8J
    C VDDIO3 VSS21 VSS86 2 2 C
    M6 VDD18 VDDIO4 K21 AE13 VSS22 VSS87 M7
    M8 VDD19 VDDIO5 K23 AE15 VSS23 VSS88 M9
    Power

    M10 VDD20 VDDIO6 K25 AE17 VSS24 VSS89 M11


    N7 VDD21 VDDIO7 L17 AE19 VSS25 VSS90 M17
    N9 VDD22 M18 AE21 N4
    N11 VDD23
    P8 VDD24
    VDDIO8
    VDDIO9 M21
    M23
    AE23
    B4
    VSS26
    VSS27
    VSS91
    VSS92 N8
    N10
    DECOUPLING BETWEEN PROCESSOR AND DIMMs
    VDDIO10 VSS28 VSS93
    P10 VDD25 M25 B6 N16
    R4 VDD26
    VDDIO11
    N17 B8
    VSS29 VSS94
    N18 PLACE CLOSE TO PROCESSOR AS POSSIBLE

    Ground
    VDDIO12 VSS30 VSS95
    R7 VDD27 VDDIO13 P18 B9 VSS31 VSS96 P2
    R9 VDD28 VDDIO14 P21 B11 VSS32 VSS97 P7
    R11 VDD29 VDDIO15 P23 B13 VSS33 VSS98 P9
    T2 VDD30 VDDIO16 P25 B15 VSS34 VSS99 P11
    T6 VDD31 R17 B17 P17 +1.8V
    VDDIO17 VSS35 VSS100
    T8 VDD32 VDDIO18 T18 B19 VSS36 VSS101 R8
    T10 VDD33 VDDIO19 T21 B21 VSS37 VSS102 R10
    T12 VDD34 VDDIO20 T23 B23 VSS38 VSS103 R16 1 1 1 1 1 1 1
    T14 VDD35 T25 B25 R18 C49 C50 C51 C52 C53 C54 C55
    VDDIO21 VSS39 VSS104
    U7 VDD36 VDDIO22 U17 D6 VSS40 VSS105 T7
    U9 VDD37 V18 D8 T9 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_10V7K 0.22U_0603_10V7K 0.22U_0603_10V7K
    VDDIO23 VSS41 VSS106 2 2 2 2 2 2 2
    U11 VDD38 VDDIO24 V21 D9 VSS42 VSS107 T11
    U13 VDD39 VDDIO25 V23 D11 VSS43 VSS108 T13
    V6 VDD40 VDDIO26 V25 D13 VSS44 VSS109 T15
    V8 VDD41 VDDIO27 Y25 D15 VSS45 VSS110 T17 1
    V10 VDD42 D17 VSS46 VSS111 U4 1 1 1 1 1
    D19 U6 C56 C57 C58 C59 C60 + C795
    VSS47 VSS112
    D21 VSS48 VSS113 U8
    D23 U10 0.22U_0603_10V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 180P_0402_50V8J 180P_0402_50V8J 220U_D2_4VM
    Athlon 64 S1 VSS49 VSS114 2 2 2 2 2 2
    D25 VSS50 VSS115 U12
    Processor Socket E4 U14
    VSS51 VSS116
    F2 VSS52 VSS117 U16
    F11 VSS53 VSS118 U18
    F13 VSS54 VSS119 V2
    F15 VSS55 VSS120 V7
    F17 VSS56 VSS121 V9
    F19 VSS57 VSS122 V11 CPU left-hand side CPU right-hand side
    F21 VSS58 VSS123 V13
    F23 V15 +0.9V +0.9V
    B VSS59 VSS124 B
    F25 VSS60 VSS125 V17
    H7 VSS61 VSS126 W6
    H9 VSS62 VSS127 Y21 1 1 1 1
    H21 Y23 C61 C68 C63 C65
    VSS63 VSS128
    H23 VSS64 VSS129 N6
    J4 4.7U_0805_10V4Z 0.22U_0603_10V7K 4.7U_0805_10V4Z 0.22U_0603_10V7K
    VSS65 2 2 2 2
    +CPU_CORE

    Athlon 64 S1
    Processor Socket
    1 1 1 1 1 1 1 1
    C69 C74 C71 C76
    + C796 45@ + C797 + C798 + C799
    45@ 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J
    820U_E9_2.5V_M_R7 820U_E9_2.5V_M_R7 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 2 2 2 2
    2 2 2 2

    A1 A26

    PROCESSOR POWER AND GROUND


    Athlon 64 S1g1
    uPGA638
    Top View

    A A

    AF1

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 8 of 55
    5 4 3 2 1
    5 4 3 2 1

    +1.8V +1.8V +DIMM_VREF +1.8V


    DDR_A_D[0..63]
    <6> DDR_A_D[0..63]
    DDR_A_DM[0..7]
    <6> DDR_A_DM[0..7]

    1
    0.1U_0402_16V4Z
    R45
    JP1 C77 DDR_A_DQS[0..7]
    <6> DDR_A_DQS[0..7]
    1 VREF VSS 2 1 1
    3 4 DDR_A_D4 1K_0402_1% DDR_A_MA[0..15]
    VSS DQ4 <6> DDR_A_MA[0..15]

    4.7U_0805_10V4Z

    C78
    DDR_A_D0 5 6 DDR_A_D5

    2
    DDR_A_D1 DQ0 DQ5 DDR_A_DQS#[0..7]
    7 DQ1 VSS 8 <6> DDR_A_DQS#[0..7]
    DDR_A_DM0 2 2
    9 VSS DM0 10
    D DDR_A_DQS#0 D
    11 DQS0# VSS 12
    DDR_A_DQS0 13 14 DDR_A_D6
    DQS0 DQ6

    1
    15 16 DDR_A_D7 R46
    DDR_A_D2 VSS DQ7
    17 DQ2 VSS 18
    DDR_A_D3 19 20 DDR_A_D12
    DQ3 DQ12 DDR_A_D13 1K_0402_1%
    21 VSS DQ13 22
    DDR_A_D8 23 24

    2
    DDR_A_D9 DQ8 VSS DDR_A_DM1
    25 DQ9 DM1 26
    27 VSS VSS 28
    DDR_A_DQS#1 29 30 DDR_A_CLK1 +1.8V
    DQS1# CK0 DDR_A_CLK1 <6>
    DDR_A_DQS1 31 32 DDR_A_CLK#1
    DQS1 CK0# DDR_A_CLK#1 <6>
    33 VSS VSS 34
    DDR_A_D10 35 36 DDR_A_D14
    DDR_A_D11 DQ10 DQ14 DDR_A_D15
    37 DQ11 DQ15 38
    39 VSS VSS 40

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z
    1
    1 1 1 1 1 1 1 1 1 1
    41 42 + C802
    DDR_A_D16 VSS VSS DDR_A_D20
    43 DQ16 DQ20 44

    C79

    C80

    C81

    C82

    C83

    C84

    C85

    C86

    C87

    C88
    DDR_A_D17 45 46 DDR_A_D21 220U_D2_4VM
    DQ17 DQ21 2 2 2 2 2 2 2 2 2 2 2
    47 VSS VSS 48
    DDR_A_DQS#2 49 50
    DDR_A_DQS2 DQS2# NC DDR_A_DM2
    51 DQS2 DM2 52
    53 VSS VSS 54
    DDR_A_D18 55 56 DDR_A_D22
    DDR_A_D19 DQ18 DQ22 DDR_A_D23
    57 DQ19 DQ23 58
    59 VSS VSS 60 Layout Note:
    DDR_A_D24 61 62 DDR_A_D28
    DDR_A_D25 63
    DQ24 DQ28
    64 DDR_A_D29 Place one cap close to every 2 pullup
    DQ25 DQ29
    C
    65 VSS VSS 66 resistors terminated to +0.9V C
    DDR_A_DM3 67 68 DDR_A_DQS#3
    DM3 DQS3# DDR_A_DQS3
    69 NC DQS3 70
    71 VSS VSS 72
    DDR_A_D26 73 74 DDR_A_D30 +0.9V
    DDR_A_D27 DQ26 DQ30 DDR_A_D31
    75 DQ27 DQ31 76
    77 VSS VSS 78
    DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA 11/01 modify
    <6> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <6>

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    81 VDD VDD 82
    DDR_CS2_DIMMA# 83 84 DDR_A_MA15 1
    <6> DDR_CS2_DIMMA# NC NC/A15
    DDR_A_BS#2 85 86 DDR_A_MA14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    <6> DDR_A_BS#2 BA2 NC/A14 +
    87 88 C925
    DDR_A_MA12 VDD VDD DDR_A_MA11
    89 A12 A11 90
    DDR_A_MA9 91 92 DDR_A_MA7 150U_D2_6.3VM
    DDR_A_MA8 A9 A7 DDR_A_MA6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    93 A8 A6 94

    C100

    C101

    C102

    C103
    C89

    C90

    C91

    C92

    C93

    C94

    C95

    C96

    C97

    C98

    C99
    95 VDD VDD 96
    DDR_A_MA5 97 98 DDR_A_MA4
    DDR_A_MA3 A5 A4 DDR_A_MA2
    99 A3 A2 100
    DDR_A_MA1 101 102 DDR_A_MA0
    A1 A0
    103 VDD VDD 104 Layout Note:
    DDR_A_MA10 105 106 DDR_A_BS#1
    A10/AP BA1 DDR_A_BS#1 <6> Place one cap close to every 2 pullup
    DDR_A_BS#0 107 108 DDR_A_RAS#
    <6> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6>
    DDR_A_WE# 109 110 DDR_CS0_DIMMA# resistors terminated to +0.9V
    <6> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6>
    111 VDD VDD 112
    DDR_A_CAS# 113 114 DDR_A_ODT0
    <6> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
    DDR_CS1_DIMMA# 115 116 DDR_A_MA13
    <6> DDR_CS1_DIMMA# NC/S1# NC/A13
    117 118 +0.9V
    DDR_A_ODT1 VDD VDD DDR_CS3_DIMMA#
    <6> DDR_A_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMA# <6>
    121 VSS VSS 122
    DDR_A_D32 123 124 DDR_A_D36 DDR_A_MA15 R47 1 2 47_0402_5%
    DDR_A_D33 DQ32 DQ36 DDR_A_D37 DDR_A_MA14 R48 47_0402_5%
    125 DQ33 DQ37 126 1 2
    B DDR_A_MA13 R49 47_0402_5% B
    127 VSS VSS 128 1 2
    DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_A_MA12 R50 1 2 47_0402_5%
    DDR_A_DQS4 DQS4# DM4 DDR_A_MA11 R51 47_0402_5%
    131 DQS4 VSS 132 1 2
    133 134 DDR_A_D38 DDR_A_MA10 R52 1 2 47_0402_5%
    DDR_A_D34 135
    VSS DQ38
    136 DDR_A_D39 DDR_A_MA9 R53 1 2 47_0402_5% 11/3 Modify +1.8V
    DDR_A_D35 DQ34 DQ39 DDR_A_MA8 R54 47_0402_5%
    137 DQ35 VSS 138 1 2

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    139 140 DDR_A_D44 DDR_A_MA7 R55 1 2 47_0402_5%
    DDR_A_D40 VSS DQ44 DDR_A_D45 DDR_A_MA6 R56 47_0402_5%
    141 DQ40 DQ45 142 1 2
    DDR_A_D41 143 144 DDR_A_MA5 R57 1 2 47_0402_5% 1 1 1 1 1 1 1 1
    DQ41 VSS DDR_A_DQS#5 DDR_A_MA4 R58 47_0402_5%
    145 VSS DQS5# 146 1 2
    DDR_A_DM5 147 148 DDR_A_DQS5 DDR_A_MA3 R59 1 2 47_0402_5%
    DM5 DQS5 DDR_A_MA2 R60 47_0402_5%
    149 VSS VSS 150 1 2
    DDR_A_D42 DDR_A_D46 DDR_A_MA1 R61 47_0402_5% 2 2 2 2 2 2 2 2
    151 DQ42 DQ46 152 1 2

    C926

    C927

    C928

    C929

    C930

    C931

    C932

    C933
    DDR_A_D43 153 154 DDR_A_D47 DDR_A_MA0 R62 1 2 47_0402_5% +0.9V
    DQ43 DQ47
    155 VSS VSS 156
    DDR_A_D48 157 158 DDR_A_D52 DDR_A_BS#2 R63 1 2 47_0402_5%
    DDR_A_D49 DQ48 DQ52 DDR_A_D53 DDR_A_BS#1 R64
    159 DQ49 DQ53 160 1 2 47_0402_5%
    161 162 DDR_A_BS#0 R65 1 2 47_0402_5% Layout Note:
    VSS VSS DDR_A_CLK2
    163 164 DDR_A_CLK2 <6>
    165
    NC,TEST CK1
    166 DDR_A_CLK#2 DDR_A_CAS# R66 1 2 47_0402_5% Place one 0.1uF cap close to every 2 pullup
    VSS CK1# DDR_A_CLK#2 <6>
    DDR_A_DQS#6 167 168 DDR_A_WE# R67 1 2 47_0402_5% resistors terminated to +0.9V
    DDR_A_DQS6 DQS6# VSS DDR_A_DM6 DDR_A_RAS# R68
    169 DQS6 DM6 170 1 2 47_0402_5%
    171 VSS VSS 172
    DDR_A_D50 173 174 DDR_A_D54 DDR_CKE1_DIMMA R69 1 2 47_0402_5%
    DDR_A_D51 DQ50 DQ54 DDR_A_D55 DDR_CKE0_DIMMA R70
    175 DQ51 DQ55 176 1 2 47_0402_5%
    177 VSS VSS 178
    DDR_A_D56 179 180 DDR_A_D60 DDR_CS3_DIMMA# R71 1 2 47_0402_5%
    DDR_A_D57 DQ56 DQ60 DDR_A_D61 DDR_CS2_DIMMA# R72 47_0402_5%
    181 DQ57 DQ61 182 1 2
    183 184 DDR_CS1_DIMMA# R73 1 2 47_0402_5%
    DDR_A_DM7 VSS VSS DDR_A_DQS#7 DDR_CS0_DIMMA# R74 47_0402_5%
    185 DM7 DQS7# 186 1 2
    A DDR_A_DQS7 A
    187 VSS DQS7 188
    DDR_A_D58 189 190 DDR_A_ODT1 R75 1 2 47_0402_5%
    DDR_A_D59 DQ58 VSS DDR_A_D62 DDR_A_ODT0 R76
    191 DQ59 DQ62 192 1 2 47_0402_5%
    193 194 DDR_A_D63
    SB_CK_SDAT VSS DQ63
    <10,15,23> SB_CK_SDAT 195 SDA VSS 196
    SB_CK_SCLK 197 198 R77 1 2 10K_0402_5%
    <10,15,23> SB_CK_SCLK SCL SAO
    199 200 R78 1 2 10K_0402_5%
    +3VS
    1
    C104
    VDDSPD SA1 Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
    P-TWO_A5692C-A0G16 SCHEMATIC, M/B LA-3151P
    0.1U_0402_16V4Z
    2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 9 of 55
    5 4 3 2 1

    www.laptopfix.vn
    5 4 3 2 1

    +1.8V +1.8V +DIMM_VREF

    DDR_B_D[0..63]
    <6> DDR_B_D[0..63]

    0.1U_0402_16V4Z
    DDR_B_DM[0..7]
    <6> DDR_B_DM[0..7]

    4.7U_0805_10V4Z

    C105

    C106
    JP2
    1 2 1 1 DDR_B_DQS[0..7]
    VREF VSS DDR_B_D4 <6> DDR_B_DQS[0..7]
    3 VSS DQ4 4
    DDR_B_D0 5 6 DDR_B_D5 DDR_B_MA[0..15]
    DQ0 DQ5 <6> DDR_B_MA[0..15]
    DDR_B_D1 7 8
    DQ1 VSS DDR_B_DM0 2 2 DDR_B_DQS#[0..7]
    9 VSS DM0 10 <6> DDR_B_DQS#[0..7]
    D DDR_B_DQS#0 D
    11 DQS0# VSS 12
    DDR_B_DQS0 13 14 DDR_B_D6
    DQS0 DQ6 DDR_B_D7
    15 VSS DQ7 16
    DDR_B_D2 17 18
    DDR_B_D3 DQ2 VSS DDR_B_D12
    19 DQ3 DQ12 20
    21 22 DDR_B_D13
    DDR_B_D8 VSS DQ13
    23 DQ8 VSS 24
    DDR_B_D9 25 26 DDR_B_DM1
    DQ9 DM1
    27 VSS VSS 28
    DDR_B_DQS#1 29 30 DDR_B_CLK1 +1.8V
    DQS1# CK0 DDR_B_CLK1 <6>
    DDR_B_DQS1 31 32 DDR_B_CLK#1
    DQS1 CK0# DDR_B_CLK#1 <6>
    33 VSS VSS 34
    DDR_B_D10 35 36 DDR_B_D14
    DDR_B_D11 DQ10 DQ14 DDR_B_D15
    37 DQ11 DQ15 38
    39 VSS VSS 40

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    4.7U_0805_10V4Z
    1 1 1 1 1 1 1 1 1 1
    41 VSS VSS 42
    DDR_B_D16 43 44 DDR_B_D20
    DQ16 DQ20

    C107

    C108

    C109

    C110

    C111

    C112

    C113

    C114

    C115

    C116
    DDR_B_D17 45 46 DDR_B_D21
    DQ17 DQ21 2 2 2 2 2 2 2 2 2 2
    47 VSS VSS 48
    DDR_B_DQS#2 49 50
    DDR_B_DQS2 DQS2# NC DDR_B_DM2
    51 DQS2 DM2 52
    53 VSS VSS 54
    DDR_B_D18 55 56 DDR_B_D22
    DDR_B_D19 DQ18 DQ22 DDR_B_D23
    57 DQ19 DQ23 58
    59 VSS VSS 60 Layout Note:
    DDR_B_D24 61 62 DDR_B_D28
    DDR_B_D25 63
    DQ24 DQ28
    64 DDR_B_D29 Place one cap close to every 2 pullup
    DQ25 DQ29
    C
    65 VSS VSS 66 resistors terminated to +0.9V C
    DDR_B_DM3 67 68 DDR_B_DQS#3
    DM3 DQS3# DDR_B_DQS3
    69 NC DQS3 70
    71 VSS VSS 72
    DDR_B_D26 73 74 DDR_B_D30 +0.9V
    DDR_B_D27 DQ26 DQ30 DDR_B_D31
    75 DQ27 DQ31 76
    77 VSS VSS 78
    DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB
    <6> DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB <6>

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    81 VDD VDD 82
    DDR_CS2_DIMMB# 83 84 DDR_B_MA15
    <6> DDR_CS2_DIMMB# NC NC/A15
    DDR_B_BS#2 85 86 DDR_B_MA14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    <6> DDR_B_BS#2 BA2 NC/A14
    87 VDD VDD 88
    DDR_B_MA12 89 90 DDR_B_MA11
    DDR_B_MA9 A12 A11 DDR_B_MA7
    91 A9 A7 92
    DDR_B_MA8 DDR_B_MA6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    93 A8 A6 94

    C117

    C118

    C119

    C120

    C121

    C122

    C123

    C124

    C125

    C126

    C127

    C128

    C129

    C130

    C131
    95 VDD VDD 96
    DDR_B_MA5 97 98 DDR_B_MA4
    DDR_B_MA3 A5 A4 DDR_B_MA2
    99 A3 A2 100
    DDR_B_MA1 101 102 DDR_B_MA0
    A1 A0
    103 VDD VDD 104 Layout Note:
    DDR_B_MA10 105 106 DDR_B_BS#1
    A10/AP BA1 DDR_B_BS#1 <6> Place one cap close to every 2 pullup
    DDR_B_BS#0 107 108 DDR_B_RAS#
    <6> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <6>
    DDR_B_WE# 109 110 DDR_CS0_DIMMB# resistors terminated to +0.9V
    <6> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <6>
    111 VDD VDD 112
    DDR_B_CAS# 113 114 DDR_B_ODT0
    <6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
    DDR_CS1_DIMMB# 115 116 DDR_B_MA13 +0.9V
    <6> DDR_CS1_DIMMB# NC/S1# NC/A13
    117 VDD VDD 118
    DDR_B_ODT1 119 120 DDR_CS3_DIMMB#
    <6> DDR_B_ODT1 NC/ODT1 NC DDR_CS3_DIMMB# <6>
    121 122 DDR_B_MA15 R79 1 2 47_0402_5%
    DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_MA14 R80 47_0402_5%
    123 DQ32 DQ36 124 1 2
    DDR_B_D33 125 126 DDR_B_D37 DDR_B_MA13 R81 1 2 47_0402_5%
    B DQ33 DQ37 DDR_B_MA12 R82 47_0402_5% B
    127 VSS VSS 128 1 2
    DDR_B_DQS#4 129 130 DDR_B_DM4 DDR_B_MA11 R83 1 2 47_0402_5%
    DDR_B_DQS4 DQS4# DM4 DDR_B_MA10 R84 47_0402_5%
    131 DQS4 VSS 132 1 2
    133 134 DDR_B_D38 DDR_B_MA9 R85 1 2 47_0402_5%
    DDR_B_D34 VSS DQ38 DDR_B_D39 DDR_B_MA8 R86 47_0402_5%
    DDR_B_D35
    135
    137
    DQ34 DQ39 136
    138 DDR_B_MA7 R87
    1
    1
    2
    2 47_0402_5% 11/3 Modify +1.8V
    DQ35 VSS DDR_B_D44 DDR_B_MA6 R88 47_0402_5%
    139 VSS DQ44 140 1 2

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    DDR_B_D40 141 142 DDR_B_D45 DDR_B_MA5 R89 1 2 47_0402_5%
    DDR_B_D41 DQ40 DQ45 DDR_B_MA4 R90 47_0402_5%
    143 DQ41 VSS 144 1 2
    145 146 DDR_B_DQS#5 DDR_B_MA3 R91 1 2 47_0402_5% 1 1 1 1 1 1 1 1
    DDR_B_DM5 VSS DQS5# DDR_B_DQS5 DDR_B_MA2 R92 47_0402_5%
    147 DM5 DQS5 148 1 2
    149 150 DDR_B_MA1 R93 1 2 47_0402_5%
    DDR_B_D42 VSS VSS DDR_B_D46 DDR_B_MA0 R94 47_0402_5%
    151 DQ42 DQ46 152 1 2
    DDR_B_D43 DDR_B_D47 2 2 2 2 2 2 2 2
    153 DQ43 DQ47 154

    C934

    C935

    C936

    C937

    C938

    C939

    C940

    C941
    155 156 DDR_B_BS#2 R95 1 2 47_0402_5% +0.9V
    DDR_B_D48 VSS VSS DDR_B_D52 DDR_B_BS#1 R96
    157 DQ48 DQ52 158 1 2 47_0402_5%
    DDR_B_D49 159 160 DDR_B_D53 DDR_B_BS#0 R97 1 2 47_0402_5%
    DQ49 DQ53
    161 VSS VSS 162
    163 164 DDR_B_CLK2 DDR_B_CAS# R98 1 2 47_0402_5% Layout Note:
    NC,TEST CK1 DDR_B_CLK2 <6>
    165 166 DDR_B_CLK#2 DDR_B_WE# R99 1 2 47_0402_5%
    VSS CK1# DDR_B_CLK#2 <6> Place one 0.1uF cap close to every 2 pullup
    DDR_B_DQS#6 167 168 DDR_B_RAS# R100 1 2 47_0402_5%
    DDR_B_DQS6 DQS6# VSS DDR_B_DM6
    169 DQS6 DM6 170 resistors terminated to +0.9V
    171 172 DDR_CKE1_DIMMB R101 1 2 47_0402_5%
    DDR_B_D50 VSS VSS DDR_B_D54 DDR_CKE0_DIMMB R102 1
    173 DQ50 DQ54 174 2 47_0402_5%
    DDR_B_D51 175 176 DDR_B_D55
    DQ51 DQ55 DDR_CS3_DIMMB# R103 47_0402_5%
    177 VSS VSS 178 1 2
    DDR_B_D56 179 180 DDR_B_D60 DDR_CS2_DIMMB# R104 1 2 47_0402_5%
    DDR_B_D57 DQ56 DQ60 DDR_B_D61 DDR_CS1_DIMMB# R105 47_0402_5%
    181 DQ57 DQ61 182 1 2
    183 184 DDR_CS0_DIMMB# R106 1 2 47_0402_5%
    DDR_B_DM7 VSS VSS DDR_B_DQS#7
    185 DM7 DQS7# 186
    A DDR_B_DQS7 DDR_B_ODT1 R107 1 A
    187 VSS DQS7 188 2 47_0402_5%
    DDR_B_D58 189 190 DDR_B_ODT0 R108 1 2 47_0402_5%
    DDR_B_D59 DQ58 VSS DDR_B_D62
    191 DQ59 DQ62 192
    193 194 DDR_B_D63
    SB_CK_SDAT VSS DQ63
    <9,15,23> SB_CK_SDAT 195 SDA VSS 196
    SB_CK_SCLK 197 198 R109 1 2 10K_0402_5% +3VS
    <9,15,23> SB_CK_SCLK SCL SAO
    199 200 R110 1 2 10K_0402_5%
    +3VS
    1
    C132
    VDDSPD SA1 Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
    P-TWO_A5652C-A0G16 SCHEMATIC, M/B LA-3151P
    0.1U_0402_16V4Z
    2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 10 of 55
    5 4 3 2 1

    www.laptopfix.vn
    5 4 3 2 1

    D D

    H_CADOP[0..15] H_CADIP[0..15]
    H_CADON[0..15] H_CADOP[0..15] <5> <5> H_CADIP[0..15] H_CADIN[0..15]
    H_CADON[0..15] <5> <5> H_CADIN[0..15]

    U58A

    H_CADOP15 R19 P21 H_CADIP15


    H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
    H_CADOP14
    R18 HT_RXCAD15N PART 1 OF 5 HT_TXCAD15N P22
    H_CADIP14
    R21 HT_RXCAD14P HT_TXCAD14P P18
    H_CADON14 R22 P19 H_CADIN14
    H_CADOP13 HT_RXCAD14N HT_TXCAD14N H_CADIP13
    U22 HT_RXCAD13P HT_TXCAD13P M22
    H_CADON13 U21 M21 H_CADIN13
    H_CADOP12 HT_RXCAD13N HT_TXCAD13N H_CADIP12
    U18 HT_RXCAD12P HT_TXCAD12P M18
    H_CADON12 U19 M19 H_CADIN12
    H_CADOP11 HT_RXCAD12N HT_TXCAD12N H_CADIP11
    W19 HT_RXCAD11P HT_TXCAD11P L18
    H_CADON11 W20 L19 H_CADIN11
    H_CADOP10 HT_RXCAD11N HT_TXCAD11N H_CADIP10
    AC21 HT_RXCAD10P HT_TXCAD10P G22
    C H_CADON10 AB22 G21 H_CADIN10 C
    H_CADOP9 HT_RXCAD10N HT_TXCAD10N H_CADIP9
    AB20 J20

    HYPER TRANSPORT CPU


    H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
    AA20 HT_RXCAD9N HT_TXCAD9N J21
    H_CADOP8 AA19 F21 H_CADIP8
    H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8
    Y19 HT_RXCAD8N HT_TXCAD8N F22

    H_CADOP7 T24 N24 H_CADIP7


    H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
    R25 HT_RXCAD7N HT_TXCAD7N N25
    H_CADOP6 U25 L25 H_CADIP6
    H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
    U24 HT_RXCAD6N HT_TXCAD6N M24
    H_CADOP5 V23 K25 H_CADIP5
    H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
    U23 HT_RXCAD5N HT_TXCAD5N K24
    H_CADOP4 V24 J23 H_CADIP4
    H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
    V25 HT_RXCAD4N HT_TXCAD4N K23
    H_CADOP3 AA25 G25 H_CADIP3
    H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
    AA24 HT_RXCAD3N HT_TXCAD3N H24
    H_CADOP2 AB23 F25 H_CADIP2
    H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
    AA23 HT_RXCAD2N HT_TXCAD2N F24
    H_CADOP1 AB24 E23 H_CADIP1
    H_CADON1 HT_RXCAD1P HT_TXCAD1P H_CADIN1
    AB25 HT_RXCAD1N HT_TXCAD1N F23
    H_CADOP0 AC24 E24 H_CADIP0
    H_CADON0 HT_RXCAD0P HT_TXCAD0P H_CADIN0
    AC25 HT_RXCAD0N HT_TXCAD0N E25

    <5> H_CLKOP1 H_CLKOP1 W21 L21 H_CLKIP1 H_CLKIP1 <5>

    I/F
    H_CLKON1 HT_RXCLK1P HT_TXCLK1P H_CLKIN1
    <5> H_CLKON1 W22 HT_RXCLK1N HT_TXCLK1N L22 H_CLKIN1 <5>

    <5> H_CLKOP0 H_CLKOP0 Y24 J24 H_CLKIP0 H_CLKIP0 <5>


    H_CLKON0 HT_RXCLK0P HT_TXCLK0P H_CLKIN0
    <5> H_CLKON0 W25 HT_RXCLK0N HT_TXCLK0N J25 H_CLKIN0 <5>

    <5> H_CTLOP0 H_CTLOP0 P24 N23 H_CTLIP0 H_CTLIP0 <5>


    B H_CTLON0 HT_RXCTLP HT_TXCTLP H_CTLIN0 B
    <5> H_CTLON0 P25 HT_RXCTLN HT_TXCTLN P23 H_CTLIN0 <5>
    R111 1 2 49.9_0402_1% HT_RXCALP A24 C25 HT_TXCALP 1 R112 2
    R113 1 HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
    +1.2V_HT 2 49.9_0402_1% C24 HT_RXCALN HT_TXCALN D24 100_0402_1%

    215NSA4ALA11FG RS485M_BGA465

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 11 of 55
    5 4 3 2 1
    5 4 3 2 1

    PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
    <16> PCIE_GTX_C_MRX_P[0..15] <16> PCIE_MTX_C_GRX_P[0..15]
    PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
    D <16> PCIE_GTX_C_MRX_N[0..15] <16> PCIE_MTX_C_GRX_N[0..15] D

    U58B

    PCIE_GTX_C_MRX_P0 G5 PART 2 OF 5 J1 PCIE_MTX_GRX_P0 C133 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0


    PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C134 1 PCIE_MTX_C_GRX_N0
    G4 GFX_RX0N GFX_TX0N H2 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P1 J8 K2 PCIE_MTX_GRX_P1 C135 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
    PCIE_GTX_C_MRX_N1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C136 1
    J7 GFX_RX1N GFX_TX1N K1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
    PCIE_GTX_C_MRX_P2 J4 K3 PCIE_MTX_GRX_P2 C137 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
    PCIE_GTX_C_MRX_N2 GFX_RX2P GFX_TX2P PCIE_MTX_GRX_N2 C138 1 PCIE_MTX_C_GRX_N2
    J5 GFX_RX2N GFX_TX2N L3 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P3 L8 L1 PCIE_MTX_GRX_P3 C139 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
    PCIE_GTX_C_MRX_N3 GFX_RX3P GFX_TX3P PCIE_MTX_GRX_N3 C140 1 PCIE_MTX_C_GRX_N3
    L7 GFX_RX3N GFX_TX3N L2 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P4 L4 N2 PCIE_MTX_GRX_P4 C141 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
    PCIE_GTX_C_MRX_N4 GFX_RX4P GFX_TX4P PCIE_MTX_GRX_N4 C142 1 PCIE_MTX_C_GRX_N4
    L5 GFX_RX4N GFX_TX4N N1 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P5 M8 P2 PCIE_MTX_GRX_P5 C143 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
    PCIE_GTX_C_MRX_N5 GFX_RX5P GFX_TX5P PCIE_MTX_GRX_N5 C144 1 PCIE_MTX_C_GRX_N5
    M7 GFX_RX5N GFX_TX5N P1 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P6 M4 P3 PCIE_MTX_GRX_P6 C145 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
    PCIE_GTX_C_MRX_N6 GFX_RX6P GFX_TX6P PCIE_MTX_GRX_N6 C146 1
    M5 GFX_RX6N GFX_TX6N R3 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
    PCIE_GTX_C_MRX_P7 P8 R1 PCIE_MTX_GRX_P7 C147 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
    PCIE_GTX_C_MRX_N7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C148 1 PCIE_MTX_C_GRX_N7
    P7 GFX_RX7N GFX_TX7N R2 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P8 P4 T2 PCIE_MTX_GRX_P8 C149 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
    PCIE_GTX_C_MRX_N8 GFX_RX8P GFX_TX8P PCIE_MTX_GRX_N8 C150 1
    P5 GFX_RX8N GFX_TX8N U1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8

    PCIE I/F GFX


    PCIE_GTX_C_MRX_P9 R4 V2 PCIE_MTX_GRX_P9 C151 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
    PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C152 1 PCIE_MTX_C_GRX_N9
    R5 GFX_RX9N GFX_TX9N V1 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P10 R7 V3 PCIE_MTX_GRX_P10 C153 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
    C PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C154 1 PCIE_MTX_C_GRX_N10 C
    R8 GFX_RX10N GFX_TX10N W3 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P11 U4 W1 PCIE_MTX_GRX_P11 C155 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
    PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C156 1
    U5 GFX_RX11N GFX_TX11N W2 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
    PCIE_GTX_C_MRX_P12 W4 Y2 PCIE_MTX_GRX_P12 C157 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
    PCIE_GTX_C_MRX_N12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C158 1 PCIE_MTX_C_GRX_N12
    W5 GFX_RX12N GFX_TX12N AA1 2 0.1U_0402_16V7K
    PCIE_GTX_C_MRX_P13 Y4 AA2 PCIE_MTX_GRX_P13 C159 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
    PCIE_GTX_C_MRX_N13 GFX_RX13P GFX_TX13P PCIE_MTX_GRX_N13 C160 1
    Y5 GFX_RX13N GFX_TX13N AB2 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
    PCIE_GTX_C_MRX_P14 V9 AB1 PCIE_MTX_GRX_P14 C161 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
    PCIE_GTX_C_MRX_N14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C162 1
    W9 GFX_RX14N GFX_TX14N AC1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
    PCIE_GTX_C_MRX_P15 AB7 AE3 PCIE_MTX_GRX_P15 C163 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
    PCIE_GTX_C_MRX_N15 GFX_RX15P GFX_TX15P PCIE_MTX_GRX_N15 C164 1
    AB6 GFX_RX15N GFX_TX15N AE4 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15

    R114 1 2 0_0402_5% PCIE_MRX_PTX_P0_R W11 AD8 PCIE_MTX_PRX_P0 C165 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_P0 PCIE_MTX_C_PRX_P0 <39>
    <39> PCIE_MRX_PTX_P0 GPP_RX0P GPP_TX0P
    R115 1 2 0_0402_5% PCIE_MRX_PTX_N0_R W12 AE8 PCIE_MTX_PRX_N0 C166 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_N0 PCIE_MTX_C_PRX_N0 <39>
    <39> PCIE_MRX_PTX_N0 GPP_RX0N GPP_TX0N
    R116 1 2 0_0402_5% PCIE_MRX_PTX_P1_R AA11 AD7 PCIE_MTX_PRX_P1 C167 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_P1 PCIE_MTX_C_PRX_P1 <36>
    <36> PCIE_MRX_PTX_P1 GPP_RX1P GPP_TX1P
    R117 1 2 0_0402_5% PCIE_MRX_PTX_N1_R AB11 AE7 PCIE_MTX_PRX_N1 C168 1 2 0.1U_0402_16V7K PCIE_MTX_C_PRX_N1 PCIE_MTX_C_PRX_N1 <36>
    <36> PCIE_MRX_PTX_N1 GPP_RX1N GPP_TX1N
    PCIE I/F GPP
    Y7 GPP_RX2P GPP_TX2P AD4
    AA7 GPP_RX2N GPP_TX2N AE5

    AB9 GPP_RX3P GPP_TX3P AD5


    AA9 GPP_RX3N GPP_TX3N AD6

    A_MRX_STX_P0 W14 AE9 A_MTX_SRX_P0 C169 1 2 0.1U_0402_16V7K A_MTX_C_SRX_P0 A_MTX_C_SRX_P0 <22>


    <22> A_MRX_STX_P0 SB_RX0P SB_TX0P
    A_MRX_STX_N0 W15 PCIE I/F SB AD10 A_MTX_SRX_N0 C170 1 2 0.1U_0402_16V7K A_MTX_C_SRX_N0 A_MTX_C_SRX_N0 <22>
    <22> A_MRX_STX_N0 SB_RX0N SB_TX0N
    A_MRX_STX_P1 AB12 AC8 A_MTX_SRX_P1 C171 1 2 0.1U_0402_16V7K A_MTX_C_SRX_P1 A_MTX_C_SRX_P1 <22>
    <22> A_MRX_STX_P1 SB_RX1P SB_TX1P
    A_MRX_STX_N1 AA12 AD9 A_MTX_SRX_N1 C172 1 2 0.1U_0402_16V7K A_MTX_C_SRX_N1 A_MTX_C_SRX_N1 <22>
    <22> A_MRX_STX_N1 SB_RX1N SB_TX1N
    B R118 1 2 10K_0402_1% AA14 AD11 R119 1 2 150_0402_1% B
    R120 1 PCEH_ISET PCEH_PCAL
    R214: 10KOhm FOR RS485 2 8.25K_0402_1% AB14 PCEH_TXISET PCEH_NCAL AE11 R121 1 2 100_0402_1% +1.2V_HT
    1.47KOhm FOR RS690
    R119: 150 Ohm FOR RS485
    R213: 8.25KOhm FOR RS485 215NSA4ALA11FG RS485M_BGA465
    562 Ohm FOR RS690
    DNI FOR RS690 ATI side check , use +1.2V or not
    R121: 100 Ohm FOR RS485
    2KOhm FOR RS690

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 12 of 55
    5 4 3 2 1
    5 4 3 2 1

    ATI check , CRT / TV/ LVDS can delete or not when I use RX485
    D Modify 11/29 D

    +1.8VS U58C
    R846
    1 2 0_0603_5% +3VS 1 2 B22 AVDD1 TXOUT_L0P B14
    1 R809 0_0603_5% C22 PART 3 OF 5 B15
    C947 AVDD2 TXOUT_L0N
    G17 AVSSN1 TXOUT_L1P B13
    @ 1U_0402_6.3V4Z H17 A13
    +1.8VS AVSSN2 TXOUT_L1N
    A20 AVDDDI TXOUT_L2P H14
    R847 2
    B20 AVSSDI TXOUT_L2N G14
    +1.8VS 1 2 0_0603_5% D17
    PLLVDD TXOUT_L3P
    1 A21 AVDDQ TXOUT_L3N E17
    C948 A22
    L63 @ 1U_0402_6.3V4Z AVSSQ
    TXOUT_U0P A15

    CRT/TVOUT
    1 2 C21 C_R TXOUT_U0N B16
    MBK1608800YZF_0805 1 2
    1 C20 Y_G TXOUT_U1P C17
    C173 C174 D19 C18 Modify 11/29
    COMP_B TXOUT_U1N
    TXOUT_U2P B17
    4.7U_0805_10V4Z E19 A17
    2 2 RED TXOUT_U2N
    F19 GREEN TXOUT_U3P A18
    G19 BLUE TXOUT_U3N B18
    10U_0805_10V4Z Modify : 11/07 C6 +1.8VS
    DACVSYNC R848
    A5 DACHSYNC TXCLK_LP E15
    TXCLK_LN D15 1 2
    1 2 B21 H15 1 0_0603_5%
    R123 @ 715_0402_1% RSET TXCLK_UP
    TXCLK_UN G15
    +1.8VS +1.8VS B6 C949
    HTPVDD DACSCL @ 1U_0402_6.3V4Z
    A6 DACSDA LPVDD D14
    C +3VS 2 +1.8VS C
    LPVSS E14

    1
    L67 PLLVDD A10 R849
    R810 PLLVDD

    PM PLL PWR
    1 2 B10 PLLVSS LVDDR18D_1 A12 1 2

    1
    10K_0402_5% B12 0_0603_5%
    MBK1608800YZF_0805 1 R125 LVDDR18D_2 R850
    1 HTPVDD B24 HTPVDD LVDDR18A_1 C12
    C175 C176 1K_0402_5% B25 C13 1 2
    2 2

    HTPVSS LVDDR18A_2 0_0603_5%


    B

    4.7U_0805_10V4Z C10 A16


    <16,22,27,33,36,41> NB_RST#
    2
    Modify : 11/07 2 2 Q4 R126 1 0_0402_5% SYSRESET# LVSSR1
    <42> NB_PWRGD 2 C11 POWERGOOD LVSSR3 A14
    E

    10U_0805_10V4Z 3 1 LDT_STOP#_NB C5 D12


    <7,23> LDT_STOP# LDTSTOP# LVSSR5
    C

    <22> ALLOW_LDTSTOP B5 ALLOW_LDTSTOP LVSSR6 C19 1 1


    MMBT3904_SOT23 C15
    R127 2 LVSSR7
    1 10K_0402_5% C23 HTTSTCLK LVSSR8 C16 C950 C951
    B23 @ 1U_0402_6.3V4Z @ 1U_0402_6.3V4Z
    <15> HTREFCLK HTREFCLK 2 2
    C2 TVCLKIN LVSSR12 F14
    LVSSR13 F15

    CLOCKs
    <15> NB_OSC B11 OSCIN
    A11 OSCOUT

    <15> NBSRC_CLKP F2 GFX_CLKP


    E1 E12 T4 PAD
    <15> NBSRC_CLKN GFX_CLKN LVDS_DIGON
    G12 T5 PAD
    LVDS_BLON T6 PAD
    <15> SBLINK_CLKP G1 SB_CLKP LVDS_BLEN F12
    LOAD_ROM#: LOAD ROM STRAP ENABLE <15> SBLINK_CLKN G2 SB_CLKN
    DVO_D0 AD14
    R129 R128 1 2 @ 2.7K_0402_5% DFT_GPIO0 D6 AD15
    LOAD_ROM# DFT_GPIO0 DVO_D1
    High, LOAD ROM STRAP DISABLE 1 2 D7 DFT_GPIO1 DVO_D2 AE15
    @ 3K_0402_5% R130 1 2 @ 2.7K_0402_5% DFT_GPIO2 C8 AD16
    R131 @ 2.7K_0402_5% DFT_GPIO3 DFT_GPIO2 DVO_D3
    B
    Low, LOAD ROM STRAP ENABLE 1 2
    DFT_GPIO4
    C7 DFT_GPIO3 DVO_D4 AE16
    B
    R132 1 2 @ 2.7K_0402_5% B8 AC17
    DFT_GPIO4 DVO_D5

    MIS.
    R133 1 2 @ 2.7K_0402_5% DFT_GPIO5 A8 AD18
    DFT_GPIO5 DVO_D6
    DVO_D7 AE19
    <22> BMREQ# 2 1D33 1N4148_SOT23 B2 BMREQb DVO_D8 AD19
    PAD T11 A2 I2C_CLK DVO_D9 AE20
    PAD T7 B4 I2C_DATA DVO_D10 AD20
    AA15 THERMALDIODE_P DVO_D11 AE21
    AB15 THERMALDIODE_N
    DVO_VSYNC AD13
    PAD T8 C14 AC13
    PAD T9 TMDS_HPD DVO_DE
    B3 DDC_DATA DVO_HSYNC AE13
    C3 TESTMODE DVO_IDCKP AE17
    PAD T10 A3 AD17
    STRP_DATA DVO_IDCKN
    1

    R134 215NSA4ALA11FG RS485M_BGA465


    4.7K_0402_5%
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 13 of 55
    5 4 3 2 1
    5 4 3 2 1

    NB RS485 POWER STATES


    Power Signal S0 S1 S3 S4/S5 G3
    VDDHT ON ON OFF OFF OFF
    VDDR ON ON OFF OFF OFF
    VDD18 ON ON OFF OFF OFF
    VDDC ON ON OFF OFF OFF
    D VDDA18 ON ON OFF OFF OFF D

    VDDA12 ON ON OFF OFF OFF


    AVDD ON ON OFF OFF OFF
    AVDDDI ON ON OFF OFF OFF
    PLLVDD ON ON OFF OFF OFF
    HTPVDD ON ON OFF OFF OFF
    VDDR3 ON ON OFF OFF OFF
    LPVDD ON ON OFF OFF OFF
    LVDDR18D ON ON OFF OFF OFF
    LVDDR18A ON ON OFF OFF OFF
    U58E

    A25 VSS1 VSSA1 M3


    F11 VSS2 PAR 5 OF 5 VSSA2 V12
    CURRENT MEASUREMENT D23 VSS3 VSSA3 V11
    +1.2V_HT E9 V14
    +VDDA_12 VSS4 VSSA4
    G11 VSS5 VSSA5 F3
    +1.2V_HT +VDD_HT U58D L69 Y23 V15
    L70 1U_0402_6.3V4Z 10U_0805_10V4Z VSS6 VSSA6
    10U_0805_10V4Z
    AE24 VDD_HT1 PART 4 OF 5 VDDA_12_1 D1 1 2 P11 VSS7 VSSA7 A1
    1 2 AD24 VDD_HT2 VDDA_12_2 G7 1 1 1 1 1 R24 VSS8 VSSA8 H1
    C AD22 E2 C178 C179 C180 C181 C182 KC FBM-L11-201209-221LMAT_0805 AE18 G3 C
    1 1 1 1 1 1 1 VDD_HT5 VDDA_12_3 VSS9 VSSA9
    C183 C184 C185 C186 C187 C188 C189 AB17 C1 M15 J2
    VDD_HT6 VDDA_12_4 VSS10 VSSA10
    AE23 VDD_HT9 VDDA_12_5 E3 J22 VSS11 VSSA11 H3
    KC FBM-L11-201209-221LMAT_0805 1U_0402_6.3V4Z 2 2 2 2 2
    Y17 VDD_HT10 VDDA_12_6 D2 G23 VSS12 VSSA12 AE10
    2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0805_10V4Z
    W17 VDD_HT11 VDDA_12_7 M9 J12 VSS13 VSSA13 J6
    1U_0402_6.3V4Z 1U_0402_6.3V4Z AC18 F4 L12 AE6
    10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDD_HT12 VDDA_12_8 VSS14 VSSA14
    AD21 VDD_HT13 VDDA_12_9 B1 L14 VSS15 VSSA15 F1
    +1.8VS VDD18 AC19 D3 L20 L6
    L2 VDD_HT14 VDDA_12_10 VSS16 VSSA16
    AC20 VDD_HT15 VDDA_12_11 L9 L23 VSS17 VSSA17 M2
    1 2 AB19 E6 +1.2V_HT M11 M6
    MBK1608800YZF_0805 VDD_HT16 VDDA_12_12 VSS18 VSSA18
    1 1 AD23 VDD_HT17 M20 VSS19 VSSA19 J3
    C190 C191 AA17 L11 10U_0805_10V4Z 1U_0402_6.3V4Z M23 P6
    VDD_HT18 VDDC_1 VSS20 VSSA20
    RS690: VDDA18=1.2V AE25 VDD_HT19 VDDC_2 L13 1 1 1 1 1 1 M25 VSS21 VSSA21 T1
    2.2U_0603_6.3V6K 2.2U_0603_6.3V6K L15 C192 C193 C194 C195 C196 C197 N12 N3
    RS485: VDDA18=1.8V 2 2 VDDC_3 VSS22 VSSA22

    GROUND
    J14 VDD18_1 VDDC_4 M12 N14 VSS23 VSSA23 P9
    +1.8VS VDDA18 J15 R15 1U_0402_6.3V4Z B7 R6
    L64 VDD18_2 VDDC_5 2 2 2 2 2 2 VSS24 VSSA24
    3A bead VDDC_6 M14 L24 VSS25 VSSA25 U2

    POWER
    1 2 AE2 N11 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z P13 T3
    VDDA18_1 VDDC_7 VSS26 VSSA26
    1 1 1 1 1 1 1 AB3 VDDA18_2 VDDC_8 N13 P20 VSS27 VSSA27 U3
    KC FBM-L11-201209-221LMAT_0805 C198 C199 C200 C201 C202 C203 C204 U7 N15 1 1 1 1 P15 U6
    VDDA18_3 VDDC_9 VSS28 VSSA28
    10U_0805_10V4Z

    W7 J11 C205 C206 C207 R12 AC4


    VDDA18_4 VDDC_10 + C803 VSS29 VSSA29
    AB4 VDDA18_5 VDDC_11 H11 R14 VSS30 VSSA30 Y1
    2 2 2 2 2 2 2
    AC3 VDDA18_6 VDDC_12 P12 R20 VSS31 VSSA31 Y15
    10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 220U_D2_4VM 2 2 2
    AD2 VDDA18_7 VDDC_13 P14 W23 VSS32 VSSA32 W6
    +3VS VDDR3 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
    AE1 VDDA18_8 VDDC_14 R11 Y25 VSS33 VSSA33 AC2
    L3 R13 1U_0402_6.3V4Z AD25 Y3
    VDDC_15 VSS34 VSSA34
    1 2 E11 VDDR3_2 VDDC_16 A19 U20 VSS35 VSSA35 Y9
    MBK1608800YZF_0805 1 D11 B19 H25 Y11
    C208 VDDR3_1 VDDC_17 VSS36 VSSA36
    VDDC_18 U11 W24 VSS37 VSSA93 Y12
    AC12 VDDR_1 VDDC_19 U14 Y22 VSS38 VSSA94 Y14
    B 4.7U_0805_10V4Z AD12 P17 AC23 AA3 B
    2 VDDR_2 VDDC_20 VSS39 VSSA95
    AE12 VDDR_3 VDDC_21 L17 D25 VSS40 VSSA37 R9
    VDDC_22 J19 G24 VSS41 VSSA38 AD1
    +1.8VS VDDR E7 D20 AC14 AC5
    L4 VDDA12/VDDPLL_1 VDDC_23 VSS42 VSSA39
    F7 VDDA12/VDDPLL_2 VDDC_24 G20 H12 VSS43 VSSA40 AC6
    1 2 F9 VSSA12/VSSPLL_1 VDDC_25 A9 AC22 VSS44 VSSA41 AC7
    MBK1608800YZF_0805 1 1 1 G9 B9 R23 AD3
    VSSA12/VSSPLL_2 VDDC_26 VSS45 VSSA42
    1U_0402_6.3V4Z

    @ C209 C210 C211 C9 C4 AC9


    VDDC_27 VSS46 VSSA43
    +1.2V_HT D22 VDDHT_PKG VDDC_28 D9 AE22 VSS47 VSSA44 AC10
    +1.2V_HT M1 VDDA12_PKG1 VDDC_29 A7 T23 VSS48 VSSA45 G6
    2 2 2
    +1.2V_HT AC11 VDDA12_PKG2 VDDC_30 A4 T25 VSS49
    @ 1U_0402_6.3V4Z +1.2V_HT U12 AE14
    @ 1U_0402_6.3V4Z VDDC_31 VSS50
    VDDC_32 U15 R17 VSS51
    1 H23 VSS52
    +VDDA_12 215NSA4ALA11FG RS485M_BGA465 M17
    C212 VSS53
    A23 VSS54
    10U_0805_10V4Z AC15
    2 VSS55
    1 1 F17 VSS56
    4.7U_0805_10V4Z

    C213 C214 D4
    Modify 11/07 for EMI VSS57
    Close to U58.M1 AC16 VSS58
    1U_0402_6.3V4Z M13
    2 2 VSS59

    215NSA4ALA11FG RS485M_BGA465

    RS485: 0 Ohm RESISTOR


    RS690: 220 Ohm 500mA FERRITE BEAD
    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 14 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    CLK_VDD
    L5
    1 2 10U_0805_10V4Z +3VS
    MBK2012121YZF_0805 1 1 1 1 1 1 1 1 1 L6
    C215 C216 C217 C218 C219 C220 C221 C222 C223 CLK_VDDA 1 2
    2 1 MBK2012121YZF_0805
    C224 C225
    2 2 2 2 2 2 2 2 2
    0.1U_0402_16V4Z 10U_0805_10V4Z
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
    D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D

    +3VS

    1- PLACE ALL SERIAL TERMINATION L7 CLK_VDD


    RESISTORS CLOSE TO U800 1 2
    MBK2012121YZF_0805 U8
    2- PUT DECOUPLING CAPS CLOSE TO U800 1 R139
    POWER PIN C226 54 50 261_0402_1%
    VDDCPU VDDA
    14 VDDSRC GNDA 49 1 2
    +3VS 2.2U_0603_6.3V6K 23
    2 VDDSRC CPUCLK_EXT_R R140 1
    28 VDDSRC CPUCLK8T0 56 2 47_0402_1% CPUCLK <7>
    L8 44 55 CPUCLK#_EXT_R R141 1 2 47_0402_1% CPUCLK# <7>
    VDDSRC CPUCLK8C0
    1 2 5 VDD48 CPUCLK8T1 52
    MBK2012121YZF_0805 39 51
    VDDATIG CPUCLK8C1
    1 2 VDDREF
    C227 60 16 SBLINK_CLKP_R R142 1 2 33_0402_1% SBLINK_CLKP <13>
    VDDHTT SRCCLKT6 SBLINK_CLKN_R R143 33_0402_1%
    SRCCLKC6 17 1 2 SBLINK_CLKN <13>
    2.2U_0603_6.3V6K 53 41 NBSRC_CLKP_R R144 1 2 33_0402_1% NBSRC_CLKP <13>
    2 GNDCPU ATIGCLKT0 NBSRC_CLKN_R R145 33_0402_1%
    15 GNDSRC ATIGCLKC0 40 1 2 NBSRC_CLKN <13>
    22 37 GFX_CLKP_R R146 1 2 33_0402_1% CLK_PCIE_VGA <16>
    GNDSRC ATIGCLKT1 GFX_CLKN_R R147 33_0402_1%
    Parallel Resonance Crystal 29
    45
    GNDSRC ATIGCLKC1 36
    35
    1 2 CLK_PCIE_VGA# <16>
    C228 1 GNDSRC ATIGCLKT2
    2 8 GND48 ATIGCLKC2 34
    38 GNDATIG ATIGCLKT3 30

    2
    33P_0402_50V8J 1 31
    CLK_VDD R148 GNDREF ATIGCLKC3 SBSRC_CLKP_R R149 33_0402_1%
    58 GNDHTT SRCCLKT5 18 1 2 SBSRC_CLKP <22>
    Y1 @ 19 SBSRC_CLKN_R R150 1 2 33_0402_1% SBSRC_CLKN <22>
    SRCCLKC5 GPP_CLK4P_R R151 33_0402_1%
    3 20 1 2 CLK_PCIE_CARD <39>

    2
    X1 SRCCLKT4
    1

    33P_0402_50V8J 1M_0402_5% 21 GPP_CLK4N_R R152 1 2 33_0402_1% CLK_PCIE_CARD# <39>

    1
    C R153 R154 2 SRCCLKC4 GPP_CLK0P_R C
    1 2 1 0_0402_5% 4 X2 SRCCLKT3 24 R155 1 2 33_0402_1% CLK_PCIE_MINI1 <36>
    10K_0402_5% C229 14.31818MHz_20P_1BX14318BE1A 25 GPP_CLK0N_R R156 1 2 33_0402_1% CLK_PCIE_MINI1# <36>
    SRCCLKC3
    SRCCLKT2 26

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%

    2 49.9_0402_1%
    27
    2

    SRCCLKC2
    11 RESET_IN# SRCCLKT0 47
    61 NC SRCCLKC0 46
    SRCCLKT1 43
    1 SRCCLKC1 42
    SRCCLKT7 12
    C230 13
    0.1U_0402_16V4Z SRCCLKC7
    2 @ SB_CK_SCLK
    <9,10,23> SB_CK_SCLK 9 SMBCLK CLKREQA# 57

    1 R159

    1 R160

    1 R161

    1 R162

    1 R163

    1 R164

    1 R165

    1 R166

    1 R167

    1 R168

    1 R169

    1 R170
    SB_CK_SDAT 10 32 R158 1 2 0_0402_5%
    <9,10,23> SB_CK_SDAT SMBDAT CLKREQB# EXP_CLKREQ# <39>
    33 R171 1 2 0_0402_5% MINI1_CLKREQ# <36>
    CLKREQC#
    48 7 CLK_48M_SIO_R
    IREF 48MHz_1 CLK_48M_USB_R
    Ioh = 5 * Iref 48MHz_0 6
    (2.32mA) 2 CLK_VDD 2.2K_0402_5%
    R173

    1
    Voh = 0.71V @ 60 ohm 475_0402_1% 63 R175 1 2 33_0402_1% CLK_SD_48M <37>
    FS1/REF1 R176 1
    FS0/REF0 64 2 33_0402_1% CLK_USB_48M <23> R177 R178 R179
    62
    1

    FS2/REF2 2.2K_0402_5% 2.2K_0402_5%


    HTTCLK0 59

    2
    R180 1 2 8.2K_0402_5% R181 2 1 @ 0_0402_5%
    ICS951462AGLFT_TSSOP64 R182 1 2 8.2K_0402_5% R183 2 1 @ 0_0402_5%
    R184 1 2 8.2K_0402_5% R185 2 1 @ 0_0402_5%
    <36,39> ICH_SMBDATA ICH_SMBDATA R192 1 2 0_0402_5% SB_CK_SDAT
    SB_OSCIN_R R186 1 2 33_0402_1% SB_OSCIN <23>
    <36,39> ICH_SMBCLK ICH_SMBCLK R193 1 2 0_0402_5% SB_CK_SCLK
    B FS0 R187 1 2 33_0402_1% B
    CLK_14M_SIO <41>

    NB_OSCIN_R R188 1 2 33_0402_1% NB_OSC <13>


    HTREFCLK_R R190 1 2 33_0402_1% HTREFCLK <13>

    1
    R191
    51.1_0402_1%

    2
    EXT CLK FREQUENCY SELECT TABLE(MHZ)
    FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
    [2:1]

    A
    0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved A

    0 0 1 X 100.00 X/3 X/6 48.00 Reserved


    0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
    0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
    1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
    Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 15 of 55
    5 4 3 2 1
    5 4 3 2 1

    U9A +3VS Straps: (Internal pull down)


    PCIE Lane Reversal Transmitter power GPIO[0] 0: 50% TX output swing
    CLK_PCIE_VGA AL28 AD4 R194 1 2 10K_0402_5%
    <15> CLK_PCIE_VGA
    CLK_PCIE_VGA# PCIE_REFCLKP GPIO_0 R195 1
    saving enable 1: Full TX output swing
    AK28 AD2 2 10K_0402_5%
    <15> CLK_PCIE_VGA# PCIE_REFCLKN GPIO GPIO_1
    GPIO_2 AD1 Transmitter GPIO[1] 0: TX de-emphasis disable
    PCIE_GTX_C_MRX_N15 C2321 2 0.1U_0402_16V7K PCIE_GTX_MRX_N15 AK27 AD3
    PCIE_GTX_C_MRX_P15 C2311 PCIE_TX0P GPIO_3 de-emphasis enable 1: TX de-emphasis enable
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P15 AJ27 PCIE_TX0N GPIO_4 AC1 R196 1 2@ 10K_0402_5%
    PCIE_GTX_C_MRX_N14 C2341 2 0.1U_0402_16V7K PCIE_GTX_MRX_N14 AJ25 AC2 R197 1 2 10K_0402_5% Debug Access GPIO[4] 0: OFF Pad must be available
    PCIE_GTX_C_MRX_P14 C2331 PCIE_TX1P GPIO_5
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P14 AH25 PCIE_TX1N GPIO_6 AC3 1: ON
    PCIE_GTX_C_MRX_N13 C2361 2 0.1U_0402_16V7K PCIE_GTX_MRX_N13 AH28 AB2 R198 1 2@ 10K_0402_5%
    PCIE_GTX_C_MRX_P13 C2351 PCIE_TX2P GPIO_7_BLON
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P13 AG28 PCIE_TX2N GPIO_8 AC6 PLL_IBIAS_RD GPIO[6,5] Default : 01
    PCIE_GTX_C_MRX_N12 C2381 2 0.1U_0402_16V7K PCIE_GTX_MRX_N12 AG27 AC5 R199 1 @ 2 10K_0402_5%
    PCIE_GTX_C_MRX_P12 C2371 PCIE_TX3P GPIO_9 000X: No ROM,
    D 2 0.1U_0402_16V7K PCIE_GTX_MRX_P12 AF27 PCIE_TX3N GPIO_10 AC4 TP1 ROM ID Config GPIO[9, D
    PCIE_GTX_C_MRX_N11 C2401 2 0.1U_0402_16V7K PCIE_GTX_MRX_N11 AF25 AB3 R200 1 @ 2 10K_0402_5% AP_SIZE=00 128M share
    PCIE_GTX_C_MRX_P11 C2391 PCIE_TX4P GPIO_11 13:11] Memory
    001X: No ROM,
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P11 AE25 PCIE_TX4N GPIO_12 AB4 R201 1 X76@ 2 10K_0402_5% Low -> VDDC=1.2V
    PCIE_GTX_C_MRX_N10 C2421 2 0.1U_0402_16V7K PCIE_GTX_MRX_N10 AE28 AB5 R202 1 X76@ 2 10K_0402_5% AP_SIZE=01 256M share
    PCIE_GTX_C_MRX_P10 C2411 PCIE_TX5P GPIO_13 High -> VDDC=1.0V Memory
    010X: No ROM,
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P10 AD28 PCIE_TX5N GPIO_14 AD5
    PCIE_GTX_C_MRX_N9 C2441 2 0.1U_0402_16V7K PCIE_GTX_MRX_N9 AD27 AB8 POWER_SEL AP_SIZE=10 64M share
    PCIE_TX6P GPIO_15 POWER_SEL <53> Memory
    011X: No ROM,
    PCIE_GTX_C_MRX_P9 C2431 2 0.1U_0402_16V7K PCIE_GTX_MRX_P9 AC27 AA8 OSC_SPREAD
    PCIE_GTX_C_MRX_N8 C2461 PCIE_TX6N GPIO_16 AP_SIZE=11 Reserved
    2 0.1U_0402_16V7K PCIE_GTX_MRX_N8 AC25 PCIE_TX7P GPIO_17 AB7 THER_ALERT#
    PCIE_GTX_C_MRX_P8 C2451 2 0.1U_0402_16V7K PCIE_GTX_MRX_P8 AB25 AB6 +3VS
    PCIE_GTX_C_MRX_N7 C2481 PCIE_TX7N NC
    2 0.1U_0402_16V7K PCIE_GTX_MRX_N7 AB28 PCIE_TX8P
    R203 2 1 499_0402_1%
    PCIE_GTX_C_MRX_P7 C2471 2 0.1U_0402_16V7K PCIE_GTX_MRX_P7 AA28 AC8 R204 1 2 499_0402_1%
    PCIE_GTX_C_MRX_N6 C2511 PCIE_TX8N VREFG
    2 0.1U_0402_16V7K PCIE_GTX_MRX_N6 AA27 PCIE_TX9P
    C250 1 2
    PCIE_GTX_C_MRX_P6 C2491 2 0.1U_0402_16V7K PCIE_GTX_MRX_P6 Y27 0.1U_0402_16V4Z
    PCIE_GTX_C_MRX_N5 C2531 PCIE_TX9N
    2 0.1U_0402_16V7K PCIE_GTX_MRX_N5 Y25 PCIE_TX10P NC_DVOVMODE_0 AK4
    PCIE_GTX_C_MRX_P5 C2521 2 0.1U_0402_16V7K PCIE_GTX_MRX_P5 W25 AL4
    PCIE_GTX_C_MRX_N4 C2551 0.1U_0402_16V7K PCIE_GTX_MRX_N4 PCIE_TX10N NC_DVOVMODE_1
    2 W28 PCIE_TX11P
    PCIE_GTX_C_MRX_P4 C2541 2 0.1U_0402_16V7K PCIE_GTX_MRX_P4 V28 AF2
    PCIE_GTX_C_MRX_N3 C2571 PCIE_TX11N DVPCNTL_0
    2 0.1U_0402_16V7K PCIE_GTX_MRX_N3 V27 AF1

    VIP HOST/ EXTERNAL TMDS


    PCIE_GTX_C_MRX_P3 C2561 PCIE_TX12P DVPCNTL_1
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P3 U27 PCIE_TX12N DVPCNTL_2 AF3
    PCIE_GTX_C_MRX_N2 C2591 2 0.1U_0402_16V7K PCIE_GTX_MRX_N2 U25 AG1
    PCIE_GTX_C_MRX_P2 C2581 PCIE_TX13P DVPCLK
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P2 T25 PCIE_TX13N DVPDATA_0 AG2
    PCIE_GTX_C_MRX_N1 C2611 2 0.1U_0402_16V7K PCIE_GTX_MRX_N1 T28 AG3
    PCIE_GTX_C_MRX_P1 C2601 PCIE_TX14P DVPDATA_1
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P1 R28 PCIE_TX14N DVPDATA_2 AH2

    PCI EXPRESS
    PCIE_GTX_C_MRX_N0 C2631 2 0.1U_0402_16V7K PCIE_GTX_MRX_N0 R27 AH3
    PCIE_GTX_C_MRX_P0 C2621 PCIE_TX15P DVPDATA_3
    2 0.1U_0402_16V7K PCIE_GTX_MRX_P0 P27 PCIE_TX15N DVPDATA_4 AJ2
    DVPDATA_5 AJ1
    PCIE_MTX_C_GRX_N15 AJ31 AK2
    PCIE_MTX_C_GRX_P15 PCIE_RX0P DVPDATA_6
    AH31 PCIE_RX0N DVPDATA_7 AK1
    PCIE_MTX_C_GRX_N14 AH30 AK3
    C PCIE_MTX_C_GRX_P14 PCIE_RX1P DVPDATA_8 C
    AG30 PCIE_RX1N DVPDATA_9 AL2
    PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_N13 AG32 AL3
    <12> PCIE_GTX_C_MRX_P[0..15] PCIE_RX2P DVPDATA_10
    PCIE_MTX_C_GRX_P13 AF32 AM3
    PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N12 PCIE_RX2N DVPDATA_11
    <12> PCIE_GTX_C_MRX_N[0..15] AF31 PCIE_RX3P DVPDATA_12 AE6
    PCIE_MTX_C_GRX_P12 AE31 AF4
    PCIE_MTX_C_GRX_N11 PCIE_RX3N DVPDATA_13 +3VS
    AE30 PCIE_RX4P DVPDATA_14 AF5
    PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_P11 AD30 AG4
    <12> PCIE_MTX_C_GRX_P[0..15] PCIE_RX4N DVPDATA_15
    PCIE_MTX_C_GRX_N10 AD32 AJ3 TP2 R2051 2 4.7K_0402_5%
    PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P10 PCIE_RX5P DVPDATA_16 TP3 R2061
    <12> PCIE_MTX_C_GRX_N[0..15] AC32 PCIE_RX5N DVPDATA_17 AH4 2 4.7K_0402_5%
    PCIE_MTX_C_GRX_N9 AC31 AJ4 I2C_DAT
    PCIE_RX6P DVPDATA_18 I2C_DAT <29>
    PCIE_MTX_C_GRX_P9 AB31 AG5 I2C_CLK
    PCIE_RX6N DVPDATA_19 I2C_CLK <29>
    PCIE_MTX_C_GRX_N8 AB30 AH5 MEMID0 R207 1 2 10K_0402_5% X76@ +3VS
    PCIE_RX7P DVPDATA_20 MEMID1 R208 1
    PCIE_MTX_C_GRX_P8 AA30 PCIE_RX7N DVPDATA_21 AF6 2 10K_0402_5% X76@
    PCIE_MTX_C_GRX_N7 AA32 AE7 MEMID2 R209 1 2 10K_0402_5% X76@
    +3VS PCIE_MTX_C_GRX_P7 PCIE_RX8P DVPDATA_22 TP4
    Y32 PCIE_RX8N DVPDATA_23 AG6
    +3VS PCIE_MTX_C_GRX_N6 Y31
    PCIE_MTX_C_GRX_P6 PCIE_RX9P
    Thermal sensor PCIE_MTX_C_GRX_N5
    W31
    W30
    PCIE_RX9N
    PCIE_RX10P
    1

    PCIE_MTX_C_GRX_P5 V30 AK24 VGA_CRT_R


    PCIE_RX10N CRT R VGA_CRT_R <28>
    2

    R210 PCIE_MTX_C_GRX_N4 V32 AM24 VGA_CRT_G


    PCIE_RX11P G VGA_CRT_G <28>
    2.2K_0402_5% U10 R211 PCIE_MTX_C_GRX_P4 U32 AL24 VGA_CRT_B
    PCIE_RX11N B VGA_CRT_B <28>
    THM@ 1 8 THERM_SCL PCIE_MTX_C_GRX_N3 U31
    VDD SCLK 2.2K_0402_5% PCIE_MTX_C_GRX_P3 PCIE_RX12P CRT_HSYNC
    T31 AJ23 CRT_HSYNC <28>
    2

    D+ THERM_SDA PCIE_MTX_C_GRX_N2 PCIE_RX12N HSYNC CRT_VSYNC Need Level Shift


    2 7 THM@ T30 AJ22 CRT_VSYNC <28>
    1

    D+ SDATA PCIE_MTX_C_GRX_P2 PCIE_RX13P VSYNC


    R30 PCIE_RX13N
    D- 3 6 1 2 THER_ALERT# PCIE_MTX_C_GRX_N1 R32 R2131 2 4.7K_0402_5% +3VS
    D- ALERT# R212 0_0402_5% PCIE_MTX_C_GRX_P1 PCIE_RX14P R2141
    P32 PCIE_RX14N 2 4.7K_0402_5% Need Level Shift
    C264 4 5 THM@ PCIE_MTX_C_GRX_N0 P31 AH22 VGA_CRT_DAT
    OVERT# GND PCIE_RX15P DDC1DATA VGA_CRT_DAT <28>
    1 2 PCIE_MTX_C_GRX_P0 N31 AH23 VGA_CRT_CLK
    B PCIE_RX15N DDC1CLK VGA_CRT_CLK <28> B
    +1.2VS
    THM@ 2200P_0402_50V7K THM@ MAX6649MUA_8UMAX AK22 GENERICA NC,GENERICB Grounded -->Internal SS
    R2151 GENERICA
    2 2K_0402_1% AE24 PCIE_CALRN GENERICB AF23 R216 2 1 1K_0402_5% LVDS Bus Vedio Memory Config. (VGA Internal PD)
    R2171 2 562_0603_1% AD24
    R2181 PCIE_CALRP
    2 1.47K_0603_1% AB24 PCIE_CALI RSET AL22 R219 2 1 499_0402_1% MEMID[2:0] Size Size Vender Chips VGA Frequence

    R220 1 0 0 0 64MB 16M16 Hynix 2


    2 0_0402_5% AG24 AK15
    <13,22,27,33,36,41> NB_RST# PERST# TV R2
    G2 AM15 0 0 1 64MB 16M16 Samsung 2
    AA24 PCIE_TEST B2 AL15
    R2211 2 10K_0402_5% AF24 128MB 16M16 Hynix 4 A-test
    +3VS PERST#_MASK
    AF15
    0 1 0
    H2SYNC
    V2SYNC AG15 0 1 1 128MB 16M16 Samsung 4
    THERMAL
    1
    0_0603_5%

    D+ AG12 AJ15 VGA_TV_Y 256MB 32M16 Hynix 4 A-test


    DPLUS Y VGA_TV_C
    VGA_TV_Y <28> 1 0 0
    Spread spectrum C AJ13 VGA_TV_C <28>
    SSC@

    R222

    D- AH12 AH15 VGA_TV_COMP 256MB 32M16 Samsung 4


    +3VS DMINUS COMP VGA_TV_COMP <28> 1 0 1
    4.7K_0402_5% AK14 R223 2 1 715_0402_1% Resreved
    1 1 0
    2

    U11 R2241 THERM_SDA R2SET


    2 AE12 DDC3DATA
    7 5 Memory Interface SS R2251 2 THERM_SCL AF12 Resreved
    VDD REF 4.7K_0402_5% DDC3CLK
    AC7
    1 1 1
    ROMCS#
    1 4 1 2 OSC_SPREAD
    C265
    1 XIN MODOUT R226 22_0402_5% OSC_IN 1 2 AL26
    XTAL AG14
    SSC@ R227 121_0402_1% XTALIN PLLTEST R228 2 1K_0402_5%
    8 XOUT NC 3 TESTEN AG22 1
    SSC@

    0.1U_0402_16V4Z

    AM26 XTALOUT
    1

    2
    2 VSS PD# 6
    R229
    ASM3P1819N-SR_SO8 M56P
    A A
    SSC@ 71.5_0402_1% M56@
    +3VS Minimize distance from X1 pin3 to U3 pin1
    2

    1 2
    TBD
    C266
    1

    0.1U_0402_16V4Z
    R230 X1 Security Classification Compal Secret Data Compal Electronics, Inc.
    1K_0402_5%

    4 VDD 3 OSC_IN Title


    OUT Issued Date 2005/09/10 Deciphered Date 2006/09/10
    1 2
    SCHEMATIC, M/B LA-3151P
    2

    OE GND THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Keep away from other signal at last 25mils Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    27MHZ_15P DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期 |, 三月 09, 2006 Sheet 16 of 55
    5 4 3 2 1
    5 4 3 2 1

    U9F
    U9G

    U9B B1 VSS VSS C27


    AH27 PCIE_VSS TXVSSR AJ7 H1 VSS VSS E32
    AC23 PCIE_VSS TXVSSR AK7 L1 VSS VSS H28
    AE13 AJ21 VGA_LVDSBC+ AL27 AL7 P1 J30
    GPIO_18 TXCLK_UP VGA_LVDSBC+ <29> PCIE_VSS TXVSSR VSS VSS
    AF13 AK21 VGA_LVDSBC- R23 AM7 U1 K17

    TMDS GND
    GPIO_19 TXCLK_UN VGA_LVDSBC- <29> PCIE_VSS TXVSSR VSS VSS
    AF9 AG18 VGA_LVDSB0+ P25 AK8 Y1 K27
    GPIO_20 TXOUT_U0P VGA_LVDSB0+ <29> PCIE_VSS TXVSSR VSS VSS
    AG7 AH18 VGA_LVDSB0- R25 AD7 M32
    GPIO_21 TXOUT_U0N VGA_LVDSB0- <29> PCIE_VSS VSS VSS
    VGA_LVDSB1+

    EXPAND GPIO
    AE10 GPIO_22 TXOUT_U1P AK20 VGA_LVDSB1+ <29> T26 PCIE_VSS TPVSS AL8 AE8 VSS VSS A22
    AE9 AJ20 VGA_LVDSB1- U26 AL1 C20
    GPIO_23 TXOUT_U1N VGA_LVDSB1- <29> PCIE_VSS VSS VSS
    AF7 AG20 VGA_LVDSB2+ Y26 A2 E19
    GPIO_24 TXOUT_U2P VGA_LVDSB2+ <29> PCIE_VSS VSS VSS
    D AF8 AH20 VGA_LVDSB2- AB26 AK23 AM2 H20 D
    GPIO_25 TXOUT_U2N VGA_LVDSB2- <29> PCIE_VSS AVSSQ VSS VSS
    AH6 GPIO_26 TXOUT_U3P AH21 AC26 PCIE_VSS AVSSN AK25 AD10 VSS VSS J24
    AF10 GPIO_27 TXOUT_U3N AG21 AD25 PCIE_VSS AVSSN AJ24 E8 VSS VSS M28
    AG10 AE26 Use 15mils trace H5 J28

    CRT GND
    GPIO_28 PCIE_VSS VSS VSS

    LVDS
    AH9 AL18 VGA_LVDSAC- AF26 AL23 K10 J16
    GPIO_29 TXCLK_LN VGA_LVDSAC+
    VGA_LVDSAC- <29> PCIE_VSS VSS1DI connect to GND VSS VSS
    AJ8 GPIO_30 TXCLK_LP AM18 VGA_LVDSAC+ <29> AD26 PCIE_VSS M8 VSS VSS F30
    AH8 AL19 VGA_LVDSA0+ AG25 T10 L29
    GPIO_31 TXOUT_L0P VGA_LVDSA0+ <29> PCIE_VSS VSS VSS
    AG9 AK19 VGA_LVDSA0- AH26 AK13 E12 A31
    GPIO_32 TXOUT_L0N VGA_LVDSA0- <29> PCIE_VSS A2VSSQ VSS VSS
    AH7 AM20 VGA_LVDSA1+ AC28 AM17 AC9 B32
    GPIO_33 TXOUT_L1P VGA_LVDSA1+ <29> PCIE_VSS A2VSSN VSS VSS
    AG8 AL20 VGA_LVDSA1- Y28 AL17 AF14 E30
    GPIO_34 TXOUT_L1N VGA_LVDSA1- <29> PCIE_VSS A2VSSN VSS VSS
    VGA_LVDSA2+

    TV GND
    TXOUT_L2P AM21 VGA_LVDSA2+ <29> U28 PCIE_VSS AD8 VSS VSS AE15
    AL21 VGA_LVDSA2- P28 AJ17 C5 AG23
    TXOUT_L2N VGA_LVDSA2- <29> PCIE_VSS VSS2DI VSS VSS
    AE23 GENERICC TXOUT_L3P AJ18 AH29 PCIE_VSS F10 VSS VSS AD9
    TXOUT_L3N AK18 AF28 PCIE_VSS J3 VSS VSS AF16
    ENBKL <33> To EC V29 PCIE_VSS PVSS AH14 L6 VSS VSS AH10
    Y23 BBN AC29 PCIE_VSS M6 VSS VSS AJ10
    K15 AD12 R2311 2 10K_0402_5% W27 A5 P6 AD15

    PLL GND
    BBN VARY_BL ENVDD PCIE_VSS MPVSS VSS VSS
    R10 BBN DIGON AE11 ENVDD <29> AB27 PCIE_VSS AA4 VSS VSS AH16

    COMPATIBILITY
    AC17 BBN GENERICD AD23 V26 PCIE_VSS AG11 VSS VSS K23
    10/20/05" AJ26 AE18 V3 U18
    100mA PCIE_VSS LPVSS VSS VSS
    AC14 AJ32 AG16 AE16
    M23
    BBP
    AL9 DVI_TXC-_L R629 2 1 0_0402_5% DVI@ DVI_TXC- AK29
    PCIE_VSS
    AK17 R3
    VSS
    CORE VSS
    AE17

    PCIE GND
    BBP TXCM PCIE_VSS LVSSR VSS VSS

    FOREARD
    V10 AM9 DVI_TXC+_L R630 2 1 0_0402_5% DVI@ DVI_TXC+ P26 AJ19 C6 A19

    LVDS PLL&I/O GND


    BBP TXCP PCIE_VSS LVSSR VSS VSS
    +VDD_CORE K18 BBP P29 PCIE_VSS LVSSR AF18 C9 VSS VSS H32
    AK10 DVI_TX0-_L R631 2 1 0_0402_5% DVI@ DVI_TX0- R29 AH17 F6 F19
    TX0M DVI_TX0+_L R632 2 PCIE_VSS LVSSR VSS VSS
    1 0_0402_5% DVI@ DVI_TX0+
    TX0P AL10 T29 PCIE_VSS LVSSR AG17 H7 VSS GND VSS G19

    INTERGRATED TMDS
    L10 VDD25 U29 PCIE_VSS LVSSR AG19 J6 VSS VSS N8
    K22 AL11 DVI_TX1-_L R633 2 1 0_0402_5% DVI@ DVI_TX1- W29 AH19 AD16 Y7
    VDD25 TX1M DVI_TX1+_L R634 2 PCIE_VSS LVSSR VSS VSS
    +VDD25 100mA AA10 VDD25 TX1P AM11 1 0_0402_5% DVI@ DVI_TX1+ Y29 PCIE_VSS LVSSR AF22 AA6 VSS VSS T19
    C 1 1 AA29 AF17 P7 V19 C
    C267 C268 DVI_TX2-_L R635 2 PCIE_VSS LVSSR VSS VSS
    TX2M AL12 1 0_0402_5% DVI@ DVI_TX2- AB29 PCIE_VSS LVSSR AF21 P5 VSS VSS G21
    0.1U_0402_16V4Z AM12 DVI_TX2+_L R636 2 1 0_0402_5% DVI@ DVI_TX2+ AD29 M3 C21
    TX2P PCIE_VSS VSS VSS
    AE29 PCIE_VSS PCIE_PVSS W23 M9 VSS VSS F21
    2 2
    TX3M AK9 AF29 PCIE_VSS PCIE_VSS AB23 L7 VSS VSS AE14
    AJ9 11/07/05" AG29 P24 M7 AK16
    0.1U_0402_16V4Z TX3P PCIE_VSS PCIE_VSS VSS VSS
    AJ29 PCIE_VSS PCIE_VSS R24 AD17 VSS VSS U5
    TX4M AK11 AK26 PCIE_VSS PCIE_VSS T24 AH11 VSS VSS F22
    TX4P AJ11 AK30 PCIE_VSS PCIE_VSS U24 A8 VSS VSS F18
    AG26 PCIE_VSS PCIE_VSS V24 U7 VSS VSS K30
    AK12 +3VS N30 W24 C10 C24
    TX5M PCIE_VSS PCIE_VSS VSS VSS
    TX5P AJ12 R31 PCIE_VSS PCIE_VSS Y24 E9 VSS VSS F24
    R2361 2 6.8K_0402_5% Need Level AF30 AC24 F3 M24
    R2371 Shift PCIE_VSS PCIE_VSS VSS VSS
    2 6.8K_0402_5% AC30 PCIE_VSS PCIE_VSS AH24 J9 VSS VSS A25
    AH13 VGA_DVI_DAT V31 V25 N7 D30
    DDC2DATA VGA_DVI_DAT <30> PCIE_VSS PCIE_VSS VSS VSS
    AG13 VGA_DVI_CLK P30 AA25 N3 E25
    DDC2CLK VGA_DVI_CLK <30> PCIE_VSS PCIE_VSS VSS VSS
    AA31 PCIE_VSS PCIE_VSS R26 Y5 VSS VSS G25
    AF11 VGA_DVI_DET U30 AA26 AM13 G20
    HPD1 VGA_DVI_DET <30> PCIE_VSS PCIE_VSS VSS VSS
    AD31 PCIE_VSS PCIE_VSS T27 AC10 VSS VSS G22
    AK32 PCIE_VSS PCIE_VSS AE27 Y6 VSS VSS F27
    M56P AJ28 PCIE_VSS PCIE_VSS AG31 U6 VSS VSS E28
    M56@ Y30 W26 E5 H21
    PCIE_VSS PCIE_VSS VSS VSS
    AJ30 PCIE_VSS PCIE_VSS N24 AL13 VSS VSS J21
    AK31 PCIE_VSS PCIE_VSS AA23 A11 VSS VSS H16
    U8 VSS VSS T15
    U9 VSS VSS V17
    M56P U10 VSS VSS C15
    M56@ R6 C4
    VSS VSS
    AD6 VSS VSS U14
    B B
    V6 VSS VSS P15
    AD14 VSS VSS A16
    AD13 VSS VSS E16
    D11 VSS VSS G13
    J12 VSS VSS G16
    K12 VSS VSS P17
    A13 VSS VSS R16
    R2321 2 180_0402_5% DVI@ F13 R14
    DVI_TXC- VSS VSS
    DVI_TXC- <30> E13 VSS VSS W16
    DVI_TXC+ F15 C18
    DVI_TXC+ <30> VSS VSS
    R2331 2 180_0402_5% DVI@ K16 F16
    DVI_TX0- VSS VSS
    DVI_TX0- <30> W18 VSS
    DVI_TX0+
    DVI_TX0+ <30>
    R2341 2 180_0402_5% DVI@
    DVI_TX1- M56P
    DVI_TX1- <30>
    DVI_TX1+ M56@
    DVI_TX1+ <30>
    R2351 2 180_0402_5% DVI@
    DVI_TX2-
    DVI_TX2- <30>
    DVI_TX2+
    DVI_TX2+ <30>
    10/20/05"
    Close to connector

    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2005/09/10 Deciphered Date 2006/09/10
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期 |, 三月 09, 2006 Sheet 17 of 55
    5 4 3 2 1
    5 4 3 2 1

    U9D
    U9C
    FBCD0 B12 G4 FBCA0
    FBCD[0..63] FBCD1 DQB_0 MAB_0 FBCA1
    M31 DQA_0 MAA_0 D26 <20,21> FBCD[0..63] C12 DQB_1 MAB_1 E6
    M30 F28 FBCD2 B11 E4 FBCA2
    DQA_1 MAA_1 FBCD3 DQB_2 MAB_2 FBCA3
    L31 DQA_2 MAA_2 D28 C11 DQB_3 MAB_3 H4
    L30 D25 FBCA[0..12] FBCD4 C8 J5 FBCA4
    DQA_3 MAA_3 <20,21> FBCA[0..12] DQB_4 MAB_4
    H30 E24 FBCD5 B7 G5 FBCA5
    G31
    DQA_4 MAA_4
    E26 FBCD6 C7
    DQB_5 MEMORY B MAB_5
    F4 FBCA6
    G30
    DQA_5 MEMORY A MAA_5
    D27 <20,21> FBCDQS[0..7]
    FBCDQS[0..7] FBCD7 B6
    DQB_6 MAB_6
    H6 FBCA7
    DQA_6 MAA_6 FBCD8 DQB_7 MAB_7 FBCA8
    F31 DQA_7 MAA_7 F25 F12 DQB_8 MAB_8 G3
    M27 C26 FBCD9 D12 G2 FBCA9
    DQA_8 MAA_8 FBCDQS#[0..7] FBCD10 DQB_9 MAB_9 FBCA10
    M29 DQA_9 MAA_9 B26 <20,21> FBCDQS#[0..7] E11 DQB_10 MAB_10 D4
    D L28 D29 FBCD11 F11 F2 FBCA11 D
    DQA_10 MAA_10 FBCD12 DQB_11 MAB_11 FBC_BA0
    L27 DQA_11 MAA_11 B27 F9 DQB_12 MAB_12 H2
    J27 B25 FBCDQM#[0..7] FBCD13 D8 H3 FBC_BA1
    DQA_12 MAA_12 <20,21> FBCDQM#[0..7] DQB_13 MAB_13
    H29 C25 FBCD14 D7 F5 FBCA12
    DQA_13 MAA_13 FBCD15 DQB_14 MAB_14
    G29 DQA_14 MAA_14 E27 F7 DQB_15 MAB_15 D5
    G27 E29 FBC_BA0 FBCD16 G12
    DQA_15 MAA_15 <20,21> FBC_BA0 DQB_16
    M26 FBCD17 G11
    DQA_16 FBC_BA1 FBCD18 DQB_17 FBCDQM#0
    L26 DQA_17 <20,21> FBC_BA1 H12 DQB_18 DQMB#_0 B8
    M25 H31 FBCD19 H11 D9 FBCDQM#1
    DQA_18 DQMA#_0 FBCD20 DQB_19 DQMB#_1 FBCDQM#2
    L25 DQA_19 DQMA#_1 J29 H9 DQB_20 DQMB#_2 G9
    J25 J26 FBCD21 E7 K7 FBCDQM#3
    DQA_20 DQMA#_2 FBCD22 DQB_21 DQMB#_3 FBCDQM#4
    G28 DQA_21 DQMA#_3 G23 F8 DQB_22 DQMB#_4 M5
    H27 E21 FBCD23 G8 V2 FBCDQM#5
    DQA_22 DQMA#_4 FBCD24 DQB_23 DQMB#_5 FBCDQM#6
    H26 DQA_23 DQMA#_5 B15 G6 DQB_24 DQMB#_6 W4
    F26 D14 FBCD25 G7 T9 FBCDQM#7
    DQA_24 DQMA#_6 FBCD26 DQB_25 DQMB#_7
    G26 DQA_25 DQMA#_7 J17 H8 DQB_26
    H25 FBCD27 J8
    DQA_26 FBCD28 DQB_27 FBCDQS0
    H24 DQA_27 K8 DQB_28 QSB_0 B9
    H23 J31 FBCD29 L8 D10 FBCDQS1
    DQA_28 QSA_0 FBCD30 DQB_29 QSB_1 FBCDQS2
    H22 DQA_29 QSA_1 K29 K9 DQB_30 QSB_2 H10
    J23 K25 FBCD31 L9 K6 FBCDQS3
    DQA_30 QSA_2 FBCD32 DQB_31 QSB_3 FBCDQS4
    J22 DQA_31 QSA_3 F23 K5 DQB_32 QSB_4 N4
    E23 D20 FBCD33 L4 U2 FBCDQS5
    DQA_32 QSA_4 FBCD34 DQB_33 QSB_5 FBCDQS6
    D22 DQA_33 QSA_5 B16 K4 DQB_34 QSB_6 U4
    D23 D16 FBCD35 L5 V8 FBCDQS7
    DQA_34 QSA_6 FBCD36 DQB_35 QSB_7
    E22 DQA_35 QSA_7 H15 N5 DQB_36
    E20 R637 56_0402_5% FBCD37 N6 B10 FBCDQS#0
    DQA_36 C804 DQB_37 QSB_0#
    F20 K31 FBCCLK0 2 1 FBCD38 P4 E10 FBCDQS#1
    DQA_37 QSA_0# R638 56_0402_5% FBCD39 DQB_38 QSB_1# FBCDQS#2
    D19 DQA_38 QSA_1# K28 1 2 R4 DQB_39 QSB_2# G10
    C D18 K26 FBCCLK0# 2 1 FBCD40 P2 J7 FBCDQS#3 C
    DQA_39 QSA_2# 470P_0402_50V7K FBCD41 DQB_40 QSB_3# FBCDQS#4
    B19 DQA_40 QSA_3# G24 R2 DQB_41 QSB_4# M4
    B18 D21 FBCD42 T3 U3 FBCDQS#5
    DQA_41 QSA_4# 64BIT@ FBCD43 DQB_42 QSB_5# FBCDQS#6
    C17 DQA_42 QSA_5# C16 T2 DQB_43 QSB_6# V4
    B17 D15 R639 56_0402_5% FBCD44 W3 V9 FBCDQS#7
    DQA_43 QSA_6# C805 DQB_44 QSB_7#
    C14 J15 FBCCLK1 2 1 FBCD45 W2
    DQA_44 QSA_7# R640 56_0402_5% FBCD46 DQB_45
    B14 DQA_45 1 2 Y3 DQB_46
    C13 FBCCLK1# 2 164BIT@ FBCD47 Y2 D6 FBCODT0
    DQA_46 DQB_47 ODTB0 FBCODT0 <20>
    B13 F29 470P_0402_50V7K FBCD48 T4 J4 FBCODT1
    DQA_47 ODTA0 DQB_48 ODTB1 FBCODT1 <21>
    D17 D24 64BIT@ FBCD49 R5
    DQA_48 ODTA1 FBCD50 DQB_49 FBCCLK0
    E18 DQA_49 T5 DQB_50 CLKB0 B4 FBCCLK0 <20>
    E17 D31 FBCD51 T6 B5 FBCCLK0#
    DQA_50 CLKA0 DQB_51 CLKB0# FBCCLK0# <20>
    F17 E31 FBCD52 V5
    DQA_51 CLKA0# FBCD53 DQB_52 FBC_CKE0
    E15 DQA_52
    10/20/05" W5 DQB_53 CKEB0 C2 FBC_CKE0 <20>
    E14 B30 Close to Memory Side FBCD54 W6
    DQA_53 CKEA0 FBCD55 DQB_54 FBCRAS0#
    F14 DQA_54 Y4 DQB_55 RASB0# E2 FBCRAS0# <20>
    D13 B28 FBCD56 R8
    DQA_55 RASA0# FBCD57 DQB_56 FBCCAS0#
    H18 DQA_56 T8 DQB_57 CASB0# D3 FBCCAS0# <20>
    H17 C29 +1.8VS +1.8VS FBCD58 R7
    DQA_57 CASA0# FBCD59 DQB_58 FBCWE0#
    G18 DQA_58 T7 DQB_59 WEB0# B2 FBCWE0# <20>
    G17 B31 FBCD60 V7
    DQA_59 WEA0# DQB_60
    1

    1
    G15 FBCD61 W7 D2 FBCCS0#
    DQA_60 DQB_61 CSB0#_0 FBCCS0# <20>
    G14 B29 R238 R239 FBCD62 W8 E3
    DQA_61 CSA0#_0 100_0402_1% 100_0402_1% FBCD63 DQB_62 CSB0#_1
    H14 DQA_62 CSA0#_1 C28 W9 DQB_63
    J14 DQA_63
    N2 FBCCLK1
    FBCCLK1 <21>
    2

    2
    +MVREFD_1 CLKB1 FBCCLK1#
    CLKA1 B20 B3 MVREFD_1 CLKB1# P3 FBCCLK1# <21>
    PAD T32 C31 C19 +MVREFS_1 C3
    PAD T33 MVREFD_0 CLKA1# +MVREFD_1 (15mils) MVREFS_1 FBC_CKE1
    C30 MVREFS_0 CKEB1 L3 FBC_CKE1 <21>

    1
    B (15mils) B
    CKEA1 C22 1
    1

    1 R241 1 2 MEM_RST AA3 J2 FBCRAS1#


    DRAM_RST RASB1# FBCRAS1# <21>
    B24 R242 C269 4.7K_0402_5%
    RASA1#

    0.1U_0402_16V4Z
    Modify 11/22 C270 100_0402_1% R240 R243 1 2 AA5 L2 FBCCAS1#
    2 TEST_MCLK CASB1# FBCCAS1# <21>
    0.1U_0402_16V4Z

    B22 100_0402_1% 4.7K_0402_5%

    2
    CASA1# 2 R244 1 FBCWE1#
    2 AA2 M2 FBCWE1# <21>
    2

    4.7K_0402_5% TEST_YCLK WEB1#


    WEA1# B21
    R245 1 2 MEMTEST AA7 K2 FBCCS1#
    (15mil) MEMTEST CSB1#_0 FBCCS1# <21>
    B23 243_0603_1% K3
    CSA1#_0 CSB1#_1
    CSA1#_1 C23

    M56P
    M56P M56@
    M56@

    A A

    GDDR2 Security Classification


    Issued Date 2005/09/10
    Compal Secret Data
    Deciphered Date 2006/09/10
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Title
    Compal Electronics, Inc.
    SCHEMATIC, M/B LA-3151P
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期 |, 三月 09, 2006 Sheet 18 of 55
    5 4 3 2 1
    5 4 3 2 1

    +1.8VS
    220U_D2_4VM@ C271 10/20/05"
    2 1 1000mA for GDDR1
    2400mA for GDDR3 +1.8VS U9E +1.2VS For PCIE_PVDD_12 only

    +
    C272 C273 C274 L47
    1 2 1 2 1 2 C1 VDDR1
    POWERPCIE_PVDD_12 V23 100mA 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +PCIE_PVDD 1 2
    BLM18PG121SN1D_0603
    L need close to chip
    J1 VDDR1 PCIE_PVDD_12 N23 2 2 2 2 2 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M M1 P23
    VDDR1 PCIE_PVDD_12 C275 C276 C277 C278 C279 C280
    R1 VDDR1 PCIE_PVDD_12 U23
    C281 C282 C283 V1 VDDR1 1 1 1 1 1 1
    1 2 1 2 1 2 AA1 VDDR1 PCIE_VDDR_12 N29 1500mA
    A3 N28 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M VDDR1 PCIE_VDDR_12
    P9 VDDR1 PCIE_VDDR_12 N27
    D J10 VDDR1 PCIE_VDDR_12 N26 D
    +1.2VS

    P CI EXPRESS
    C284 C285 C286 N9 N25
    VDDR1 PCIE_VDDR_12 R641
    1 2 1 2 1 2 P10 VDDR1
    A9 AL31 22U_0805_6.3V6M 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +PCIE_VDDR 0.1U_0402_16V4Z
    1 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1 PCIE_VDDR_12 0_0805_5%
    Y10 VDDR1 PCIE_VDDR_12 AM31 2 2 2 2 2 2 2 2 2
    P8 VDDR1 PCIE_VDDR_12 AM30
    C294 C295 C296 R9 AL32 C287 C288 C289 C290 C291 C292 C293 C806 C807
    VDDR1 PCIE_VDDR_12
    1 2 1 2 1 2 Y9 VDDR1 PCIE_VDDR_12 AL30
    1 1 1 1 1 1 1 1 1 10/20/05"
    J11 VDDR1 PCIE_VDDR_12 AM28
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A21 AL29 22U_0805_6.3V6M 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR1 PCIE_VDDR_12
    M10 AM29

    MEMORY I/O
    C297 C298 C299 VDDR1 PCIE_VDDR_12
    N10 VDDR1 PCIE_VDDR_12 AM27
    1 2 1 2 1 2 Y8 +VDD_CORE VDDC+VDDCI=18A +VDD_CORE +VDD_CORE
    VDDR1 C300 C301 C302 C303
    J18 VDDR1
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J19 AC11 1 2 1 2 1 2 1 2
    VDDR1 VDDC
    K21 VDDR1 VDDC AC12
    C304 C305 C306 A12 P14 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR1 VDDC
    1 2 1 2 1 2 H13 VDDR1 VDDC U15
    A15 W14 C307 C308 C309 C310
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1 VDDC
    J20 VDDR1 VDDC W15 1 2 1 2 1 2 1 2
    J13 VDDR1 VDDC R17
    C311 C312 C313 K11 R15 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR1 VDDC
    1 2 1 2 1 2 K19 VDDR1 VDDC V15
    A18 V16 C314 C315 C316 C317
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1 VDDC
    L23 VDDR1 VDDC T16 1 2 1 2 1 2 2 1

    +
    K20 U16

    CO RE
    C318 C319 C320 VDDR1 VDDC 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z @
    K24 VDDR1 VDDC T17 220U_D2_4VM
    1 2 1 2 1 2 L24 VDDR1 VDDC U17
    H19 V14 C321 C322 C323
    C 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1 VDDC C
    A24 VDDR1 VDDC R18 1 2 1 2 1 2
    K13 VDDR1 VDDC T18
    C324 C325 C326 J32 V18 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR1 VDDC
    1 2 1 2 1 2 A30 VDDR1 VDDC P18
    C32 P19 C327 C328 C329
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR1 VDDC
    F32 VDDR1 VDDC R19 1 2 1 2 1 2
    L32 VDDR1 VDDC W19
    AD11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    +3VS +3VS VDDC
    C330 C331 C332
    1 2 1 2 1 2 400mA AB9 AC13 100mA +VDD25 L9
    VDDR3 VDD25 22U_0805_6.3V6M
    AB10 VDDR3 VDD25 AC16 1 2 +2.5VS
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M AA9 AC18 2 2 2 MBK1608301YZF_0603
    VDDR3 VDD25 L10
    AC19 VDDR3
    C336 C337 AD18 AC15 60mA +VDDPLL 1 2 C333 C334 C335
    VDDR3 VDDPLL +1.2VS

    I/O INTERNAL
    1 2 1 2 AC20 VDDR3 2 2 BLM15AG121SN1D_0402 1 1 1
    0.1U_0402_16V4Z
    AD19 W10 500mA @
    0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR3 VDDCI C808 C338 0.1U_0402_16V4Z
    AD20 VDDR3 VDDCI T14
    W17 0.1U_0402_16V4Z
    C339 C340 VDDCI 1 1
    VDDCI P16
    1 2 1 2 50mA AJ5 T23 22U_0805_6.3V6M L11
    VDDR4 VDDCI +VDDCI 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    AM5 K14 1 2 +VDD_CORE

    I/O
    0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR4 VDDCI
    AL5 VDDR4 VDDCI U19 2 2 2 2 BLM18PG121SN1D_0603
    AK5 VDDR4
    C345 C346 C341 C342 C343 C344
    1 2 1 2 +LPVDD
    100mA 20mA C347 2 1 1 1 1
    AE2 VDDR5 LPVDD/VDDL0 AE19 1
    0.1U_0402_16V4Z 0.1U_0402_16V4Z AE3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDDR5 300mA 0.1U_0402_16V4Z
    AE4 VDDR5 LVDDR/VDDL0 AF20 Modify 11/18
    B B
    AE5 VDDR5 LVDDR/VDDL0 AE20

    LVDS PLL, I/O


    LVDDR/VDDL0 AF19
    L71
    L12 AC21 0.1U_0402_16V4Z 0.1U_0402_16V4Z +LVDDR 1 2 +2.5VS
    +VDDRH0 0.1U_0402_16V4Z ?mA LVDDR/VDDL1 BLM18PG121SN1D_0603
    +1.8VS 1 2 A27 VDDRH0 LVDDR/VDDL1 AC22 2 2 2 2 2 2
    BLM18PG121SN1D_0603 2 2 +VDDRH1 F1 AD22
    VDDRH1 LVDDR/VDDL1 C348 C349 C350 C351 C352 C353
    MEM I/O

    C354 C355 0.1U_0402_16V4Z


    CLOCK

    A28 VSSRH0 LVDDR/VDDL2 AE21


    22U_0805_6.3V6M 1 1 1 1 1 1
    E1 VSSRH1 LVDDR/VDDL2 AD21
    1 1 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    LVDDR/VDDL2 AE22
    L13 +LPVDD L14
    1 2 22U_0805_6.3V6M +AVDD 100mA AL25 AM8 60mA 1 2
    +2.5VS AVDD TPVDD +2.5VS
    BLM15AG121SN1D_0402 2 2 L15 AM25 1 BLM15AG121SN1D_0402
    AVDD
    BLM15AG121SN1D_0402 AJ6 150mA 22U_0805_6.3V6M
    TM DS

    TXVDDR +2.5VS
    C RT

    C357 C358 +2.5VS 1 2+VDD1DI 50mA AM23 VDD1DI TXVDDR AK6 2 2 2 C359
    2 1 TXVDDR AL6 0.1U_0402_16V4Z
    1 1 C360 0.1U_0402_16V4Z C361 C362 C363 2
    TXVDDR AM6
    0.1U_0402_16V4Z 120mA AM16 0.1U_0402_16V4Z
    22U_0805_6.3V6M +A2VDD A2VDD 1 1 1 L16
    AL16 A2VDD
    L17 2 2 PVDD AJ14 160mA 0.1U_0402_16V4Z +PVDD 1 2 +2.5VS
    +2.5VS 1 2 AL14 L18 2 2 BLM15AG121SN1D_0402
    TV

    NC_A2VDDQ
    PLL

    BLM15AG121SN1D_0402 C364 C365


    MPVDD A6 240mA +MPVDD 1 2 +VDD_CORE
    1 1 +VDD1DI 50mA AJ16 VDD2DI 2 2 BLM15AG121SN1D_0402 C366 C367
    2 0.1U_0402_16V4Z
    0.1U_0402_16V4Z C370 C368 C369 1 1
    M56P 0.1U_0402_16V4Z 22U_0805_6.3V6M
    +1.8VS 0.1U_0402_16V4Z M56@ 1 1
    1 22U_0805_6.3V6M
    A A
    L60
    1 2 +VDDRH1
    BLM18PG121SN1D_0603 2 2
    C922 C356
    22U_0805_6.3V6M 0.1U_0402_16V4Z
    1 1 Security Classification Compal Secret Data
    Title
    Compal Electronics, Inc.
    Issued Date 2005/09/10 Deciphered Date 2006/09/10
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期 |, 三月 09, 2006 Sheet 19 of 55
    5 4 3 2 1
    5 4 3 2 1

    11/03/05' SWAP NET


    11/04/05' SWAP NET
    11/08/05' SWAP NET 11/03/05' SWAP NET

    U12 U13
    FBC_BA0 L2 B9 FBCD26 FBC_BA0 L2 B9 FBCD20 FBCD[0..63]
    BA0 DQ15 BA0 DQ15 <18,21> FBCD[0..63]
    FBC_BA1 L3 B1 FBCD30 FBC_BA1 L3 B1 FBCD17
    D BA1 DQ14 FBCD24 BA1 DQ14 FBCD18 D
    DQ13 D9 DQ13 D9
    FBCA12 R2 D1 FBCD29 FBCA12 R2 D1 FBCD23 FBCA[0..12]
    A12 DQ12 A12 DQ12 <18,21> FBCA[0..12]
    FBCA11 P7 D3 FBCD28 FBCA11 P7 D3 FBCD22
    FBCA10 A11 DQ11 FBCD27 FBCA10 A11 DQ11 FBCD19
    M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
    FBCA9 P3 C2 FBCD31 FBCA9 P3 C2 FBCD21 FBCDQS[0..7]
    A9 DQ9 A9 DQ9 <18,21> FBCDQS[0..7]
    FBCA8 P8 C8 FBCD25 FBCA8 P8 C8 FBCD16
    FBCA7 A8 DQ8 FBCD11 FBCA7 A8 DQ8 FBCD7
    P2 A7 DQ7 F9 P2 A7 DQ7 F9
    FBCA6 N7 F1 FBCD14 FBCA6 N7 F1 FBCD0 FBCDQS#[0..7]
    A6 DQ6 A6 DQ6 <18,21> FBCDQS#[0..7]
    FBCA5 N3 H9 FBCD9 FBCA5 N3 H9 FBCD6
    FBCA4 A5 DQ5 FBCD15 FBCA4 A5 DQ5 FBCD3
    N8 A4 DQ4 H1 N8 A4 DQ4 H1
    FBCA3 N2 H3 FBCD13 FBCA3 N2 H3 FBCD2 FBCDQM#[0..7]
    A3 DQ3 A3 DQ3 <18,21> FBCDQM#[0..7]
    FBCA2 M7 H7 FBCD10 FBCA2 M7 H7 FBCD5
    FBCA1 A2 DQ2 FBCD12 FBCA1 A2 DQ2 FBCD1
    M3 A1 DQ1 G2 M3 A1 DQ1 G2
    FBCA0 M8 G8 FBCD8 FBCA0 M8 G8 FBCD4 FBC_BA0
    A0 DQ0 A0 DQ0 <18,21> FBC_BA0
    FBC_BA1
    <18,21> FBC_BA1
    FBCCLK0# K8 A9 FBCCLK0# K8 A9
    FBCCLK0 CK VDDQ1 FBCCLK0 CK VDDQ1 FBCODT0
    J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 <18> FBCODT0
    VDDQ3 C3 VDDQ3 C3
    FBC_CKE0 K2 C7 FBC_CKE0 K2 C7 FBC_CKE0
    CKE VDDQ4 CKE VDDQ4 <18> FBC_CKE0
    VDDQ5 C9 VDDQ5 C9
    E9 E9 FBCRAS0#
    VDDQ6 VDDQ6 +1.8VS <18> FBCRAS0#
    VDDQ7 G1 VDDQ7 G1
    FBCCS0# L8 G3 +1.8VS FBCCS0# L8 G3 FBCCAS0#
    CS VDDQ8 CS VDDQ8 <18> FBCCAS0#
    VDDQ9 G7 VDDQ9 G7
    FBCWE0# K3 G9 FBCWE0# K3 G9 FBCWE0#
    WE VDDQ10 WE VDDQ10 <18> FBCWE0#
    FBCRAS0# K7 A1 FBCRAS0# K7 A1 FBCCS0#
    RAS VDD1 RAS VDD1 <18> FBCCS0#
    VDD2 E1 VDD2 E1
    FBCCAS0# L7 J9 FBCCAS0# L7 J9 FBCCLK0
    CAS VDD3 CAS VDD3 <18> FBCCLK0
    VDD4 M9 VDD4 M9
    FBCDQM#1 F3 R1 FBCDQM#0 F3 R1 FBCCLK0#
    C LDM VDD5 LDM VDD5 <18> FBCCLK0# C
    FBCDQM#3 B3 FBCDQM#2 B3
    UDM UDM
    VDDL J1 VDDL J1
    VSSDL J7 1 1 VSSDL J7 1 1
    FBCODT0 K9 C371 C372 FBCODT0 K9 C373 C374
    ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z

    +1.8VS FBCDQS1 2 2 FBCDQS0 2 2


    F7 LDQS F7 LDQS
    FBCDQS#1 E8 A7 FBCDQS#0 E8 A7
    LDQS VSSQ1 LDQS VSSQ1
    VSSQ2 B2 VSSQ2 B2
    VSSQ3 B8 VSSQ3 B8
    1

    VSSQ4 D2 VSSQ4 D2
    R247 FBCDQS3 B7 D8 FBCDQS2 B7 D8
    +VRAM_VREFC 1K_0402_1% FBCDQS#3 UDQS VSSQ5 +VRAM_VREFC FBCDQS#2 UDQS VSSQ5
    A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
    VSSQ7 F2 VSSQ7 F2
    F8 F8
    2

    VSSQ8 VSSQ8
    J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
    VSSQ10 H8 VSSQ10 H8
    1

    1 (SSTL-1.8) VREF = .5*VDDQ A2 1 (SSTL-1.8) VREF = .5*VDDQ A2


    R248 C375 NC#A2 C376 NC#A2 +0.9VS
    E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3
    1K_0402_1% 0.047U_0402_16V4Z L1 E3 0.047U_0402_16V4Z L1 E3
    NC#L1 VSS2 NC#L1 VSS2
    R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
    2 2 M56@ R249 56_0402_5%
    R7 N1 R7 N1
    2

    NC#R7 VSS4 NC#R7 VSS4 FBCODT0


    R8 NC#R8 VSS5 P9 Close to U13 R8 NC#R8 VSS5 P9 2 1
    Close to U12 M56@ R250 56_0402_5%
    FBC_CKE0 2 1
    X76@ HY5PS561621AFP-25 X76@ HY5PS561621AFP-25 M56@ R251 56_0402_5%
    FBCRAS0# 2 1
    M56@ R252 56_0402_5%
    FBCCAS0# 2 1
    M56@ R253 56_0402_5%
    FBCWE0# 2 1
    DDR2 BGA MEMORY DDR2 BGA MEMORY M56@ R254 56_0402_5%
    B FBCCS0# B
    2 1
    M56@ R255 56_0402_5%
    FBC_BA0 2 1
    M56@ R256 56_0402_5%
    +1.8VS +1.8VS FBC_BA1 2 1
    M56@ R257 56_0402_5%
    0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z FBCA12 2 1
    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 M56@ R258 56_0402_5%
    C377 C378 C379 C380 C381 C382 C383 C384 C385 C386 C387 C388 C389 C390 C391 C392 FBCA11 2 1
    0.01U_0402_16V7K 0.01U_0402_16V7K M56@ R259 56_0402_5%
    FBCA10 2 1
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 M56@ R260 56_0402_5%
    1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z FBCA9 2 1
    M56@ R261 56_0402_5%
    FBCA8 2 1
    M56@ R262 56_0402_5%
    FBCA7 2 1
    M56@ R263 56_0402_5%
    FBCA6 2 1
    M56@ R264 56_0402_5%
    FBCA5 2 1
    M56@ R265 56_0402_5%
    FBCA4 2 1
    M56@ R266 56_0402_5%
    FBCA3 2 1
    M56@ R267 56_0402_5%
    FBCA2 2 1
    M56@ R268 56_0402_5%
    FBCA1 2 1
    M56@ R269 56_0402_5%
    FBCA0 2 1
    A A

    M56 Only

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 20 of 55
    5 4 3 2 1
    5 4 3 2 1

    11/03/05' SWAP NET 11/03/05' SWAP NET

    U14 U15
    FBC_BA0 L2 B9 FBCD32 FBC_BA0 L2 B9 FBCD62
    FBC_BA1 BA0 DQ15 FBCD39 FBC_BA1 BA0 DQ15 FBCD58
    L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
    D FBCD34 FBCD63 D
    DQ13 D9 DQ13 D9
    FBCA12 R2 D1 FBCD37 FBCA12 R2 D1 FBCD56
    FBCA11 A12 DQ12 FBCD38 FBCA11 A12 DQ12 FBCD57
    P7 A11 DQ11 D3 P7 A11 DQ11 D3
    FBCA10 M2 D7 FBCD33 FBCA10 M2 D7 FBCD61 FBCD[0..63]
    A10/AP DQ10 A10/AP DQ10 <18,20> FBCD[0..63]
    FBCA9 P3 C2 FBCD36 FBCA9 P3 C2 FBCD59
    FBCA8 A9 DQ9 FBCD35 FBCA8 A9 DQ9 FBCD60
    P8 A8 DQ8 C8 P8 A8 DQ8 C8
    FBCA7 P2 F9 FBCD49 FBCA7 P2 F9 FBCD45 FBCA[0..12]
    A7 DQ7 A7 DQ7 <18,20> FBCA[0..12]
    FBCA6 N7 F1 FBCD55 FBCA6 N7 F1 FBCD41
    FBCA5 A6 DQ6 FBCD50 FBCA5 A6 DQ6 FBCD47
    N3 A5 DQ5 H9 N3 A5 DQ5 H9
    FBCA4 N8 H1 FBCD53 FBCA4 N8 H1 FBCD42 FBCDQS[0..7]
    A4 DQ4 A4 DQ4 <18,20> FBCDQS[0..7]
    FBCA3 N2 H3 FBCD54 FBCA3 N2 H3 FBCD43
    FBCA2 A3 DQ3 FBCD48 FBCA2 A3 DQ3 FBCD46
    M7 A2 DQ2 H7 M7 A2 DQ2 H7
    FBCA1 M3 G2 FBCD52 FBCA1 M3 G2 FBCD40 FBCDQS#[0..7]
    A1 DQ1 A1 DQ1 <18,20> FBCDQS#[0..7]
    FBCA0 M8 G8 FBCD51 FBCA0 M8 G8 FBCD44
    A0 DQ0 A0 DQ0
    FBCDQM#[0..7]
    <18,20> FBCDQM#[0..7]
    FBCCLK1# K8 A9 FBCCLK1# K8 A9
    FBCCLK1 CK VDDQ1 FBCCLK1 CK VDDQ1
    J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
    C3 C3 FBC_BA0
    VDDQ3 VDDQ3 <18,20> FBC_BA0
    FBC_CKE1 K2 C7 FBC_CKE1 K2 C7
    CKE VDDQ4 CKE VDDQ4 FBC_BA1
    VDDQ5 C9 VDDQ5 C9 <18,20> FBC_BA1
    VDDQ6 E9 VDDQ6 E9
    G1 +1.8VS G1 +1.8VS FBCODT1
    VDDQ7 VDDQ7 <18> FBCODT1
    FBCCS1# L8 G3 FBCCS1# L8 G3
    CS VDDQ8 CS VDDQ8 FBC_CKE1
    VDDQ9 G7 VDDQ9 G7 <18> FBC_CKE1
    FBCWE1# K3 G9 FBCWE1# K3 G9
    WE VDDQ10 WE VDDQ10 FBCRAS1#
    <18> FBCRAS1#
    FBCRAS1# K7 A1 FBCRAS1# K7 A1
    RAS VDD1 RAS VDD1 FBCCAS1#
    VDD2 E1 VDD2 E1 <18> FBCCAS1#
    FBCCAS1# L7 J9 FBCCAS1# L7 J9
    CAS VDD3 CAS VDD3 FBCWE1#
    VDD4 M9 VDD4 M9 <18> FBCWE1#
    FBCDQM#6 F3 R1 FBCDQM#5 F3 R1
    C FBCDQM#4 LDM VDD5 FBCDQM#7 LDM VDD5 FBCCS1# C
    B3 UDM B3 UDM <18> FBCCS1#
    VDDL J1 VDDL J1
    J7 1 1 J7 1 1 FBCCLK1
    VSSDL VSSDL <18> FBCCLK1
    FBCODT1 K9 C393 C394 FBCODT1 K9 C395 C396
    ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBCCLK1#
    <18> FBCCLK1#
    64BIT@ 64BIT@ 64BIT@ 64BIT@
    +1.8VS FBCDQS6 2 2 FBCDQS5 2 2
    F7 LDQS F7 LDQS
    FBCDQS#6 E8 A7 FBCDQS#5 E8 A7
    LDQS VSSQ1 LDQS VSSQ1
    VSSQ2 B2 VSSQ2 B2
    VSSQ3 B8 VSSQ3 B8
    1

    VSSQ4 D2 VSSQ4 D2
    R270 FBCDQS4 B7 D8 FBCDQS7 B7 D8
    +VRAM_VREFD 1K_0402_1% FBCDQS#4 UDQS VSSQ5 +VRAM_VREFD FBCDQS#7 UDQS VSSQ5
    A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
    64BIT@ F2 F2
    VSSQ7 VSSQ7
    F8 F8
    2

    VSSQ8 VSSQ8
    J2 VREF VSSQ9 H2 J2 VREF VSSQ9 H2
    VSSQ10 H8 VSSQ10 H8
    1

    1 (SSTL-1.8) VREF = .5*VDDQ A2 1 (SSTL-1.8) VREF = .5*VDDQ A2


    R271 C397 NC#A2 C398 NC#A2
    E2 NC#E2 VSS1 A3 E2 NC#E2 VSS1 A3
    1K_0402_1% 0.047U_0402_16V4Z L1 E3 0.047U_0402_16V4Z L1 E3
    64BIT@ 64BIT@ NC#L1 VSS2 64BIT@ NC#L1 VSS2
    R3 NC#R3 VSS3 J3 R3 NC#R3 VSS3 J3
    2 2
    R7 N1 R7 N1
    2

    NC#R7 VSS4 NC#R7 VSS4


    Close to U14 R8 NC#R8 VSS5 P9 Close to U15 R8 NC#R8 VSS5 P9

    X76@ HY5PS561621AFP-25 X76@ HY5PS561621AFP-25

    B B
    DDR2 BGA MEMORY DDR2 BGA MEMORY

    +1.8VS
    +1.8VS +0.9VS
    0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 1 1 1 1 1 1 1 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    C399 C400 C401 C402 C403 C404 C405 C406 1 1 1 1 1 1 1 1 M56@ R273 56_0402_5%
    0.01U_0402_16V7K C407 C408 C409 C410 C411 C412 C413 C414 FBCRAS1# 2 1
    0.01U_0402_16V7K M56@ R274 56_0402_5%
    2 2 2 2 2 2 2 2 FBC_CKE1 2 1
    1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 M56@ R275 56_0402_5%
    1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z FBCODT1 2 1
    M56@ R276 56_0402_5%
    FBCCAS1# 2 1
    M56@ R277 56_0402_5%
    FBCWE1# 2 1
    M56@ R278 56_0402_5%
    FBCCS1# 2 1

    M56 Only

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 21 of 55
    5 4 3 2 1
    5 4 3 2 1

    PLACE THESE PCIE AC COUPLING


    CAPS CLOSE TO U600 U16A

    A_RST# AG10
    SB460 U2 CLK_PCI_LAN_R R280 1 2 22_0402_5% CLK_PCI_LAN_R
    A_RST# PCICLK0 CLK_PCI_LAN <31> CLK_PCI_LAN_R <26>
    Part 1 of 4 T2 CLK_PCI_LPC_R R281 1 2 @ 22_0402_5% CLK_PCI_LPC <33> CLK_PCI_LPC_R CLK_PCI_LPC_R <26>
    PCICLK1 CLK_PCI_MINI_R R282 @ 22_0402_5% CLK_PCI_MINI_R

    PCI CLKS
    <15> SBSRC_CLKP J24 PCIE_RCLKP PCICLK2 U1 1 2 CLK_PCI_MINI <36> CLK_PCI_MINI_R <26>
    J25 V2 CLK_PCI_PCM_R R283 1 2 @ 22_0402_5% CLK_PCI_PCM <37> CLK_PCI_PCM_R CLK_PCI_PCM_R <26>
    <15> SBSRC_CLKN PCIE_RCLKN PCICLK3
    W3 CLK_PCI_1394_R R284 1 2 @ 22_0402_5% CLK_PCI_1394 <40> CLK_PCI_1394_R CLK_PCI_1394_R <26>
    A_MRX_STX_P0 C415 1 PCICLK4
    <12> A_MRX_STX_P0 2 0.01U_0402_16V7K A_MRX_C_STX_P0 P29 PCIE_TX0P PCICLK5 U3 CLK_PCI_SIO_R R285 1 2 @ 22_0402_5% CLK_PCI_SIO <41> CLK_PCI_SIO_R CLK_PCI_SIO_R <26>
    A_MRX_STX_N0 C416 1 2 0.01U_0402_16V7K A_MRX_C_STX_N0 P28 V1 PCI_CLK6_R R286 1 2 22_0402_5% PCI_CLK6 <26>
    <12> A_MRX_STX_N0 PCIE_TX0N PCICLK6
    A_MRX_STX_P1 C417 1 2 0.01U_0402_16V7K A_MRX_C_STX_P1 M29 T1 R287 1 2 0_0402_5% SB_SPDIFO <26>
    <12> A_MRX_STX_P1 PCIE_TX1P SPDIF_OUT/GPIO41
    A_MRX_STX_N1 C418 1 2 0.01U_0402_16V7K A_MRX_C_STX_N1 M28
    <12> A_MRX_STX_N1 PCIE_TX1N
    K29 AJ9 PCIRST#
    PCIE_TX2P PCIRST#
    K28 PCIE_TX2N
    D H29 PCI_AD[31..0] D
    PCIE_TX3P PCI_AD[31..0] <26,31,36,37,40>
    H28 W7 PCI_AD0
    PCIE_TX3N AD0/ROMA18 PCI_AD1
    AD1/ROMA17 Y1
    A_MTX_C_SRX_P0 T25 W8 PCI_AD2 +3VS +3VS
    <12> A_MTX_C_SRX_P0 PCIE_RX0P AD2/ROMA16
    FOR SB600 VCC_SB= 1.2V A_MTX_C_SRX_N0 PCI_AD3
    <12> A_MTX_C_SRX_N0 T26 PCIE_RX0N AD3/ROMA15 W5
    EMI 11/2 Modify

    PCI EXPRESS INTERFACE


    A_MTX_C_SRX_P1 T22 AA5 PCI_AD4
    FOR SB460 VCC_SB= 1.8V <12> A_MTX_C_SRX_P1 PCIE_RX1P AD4/ROMA14

    1
    A_MTX_C_SRX_N1 T23 Y3 PCI_AD5
    <12> A_MTX_C_SRX_N1 PCIE_RX1N AD5/ROMA13
    R294 CALRP: SB600=562R 1%, SB460=150R 1% R289 1 2 @ 49.9_0402_1% SB_TX2P M25 AA6 PCI_AD6 L68 R834
    R290 @ 49.9_0402_1% SB_TX2N PCIE_RX2P AD6/ROMA12 PCI_AD7 FBM-L11-160808-800LMT_0603 10K_0402_5%
    R295 CALRN: SB600=2.05K 1%, SB460=150R 1% 1 2 M26 PCIE_RX2N AD7/ROMA11 AC5
    R296 CALRN: SB600=0R 1%, SB460=4.12K 1% R291 1 2 @ 49.9_0402_1% SB_TX3P M22 AA7 PCI_AD8 @ U59
    R293 @ 49.9_0402_1% SB_TX3N PCIE_RX3P AD8/ROMA9 PCI_AD9 CLKOUT1 R835
    1 2 M23 AC3 8 DLY CNTRL CLKOUT1 2 1 2 @ 22_0402_5% CLK_PCI_LAN

    2
    PCIE_RX3N AD9/ROMA8 PCI_AD10 CLK_PCI_LAN_R CLKOUT2 R836 22_0402_5% CLK_PCI_LPC
    AC7 1 CLKIN CLKOUT2 6 1 2

    2
    R294 AD10/ROMA7 PCI_AD11 CLKOUT3 CLK_PCI_MINI
    1 2 150_0402_1% E29 PCIE_CALRP AD11/ROMA6 AJ7 3 VDD CLKOUT3 7
    R837 1 2 22_0402_5%
    PCIE_VDDR R295 1 2 150_0402_1% E28 AD4 PCI_AD12 13 VDD 10 CLKOUT4 R838 1 2 22_0402_5% CLK_PCI_PCM
    PCIE_CALRN AD12/ROMA5 PCI_AD13 R8391 CLKOUT4 CLKOUT5 R840 22_0402_5% CLK_PCI_1394
    AD13/ROMA4 AB11 2 9 SSON CLKOUT5 11 1 2
    +1.8VS R296 1 2 4.12K_0402_1% E27 AE6 PCI_AD14 10K_0402_5% 4 SS% 14 CLKOUT6 R841 1 2 22_0402_5% CLK_PCI_SIO
    L19 PCIE_CALI AD14/ROMA3 PCI_AD15 CLKOUT6
    AD15/ROMA2 AC9 5 GND CLKOUT7 15

    1
    1 2 U29 AA3 PCI_AD16 12 GND
    PCIE_PVDD AD16/ROMD0 PCI_AD17 CLKOUT8 16 12/26:Modify
    1 1 AD17/ROMD1 AJ4 1 C944 R842
    KC FBM-L11-201209-221LMAT_0805 C421 C422 U28 AB1 PCI_AD18 1U_0402_6.3V4Z ASM3P623S00EF-16-TR_TSSOP16
    NC AD18/ROMD2 PCI_AD19 +3VALW
    AD19/ROMD3 AH4
    10U_0805_10V4Z 1U_0402_6.3V4Z PCIE_VDDR F27 AB2 PCI_AD20 10K_0402_5% C419

    2
    2 2 PCIE_VDDR_1 AD20/ROMD4 PCI_AD21 2
    F28 PCIE_VDDR_2 AD21/ROMD5 AJ3 1 2 0.1U_0402_16V4Z
    C608 AND C609 CLOSE F29 AB3 PCI_AD22
    PCIE_VDDR_3 AD22/ROMD6 PCI_AD23
    TO U600.U29 G26 PCIE_VDDR_4 AD23/ROMD7 AH3

    1
    G27 AC1 PCI_AD24 U17
    PCIE_VDDR_5 AD24 PCI_AD25
    G28 AH2

    OE#
    PCIE_VDDR_6 AD25 PCI_AD26 A_RST#
    G29 PCIE_VDDR_7 AD26 AC2 2 I O 4 1 2NB_RST# NB_RST# <13,16,27,33,36,41>
    J27 AH1 PCI_AD27 R279 33_0402_5%
    PCIE_VDDR_8 AD27

    G
    J29 AD2 PCI_AD28
    C +1.8VS PCIE_VDDR PCIE_VDDR_9 AD28 PCI_AD29 R292 74LVC1G125GW_SOT3535 C
    L25 AG2

    PCI INTERFACE

    3
    L20 PCIE_VDDR_10 AD29 PCI_AD30 8.2K_0402_5%
    L26 PCIE_VDDR_11 AD30 AD1
    1 2 L29 AG1 PCI_AD31 PCI_CBE#[3..0]
    PCIE_VDDR_12 AD31 PCI_CBE#[3..0] <31,36,37,40>
    1 1 1 1 1 1 N29 AB9 PCI_CBE#0

    2
    KC FBM-L11-201209-221LMAT_0805 C423 C424 C425 C426 C427 C428 PCIE_VDDR_13 CBE0#/ROMA10 PCI_CBE#1 R645 1
    CBE1#/ROMA1 AF9 2 @ 0_0402_5%
    AJ5 PCI_CBE#2
    1U_0402_6.3V4Z CBE2#/ROMWE# PCI_CBE#3 +3VALW 12/26:Modify
    CBE3# AG3
    2 2 2 2 2 2 AA2 PCI_FRAME# C420
    FRAME# PCI_FRAME# <31,36,37,40>
    22U_0805_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z AH6 PCI_DEVSEL# PCI_DEVSEL# <31,36,37,40> 1 2 0.1U_0402_16V4Z
    1U_0402_6.3V4Z 1U_0402_6.3V4Z DEVSEL#/ROMA0 PCI_I RDY#
    IRDY# AG5 PCI_IRDY# <31,36,37,40>
    AA1 PCI_TRDY# PCI_TRDY# <31,36,37,40>
    TRDY#/ROMOE#

    1
    R303 AF7 PCI_PAR PCI_PAR <31,36,37,40> U18
    20M_0603_5% PAR/ROMA19 PCI_STOP#
    Y2

    OE#
    STOP# PCI_STOP# <31,36,37,40>
    2 1 AG8 PCI_PERR# PCI_PERR# <31,36,37,40> PCIRST# 2 4 1 2 PCI_RST# PCI_RST# <31,36,37,39,40>
    PERR# PCI_SERR# I O R288 33_0402_5%
    SERR# AC11 PCI_SERR# <31,36,37>

    G
    C429 AJ8 PCI_REQ#0 PCI_REQ#0 <40>
    10P_0402_50V8K REQ0# PCI_REQ#1 R297 74LVC1G125GW_SOT3535
    AE2 PCI_REQ#1 <36>

    3
    32K_X1 REQ1# PCI_REQ#2
    1 2 REQ2# AG9 PCI_REQ#2 <37>
    AH8 PCI_REQ#3 PCI_REQ#3 <31> 8.2K_0402_5%
    REQ3#/PDMA_REQ0#
    20M_0603_5%

    Y2 AH5 PCI_REQ#4

    2
    REQ4#/PLL_BP33/PDMA_REQ1#
    2

    4 3 AD11 PCI_GNT#0 PCI_GNT#0 <40>


    OUT NC GNT0# PCI_GNT#1 R646 1
    GNT1# AF2 PCI_GNT#1 <36> 2 @ 0_0402_5%
    1 2 AH7 PCI_GNT#2 PCI_GNT#2 <37>
    IN NC GNT2#
    R298

    AB12 PCI_GNT#3 PCI_GNT#3 <31> RP2 RP3


    GNT3#/PLL_BP66/PDMA_GNT0# PCI_PLOCK# PCI_PIRQE#
    AG4 +3VS 1 8 +3VS 1 8
    1

    32.768KHZ_12.5PF_6H03200468 GNT4#/PLL_BP50/PDMA_GNT1# PM_CLKRUN# PCI_I RDY# PCI_PIRQF#


    CLKRUN# AG7 PM_CLKRUN# <31,36,41> 2 7 2 7
    1 2 32K_X2 AF6 PCI_PLOCK# 3 6 PCI_PERR# 3 6 PCI_PIRQH#
    LOCK# PCI_DEVSEL# PCI_PIRQG#
    4 5 4 5
    C430 AD3 PCI_PIRQE# PCI_PIRQE# <37,40>
    10P_0402_50V8K INTE#/GPIO33 PCI_PIRQF# 8.2K_1206_8P4R_5% 8.2K_1206_8P4R_5%
    INTF#/GPIO34 AF1 PCI_PIRQF# <31>
    B AF4 PCI_PIRQG# B
    INTG#/GPIO35 PCI_PIRQG# <36>
    PLACE THESE COMPONENTS CLOSE TO U600, AND 32K_X1 D2 AF3 PCI_PIRQH# PCI_PIRQH# <36,37>
    X1 INTH#/GPIO36
    USE GROUND GUARD FOR 32K_X1 AND 32K_X2
    RTC Battery 1
    RP4
    8 PCI_REQ#3
    FOR SB600, CONNECT TO CPU_PG/LDT_PG +3VS
    32K_X2 C1 +RTCBATT 2 7 PCI_REQ#0
    X2
    +
    XTAL
    FOR SB460, CONNECT TO SSMUXSEL/GPIO0 AG24 LPC_AD0 3 6 PCI_REQ#2
    LAD0 LPC_AD0 <33,41>
    AC26 AG25 LPC_AD1 LPC_AD1 <33,41> BATT1 45@ 4 5 PCI_REQ#1
    CPU_PG LAD1 LPC_AD2
    W26 INTR/LINT0 LAD2 AH24 LPC_AD2 <33,41>
    W24 AH25 LPC_AD3 LPC_AD3 <33,41> 2 1 +RTCBATT 8.2K_1206_8P4R_5%
    NMI/LINT1 LAD3 LPC_FRAME#
    W25 INIT# LFRAME# AF24 LPC_FRAME# <26,33,41>

    L PC
    AA24 AJ24 LPC_DRQ#0 LPC_DRQ#0 <41>
    SMI# LDRQ0#

    1
    AA23 AH26 LPC_DRQ#1
    NC LDRQ1# BMREQ# D3
    AA22 W22 BMREQ# <13> RTCBATT
    IGNNE# BMREQ#
    AA26 A20M# SERIRQ AF23 SERIRQ <33,37,41>
    Y27 FERR# C PU BAS40-04_SOT23 RP5
    AA25 D3 RTC_CLK <26> +RTCVCC 1 8 PCI_REQ#4
    <13> ALLOW_LDTSTOP STPCLK#/ALLOW_LDTSTP RTCCLK +3VS
    AH9 F5 RTC_IRQ# <26> 2 7

    2
    RP1 R777 1 CPU_STP#/DPSLP_3V# RTC_IRQ#/ACPWR_STRAP
    +1.2V_HT 2 @ 10K_0402_5% B24 NC 3 6 PM_CLKRUN#
    1 8 PCI_SERR# W23 E1 VBAT_IN R307 2 1 4 5 PCI_PAR
    +3VS DPRSLPVR VBAT +CHGRTC
    2 7 PCI_TRDY# AC25 D1 1 1 1K_0603_5%
    <7> LDT_RST# LDT_RST#/DPRSTP#/PROCHOT# RTC_GND
    RTC

    3 6 PCI_FRAME# C431 1 8.2K_1206_8P4R_5%

    2
    4 5 PCI_STOP# FOR SB460, THIS BALL C432
    IS LDT_RST# ONLY 218S4RASA11GS SB460_BGA549 0.1U_0402_16V4Z R308 C434 R812 1 2 BMREQ#
    8.2K_1206_8P4R_5% 2 2 0.1U_0402_16V4Z
    0_0603_5%
    1U_0402_6.3V4Z 2 10K_0402_5%
    JOPEN1 1
    C942

    1
    2 2 1 1
    +3VS Modify 11/07 15P_0402_50V8J
    2
    A
    SB460 ONLY @ JUMP_43X39 A
    LPC_DRQ#0 R299 1 2 10K_0402_5% Please Closed RAM
    LPC_DRQ#1 R300 1 2 10K_0402_5% Door
    LPC_AD3 R301 1 2 100K_0402_5%
    LPC_AD2 R302 1 2 100K_0402_5%
    LPC_AD1 R304 1 2 100K_0402_5%
    LPC_AD0 R305 1 2 100K_0402_5%
    SERIRQ R306 1 2 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    LPC PULL UPS SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Re v
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: ¬P期四, 三月 09, 2006 Sheet 22 of 55
    5 4 3 2 1

    www.laptopfix.vn
    5 4 3 2 1

    +3VS
    SB460 ONLY

    R309 2 1 10K_0402_5% LPC_SMI# U16D


    R310 2 1 10K_0402_5% EC_FLASH#_R
    R644 1 10K_0402_5%
    SB_INT_FLASH_SEL# Part 4 of 4
    2 SB460
    EC_SWI# A3 A17 CLK_USB_48M CLK_USB_48M <15>
    +3VALW <33> EC_SWI# PCI_PME#/GEVENT4# USBCLK
    EC_SCI# B2
    <33> EC_SCI# RI#/EXTEVNT0#
    <33> PM_SLP_S3# PM_SLP_S3# F7 A14 R312 2 1 11.3K_0402_1%
    R313 SLP_S3# USB_RCOMP
    2 1 10K_0402_5% SYS_RESET# <33> PM_SLP_S5# PM_SLP_S5# A5

    ACPI / WAKE UP EVENTS


    R314 LPC_PME# PBTN_OUT# SLP_S5#
    2 1 10K_0402_5% <33> PBTN_OUT# E3 PWR_BTN# USB_ATEST1 A11
    R315 2 1 @10K_0402_5% EC_KBRST# SB_PWRGD B5 A10
    D R316 PBTN_OUT# <7,42> SB_PWRGD SUS_STAT# PWR_GOOD USB_ATEST0 01/03/05" modify D
    2 1 10K_0402_5% <35> SUS_STAT# B3 SUS_STAT#
    F9 NC NC H12
    R318 2 1 10K_0402_5% EC_SWI# R319 2 1 10K_0402_5% E9 G12
    R320 10K_0402_5% SB_PCIE_WAKE# R321 2 TEST1 NC
    2 1 1 10K_0402_5% G9 TEST0 SB600 ONLY
    R322 2 1 4.7K_0402_5% PM_SLP_S5# EC_GA20 AF26 E12
    PM_SLP_S3# <33> EC_GA20 EC_KBRST# GA20IN NC (NC for SB460)
    R323 2 1 4.7K_0402_5% AG26 D12
    R324 2 1 4.7K_0402_5% S3_STATE_R Modify : 11/07 <33> EC_KBRST# LPC_PME# D7
    KBRST# NC
    R325 10K_0402_5% EC_SCI# LPC_SMI# LPC_PME#/GEVENT3#
    2 1 C25 LPC_SMI#/EXTEVNT1# USB_HSDP7+ E14
    R326 2 1 10K_0402_5% BLINK/GPM6# 2 1 S3_STATE_R D9 D14
    <33> S3_STATE

    USB INTERFACE
    R813 @ 0_0402_5% SYS_RESET# S3_STATE/GEVENT5# USB_HSDM7-
    F4 SYS_RESET#/GPM7#
    R328 2 1 10K_0402_5% EC_SMI# <36,39> SB_PCIE_WAKE# SB_PCIE_WAKE# E7 G14 USB20_P6 USB20_P6 <43>
    R329 10K_0402_5% USB_OC#0 BLINK/GPM6# WAKE#/GEVENT8# USB_HSDP6+ USB20_N6
    2 1 C2 BLINK/GPM6# USB_HSDM6- H14 USB20_N6 <43>
    R330 2 1 10K_0402_5% USB_OC#1 H_THERMTRIP# G7
    <7> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
    R331 2 1 10K_0402_5% USB_OC#3 D16 USB20_P5 USB20_P5 <34>
    R332 10K_0402_5% CP_PE# USB_HSDP5+ USB20_N5
    2 1 USB_HSDM5- E16 USB20_N5 <34>
    R333 2 1 10K_0402_5% USB_OC#6 EC_RSMRST# E2
    <33> EC_RSMRST# RSMRST#
    OSC / RST D18 USB20_P4 USB20_P4 <36>
    SB_OSC_INT USB_HSDP4+ USB20_N4
    <15> SB_OSCIN B23 14M_OSC USB_HSDM4- E18 USB20_N4 <36>
    C28 G16 USB20_P3 USB20_P3 <43>
    R334 2 NC USB_HSDP3+ USB20_N3
    1 10K_0402_5% A26 ROM_CS#/GPIO1 USB_HSDM3- H16 USB20_N3 <43>
    R335 2 1 10K_0402_5% B29
    R336 2 GHI#/GPIO6
    +3VS 1 10K_0402_5% A23 VGATE/GPIO7 USB_HSDP2+ G18 USB20_P2 USB20_P2 <39>
    R830 2 1 0_0402_5% EC_FLASH#_R B27 H18 USB20_N2 USB20_N2 <39>
    <35> EC_FLASH# GPIO4 USB_HSDM2-
    SB_INT_FLASH_SEL# D23
    <35> SB_INT_FLASH_SEL# GPIO5
    B26 D19 USB20_P1 USB20_P1 <39>
    <44> SB_SPKR SB_CK_SCLK SPKR/GPIO2 USB_HSDP1+ USB20_N1
    <9,10,15> SB_CK_SCLK C27 SCL0/GPOC0# USB_HSDM1- E19 USB20_N1 <39>
    SB_CK_SDAT

    GPIO
    <9,10,15> SB_CK_SDAT B28 SDA0/GPOC1#
    C3 G19 USB20_P0 USB20_P0 <39>
    NC USB_HSDP0+ USB20_N0
    F3 NC USB_HSDM0- H19 USB20_N0 <39>
    C +3VS R339 2 1 10K_0402_5% D26 AVDD_USB +3VALW C
    R340 2 DDC1_SCL/GPIO9
    1 10K_0402_5% C26 DDC1_SDA/GPIO8
    L21
    R337 2 1 2.2K_0402_5% SB_CK_SCLK CPU_PWRGD A27 B9 1 2
    <7> CPU_PWRGD LDT_PG/SSMUXSEL/GPIO0 AVDDTX_0
    R338 2 1 2.2K_0402_5% SB_CK_SDAT A4 B11 1 1 1 1 1 1 1 1
    R647 10K_0402_5% GPIO13 NC AVDDTX_1 C435 C436 C437 C438 C439 C440 C441 C442 KC FBM-L11-201209-221LMAT_0805
    2 1 AVDDTX_2 B13
    R831 2 1 10K_0402_5% IDE_HRESET# BALLS(C6 AND C5) ARE FOR SB600 ONLY (NC FOR SB460) B16
    AVDDTX_3 0.1U_0402_16V4Z
    C6 NC AVDDTX_4 B18
    2 2 2 2 2 2 2 2
    C5 NC AVDDRX_0 A9
    EC_SMI# C4 B10 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    <33> EC_SMI# USB_OC7#/GEVENT7# AVDDRX_1
    USB_OC#6 10U_0805_10V4Z 1U_0402_6.3V4Z0.1U_0402_16V4Z

    USB OC
    B4 USB_OC6#/GEVENT6# AVDDRX_2 B12
    AZ_RST# B6 B14
    CP_PE# USB_OC5#/AZ_RST#/GPM5# AVDDRX_3 +3.3V_AVDDC +3VALW
    <39> CP_PE# A6 USB_OC4#/GPM4# AVDDRX_4 B17
    EC_FLASH# R832 2 1 @ 0_0402_5% USB_OC#3 C8 L22
    EC_LID_OUT# USB_OC3#/GPM3#
    <33> EC_LID_OUT# C7 USB_OC2#/FANOUT1/LLB#/GPM2# AVDDC A12 1 2
    USB_OC#1 B8 1 1 1
    USB_OC#0 USB_OC1#/GPM1# C443 C445 KC FBM-L11-201209-221LMAT_0805
    <39> USB_OC#0 A8 USB_OC0#/GPM0# AVSSC A13
    C444
    A16 1U_0402_6.3V4Z
    AZ_BIT_CLK AVSS_USB_1 2 2 2
    N2 AZ_BITCLK AVSS_USB_2 C9
    R341 1 AZ_BIT_CLK AZ_SDATA_OUT 0.1U_0402_16V4Z

    AZALIA
    <34> ICH_BITCLK_MDC 2 M2 AZ_SDOUT AVSS_USB_3 C10
    33_0402_1% K2 C11 2.2U_0603_6.3V6K
    R342 1 AZ_SY NC NC AVSS_USB_4
    <44> ICH_BITCLK_AUDIO 2 L3 AZ_SYNC AVSS_USB_5 C12
    33_0402_1% K3 C13
    R343 1 AZ_SY NC NC AVSS_USB_6
    <34> ICH_SYNC_MDC 2 AVSS_USB_7 C14 PLACE C443,C444 AND

    USB PWR
    33_0402_1% L1 C16 C445 CLOSE TO U16
    R346 1 AC_SDATA_OUT AC_BITCLK/GPIO38 AVSS_USB_8
    <44> ICH_SYNC_AUDIO 2 <26> AC_SDATA_OUT L2 AC_SDOUT/GPIO39 AVSS_USB_9 C17
    33_0402_1% <44> ICH_AC_SDIN0 ICH_AC_SDIN0 L4 C18
    R347 1 AZ_RST# ICH_AC_SDIN1 ACZ_SDIN0/GPIO42 AVSS_USB_10
    <34> ICH_RST_MDC# 2 <34> ICH_AC_SDIN1 J2 ACZ_SDIN1/GPIO43 AVSS_USB_11 C19

    AC97
    33_0402_1% ICH_AC_SDIN2 J4 C20
    R348 1 ACZ_SDIN2/GPIO44 AVSS_USB_12
    <44> ICH_RST_AUDIO# 2 M3 AC_SYNC/GPIO40 AVSS_USB_13 D11
    B 33_0402_1% AC_RST# L5 D21 B
    R349 1 AZ_SDATA_OUT AC_RST#/GPIO45 AVSS_USB_14
    <34> ICH_SDOUT_MDC 2 SB460 ONLY AVSS_USB_15 E11
    33_0402_1% E21
    R350 1 AVSS_USB_16
    <44> ICH_SDOUT_AUDIO 2 AVSS_USB_17 F11
    33_0402_1% R814 2 1 10K_0402_5% E23 F12
    IDE_HRESET# FANOUT0/GPIO3 AVSS_USB_18
    <27> IDE_HRESET# AC21 GPIO31 AVSS_USB_19 F14
    GPIO13 AD7 F16
    GPIO13 AVSS_USB_20
    AE7 DPSLP_OD#/GPIO37 AVSS_USB_21 F18
    PAD T12 AA4 F19
    R351 ICH_AC_SDIN2 EC_THERM# GPIO14 AVSS_USB_22
    2 1 @ 10K_0402_5% <7,33> EC_THERM# T4 TALERT#/GPIO10 AVSS_USB_23 F21
    R352 2 1 @ 10K_0402_5% ICH_AC_SDIN1 R353 2 1 0_0402_5% D4 G11
    <7,13> LDT_STOP# SLP#/LDT_STP# AVSS_USB_24
    R354 2 1 @ 10K_0402_5% ICH_AC_SDIN0 AB19 G21
    NC AVSS_USB_25
    AVSS_USB_26 H11
    AVSS_USB_27 H21
    AVSS_USB_28 J11
    R355 2 1 10K_0402_5% AZ_RST# TEST POINT TP602 FOR J12
    AVSS_USB_29
    R356 2 1 @ 10K_0402_5% AZ_SY NC SB460_FANOUT0 AVSS_USB_30 J14
    R357 2 1 @ 10K_0402_5% AZ_SDATA_OUT J16
    AVSS_USB_31
    R358 2 1 @ 10K_0402_5% AZ_BIT_CLK AVSS_USB_32 J18
    R648 2 1 10K_0402_5% AC_RST# J19
    AVSS_USB_33

    218S4RASA11GS SB460_BGA549
    ICH_BITCLK_MDC ICH_BITCLK_AUDIO

    1 1
    C945 C946

    @ 10P_0402_50V8K @ 10P_0402_50V8K
    A 2 2 A

    Modify 11/27
    Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 23 of 55
    5 4 3 2 1
    5 4 3 2 1

    PLACE SATA AC COUPLING IDE_D[0..15]


    <27> IDE_D[0..15]
    D CAPS CLOSE TO U16 IDE_A[0..2] D
    <27> IDE_A[0..2]
    U16B

    SATA_STX_C_DRX_P0 SATA@ 0.01U_0402_16V7K 2 C446 SATA_STX_DRX_P0


    <27> SATA_STX_C_DRX_P0
    SATA_STX_C_DRX_N0 1
    1
    2 C447 SATA_STX_DRX_N0
    AH21
    AJ21
    SATA_TX0+ SB460 AB29 IDE_IOR DY
    <27> SATA_STX_C_DRX_N0 SATA_TX0- PIDE_IORDY IDE_IORDY <27>
    SATA@ 0.01U_0402_16V7K Part 2 of 4 AA28 IDE_IRQ IDE_IRQ <27>
    SATA_DTX_C_SRX_N0 SATA@ 0.01U_0402_16V7K SATA_DTX_SRX_N0 PIDE_IRQ IDE_A0
    <27> SATA_DTX_C_SRX_N0 1 2 C448 AH20 SATA_RX0- PIDE_A0 AA29
    SATA_DTX_C_SRX_P0 1 2 C449 SATA_DTX_SRX_P0 AJ20 AB27 IDE_A1
    <27> SATA_DTX_C_SRX_P0 SATA_RX0+ PIDE_A1
    SATA@ 0.01U_0402_16V7K Y28 IDE_A2
    PIDE_A2 IDE_DACK#
    AH18 SATA_TX1+ PIDE_DACK# AB28 IDE_DACK# <26,27>
    AJ18 AC27 IDE_DREQ IDE_DREQ <27>
    SATA_TX1- PIDE_DRQ IDE_IOR#
    PIDE_IOR# AC29 IDE_IOR# <27>
    AH17 AC28 IDE_IOW# IDE_IOW# <27>
    SATA_RX1- PIDE_IOW# IDE_CS1#
    AJ17 SATA_RX1+ PIDE_CS1# W28 IDE_CS1# <27>
    W27 IDE_CS3#
    PIDE_CS3# IDE_CS3# <27>
    AH13 SATA_TX2+
    AH14 AD28 IDE_D0
    SATA_TX2- PIDE_D0 IDE_D1
    PIDE_D1 AD26
    AH16 AE29 IDE_D2
    SATA_RX2- PIDE_D2

    ATA 66/100
    SERIAL ATA
    AJ16 AF27 IDE_D3
    SATA_RX2+ PIDE_D3 IDE_D4
    PLACE SATA_CAL PIDE_D4 AG29
    AJ11 AH28 IDE_D5
    RES & CAP VERY AH11
    SATA_TX3+ PIDE_D5
    AJ28 IDE_D6
    +1.8VS PLLVDD_ATA SATA_TX3- PIDE_D6
    CLOSE TO BALL PIDE_D7 AJ27 IDE_D7
    AH12 AH27 IDE_D8
    L23
    OF U16 SATA_RX3- PIDE_D8 IDE_D9
    AJ13 SATA_RX3+ PIDE_D9 AG27
    1 2 SATA@ AG28 IDE_D10
    MBK2012121YZF_0805 R360 2 1K_0402_1% SATA_CAL PIDE_D10 IDE_D11
    1 1 1 AF12 SATA_CAL PIDE_D11 AF28
    1
    1U_0402_6.3V4Z

    1U_0402_6.3V4Z

    C450 C451 AF29 IDE_D12


    R778 C452 SATA_X1 PIDE_D12 IDE_D13
    C650 CLOSE TO THE 1 2 AD16 SATA_X1 PIDE_D13 AE28
    C
    BALL OF U600 0_0402_5% @2.2U_0603_6.3V6K AD25 IDE_D14 C
    SATA@ 2 2 SATA_X2 PIDE_D14 IDE_D15
    SATA@ SATA@ PATA@ AD18 AD29
    SATA_X2 PIDE_D15
    2

    <33> SATA_LED# SATA_LED# R361 2 1 0_0402_5% AC12


    SATA@ SATA_ACT#

    +3VS 1 2 PLLVDD_ATA AD14 PLLVDD_SATA_1


    R362 4.7K_0402_5% AJ10 J3
    +1.8VS XTLVDD_ATA PLLVDD_SATA_2 NC
    C649 CLOSE TO THE NC J6
    BALL OF U600 XTLVDD_ATA AC16 XTLVDD_SATA NC G3

    SPI ROM
    L61 1 2 G2
    MBK2012121YZF_0805 NC
    1 NOTE: AVDD_SATA AE14 AVDD_SATA_1 NC G6
    1

    SATA@ C453 AE16


    R779 AVDD_SATA_2
    R360 IS 1K 1% FOR 25MHz AE18 AVDD_SATA_3 NC C23
    0_0402_5% 1U_0402_6.3V4Z AE19 G5
    2 SATA@ XTAL, 4.99K 1% FOR 100MHz AF19
    AVDD_SATA_4 NC
    PATA@ AVDD_SATA_5
    INTERNAL CLOCK AF21 M4
    2

    AVDD_SATA_6 NC
    AG22 AVDD_SATA_7 NC T3
    AG23 AVDD_SATA_8 NC V4
    +1.8VS AVDD_SATA AH22
    L62 SATA@ AVDD_SATA_9
    AH23 AVDD_SATA_10 NC N3
    1 2 SATA@0.1U_0402_16V4Z AJ12 P2
    KC FBM-L11-201209-221LMAT_0805 1 AVDD_SATA_11 NC
    1 1 1 1 AJ14 W4

    SERIAL ATA POWER


    AVDD_SATA_12 NC
    1

    C454 C455 C456 C457 C458 AJ19


    R780 AVDD_SATA_13
    AJ22 AVDD_SATA_14 NC P5
    22U_0805_6.3V6M 1U_0402_6.3V4Z 0_0402_5% AJ23 P7
    SATA@ 2 2 2 2 2 SATA@ AVDD_SATA_15 NC
    PATA@ NC P8
    0.1U_0402_16V4Z 0.1U_0402_16V4Z AB14 T8
    2

    SATA@ SATA@ AVSS_SATA_1 NC


    AB16 AVSS_SATA_2 NC T7

    HW MONITOR
    AB18 AVSS_SATA_3
    AC14 AVSS_SATA_4 NC V5
    B 1 R781 2 AC18 L7 B
    AVSS_SATA_5 NC
    AC19 AVSS_SATA_6 NC M8
    PATA@ 0_0402_5% AD12 V6
    SATA_X1 C459 1 27P_0402_50V8J AVSS_SATA_7 NC
    2 AD19 AVSS_SATA_8 NC M6
    SATA@ AD21 P4
    AVSS_SATA_9 NC
    1

    R363 AE12 M7
    Y3 AVSS_SATA_10 NC
    AE21 AVSS_SATA_11 NC V7
    10M_0603_5% 25MHZ_20PF_6X25000017 AF11
    SATA@ SATA@ AVSS_SATA_12
    AF14
    2

    AVSS_SATA_13
    AF16
    2

    SATA_X2 C460 1 AVSS_SATA_14


    2 AF18 AVSS_SATA_15 NC N1
    AG11 AVSS_SATA_16
    27P_0402_50V8J AG12 M1
    SATA@ AVSS_SATA_17 NC
    AG13 AVSS_SATA_18
    AG14 AVSS_SATA_19
    VCC_SB=1.2V WHEN SB600 AG16 AVSS_SATA_20
    AG17
    VCC_SB 1.8V WHEN SB460 AG18
    AVSS_SATA_21
    AVSS_SATA_22
    AG19 AVSS_SATA_23
    AG20 AVSS_SATA_24
    AG21 AVSS_SATA_25
    AH10 AVSS_SATA_26
    AH19 AVSS_SATA_27

    218S4RASA11GS SB460_BGA549

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 24 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VS U16C

    1
    A25
    A28
    VDDQ_1 SB460 VSS_1 A1
    A20
    D VDDQ_2 VSS_2 D
    1 1 1 1 1 1 C29 VDDQ_3 Part 3 of 4 VSS_3 A21
    + C461 C462 C463 C464 C465 C466 C467 D24 A29
    VDDQ_4 VSS_4
    L9 VDDQ_5 VSS_5 B1
    220U_D2_4VM L21 B7
    2 2 2 2 2 2 2 VDDQ_6 VSS_6
    M5 VDDQ_7 VSS_7 B25
    1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z P3 C21
    1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VDDQ_8 VSS_8
    P9 VDDQ_9 VSS_9 C22
    T5 VDDQ_10 VSS_10 C24
    V9 VDDQ_11 VSS_11 D6
    W2 VDDQ_12 VSS_12 E24
    1 1 1 1 W6 VDDQ_13 VSS_13 F2
    C468 C469 C470 C471 W21 F23
    VDDQ_14 VSS_14
    W29 VDDQ_15 VSS_15 G1
    0.1U_0402_16V4Z 0.1U_0402_16V4Z AA12 J1
    2 2 2 2 VDDQ_16 VSS_16
    AA16 VDDQ_17 VSS_17 J8
    0.1U_0402_16V4Z AA19 L6
    0.1U_0402_16V4Z VDDQ_18 VSS_18
    AC4 VDDQ_19 VSS_19 L8
    AC23 VDDQ_20 VSS_20 M9
    AD27 VDDQ_21 VSS_21 M12
    AE1 VDDQ_22 VSS_22 M15
    AE9 VDDQ_23 VSS_23 M18
    AE23 VDDQ_24 VSS_24 N13
    AH29 VDDQ_25 VSS_25 N17
    AJ2 VDDQ_26 VSS_26 P1
    +1.8VS AJ6 P6
    VCC_SB=1.8V WHEN SB460 AJ26
    VDDQ_27
    VDDQ_28
    VSS_27
    VSS_28 P21
    VSS_29 R12
    M13 VDD_1 VSS_30 R15
    1 1 1 1 1 M17 VDD_2 VSS_31 R18
    C473 C474 C475 C476 N12 T6
    C C472 VDD_3 VSS_32 C
    N15 VDD_4 VSS_33 T9
    22U_0805_6.3V6M 1U_0402_6.3V4Z N18 U13
    2 2 2 2 2 VDD_5 VSS_34
    R13 VDD_6 VSS_35 U17
    1U_0402_6.3V4Z 1U_0402_6.3V4Z R17 V3
    1U_0402_6.3V4Z VDD_7 VSS_36
    U12 VDD_8 VSS_37 V8
    U15 VDD_9 VSS_38 V12
    +3VALW U18 V15
    VDD_10 VSS_39
    V13 VDD_11 VSS_40 V18
    V17 VDD_12 VSS_41 V21
    1 1 1 VSS_42 W1
    C477 C478 C479 A2 W9
    S5_3.3V_1 VSS_43
    A7 S5_3.3V_2 VSS_44 Y29
    22U_0805_6.3V6M

    POWER
    F1 S5_3.3V_3 VSS_45 AA11
    2 2 2
    J5 S5_3.3V_4 VSS_46 AA14
    0.1U_0402_16V4Z J7 AA18
    +1.8VALW +USB_PHY_18 0.1U_0402_16V4Z S5_3.3V_5 VSS_47
    K1 S5_3.3V_6 VSS_48 AC6
    VSS_49 AC24
    1 2 G4 S5_1.8V_1 VSS_50 AD9
    R815 0_0805_5% H1 AD23
    S5_1.8V_2 VSS_51
    1 1 1 1 1 H2 S5_1.8V_3 VSS_52 AE3
    C480 C481 C482 C483 C484 H3 AE27
    S5_1.8V_4 VSS_53
    VSS_54 AG6
    22U_0805_6.3V6M A18 AJ1
    2 2 2 2 2 USB_PHY_1.8V_1 VSS_55
    A19 USB_PHY_1.8V_2 VSS_56 AJ25
    0.1U_0402_16V4Z 0.1U_0402_16V4Z B19 AJ29
    0.1U_0402_16V4Z 0.1U_0402_16V4Z USB_PHY_1.8V_3 VSS_57
    B20 USB_PHY_1.8V_4
    B21
    CPU_PWR=1.2V WHEN SB460 USB_PHY_1.8V_5
    PCIE_VSS_1 D27
    PCIE_VSS_2 D28
    R364 +1.2V_HT AA27 D29
    B 1K_0402_5% CPU_PWR PCIE_VSS_3 B
    PCIE_VSS_4 F26
    +5VS 1 2 V5_VREF AE11 G23
    V5_VREF PCIE_VSS_5
    PCIE_VSS_6 G24
    A24 AVDDCK PCIE_VSS_7 G25
    D4 H27
    CH751H-40_SC76 PCIE_VSS_8
    A22 NC PCIE_VSS_9 J23
    +3VS 2 1 2 2 PCIE_VSS_10 J26
    C485 C486 B22 J28
    L24 AVSSCK PCIE_VSS_11
    PCIE_VSS_12 K27
    +1.8VS 1 2 0.1U_0402_16V4Z V29 L22
    MBK1608800YZF_0805 1 1 PCIE_VSS_42 PCIE_VSS_13
    V28 PCIE_VSS_41 PCIE_VSS_14 L23
    V27 PCIE_VSS_40 PCIE_VSS_15 L24
    1 1U_0402_6.3V4Z V26 L27
    PCIE_VSS_39 PCIE_VSS_16
    V25 PCIE_VSS_38 PCIE_VSS_17 L28
    C487 V24 M21
    2.2U_0603_6.3V6K PCIE_VSS_37 PCIE_VSS_18
    V23 PCIE_VSS_36 PCIE_VSS_19 M24
    2
    V22 PCIE_VSS_35 PCIE_VSS_20 M27
    U27 PCIE_VSS_34 PCIE_VSS_21 N27
    T29 PCIE_VSS_33 PCIE_VSS_22 N28
    T28 PCIE_VSS_32 PCIE_VSS_23 P22
    T27 PCIE_VSS_31 PCIE_VSS_24 P23
    T24 PCIE_VSS_30 PCIE_VSS_25 P24
    T21 PCIE_VSS_29 PCIE_VSS_26 P25
    P27 PCIE_VSS_28 PCIE_VSS_27 P26

    218S4RASA11GS SB460_BGA549

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 25 of 55
    5 4 3 2 1
    5 4 3 2 1

    REQUIRED STRAPS
    NOTE: R365 PU RESISTOR FOR
    SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT, SB460 ONLY
    RTC_IRQ# IS REQUIRED FOR SB460
    15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
    TO KEEP THE INPUT FROM FLOATING.
    NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE +3VALW +3VS +3VS +3VS +3VS
    REQUIRED

    1
    D +3VS +3VALW +3VS +3VS +3VS +3VS R365 R366 R367 R368 R369 D
    10K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

    2
    R649 <22> RTC_IRQ#
    @10K_0402_5% <22> SB_SPDIFO

    1
    <22> CLK_PCI_MINI_R
    R370 R371 R372 R373 R374 <22> CLK_PCI_PCM_R
    2

    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% <22> CLK_PCI_SIO_R


    @ @ <22,33,41> LPC_FRAME#
    <23> AC_SDATA_OUT
    2

    1
    <22> RTC_CLK
    <22> CLK_PCI_1394_R R375 R376 R377 R378 R379 R380
    <22> PCI_CLK6 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    @ @ @ @
    <22> CLK_PCI_LAN_R

    2
    <22> CLK_PCI_LPC_R
    1

    1
    1

    R381 R382 R383


    R650 10K_0402_5% 10K_0402_5% 10K_0402_5% ACPWRON SPDIF_OUT PCI_CLK2 PCI_CLK3 PCI_CLK5 LFRAME#
    10K_0402_5% @
    2

    2
    RTC_IRQ# SB_SPDIFO CLK_PCI_MINICLK_PCI_PCM CLK_PCI_SIO LPC_FRAME#
    2

    PULL MANUAL SIO 24MHz XTAL MODE USB PHY PCIE_CM_SET ENABLE
    SB600 SB460 HIGH PWR ON POWERDOWN LOW THERMTRIP#
    N OT
    C SUPPORTED DISABLE C

    PCI_CLK4 PCI_CLK0 PCI_CLK1 PCI_CLK0 PCI_CLK1 DEFA ULT DEFA ULT DEFA ULT DEFA ULT
    AC_SDATA_OUT RTC_CLK PCI_CLK6
    CLK_PCI_1394
    CLK_PCI_LAN CLK_PCI_LPC CLK_PCI_LAN CLK_PCI_LPC PULL AUTO SIO 48MHz 48MHZ OSC USB PHY PCIE_CM_SET DISABLE
    PULL LOW PWR MODE POWERDOWN HIGH THERMTRIP#
    HIGH USE DEBUG INTERNAL USE INT. CPU IF=K8 ROM TYPE: ROM TYPE: ON ENABLE
    DEFA ULT DEFA ULT
    RTC PLL48
    STRAPS H, H = PCI ROM H, H = PCI ROM
    DEFA ULT
    DEFA ULT H, L = SPI ROM H, L = LPC I ROM
    L, H = LPC ROM DEFA ULT L, H = LPC II ROM DEFA ULT
    IGNORE DEBUG EXTERNAL USE EXT. CPU IF=P4
    PULL RTC 48MHZ L, L = FWH ROM L, L = FWH ROM OVERLAP COMMON PADS WHERE
    LOW STRAPS
    NOTE: FOR SB460, PCICLK[8:7] ARE
    DEFA ULT DEFA ULT CONNECTED TO SUBSTRATE POSSIBLE FOR DUAL-OP RESISTORS.
    BALLS PCICLK[1:0]

    DEBUG STRAPS SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]


    +3VS +3VS +3VS +3VS +3VS +3VS +3VS
    1

    R384 R385 R386 R387 R388 R389 R390


    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    B @ @ B
    2

    <24,27> IDE_DACK#
    <22,31,36,37,40> PCI_AD28
    <22,31,36,37,40> PCI_AD27
    <22,31,36,37,40> PCI_AD26
    <22,31,36,37,40> PCI_AD25
    <22,31,36,37,40> PCI_AD24
    <22,31,36,37,40> PCI_AD23
    1

    2.2K IF USED FOR SB600.


    R393 R394 R395 R396 R397 R398 R399
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K IF USED FOR SB460.
    @ @ @ @ @ @ @
    2

    IDE_DACK# PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

    USE USE USE PCI USE ACPI USE IDE USE DEFAULT BOOTFAILTIMER
    PULL LONG LONG PLL BCLK PLL PCIE STRAPS DISABLED SB600 ONLY
    HIGH RESET RESET
    DEFA ULT DEFA ULT DEFA ULT DEFA ULT DEFA ULT DEFA ULT DEFA ULT

    NOTE: FOR
    PULL USE USE BYPASS BYPASS BYPASS IDE USE EEPROM BOOTFAILTIMER SB460,
    A A
    LOW SHORT SHORT PCI PLL ACPI PLL PCIE STRAPS ENABLED PCI_AD23 IS
    RESET RESET BCLK RESERVED

    SB460 ONLY SB600 ONLY Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number R ev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B

    www.laptopfix.vn
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 26 of 55
    5 4 3 2 1
    5 4 3 2 1

    HDD CONN
    IDE_D[0..15]
    <24> IDE_D[0..15]
    IDE_A[0..2]
    <24> IDE_A[0..2] +3VS

    C943
    D JP5 1 2 @ 0.1U_0402_16V4Z D
    IDE_RESET# 1 2
    IDE_D7 1 2 IDE_D8
    3 3 4 4

    5
    IDE_D6 5 6 IDE_D9 U60
    IDE_D5 5 6 IDE_D10 IDE_HRESET#
    7 8 1

    P
    7 8 <23> IDE_HRESET# IN1
    IDE_D4 9 10 IDE_D11 4 IDE_RESET#
    IDE_D3 9 10 IDE_D12 NB_RST# O
    11 11 12 12 <13,16,22,33,36,41> NB_RST# 2 IN2

    G
    IDE_D2 13 14 IDE_D13
    IDE_D1 13 14 IDE_D14 SN74AHC1G08DCKR_SC70
    15 16

    3
    +5VS IDE_D0 15 16 IDE_D15
    17 17 18 18 @
    19 19 20 20
    IDE_DREQ 21 22
    <24> IDE_DREQ 21 22
    IDE_IOW# 23 24
    <24> IDE_IOW# 23 24
    1

    IDE_IOR# 25 26
    <24> IDE_IOR# 25 26
    R402 ID E_IORDY 27 28 IDE_CSEL R403 1 2 470_0402_5%
    <24> IDE_IORDY 27 28
    100K_0402_5% IDE_DACK# 29 30 PATA@
    <24,26> IDE_DACK# 29 30
    IDE_IRQ 31 32 R833
    <24> IDE_IRQ 31 32
    IDE_A1 33 34 PDIAG# 1 2
    2

    IDE_A0 33 34 IDE_A2 33_0402_5%


    35 35 36 36
    IDE_CS1# 37 38 IDE_CS3#
    <24> IDE_CS1# 37 38 IDE_CS3# <24>
    <33> IDE_LED# IDE_LED# 39 40
    39 40
    +5VS 41 41 42 42 +5VS
    80mils 43 43 44 44 80mils
    1
    OCTEK_HDD-22SG1G_NR
    C489 + PATA@
    150U_D2_6.3VM
    @
    2 +5VS
    C C

    0.1U_0402_16V4Z

    1 1 1 1
    C493
    C490 C491 C492
    10U_0805_10V4Z
    2 2 2 2

    +5VS +3VS 1U_0603_10V4Z 1000P_0402_50V7K

    0.1U_0402_16V4Z 0.1U_0402_16V4Z

    1 1 1 1 1 1 1 1
    C498 C499 C500 C501
    C494
    C495 C496 C497
    10U_0805_10V4Z 10U_0805_10V4Z
    2 2 2 2 2 2 2 2

    0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K


    CDROM CONN
    JP6
    1 1 2 2
    3 3 4 4
    IDE_RESET# 5 6 IDE_D8
    IDE_D7 5 6 IDE_D9
    7 7 8 8
    B IDE_D6 IDE_D10 B
    9 9 10 10
    IDE_D5 11 12 IDE_D11
    SATA HDD Conn. IDE_D4
    IDE_D3
    13
    15
    11
    13
    12
    14 14
    16
    IDE_D12
    IDE_D13
    JP7 IDE_D2 15 16 IDE_D14
    17 17 18 18
    IDE_D1 19 20 IDE_D15
    IDE_D0 19 20 IDE_DREQ
    1 GND 21 21 22 22
    SATA_STX_C_DRX_P0 2 23 24 IDE_IOR#
    <24> SATA_STX_C_DRX_P0 SATA_STX_C_DRX_N0 HTX+ IDE_IOW# 23 24
    <24> SATA_STX_C_DRX_N0 3 HTX- 25 25 26 26
    4 ID E_IORDY 27 28 IDE_DACK#
    SATA_DTX_C_SRX_N0 GND IDE_IRQ 27 28
    <24> SATA_DTX_C_SRX_N0 5 HRX- 29 29 30 30
    SATA_DTX_C_SRX_P0 6 IDE_A1 31 32 PDIAG# 1 2
    <24> SATA_DTX_C_SRX_P0 HRX+ 31 32 +5VS
    7 IDE_A0 33 34 IDE_A2 R782
    GND IDE_CS1# 33 34 IDE_CS3# @ 100K_0402_5%
    35 35 36 36
    IDE_LED# 37 38
    37 38 +5VS
    +5VS 39 39 40 40 80mils
    +3VS 1 2 8 VCC3.3 41 41 42 42
    R816 0_0805_5% 9 2 1 43 44
    VCC3.3 +5VS 43 44
    10 R783 @ 470_0402_5% 45 46
    VCC3.3 SD_CSEL 45 46
    11 GND 2 1 47 47 48 48
    12 R405 SATA@470_0402_5% 49 50 1 2
    GND 49 50 +5VS
    13 R406
    GND OCTEK_CDR-50JL1G @ 100K_0402_5%
    +5VS 1 2 14 VCC5
    R817 0_0805_5% 15 VCC5
    16 VCC5
    17 GND IDE_CSEL
    18 RESERVED
    19 Grounding for Master (When use SATA HDD)
    GND
    A 20 VCC12 Open or High for Slaver (Normal) A
    Modify 11/07 for EMI 21 VCC12
    22 VCC12

    SATA@ OCTEK_SAT-22SG1G_NR
    (NEW) Compal Electronics, Inc.
    Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401412
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 27 of 55
    5 4 3 2 1
    A B C D E

    D8 D9 D10
    W=40mils
    @ @ @ +5VS +R_CRT_VCC +CRT_VCC
    DAN217_SC59 DAN217_SC59 DAN217_SC59
    D7 F1 W=40mils

    1
    2 1 1 2

    RB411D_SOT23 1.1A_6VDC_FUSE
    1
    1 1

    CRT Connector C503

    3
    0.1U_0402_16V4Z
    2
    +3VS

    VGA:8P_0402_50V8K
    UMA:10P_0402_50V8J
    JP8
    VGA_CRT_R 1 2 CRT_R_L 6
    <16> VGA_CRT_R
    L25 11
    FCM2012C-800_0805 1
    VGA_CRT_G 1 2 CRT_G_L 7
    <16> VGA_CRT_G
    L26 12
    FCM2012C-800_0805 2
    VGA_CRT_B 1 2 CRT_B_L 8
    <16> VGA_CRT_B
    L27 13
    FCM2012C-800_0805 3

    1
    1 1 1 1 1 1 DDC_MD2 9
    R407 R408 R409 C504 C505 C506
    Close to Connector C507 C508 C509
    14
    4
    Route 8mil width (for 37.5ohm) 75_0402_1% 75_0402_1% 75_0402_1% 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 10
    2 2 2 2 2 2
    15

    2
    8P_0402_50V8K 1 5
    C510
    SUYIN_070549FR015S208CR
    +CRT_VCC CRT_HSYNC_L
    1 2
    L28 MBK1608301YZF_0603 2
    1 2 2 1 100P_0402_50V8J DSUB_12
    C511 0.1U_0402_16V4Z R410 10K_0402_5% 1 2 CRT_VSYNC_L
    L29 MBK1608301YZF_0603 1

    1
    U20
    2 2
    1 1

    OE#
    CRT_HSYNC 2 4 CRT_HSYNC_B C514
    <16> CRT_HSYNC A Y C513 C512 2

    G
    10P_0402_50V8K 10P_0402_50V8K 68P_0402_50V8K DSUB_15
    SN74AHCT1G125DCKR_SC70-5 2 2

    3
    +CRT_VCC 1

    Place closed to chipset C515


    1 2 68P_0402_50V8K
    C516 0.1U_0402_16V4Z 2

    1
    U21

    OE#
    CRT_VSYNC 2 4 CRT_VSYNC_B
    <16> CRT_VSYNC A Y

    G
    SN74AHCT1G125DCKR_SC70-5

    3
    Place closed to chipset
    +CRT_VCC

    +3VS

    1
    R411
    4.7K_0402_5% R412

    2
    G
    D11 D12 D13 4.7K_0402_5%
    3 @ @ @ DSUB_12 3
    1 3
    DAN217_SC59 DAN217_SC59 DAN217_SC59 VGA_CRT_DAT <16>

    S
    Q7
    1

    2
    2N7002_SOT23

    G
    DSUB_15 1 3 VGA_CRT_CLK <16>

    S
    Q8
    2N7002_SOT23
    TV-OUT Conn.
    2

    3
    +3VS

    C517 1 2 22P_0402_50V8J JP9


    VGA_TV_Y 1 2 TVOUT@ 3
    <16> VGA_TV_Y
    L30 MBK1608301YZF_0603 TV_CRMA_L 6
    C518 1 2TVOUT@ 22P_0402_50V8J TV_COMPS_L 7
    VGA_TV_C 1 2 TVOUT@ 5
    <16> VGA_TV_C
    L31 MBK1608301YZF_0603 2
    C519 1 2TVOUT@ 22P_0402_50V8J TV_LUMA_L 4
    VGA_TV_COMP 1 2 TVOUT@ 1
    <16> VGA_TV_COMP
    L56 MBK1608301YZF_0603 8
    TVOUT@ 9
    1

    1 1 1 2005/09/22 1 1 1
    R413 R414 R415 C520 C521 C522 C523 C524 C525 SUYIN_030107FR007SX08FU
    TVOUT@
    75_0402_1% 75_0402_1% 150P_0402_50V8J 150P_0402_50V8J 150P_0402_50V8J 150P_0402_50V8J
    TVOUT@ TVOUT@ 2 2
    150P_0402_50V8J 2 TVOUT@ 2 TVOUT@ 2 TVOUT@ 2 TVOUT@ (ECQ60)
    2

    TVOUT@
    1 2
    75_0402_1% 150P_0402_50V8J R818 TVOUT@ 0_0805_5%
    4 TVOUT@ TVOUT@ VGA:82P_0402_50V8J 4

    UMA:6P_0402_50V8J Modify 11/07 for EMI


    Close to Connector
    Route 8mil width (for 37.5ohm)
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 28 of 55
    A B C D E
    5 4 3 2 1

    LCD POWER CIRCUIT

    D D

    07/07/'05
    +INVPWR_B+

    L45 2 1 B+
    KC FBM-L11-201209-221LMAT_0805
    +LCDVDD +5VALW
    L46 2 1
    Modify 11/22 KC FBM-L11-201209-221LMAT_0805
    1

    2
    1
    R416 C790
    R417 +3VS
    360_0402_5%
    68P_0402_50V8K
    100K_0402_5% 2
    W=60mils
    1 2

    1
    R418

    3
    D S
    G
    Q9 2 2 1 2 Q10
    2N7002_SOT23 G SI2301BDS_SOT23
    S 1
    3

    1K_0402_5% C526 +LCDVDD


    0.047U_0402_16V4Z
    D W=60mils
    7.3
    LCD/PANEL BD. Conn.

    1
    +LCDVDD
    2
    1

    D
    1 1
    ENVDD 2 C893 C894
    <17> ENVDD
    G JP10
    1

    S 4.7U_0805_10V4Z 0.1U_0402_16V4Z +INVPWR_B+ DAC_BRIG


    DAC_BRIG <33>
    3

    R419 Q11 2 2 40 20 INVT_PWM


    39 19 INVT_PWM <33>
    C 10K_0402_5% KC FBM-L11-201209-221LMAT_0805 DISPOFF# C
    BSS138_SOT23 L72 2 38 18 L73 2
    +3VS 1 37 17 1 +LCDVDD
    <16> I2C_CLK I2C_CLK KC FBM-L11-201209-221LMAT_0805
    (60 MIL)
    2

    I2C_DAT 36 16
    <16> I2C_DAT 35 15 Modify 11/07 for EMI
    Modify 11/07 for EMI TZOUT0- 34 14 VGA_LVDSA0-
    <17> VGA_LVDSB0- 33 13 VGA_LVDSA0- <17>
    TZOUT0+ VGA_LVDSA0+ VGA_LVDSA0+ <17>
    <17> VGA_LVDSB0+ 32 12
    +3VS +3VS TZOUT1+ 31 11 VGA_LVDSA1-
    <17> VGA_LVDSB1+ 30 10 VGA_LVDSA1- <17>
    TZOUT1- VGA_LVDSA1+ VGA_LVDSA1+ <17>
    <17> VGA_LVDSB1- 29 9
    28 8

    1
    1 TZOUT2+ VGA_LVDSA2+ VGA_LVDSA2+ <17>
    <17> VGA_LVDSB2+ 27 7
    R420 TZOUT2- VGA_LVDSA2- VGA_LVDSA2- <17>
    <17> VGA_LVDSB2- 26 6
    C529
    0.1U_0402_16V4Z 4.7K_0402_5% TZCLK- 25 5 VGA_LVDSAC-
    2 <17> VGA_LVDSBC- 24 4 VGA_LVDSAC- <17>
    D14 TZCLK+ VGA_LVDSAC+ VGA_LVDSAC+ <17>
    <17> VGA_LVDSBC+

    2
    BKOFF# 23 3
    <33> BKOFF# 1 2 RB751V_SOD323 DISPOFF#
    22 2
    21 1
    ACES_88107-4000G

    INVT_PWM
    (SAME AS ACES_87216-4016)
    1

    1
    D15
    C530
    @ 1N4148_SOT23 @ 1U_0402_6.3V4Z
    2
    2

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 29 of 55
    5 4 3 2 1
    5 4 3 2 1

    D D

    H5 H30 H20
    H_C177D144 H_C177D144 H_C163D163N

    1 @ @ @

    1
    H1
    H_S394D138
    H2
    H_S394D138
    H4
    H_S394D138
    H21
    H_S394D138
    H22
    H_S394D138
    DVI-D Connector D32
    +DVI_VCC DVI@ RB411D_SOT23
    JP11
    @ @ @ @ @ 17 14 1 2 +5VS
    <17> DVI_TX0-
    1

    1
    TMDS_DATA0- +5V
    <17> DVI_TX0+ 18 TMDS_DATA0+ W=40mils 1

    9 C531
    <17> DVI_TX1- TMDS_DATA1-
    10 DVI@ 0.1U_0402_16V4Z
    <17> DVI_TX1+ TMDS_DATA1+ 2
    H23 H14 H15 H28 H7 1
    <17> DVI_TX2- TMDS_DATA2-
    H_S394D138 H_S394D138 H_S394D138 H_S394D138 H_C236D165 2 6 DVI_SCLK
    <17> DVI_TX2+ TMDS_DATA2+ DDC_CLOCK
    12 TMDS_DATA3-
    @ @ @ @ @ 13 7 DVI_SDATA
    1

    1
    TMDS_DATA3+ DDC_DATA
    4 TMDS_DATA4-
    5 TMDS_DATA4+
    C C
    H8 H9 H10 H3 H6 20
    H_C236D165 H_C236D165 H_C236D165 H_C236D161 H_C236D161 TMDS_DATA5-
    21 TMDS_DATA5+ Hot Plug Detect 16

    @ @ @ @ @ 23
    <17> DVI_TXC+
    1

    1
    TMDS_Clock+
    <17> DVI_TXC- 24 TMDS_Clock-

    TMDS_DATA2/4 shield 3
    TMDS_DATA1/3 shield 11
    H29 H31 H11 H12 H17 19
    H_C236D161 H_S315D118 H_O134X118D55X39 H_O134X118D55X39 H_O134X118D55X39 TMDS_DATA0/5 shield
    TMDS_Clock shield 22

    @ @ @ @ @
    1

    1
    8 Analog VSYNC GND 15

    H18 H16 H19 H13 H24


    H_O134X118D55X39 H_C276D118 H_C276D118 H_S354D138 H_S354D138 DVI@ SUYIN_070939FR024S531PL

    R423
    @ @ @ @ @ <17> VGA_DVI_DET VGA_DVI_DET 1 2
    1

    DVI@ 20K_0402_5%

    1
    R424
    D17 DVI@
    H25 H32 H33 H34 @ SKS10-04AT_TSMA 100K_0402_5%
    H_S354D138 H_S315D138 H_C315D236 H_O217X157D217X157N

    2
    B @ @ @ @ (HDQ70) B
    1

    +DVI_VCC

    +3VS

    1
    R421 DVI@
    FD2 FD1 FD3 FD5 FD4 FD6 4.7K_0402_5% R422
    DVI@

    2
    G
    @ @ @ @ @ @ 4.7K_0402_5%
    1

    DVI_SDATA 1 3
    VGA_DVI_DAT <17>

    S
    Q12

    2
    2N7002_SOT23

    G
    CF20 CF14 CF18 CF21 CF7 CF10 CF12 CF4 CF6 CF15 DVI@
    DVI_SCLK 1 3 VGA_DVI_CLK <17>

    S
    @ @ @ @ @ @ @ @ @ @ Q13
    1

    2N7002_SOT23
    DVI@

    CF17 CF16 CF19 CF13 CF9 CF1 CF2 CF3 CF5 CF11

    A A
    @ @ @ @ @ @ @ @ @ @
    1

    CF8 CF22 CF23 CF24

    @ @ @ @
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1

    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 30 of 55
    5 4 3 2 1
    5 4 3 2 1

    PCI_AD[0..31]
    <22,26,36,37,40> PCI_AD[0..31]
    R425 1 2 3.6K_0402_5% +3VALW PIN 8100CL(10/100 LAN) 8110SBL(10/100/1000 LAN)
    U22 U23
    PCI_AD0 104 108 LAN_EEDO 4 5 1 RSET 5.6K 2.49K
    PCI_AD1 AD0 EEDO LAN_EEDI DO GND
    103 AD1 AUX/EEDI 109 3 DI NC 6
    PCI_AD2 102 111 LAN_EECLK 2 7 C895 0.1U_0402_16V4Z
    PCI_AD3 AD2 EESK LAN_EECS SK NC
    D 98 AD3 EECS 106 1 CS VCC 8 +3VALW D
    PCI_AD4 2
    97 AD4 BOM structure 8100CL(10/100 LAN) 8110SBL(10/100/1000 LAN)
    PCI_AD5 96 117 ACTIVITY# AT93C46-10SU-2.7_SO8
    PCI_AD6 AD5 LED0 LINK_100# LAN_ACTIVITY# <32>
    95 AD6 LED1 115 1 2 LAN_LINK# <32> 8100C@ Stuff No_Stuff
    PCI_AD7 93 114 R426 0_0402_5%
    PCI_AD8 AD7 LED2 LINK_1000#
    90 AD8 NC/LED3 113 2 1 8110S@ No_Stuff Stuff
    PCI_AD9 89 R427 @ 0_0402_5%
    PCI_AD10 AD9 LAN_MDI0+
    87 AD10 TXD+/MDI0+ 1 LAN_MIDI0+ <32> @ No_Stuff No_Stuff
    PCI_AD11 86 2 LAN_MDI0-
    AD11 TXD-/MDI0- LAN_MIDI0- <32>
    PCI_AD12 85 5 LAN_MDI1+
    AD12 RXIN+/MDI1+ LAN_MIDI1+ <32>
    PCI_AD13 83 6 LAN_MDI1-
    AD13 RXIN-/MDI1- LAN_MIDI1- <32>
    PCI_AD14 82
    PCI_AD15 AD14 LAN_MDI2+
    79 AD15 NC/MDI2+ 14 LAN_MIDI2+ <32>
    PCI_AD16 59 15 LAN_MDI2-
    AD16 NC/MDI2- LAN_MIDI2- <32>
    PCI_AD17 58 18 LAN_MDI3+
    AD17 NC/MDI3+ LAN_MIDI3+ <32>
    PCI_AD18 57 19 LAN_MDI3-
    AD18 NC/MDI3- LAN_MIDI3- <32>
    PCI_AD19 55
    PCI_AD20 AD19 LAN_X1
    53 AD20 X1 121
    PCI_AD21 50 122 LAN_X2
    PCI_AD22 AD21 X2
    49 AD22

    PCI I/F
    PCI_AD23 47 105 R428 1 2 1K_0402_5%
    PCI_AD24 AD23 LWAKE R429 +3VS
    43 AD24 ISOLATE# 23 1 2 15K_0402_5%
    PCI_AD25 42 127 1 2 8100C@ 5.6K_0603_1% RSET 5.6K for 8100CL
    PCI_AD26 AD25 RTSET R784
    40 72
    PCI_AD27 39
    AD26 NC/SMBCLK
    74 1 2 8110S@ 2.49K_0603_1%
    2.49K for 8110S(B)
    PCI_AD28 AD27 NC/SMBDATA R431
    37 AD28
    PCI_AD29 36 88
    PCI_AD30 AD29 NC/M66EN
    PCI_AD31
    34 AD30 +LAN_AVDDH
    20mils
    33 AD31 NC/AVDDH 10 1 R432 2 +3VALW
    C 120 1 8110S@ 0_0805_5% C
    AVDDH
    <22,36,37,40> PCI_CBE#0 92 C/BE#0 1
    77 11 2 8110S@
    1 0_0402_5% C534 C896 C897 +3VALW +3VALW
    <22,36,37,40> PCI_CBE#1 C/BE#1 NC/HSDAC+
    60 123 R785 8110S@ 0.1U_0402_16V4Z 1U_0402_6.3V4Z
    <22,36,37,40> PCI_CBE#2 C/BE#2 NC/HG 2
    44 124 8110S@ 0.1U_0402_16V4Z
    <22,36,37,40> PCI_CBE#3 C/BE#3 NC/LG2 2
    2 1 8110S@
    PCI_AD17 1 2 LAN_IDSEL 46 2SB1197K_SOT23
    IDSEL

    3
    R434 100_0402_5% E

    3
    <22,36,37,40> PCI_PAR 76 PAR
    LAN I/F E
    +2.5V_LAN
    CTRL12 2 Q14 +1.2V_LAN
    61 9 CTRL25 2 Q15 B
    <22,36,37,40> PCI_FRAME# FRAME# NC/VSS B C
    63 13 2SB1197K_SOT23 40mils
    <22,36,37,40> PCI_IRDY#

    1
    IRDY# NC/VSS C
    <22,36,37,40> PCI_TRDY# 67

    1
    TRDY#
    <22,36,37,40> PCI_DEVSEL# 68 DEVSEL# Y4
    40mils
    <22,36,37,40> PCI_STOP# 69 STOP# NC/GND 22
    48 LAN_X1 1 2 LAN_X2 1 1 1
    NC/GND C536 C898
    <22,36,37,40> PCI_PERR# 70 PERR# NC/GND 62
    75 73 1 25MHZ_20P 1 C899
    <22,36,37> PCI_SERR# SERR# NC/GND
    112 22U_0805_6.3V6M 22U_0805_6.3V6M
    NC/GND C900 C540 2 8110S@ 2 2 0.1U_0402_16V4Z
    <22> PCI_REQ#3 30 REQ# NC/GND 118
    29 27P_0402_50V8J 27P_0402_50V8J 8110S@
    <22> PCI_GNT#3 GNT# 2 2

    <22> PCI_PIRQF# 25 INTA#


    8 CTRL25
    CTRL25
    <33> LAN_PME# 31 PME#
    125 CTRL12
    CTRL12
    <22,36,37,39,40> PCI_RST# 27 RST#
    VDD33 26 +3VALW
    CLK_PCI_LAN 28 41 1 1 1 1 1
    <22> CLK_PCI_LAN CLK VDD33
    PM_CLKRUN# 65 56
    B <22,36,41> PM_CLKRUN# CLKRUN# VDD33 C541 C901 C902 C903 C904 B
    VDD33 71
    84 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    VDD33 2 2 2 2 2
    VDD33 94
    VDD33 107
    4 +LAN_AVDDL R435 1 2 +3VALW
    GND/VSS 8100C@ 0_0805_5%
    17 GND/VSS 1 1 1 1 40mils
    128 GND/VSS
    3 C905 C906 C907 C908 8110S@ 0_0805_5%
    AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R436 1
    AVDDL 7 2 +2.5V_LAN
    2 2 2 2
    21 GND/VSSPST AVDDL 20
    CLK_PCI_LAN 38 16 +LAN_AVDDL25 1 2 +2.5V_LAN
    GND/VSSPST AVDDL R437
    51 GND/VSSPST 20mils
    1

    66 126 8110S@ 0_0402_5%


    GND/VSSPST VDD12 +LAN_DVDD R439 1
    81 GND/VSSPST VDD12 32 2 +1.2V_LAN
    R786 91 54 1 1 1 1 40mils 8110S@ 0_0805_5%
    @ 10_0402_5% GND/VSSPST VDD12
    101 GND/VSSPST VDD12 78
    119 99 C909 C551 C552 C910 8100C@ 0_0805_5%
    2

    GND/VSSPST VDD12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R440 1


    1 2 +2.5V_LAN
    2 2 2 2
    Power

    C911 35 24 +1.2V_LAN
    @ 18P_0402_50V8J GND NC/VDD12
    52 GND NC/VDD12 45 2 2 2 2 2
    2 C555 C912 C913 C914 C915
    80 GND NC/VDD12 64
    100 GND NC/VDD12 110
    116 8110S@ 0.1U_0402_16V4Z 8110S@ 0.1U_0402_16V4Z
    NC/VDD12 1 1 1 1 1
    8110S@ 0.1U_0402_16V4Z 8110S@ 0.1U_0402_16V4Z
    12 V_12P R441 1 2 +2.5V_LAN 8110S@ 0.1U_0402_16V4Z
    NC
    8110S@ RTL8110SBL_LQFP128
    20mils1 C560 R787 8100C@ 0_0402_5% +LAN_AVDDH
    A 1 2 A
    8110S@ 0_0402_5%
    0.1U_0402_16V4Z
    2
    RTL8110SBL change to Ver.D

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/07/29 Deciphered Date 2006/07/29 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 31 of 55
    5 4 3 2 1
    5 4 3 2 1

    LAN RTL8110SBL/RTL8100CL
    D D

    unpop when use RTL8100CL(10/100)

    1 1
    C916 C917

    8110S@ 0.01U_0402_16V7K 8110S@ 0.01U_0402_16V7K JP75


    2 2 +2.5V_LAN 24HST1041A-3(SP050002110) for RTL8110SBL(GbE) <31> LAN_ACTIVITY#
    LAN_ACTIVITY# 12 Amber LED-
    24ST0023-3(SP050005000) for RTL8100CL(10/100) +3VALW
    R788 2 1 300_0603_5% 11 Amber LED+
    24ST0023-3: Half port(TD[3:4], MX[3:4]) SHLD4 16

    1
    RJ45_MDI3- 8 PR4-
    1

    R446 R444 15
    8110S@ 49.9_0402_1% R448 8110S@ 0_0603_5% RJ45_MDI3+ SHLD3
    7 PR4+
    C R789 R447 8110S@ 49.9_0402_1% C
    8110S@ 49.9_0402_1% 8110S@ 49.9_0402_1% T3 RJ45_MDI1- 6

    2
    PR2-
    2

    1 24 RJ45_MDI2- 5
    LAN_MDI3- TCT1 MCT1 RJ45_MDI3- PR3-
    <31> LAN_MIDI3- 2 TD1+ MX1+ 23
    <31> LAN_MIDI3+ LAN_MDI3+ 3 22 RJ45_MDI3+ RJ45_MDI2+ 4
    TD1- MX1- PR3+
    4 21 RJ45_MDI1+ 3
    LAN_MDI2- TCT2 MCT2 RJ45_MDI2- PR2+
    <31> LAN_MIDI2- 5 TD2+ MX2+ 20
    <31> LAN_MIDI2+ LAN_MDI2+ 6 19 RJ45_MDI2+ RJ45_MDI0- 2
    TD2- MX2- PR1-
    SHLD2 14
    7 18 RJ45_MDI0+ 1
    LAN_MDI1- TCT3 MCT3 RJ45_MDI1- PR1+
    <31> LAN_MIDI1- 8 TD3+ MX3+ 17 SHLD1 13
    <31> LAN_MIDI1+ LAN_MDI1+ 9 16 RJ45_MDI1+ LAN_LINK# 10
    TD3- MX3- <31> LAN_LINK# Green LED-
    1 2 10 15 R450 2 1 300_0603_5% 9
    TCT4 MCT4 +3VALW Green LED+
    <31> LAN_MIDI0- LAN_MDI0- R449 8110S@ 0_0402_5% 11 14 RJ45_MDI0-
    LAN_MDI0+ TD4+ MX4+ RJ45_MDI0+ SUYIN_100073FR012S100ZL
    <31> LAN_MIDI0+ 12 TD4- MX4- 13
    HBL-50
    1

    R790 R791 R453 R454

    1
    49.9_0402_1% 49.9_0402_1% 8110S@ 0.01U_0402_16V7K 0.5u_GST5009
    49.9_0402_1% 49.9_0402_1% 8110S@
    R792 R793 RJ45_GND 1 2 LANGND
    2

    1 1 1 1 75_0402_1% 75_0402_1% 1 1
    C564 C565 C919 C567 C918

    2
    C5701 C5711 1000P_1206_2KV7K C920 C921
    0.01U_0402_16V7K 4.7U_0805_10V4Z
    2 2 2 2 8110S@ 2 2
    B 0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K B
    2 2 8110S@ 0.01U_0402_16V7K 0.1U_0402_16V4Z

    RJ45_MDI3+ R794 1 2 8100C@ 0_0402_5%


    RJ45_MDI3- R795 1 2 8100C@ 0_0402_5%
    RJ45_MDI2+ R459 1 2 8100C@ 0_0402_5%
    RJ45_MDI2- R460 1 2 8100C@ 0_0402_5%
    1

    reseved for RTL8100CL(10/100)


    R461 R796
    75_0402_1% 75_0402_1%
    2

    RJ45_GND

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/07/29 Deciphered Date 2006/07/29 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 32 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VALW
    KBA[0..19]
    KBA[0..19] <35> L57 +3VALW For EC Tools
    ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA
    ADB[0..7] <35> +3VALW
    1 1 C573 1 1 2 2 FBM-L11-160808-800LMT_0603 20mil
    C572 1 JP76
    C574 C575 C576 C577 KSI[0..7]
    1000P_0402_50V7K 1000P_0402_50V7K C578
    20mil KSI[0..7] <34> 1 1
    E51_RXD
    1 1 2 2
    L58 2 2 2 2 1 1 C579 C580 KSO[0..15] E51_TXD
    KSO[0..15] <34> 3 3

    ECAGND
    ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
    1 2 4 4
    FBM-L11-160808-800LMT_0603 20mil 0.1U_0402_16V4Z 1U_0402_6.3V4Z
    2 2 @ ACES_85205-0400

    123
    136
    157
    166

    161

    159
    D +3VALW +3VALW D

    16
    34
    45

    95

    96
    U24
    LPC_AD0 15

    VCCA
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AGND

    BATGND
    VCCBAT
    <22,41> LPC_AD0 LAD0

    2
    C581 LPC_AD1 14 49 KSO0
    <22,41> LPC_AD1 LAD1 GPOK0/KSO0
    @ 22P_0402_50V8J LPC_AD2 13 50 KSO1 R797 R465
    <22,41> LPC_AD2 LAD2 GPOK1/KSO1
    2 1 R463 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2 Ra 100K_0402_5% Rc SATA@ 100K_0402_5%
    <22,41> LPC_AD3 LAD3 GPOK2/KSO2 KSO3
    <22,26,41> LPC_FRAME# 9 LFRAME# LPC Interface GPOK3/KSO3 52
    KSO4
    <13,16,22,27,36,41> NB_RST# 165 53

    1
    LRST#/GPIO2C GPOK4/KSO4

    ENE-KB910-B4
    18 56 KSO5 AD_BID0 SKU_ID
    <22> CLK_PCI_LPC LCLK GPOK5/KSO5
    7 57 KSO6
    <22,37,41> SERIRQ SERIRQ GPOK6/KSO6

    2
    25 58 KSO7 1 1
    CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8 R800 C582 R801 C583
    24 LPCPD#/GPIO0B * GPOK8/KSO8 59
    +3VALW 60 KSO9 Rb Rd
    FR D# GPOK9/KSO9 KSO10 0_0402_5% 0_0402_5% 0.1U_0402_16V4Z
    <35> FRD# 150 RD# GPOK10/KSO10 61
    FWR# KSO11 @ 2
    0.1U_0402_16V4Z PATA@ 2 PATA@

    Internal Keyboard
    <35> FWR# 151 64

    1
    WR# GPOK11/KSO11
    2
    FSEL# 173 65 KSO12
    <35> FSEL# MEMCS# GPOK12/KSO12
    R798 SELIO# 152 66 KSO13
    10K_0402_5% ADB0 IOCS# GPOK13/KSO13 KSO14
    138 D0 GPOK14/KSO14 67
    ADB1 139 68 KSO15
    ADB2 D1 GPOK15/KSO15 KSO16
    140 153 KSO16 <34>
    1

    R799 1 ADB3 D2 GPOK16/KSO16 KSO17


    <36> MINI_PME# 2 0_0402_5% 141 D3 GPOK17/KSO17 154 KSO17 <34>
    ADB4 144
    R470 1 EC_PME# ADB5 D4 KSI0 SATA Status
    <31> LAN_PME# 2 0_0402_5% 145 D5 GPIK0/KSI0 71 Board ID Ra Rb Rc Rd

    X-BUS Interface
    ADB6 146 72 KSI1
    ADB7 D6 GPIK1/KSI1 KSI2
    147 D7 GPIK2/KSI2 73
    KBA0 124 74 KSI3 VGA V X W/S SATA V X
    KBA1 A0 GPIK3/KSI3 KSI4
    125 A1/XIOP_TP GPIK4/KSI4 77
    KBA2 126 78 KSI5
    KBA3 A2 GPIK5/KSI5 KSI6
    127 A3 GPIK6/KSI6 79 UMA X V W/O SATA X V
    KBA4 128 80 KSI7
    KBA5 A4/DMRP_TP GPIK7/KSI7
    131 A5/EMWB_TP
    +3VALW KBA6 132 32 INVT_PWM
    C A6 GPOW0/PWM0 INVT_PWM <29> C
    KBA7 133 33 BEEP#
    A7 GPOW1/PWM1 BEEP# <44>
    KBA8 143 36 VLDT_EN
    A8 FAN2PWM/GPOW2/PWM2 VLDT_EN <42,46>
    2

    KBA9 142 37 ACOFF


    R471 KBA10 A9 GPOW3/PWM3 ACOFF <47,49>
    10K_0402_5%
    135 A10 Pulse Width GPOW4/PWM4 38 USB_EN# <39,43>
    KBA11 134 39 EC_ON
    A11 GPOW5/PWM5 EC_ON <42>
    KBA12 130 40 EC_LID_OUT#
    A12 GPOW6/PWM6 EC_LID_OUT# <23>
    KBA13 129 43 EC_MUTE
    EC_MUTE <45>
    1

    D18 KBA14 A13 FAN1PWM/GPOW7/PWM7


    121 A14
    KBA15 120 2 ON/OFF
    A15 GPWU0 ON/OFF <42>
    1 2 EC_RCIRRX KBA16 113 26
    <43> RCIRRX A16 GPWU1 ACIN <50> +3VS
    KBA17 112 29 R472
    KBA18 A17 GPWU2 PM_SLP_S3# 100K_0402_5%
    RB751V_SOD323 104 A18 GPWU3 30 PM_SLP_S3# <23>
    KBA19 103 Wake Up Pin 44 PM_SLP_S5# TV_THERM# 2 1
    A19 GPWU4 PM_SLP_S5# <23>
    +5VS 108 76 EC_RCIRRX
    RP6 A20/GPIO23 GPWU5 EC_PME#
    +3VALW 2 1 105 E51CS#/GPIO20/ISPEN TIN1/GPWU6 172
    1 8 KB_CLK R473 100K_0402_5% 176 S3_STATE
    KB_DATA KB_CLK TIN2/FANFB2/GPWU7 S3_STATE <23> ECAGND
    2 7 110 PSCLK1 2 1
    3 6 PS_CLK KB_DATA 111 81 BATT_TEMP C584 0.01U_0402_16V7K
    +3VALW PSDAT1 GPIAD0/AD0 BATT_TEMP <50>
    4 5 PS_DATA PS_CLK 114 82 SKU_ID
    PS_DATA PSCLK2 GPIAD1/AD1 BATT_OVP
    4.7K_1206_8P4R_5% TP_CLK
    115 PSDAT2PS2 Interface GPIAD2/AD2 83 BATT_OVP <49>
    <34> TP_CLK 116 PSCLK3 GPIAD3/AD3 84
    +3VALW 1 2 BTSW_EN# TP_DATA 117 Analog To Digital 87
    <34> TP_DATA PSDAT3 GPIAD4/AD4
    RP7 R474 100K_0402_5% 88 TV_THERM#
    GPIAD5/AD5 TV_THERM# <36>
    1 8 1 2 WLSW_EN# <35,50> EC_SMB_CK1
    EC_SMB_CK1 163 SCL1 GPIAD6/AD6 89 AD_BID0
    2 7 FR D# R475 100K_0402_5% EC_SMB_DA1 164 90 POUT
    <35,50> EC_SMB_DA1 SDA1 GPIAD7/AD7 POUT <54>
    3 6 SELIO# EC_SMB_CK2 169 SMBus
    <7> EC_SMB_CK2 SCL2
    4 5 FSEL# EC_SMB_DA2 170 99 DAC_BRIG
    <7> EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG <29>
    GPODA1/DA1 100
    10K_1206_8P4R_5% EMPWR_BTN# 8 101 IR EF
    <43> EMPWR_BTN# GPIO04 GPODA2/DA2 IREF <49>
    +3VALW EC_SCI# 20 102 EN_DFAN1
    <23> EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 <5>
    RP8 E-MAIL_BTN# 21 Digital To Analog 1
    <43> E-MAIL_BTN# GPIO08 GPODA4/DA4 WL_OFF# <36>
    1 8 IE_BTN# IE_BTN# 22 42
    B <43> IE_BTN# GPIO09 GPODA5/DA5 MINI1_OFF# <36> B
    2 7 EMPWR_BTN# <17> ENBKL ENBKL 27 47
    E-MAIL_BTN# BKOFF# GPIO0D GPODA6/DA6
    3 6 <29> BKOFF# 28 GPIO0E GPODA7/DA7 174
    4 5 USER_BTN# FSTCHG 48
    <49> FSTCHG GPIO10
    EC_SMI# 62 85 PW R_LED PWR_LED <43>
    <23> EC_SMI# GPIO13 * GPIO18/XIO8CS#
    100K_1206_8P4R_5% IDE_LED# 63 86 PWR_SUSP_LED# PWR_SUSP_LED# <43>
    <27> IDE_LED# USER_BTN# GPIO14 * GPIO19/XIO9CS# BATT_GRN_LED#
    <43> USER_BTN# 69 GPIO15 91 BATT_GRN_LED# <43>
    +3VS *GPIO1A/XIOACS# BATT_AMB_LED# C RY1 C RY2
    <23> EC_SWI# 70 GPIO16 GPIO * GPIO1B/XIOBCS# 92 BATT_AMB_LED# <43>
    VGATE 75 Expanded I/O * GPIO1C/XIOCCS# 93 WL_LED# WL_LED# <43>
    <54> VGATE GPIO17
    1 2 5IN1_LED# 109 GPIO24 94 BT_LED# BT_LED# <43> 1 1
    R476 10K_0402_5% LID_SW# 118 * GPIO1D/XIODCS# 97 E-MAIL_LED# C585 C586
    <42> LID_SW# GPIO25 E-MAIL_LED# <43>
    * GPIO1E/XIOECS#

    4
    BT_ON# 119 98 MEDIA_LED# MEDIA_LED# <43>
    <34> BT_ON# GPIO26 * GPIO1F/XIOFCS#
    SYSON 148 10P_0402_50V8K 10P_0402_50V8K

    IN

    OUT
    <39,46> SYSON GPIO27 2 2
    SUSP# 149 171 FAN_SPEED1
    +5VALW <35,39,46,51,53> SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 <5>
    VR_ON 155 12 DPLL_TP
    <54> VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
    RP9 156 FANTEST_TP/GPIO05/FAN3PWM 11 TEST_TP X2
    <37> 5IN1_LED# GPIO2A
    EC_SMB_CK1 BTSW_EN#

    NC

    NC
    1 8 <43> BTSW_EN# 162 GPIO2B
    2 7 EC_SMB_DA1 PBTN_OUT# 168 175 EC_THERM#
    <23> PBTN_OUT# GPIO2D TOUT2/GPIO2F EC_THERM# <7,23>
    3 6 EC_SMB_CK2 Timer Pin

    3
    4 5 EC_SMB_DA2 55 3
    C587 0.1U_0402_16V4Z CAPS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 WLSW_EN# EC_RSMRST# <23>
    <43> CAPS_LED# 54 CapLock#/GPIO011 * E51IT1/GPIO01 4 WLSW_EN# <43>
    4.7K_1206_8P4R_5% 2 1 NUM_LED# 23 106 E51_RXD 1 2 EAPD
    <43> NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK EAPD <44>
    <24> SATA_LED# SATA_LED# 41 107 E51_TXD R477 0_0402_5% 32.768KHZ_12.5P_1TJS125DJ2A073
    +5VS ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
    +3VALW 2 1 19 ECRST# MISC
    R478 47K_0402_5% 5 158 C RY2
    TP_CLK <23> EC_GA20 GA20/GPIO02 XCLKI C RY1
    2 1 <23> EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160
    4.7K_0402_5% R479 31
    GND
    GND
    GND
    GND
    GND
    GND

    ECSCI# +3VS
    2 1 TP_DATA R481
    4.7K_0402_5% R480 @ 100K_0402_5%
    KB910Q B4_LQFP176 EAPD 2 1
    17
    35
    46
    122
    137
    167

    +3VALW
    KB910 C1 VERSION
    A KBA1 A
    2 1
    1K_0402_5% R482
    2 1 KBA4 1 2 DPLL_TP
    1K_0402_5% R483 R484 1K_0402_5%
    2 1 KBA5 1 2 TEST_TP
    1K_0402_5% R485 R486 1K_0402_5%

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 33 of 55
    5 4 3 2 1
    Scroll Up
    SW1
    EVQPLHA15_4P
    SCRL_U 3 1
    +3VALW 4 2 SCRL_R

    1 BTN_R

    5
    6
    C588
    Scroll Left Scroll Right

    3
    1U_0402_6.3V4Z
    2 SW2 SW3 D19
    MDC Conn. SCRL_L 3
    EVQPLHA15_4P
    1 SCRL_R 3
    EVQPLHA15_4P
    1
    @
    PSOT24C_SOT23
    JP14

    1
    4 2 4 2
    1 GND1 RES0 2
    ICH_SDOUT_MDC 3 4 20mil
    <23> ICH_SDOUT_MDC

    5
    6

    5
    6
    IAC_SDATA_OUT RES1 SCRL_L
    5 6
    <23> ICH_SYNC_MDC ICH_SYNC_MDC 7
    GND2
    IAC_SYNC
    3.3V
    GND3 8
    +3VALW
    Scroll Down
    <23> ICH_AC_SDIN1 R487 1 2 33_0402_5% 9 10 SCRL_U
    ICH_RST_MDC# IAC_SDATA_IN GND4 ICH_BITCLK_MDC SW4
    <23> ICH_RST_MDC# 11 IAC_RESET# IAC_BITCLK 12 ICH_BITCLK_MDC <23>

    3
    1 EVQPLHA15_4P
    C589 SCRL_D 3 1
    D20

    GND
    GND
    GND
    GND
    GND
    GND
    22P_0402_50V8J 4 2 @
    2 PSOT24C_SOT23
    ACES_88018-124G

    13
    14
    15
    16
    17
    18

    5
    6

    1
    Left Right
    Connector for MDC Rev1.5
    SW5 SW6 SCRL_D
    EVQPLHA15_4P EVQPLHA15_4P
    BTN_L 3 1 BTN_R 3 1 BTN_L

    3
    4 2 4 2
    D21

    5
    6

    5
    6
    2005/09/04 @
    PSOT24C_SOT23
    JP15

    1
    +5VS
    1
    2
    3 C590
    To TP/B Conn.
    KSO17 4
    <33> KSO17 5
    KSI2 0.1U_0402_16V4Z BTN_R C591 1 2 100P_0402_50V8J
    KSI5 6 JP16
    KSO16 7 SCRL_R C592 1 100P_0402_50V8J
    <33> KSO16 8 +5VS 1 2
    KSI3
    KSI4 9 TP_DATA 2 SCRL_U C593 1 100P_0402_50V8J
    10 <33> TP_DATA 3 2
    TP_CLK
    <33> TP_CLK 4
    Media@ACES_85201-10051 SCRL_L C594 1 2 100P_0402_50V8J
    5
    BTN_R 6 SCRL_D C595 1 100P_0402_50V8J
    7 2
    KSI[0..7] SCRL_R
    KSI[0..7] <33> 8
    SCRL_U BTN_L C596 1 2 100P_0402_50V8J
    KSO[0..15] TP_DATA SCRL_L 9
    KSO[0..15] <33> 10
    SCRL_D TP_DATA C597 1 2 100P_0402_50V8J
    INT_KBD Conn. TP_CLK BTN_L 11
    12 TP_CLK C598 1 2 100P_0402_50V8J

    3
    ACES_87151-1207

    D34
    (Right) JP17 @
    KSO15 C599 1 2 100P_0402_50V8J KSO7 C600 1 2 100P_0402_50V8J KSO15 PSOT24C_SOT23
    KSO14 24

    1
    KSO14 C601 1 100P_0402_50V8J KSO6 C602 1 100P_0402_50V8J KSO13 23 Modify 11/07 for EMI
    2 2

    KSO13 C603 1 2 100P_0402_50V8J KSO5 C604 1 2 100P_0402_50V8J


    KSO12
    KSI0
    22
    21 Bluetooth Conn.
    KSO11 20 L76
    KSO12 C605 1 100P_0402_50V8J KSO4 C606 1 100P_0402_50V8J KSO10 19
    2 2 18 2 2 1 1
    KSI1 +3VALW USB20_N5 USB20_N5_R
    17 <23> USB20_N5
    KSI2 USB20_P5 USB20_P5_R
    16 <23> USB20_P5
    KSI0 C607 1 2 100P_0402_50V8J KSO3 C608 1 2 100P_0402_50V8J KSO9 3 4
    KSI3 15 3 4
    14

    1
    KSO11 C609 1 2 100P_0402_50V8J KSI4 C610 1 2 100P_0402_50V8J KSO8 1 WCM2012F2S-900T04_0805
    KSO7 13 R805 C613
    KSO10 C611 1 100P_0402_50V8J KSO2 C612 1 100P_0402_50V8J KSO6 12
    2 2 11
    KSO5 100K_0402_5% 1U_0402_6.3V4Z +BT_VCC
    10

    3
    KSI1 C614 1 100P_0402_50V8J KSO1 C615 1 100P_0402_50V8J KSO4
    S
    2
    2 2

    2
    KSO3 9 G
    Q16 JP18
    8 <33> BT_ON# 2
    KSI4
    KSI2 C616 1 100P_0402_50V8J KSO0 C617 1 100P_0402_50V8J KSO2 7 SI2301BDS_SOT23 1
    2 2 6 2
    KSO1 USB20_P5_R
    KSO9 C618 1 100P_0402_50V8J KSI5 C619 1 100P_0402_50V8J KSO0 5 D
    USB20_N5_R 3
    2 2

    1
    KSI5 4 4
    KSI3 C620 1 100P_0402_50V8J KSI6 C621 1 100P_0402_50V8J KSI6 3 W=40mils 5
    2 2 2 +BT_VCC <36> WLAN_BT_DATA 6
    KSI7 11/01 modify
    1 <36> WLAN_BT_CLK 7
    KSO8 C622 1 2 100P_0402_50V8J KSI7 C623 1 2 100P_0402_50V8J (Left) 1
    ACES_85201-24051 C624 C625 8
    ACES_87212-0800
    4.7U_0805_10V4Z 0.1U_0402_16V4Z
    2

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 401412 B

    www.laptopfix.vn
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 34 of 55
    KBA[0..19]
    <33> KBA[0..19]
    @ 0.1U_0402_16V4Z
    ADB[0..7] C627 1 2
    <33> ADB[0..7]

    INT_FLASH_EN# R490 1 2
    +3VALW
    @ 100K_0402_5%

    1
    +3VALW

    OE#
    FSEL# 2 4 1 2 INT_FSEL#
    A Y R491 @ 22_0402_5%

    2
    2 R488

    3
    10K_0402_5%
    U26 C626 U61 @
    @ 0.1U_0402_16V4Z +3VALW +3VALW

    1
    KBA18 1 @ SN74AHCT1G125DCKR_SC70-5
    1 A18 VDD 32 C628
    KBA16 2 31 FWE#
    A16 WE#

    1
    KBA15 3 30 KBA17 1 2 R489 +3VALW
    KBA12 A15 A17 KBA14 100K_0402_5%
    4 A12 A14 29 SUSP# <33,39,46,51,53>
    KBA7 5 28 KBA13 0.1U_0402_16V4Z 1 2
    A7 A13

    2
    KBA6 KBA8 R829 0_0402_5%

    G
    6 A6 A8 27

    5
    KBA5 7 26 KBA9 U27

    2
    KBA4 A5 A9 KBA11
    8 25 2 1 3

    P
    A4 A11 I0 EC_FLASH# <23>
    KBA3 9 24 FR D# FWE# 4

    S
    KBA2 A3 OE# KBA10 O
    10 A2 A10 23 I1 1

    G
    KBA1 11 22 FSEL# Q17
    KBA0 A1 CE# ADB7 TC7SH32FU_SSOP5 2N7002_SOT23
    12 21

    3
    ADB0 A0 DQ7 ADB6
    13 DQ0 DQ6 20
    ADB1 14 19 ADB5
    DQ1 DQ5 FWR# <33>
    ADB2 15 18 ADB4
    DQ2 DQ4 ADB3
    16 VSS DQ3 17

    @ SST39VF040-70-4C-NH_PLCC32
    FOR DEBUG ONLY
    (CL55) +3VALW
    SB_INT_FLASH_SEL# <23>

    1
    P

    OE#
    2 4 INT_FLASH_SEL
    <23> SUS_STAT# A Y

    G
    U62

    3
    @ SN74AHCT1G125DCKR_SC70-5

    1MB Flash ROM


    +3VALW
    U28

    KBA0 21 31
    1MB Flash ROM
    KBA1 A0 VCC0 +5VALW +5VALW
    20 A1 VCC1 30 1
    KBA2 19 C629
    KBA3 A2 JP19
    18 A3

    1
    KBA4 17 25 ADB0 0.1U_0402_16V4Z KBA16 KBA17
    KBA5 A4 D0 ADB1 2 KBA15 1 2 C630 1
    16 A5 D1 26 3 4 2 0.1U_0402_16V4Z R492
    KBA6 15 27 ADB2 KBA14
    KBA7 A6 D2 ADB3 KBA13 5 6 KBA19 100K_0402_5%
    14 A7 D3 28 7 8
    KBA8 8 32 ADB4 KBA12 KBA10

    2
    KBA9 A8 D4 ADB5 KBA11 9 10 ADB7 U29
    7 A9 D5 33 11 12
    KBA10 36 34 ADB6 KBA9 ADB6 8 1
    KBA11 A10 D6 ADB7 KBA8 13 14 ADB5 VCC A0
    6 A11 D7 35 15 16 7 WP A1 2
    KBA12 5 FWE# ADB4 6 3
    A12 17 18 <33,50> EC_SMB_CK1 SCL A2
    KBA13 4 RESET# +3VALW 5 4
    A13 19 20 <33,50> EC_SMB_DA1 SDA GND
    KBA14 3 10 RESET# 1 2 +3VALW INT_FLASH_EN#
    KBA15 A14 RP# R493 INT_FLASH_SEL 21 22 AT24C16AN-10SU-2.7_SO8
    2 A15 NC 11 23 24
    KBA16 1 12 100K_0402_5% KBA18 ADB3
    KBA17 A16 READY/BUSY# KBA7 25 26 ADB2
    40 A17 NC0 29 27 28
    KBA18 13 38 KBA6 ADB1
    KBA19 A18 NC1 KBA5 29 30 ADB0
    37 A19 31 32
    KBA4 FR D#
    33 34 FRD# <33>

    1
    INT_FSEL# 22 KBA3
    FR D# CE# KBA2 35 36 FSEL# R494
    24 OE# GND0 23 37 38 FSEL# <33>
    FWE# 9 39 KBA1 KBA0
    WE# GND1 39 40 100K_0402_5%
    SUYIN_80065AR-040G2T

    2
    SST39VF080-70_TSOP40 @

    Security Classification Compal Secret Data


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom 401412 B

    www.laptopfix.vn
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 35 of 55
    A B C D E

    +3VALW
    +5VS +3VS

    0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z


    W=40mils

    1 1 1 1 1 1 1 1 1 1 1
    C634
    C631 C632 C633 C635 C636 C637 C638 C639 C640 C641
    10U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2 2 2 2 2 2

    1 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K 1

    PCI_AD[0..31]
    PCI_AD[0..31] <22,26,31,37,40>

    JP20
    TIP 1 2 RING
    1 2
    KEY KEY
    3 3 4 4
    5 5 6 6
    7 7 8 8
    9 9 10 10
    D22
    11 11 12 12
    WL_OFF# 1 2 13 14
    <33> WL_OFF# 13 14
    RB751V_SOD323 15 16
    15 16
    <22,37> PCI_PIRQH# 17 17 18 18 W=40mils +5VS
    +3VS W=40mils 19 19 20 20 PCI_PIRQG# <22>
    S_YIN 21 22 S_CIN
    <43> S_YIN 21 22 S_CIN <43> +3VS +1.5VS +3VALW
    23 23 24 24 W=40mils +3VALW
    CLK_PCI_MINI 25 26
    <22> CLK_PCI_MINI 25 26 PCI_RST# <22,31,37,39,40>
    27 27 28 28 W=40mils +3VS
    PCI_REQ#1 29 30 PCI_GNT#1 1 1 1 1 1 1
    <22> PCI_REQ#1 29 30 PCI_GNT#1 <22>
    31 32 C642 C643 C644 C645 C646 C647
    PCI_AD31 31 32
    33 33 34 34 MINI_PME# <33>
    2 PCI_AD29 WLAN_BT_CLK 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
    35 35 36 36 WLAN_BT_CLK <34>
    PCI_AD30 2 2 2 2 2 2
    37 37 38 38
    PCI_AD27 39 40
    PCI_AD25 39 40 PCI_AD28
    41 41 42 42
    WLAN_BT_DATA 43 44 PCI_AD26
    <34> WLAN_BT_DATA 43 44
    45 46 PCI_AD24 JP21
    <22,31,37,40> PCI_CBE#3 45 46
    PCI_AD23 47 48 MINI_IDSEL1 1 2 R495 PCI_AD18 <23,39> SB_PCIE_WAKE# SB_PCIE_WAKE# 1 2 +3VS
    CLK_PCI_MINI 47 48 100_0402_5% WLAN_BT_DATA 1 2
    49 49 50 50 3 3 4 4
    PCI_AD21 51 52 PCI_AD22 WLAN_BT_CLK 5 6 +1.5VS
    51 52 5 6
    1

    PCI_AD19 53 54 PCI_AD20 <15> MINI1_CLKREQ# MINI1_CLKREQ# 7 8


    R496 53 54 7 8
    55 55 56 56 PCI_PAR <22,31,37,40> 9 9 10 10
    PCI_AD17 57 58 PCI_AD18 11 12
    57 58 <15> CLK_PCIE_MINI1# 11 12
    @ 10_0402_5% PCI_CBE#2 59 60 PCI_AD16 13 14
    <22,31,37,40> PCI_CBE#2 59 60 <15> CLK_PCIE_MINI1 13 14
    PCI _IRDY# 61 62 15 16
    <22,31,37,40> PCI_IRDY#
    2

    61 62 PCI_FRAME# 15 16
    1 63 63 64 64 PCI_FRAME# <22,31,37,40>
    C648 65 66 PCI_TRDY#
    <22,31,41> PM_CLKRUN# 65 66 PCI_TRDY# <22,31,37,40>
    PCI_SERR# 67 68 PCI_STOP# 17 18
    PCI_STOP# <22,31,37,40>
    @ 10P_0402_50V8K <22,31,37> PCI_SERR# 69
    67 68
    70 19
    17 18
    20 MINI1_OFF#
    2 69 70 19 20 MINI1_OFF# <33>
    PCI_PERR# 71 72 PCI_DEVSEL# 21 22 NB_RST#
    <22,31,37,40> PCI_PERR# 71 72 PCI_DEVSEL# <22,31,37,40> 21 22 NB_RST# <13,16,22,27,33,41>
    PCI_CBE#1 73 74 23 24 +3VALW
    <22,31,37,40> PCI_CBE#1 73 74 <12> PCIE_MRX_PTX_N1 23 24
    PCI_AD14 75 76 PCI_AD15 25 26
    75 76 <12> PCIE_MRX_PTX_P1 25 26
    77 78 PCI_AD13 27 28
    PCI_AD12 77 78 PCI_AD11 27 28 ICH_SMBCLK
    79 79 80 80 29 29 30 30 ICH_SMBCLK <15,39>
    PCI_AD10 81 82 <12> PCIE_MTX_C_PRX_N1 31 32 ICH_SMBDATA ICH_SMBDATA <15,39>
    81 82 PCI_AD9 31 32
    83 83 84 84 <12> PCIE_MTX_C_PRX_P1 33 33 34 34
    PCI_AD8 85 86 PCI_CBE#0 35 36
    PCI_AD7 85 86 PCI_CBE#0 <22,31,37,40> 35 36
    87 87 88 88 37 37 38 38
    89 90 PCI_AD6 39 40
    PCI_AD5 89 90 PCI_AD4 39 40
    91 91 92 92 41 41 42 42
    CVBS_IN 93 94 PCI_AD2 43 44 (MINI1_LED#)
    <43> CVBS_IN 93 94 43 44
    PCI_AD3 95 96 PCI_AD0 45 46
    95 96 45 46
    +5VS W=40mils 97 97 98 98 TV_THERM# <33> 47 47 48 48
    3 PCI_AD1 3
    99 99 100 100 49 49 50 50
    101 101 102 102 51 51 52 52
    103 103 104 104

    G1
    G2
    G3
    G3
    105 105 106 106
    107 107 108 108
    109 110 FOX_AS0B226-S99N-7F

    53
    54
    55
    56
    109 110 AUDIO_INR
    111 111 112 112 AUDIO_INR <43>
    113 113 114 114
    115 115 116 116
    117 117 118 118
    119 119 120 120
    AUDIO_INL 121 122 W=30mils
    <43> AUDIO_INL 121 122
    +5VS 123 123 124 124 +3VALW
    W=30mils W=20mils R851
    P-TWO_A53921-A0G16-P +3VS 1 2 +CAM_VDD
    1
    0_0805_5%
    C952
    (Change to SP070003200) JP43 2
    0.1U_0402_16V4Z

    1 1
    2 2 USB20_N4 <23>
    3 3 USB20_P4 <23>
    4 4
    5 5
    GND1 6
    GND2 7

    ACES_88266-05001

    4 4
    Mini Card Power Rating 2006/02/20 modify
    Power Primary Power (mA) Auxiliary Power (mA)
    Peak Normal Normal
    +3VS 1000 750
    +3VALW 330 250 250 (wake enable)
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
    +1.5VS 500 375 5 (Not wake enable) SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 36 of 55
    A B C D E
    A B C D E

    +S1_VCC +3VS
    VPPD0
    <38> VPPD0
    VPPD1
    <38> VPPD1
    VCCD0#
    +3VS <38> VCCD0#
    40mil VCCD1#
    <38> VCCD1#

    M13

    M12

    G13
    N13

    N12

    D12
    H11
    S1_A[0..25]

    G1
    C8

    N4
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

    A7

    B4

    K2

    F3
    L9
    L6
    S1_A[0..25] <38>
    U30
    1 1 1 1 1 1 1 S1_D[0..15]

    VCCD1#
    VCCD0#

    VPPD1
    VPPD0

    VCCA2
    VCCA1

    VCC10
    VCC9
    VCC8
    VCC7
    VCC6
    VCC5
    VCC4
    VCC3
    VCC2
    VCC1
    S1_D[0..15] <38>
    C649 C650 C651 C652 C653 C654 C655

    0.1U_0402_16V4Z
    2 2 2 2 2 2 2
    PCI_AD31 C2 B2 S1_D10
    1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PCI_AD30 AD31 CAD31/D10 S1_D9 1
    C1 AD30 CAD30/D9 C3
    PCI_AD29 D4 B3 S1_D1
    PCI_AD28 AD29 CAD29/D1 S1_D8
    D2 AD28 CAD28/D8 A3
    PCI_AD27 D1 C4 S1_D0 +3VS
    PCI_AD26 AD27 CAD27/D0 S1_A0
    E4 AD26 CAD26/A0 A6
    PCI_AD25 E3 D7 S1_A1
    PCI_AD24 AD25 CAD25/A1 S1_A2
    E2 AD24 CAD24/A2 C7 1 1
    PCI_AD23 F2 A8 S1_A3 C656 C657
    PCI_AD[0..31] PCI_AD22 AD23 CAD23/A3 S1_A4
    <22,26,31,36,40> PCI_AD[0..31] F1 AD22 CAD22/A4 D8
    PCI_AD21 G2 A9 S1_A5 4.7U_0805_10V4Z 0.1U_0402_16V4Z
    PCI_CBE#[0..3] PCI_AD20 AD21 CAD21/A5 S1_A6 2 2
    <22,31,36,40> PCI_CBE#[0..3] G3 AD20 CAD20/A6 C9
    PCI_AD19 H3 A10 S1_A25
    PCI_AD18 AD19 CAD19/A25 S1_A7
    H4 AD18 CAD18/A7 B10
    PCI_AD17 J1 D10 S1_A24
    PCI_AD16 AD17 CAD17/A24 S1_A17
    J2 AD16 CAD16/A17 E12
    PCI_AD15 N2 F10 S1_IOWR#
    AD15 CAD15/IOWR# S1_IOWR# <38>
    CLK_PCI_PCM CLK_SD_48M PCI_AD14 M3 E13 S1_A9
    PCI_AD13 AD14 CAD14/A9 S1_IORD# +S1_VCC
    N3 AD13 CAD13/IORD# F13 S1_IORD# <38>

    1
    PCI_AD12 K4 F11 S1_A11
    R497 R498 PCI_AD11 AD12 CAD12/A11 S1_OE#
    M4 AD11 CAD11/OE# G10 S1_OE# <38>
    @ 10_0402_5% @ 10_0402_5% PCI_AD10 K5 G11 S1_CE2# 1 1
    AD10 CAD10/CE2# S1_CE2# <38>
    PCI_AD9 L5 G12 S1_A10 C658 C659
    PCI_AD8 AD9 CAD9/A10 S1_D15
    M5 H12

    2
    PCI_AD7 AD8 CAD8/D15 S1_D7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 1 K6 AD7 CAD7/D7 H10
    C660 C661 PCI_AD6 S1_D13 2 2
    M6 AD6 CAD6/D13 J11
    PCI_AD5 N6 J12 S1_D6
    @ 15P_0402_50V8J @ 15P_0402_50V8J PCI_AD4 AD5 CAD5/D6 S1_D12
    M7 AD4 CAD4/D12 K13
    2 2 PCI_AD3 S1_D5
    N7 J10

    PCI Interface
    PCI_AD2 AD3 CAD3/D5 S1_D11
    L7 AD2 CAD2/D11 K10

    CARDBUS
    PCI_AD1 K7 K12 S1_D4
    PCI_AD0 AD1 CAD1/D4 S1_D3
    N8 AD0 CAD0/D3 L13
    2 PCI_CBE#3 S1_REG# 2
    E1 CBE3# CCBE3#/REG# B7 S1_REG# <38>
    PCI_CBE#2 J3 A11 S1_A12
    PCI_CBE#1 CBE2# CCBE2#/A12 S1_A8
    N1 CBE1# CCBE1#/A8 E11
    PCI_CBE#0 N5 H13 S1_CE1#
    CBE0# CCBE0#/CE1# S1_CE1# <38>
    PCI_RST# G4 B9 S1_RST
    <22,31,36,39,40> PCI_RST# PCIRST# CRST#/RESET S1_RST <38>
    <22,31,36,40> PCI_FRAME# J4 B11 S1_A23
    FRAME# CFRAME#/A23 S1_A15
    <22,31,36,40> PCI_IRDY# K1 IRDY# CIRDY#/A15 A12
    <22,31,36,40> PCI_TRDY# K3 A13 S1_A22
    TRDY# CTRDY#/A22 S1_A21
    <22,31,36,40> PCI_DEVSEL# L1 DEVSEL# CDEVSEL#/A21 B13
    L2 C12 S1_A20
    <22,31,36,40> PCI_STOP# STOP# CSTOP#/A20
    L3 C13 S1_A14
    <22,31,36,40> PCI_PERR# PERR# CPERR#/A14
    M1 A5 S1_WAIT#
    <22,31,36> PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# <38>
    <22,31,36,40> PCI_PAR M2 D13 S1_A13
    PCI_REQ#2 PAR CPAR/A13 S1_INPACK#
    <22> PCI_REQ#2 A1 PCIREQ# CREQ#/INPACK# B8 S1_INPACK# <38>
    B1 C11 S1_WE#
    <22> PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# <38>
    CLK_PCI_PCM H1 B12 1 2 S1_A16
    <22> CLK_PCI_PCM PCICLK CCLK/A16 R500 33_0402_5%
    L8 C5 S1_BVD1
    RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 <38>
    +3VS 1 2 L11 D5 S1_WP
    SUSPEND# CCLKRUN#/WP_IOIS16# S1_WP <38>
    R501 10K_0402_5%
    PCI_AD20 1 2 F4 D11 S1_A19
    R502 100_0402_5% IDSEL CBLOCK#/A19
    K8 D6 S1_RDY# S1_CD2# S1_CD1#
    <22,40> PCI_PIRQE# MFUNC0 CINT#/READY_IREQ# S1_RDY# <38>
    R503 1 2 SD_PULLHIGH N9 2 2
    <38> MS_PWREN# MFUNC1
    @ 0_0402_5% K9 M9 PCM_SPK# C662 C663
    <22,36> PCI_PIRQH# MFUNC2 SPKROUT PCM_SPK# <44>
    N10 B5 S1_BVD2
    <22,33,41> SERIRQ MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 <38>
    SM_CD# L10 10P_0402_50V8K 10P_0402_50V8K
    5IN1_LED# MFUNC4 S1_CD2# 1 1
    <33> 5IN1_LED# N11 MFUNC5 CCD2#/CD2# A4 S1_CD2# <38>
    M11 L12 S1_CD1#
    MFUNC6 CCD1#/CD1# S1_CD1# <38>
    SDOC# J9 D9 S1_VS2
    <38> SDOC# MFUNC7 CVS2/VS2# S1_VS2 <38>
    C6 S1_VS1
    3 CVS1/VS1 S1_VS1 <38> 3
    A2 S1_D2
    +3VS PCI_RST# CRSV3/D2 S1_A18
    M10 GRST# CRSV2/A18 E10
    MFUNC5[3:0] = (0 1 0 1) J13 S1_D14
    SM_CD# CRSV1/D14
    1 2
    R499 61@ 43K_0402_5% MFUNC5[4] = 1
    E7
    SD/MMC/MS/SM H7
    +VCC_SD VCC_SD MSINS# MS_INS# <38>
    J8 XD_PWREN#
    MSPWREN#/SMPWREN# XD_PWREN# <38>
    SD_CD# E8 H8 MSBS_XDD1
    <38> SD_CD# SDCD# MSBS/SMDATA1 MSBS_XDD1 <38>
    SD_WP# F8 E9 MS_CLK R504 1 2
    <38> SD_WP# SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# <38>
    SD_PWREN# G7 G9 MSD0_XDD2 61@ 33_0402_5%
    <38> SD_PWREN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 <38>
    H9 MSD1_XDD6
    MSDATA1/SMDATA6 MSD1_XDD6 <38>
    CLK_SD_48M H5 G8 MSD2_XDD5
    <15> CLK_SD_48M SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 <38>
    F9 MSD3_XDD3
    MSDATA3/SMDATA3 MSD3_XDD3 <38>
    R505 1 2 33_0402_5%
    61@ SD_CLK F6
    <38> SDCK_XDWE# SDCLK/SMWE#
    SDCM_XDALE E5
    <38> SDCM_XDALE SDCMD/SMALE
    SDDA0_XDD7 E6 H6
    <38> SDDA0_XDD7 SDDAT0/SMDATA7 SMBSY# XD_BSY# <38>
    SDDA1_XDD0 F7 J7 XD_CD#
    <38> SDDA1_XDD0 SDDAT1/SMDATA0 SMCD# XD_CD# <38>
    SDDA2_XDCL F5 J6 XD_WP#
    <38> SDDA2_XDCL SDDAT2/SMCLE SMWP# XD_WP# <38>
    SDDA3_XDD4 G6 J5
    <38> SDDA3_XDD4 SDDAT3/SMDATA4 SMCE# XD_CE# <38>

    2
    GND1
    GND2
    GND3
    GND4
    GND5
    GND6
    GND7
    GND8
    G5 GND_SD R506
    2.2K_0402_5%
    CB714_LFBGA169 61@
    D3
    H2
    L4
    M8
    K11
    F12
    C10
    B6

    61@

    1
    **CB714 use B0 version

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 37 of 55
    A B C D E
    A B C D E

    PCMCIA Socket 1
    JP22
    GND
    35 GND
    S1_D3 2
    S1_CD1# DATA3
    <37> S1_CD1# 36 CD1#
    S1_D4 3
    +S1_VCC S1_D11 DATA4
    37
    PCMCIA Power Control S1_D5
    S1_D12
    4
    38
    DATA11
    DATA5
    S1_D6 DATA12
    1 1 5 DATA6
    +S1_VCC C664 C665 S1_D13 39
    S1_D7 DATA13
    6 DATA7
    10U_0805_10V4Z 0.1U_0402_16V4Z S1_D14 40
    2 2 S1_CE1# DATA14
    1 U31
    40mil <37> S1_CE1# S1_D15
    7 CE1# 1
    41 DATA15
    13 S1_A10 8
    VCC S1_CE2# ADD10
    VCC 12 <37> S1_CE2# 42 CE2#
    9 11 S1_OE# 9
    12V VCC +S1_VPP <37> S1_OE# S1_VS1 OE#
    <37> S1_VS1 43 VS1#
    40mil S1_A11 10
    +5VS +S1_VPP S1_IORD# ADD11
    <37> S1_IORD# 44 IORD#
    W=40mil 1 S1_A9 11
    S1_IOWR# ADD9
    VPP 10 <37> S1_IOWR# 45 IOWR#
    1 1 C666 1 1 S1_A8 12
    C667 0.1U_0402_16V4Z C669 C670 S1_A17 ADD8
    5 5V 46 ADD17
    C668 2 S1_A13
    6 5V 13 ADD13
    10U_0805_10V4Z 0.1U_0402_16V4Z S1_A[0..25] S1_A18 47
    2 2 2 2 <37> S1_A[0..25] ADD18
    0.1U_0402_16V4Z 1 VCCD0# 10U_0805_10V4Z S1_A14 14
    VCCD0 VCCD0# <37> S1_D[0..15] ADD14
    2 VCCD1# <37> S1_D[0..15] S1_A19 48
    +3VS VCCD1 VCCD1# <37> ADD19
    15 VPPD0 S1_WE# 15
    VPPD0 VPPD0 <37> <37> S1_WE# WE#
    14 VPPD1 S1_A20 49
    VPPD1 VPPD1 <37> ADD20
    W=40mil S1_RDY# 16
    <37> S1_RDY# S1_A21 READY
    3 3.3V 50 ADD21
    1 1 4 3.3V OC 8 +S1_VCC 17 VCC
    SHDN
    C671 C672 51
    GND

    +S1_VCC VCC
    +S1_VPP 18 VPP
    10U_0805_10V4Z +S1_VPP 52 VPP
    1

    2 2
    0.1U_0402_16V4Z CP2211FD3_SSOP16 S1_OE# S1_A16
    1 2 +S1_VCC 19
    7

    16

    R508 R507 43K_0402_5% S1_A22 ADD16


    53 ADD22
    10K_0402_5% S1_WP 2 1 S1_A15 20
    +S1_VCC ADD15
    R509 43K_0402_5% S1_A23 54
    S1_RST S1_A12 ADD23
    1 2 +S1_VCC 21
    2

    R510 43K_0402_5% S1_A24 ADD12


    55 ADD24
    S1_CE1# 1 2 +S1_VCC S1_A7 22
    R511 43K_0402_5% S1_A25 ADD7
    56 ADD25
    S1_CE2# 1 2 +VCC_SD S1_A6 23
    2
    +S1_VCC ADD6 2
    R512 43K_0402_5% S1_VS2 57
    VCCD0# <37> S1_VS2 S1_A5 VS2#
    1 2 24 ADD5
    R513 10K_0402_5% 1 1 1 S1_RST 58
    VCCD1# C673 C674 C675 <37> S1_RST S1_A4 RESET
    1 2 25 ADD4
    R514 10K_0402_5% S1_WAIT# 59
    61@ 10U_0805_10V4Z 0.1U_0402_16V4Z <37> S1_WAIT# S1_A3 WAIT#
    26 ADD3
    2 2 61@ 2 S1_INPACK#
    <37> S1_INPACK# 60 INPACK#
    0.1U_0402_16V4Z S1_A2 27
    61@ S1_REG# ADD2
    <37> S1_REG# 61 REG#
    S1_A1 28
    S1_BVD2 ADD1
    <37> S1_BVD2 62 BVD2
    S1_A0 29
    +VCC_XD S1_BVD1 ADD0
    <37> S1_BVD1 S1_D0
    63
    30
    BVD1 (NEW)
    S1_D8 DATA0
    64 DATA8
    1 1 S1_D1 31
    C676 C677 S1_D9 DATA1
    65 DATA9 GND 69
    S1_D2 32 70
    10U_0805_10V4Z 0.1U_0402_16V4Z S1_D10 DATA2 GND
    66 DATA10
    61@ 2 2 61@ S1_WP
    xD PU and PD. Close to Socket <37> S1_WP S1_CD2#
    33 WP
    67
    SD/MS Power Control +3VS <37> S1_CD2#
    34
    68
    CD2#
    GND
    XD Power Control 2
    R515
    1 XD_CD#
    @ 43K_0402_5%
    GND
    SANTA_130601-7_LT
    +3VS +VCC_XD
    +3VS
    40mil 4 IN 1 Socket
    (HDQ70)
    2

    +3VS +VCC_XD 1 2 MSCLK_XDRE#


    2

    R517 R516 61@ 2.2K_0402_5% JP23


    R518 U32 1 2 SDCK_XDWE# +VCC_XD 41 15 +VCC_SD
    3 61@ 10K_0402_5% 61@ 10K_0402_5% R519 61@ 2.2K_0402_5% XD-VCC SD-VCC 3
    1 GND OUT 8 MS-VCC 9
    2 7 1 2 XD_CE# SDDA1_XDD0 33
    <37> SDDA1_XDD0
    1

    IN OUT R520 61@ 2.2K_0402_5% MSBS_XDD1 XD-D0 SDCK_XDWE#


    3 6 <37> MSBS_XDD1 34 4 IN 1 CONN 16
    1

    XD_PWREN# IN OUT SDOC# XD_BSY# MSD0_XDD2 XD-D1 SD_CLK SDDA0_XDD7


    <37> XD_PWREN# 4 EN# FLG 5 SDOC# <37> 1 2 <37> MSD0_XDD2 35 XD-D2 SD-DAT0 19
    R521 61@ 2.2K_0402_5% MSD3_XDD3 36 20 SDDA1_XDD0
    <37> MSD3_XDD3 XD-D3 SD-DAT1
    1

    G528_SO8 SDDA3_XDD4 37 11 SDDA2_XDCL


    <37> SDDA3_XDD4 XD-D4 SD-DAT2
    1

    61@ R522 MSD2_XDD5 38 12 SDDA3_XDD4


    <37> MSD2_XDD5 XD-D5 SD-DAT3
    R523 61@ 300_0402_5% MSD1_XDD6 39 13 SDCM_XDALE
    <37> MSD1_XDD6 XD-D6 SD-CMD
    0_0402_5% SDDA0_XDD7 40 21 SD_CD#
    <37> SDDA0_XDD7 XD-D7 SD-CD-SW SD_CD# <37>
    61@ 22
    1 2

    SDCK_XDWE# SD-CD-COM SD_WP#


    <37> SDCK_XDWE# 30 43 SD_WP# <37>
    2

    D XD_WP# XD-WE SD-WP-SW


    SD_PWREN# XD_PWREN# Q18
    Reserve for SD,MS CLK. <37> XD_WP#
    SDCM_XDALE
    31 XD-WP SD-WP-COM 44
    <37> SD_PWREN# 2 <37> SDCM_XDALE 29 XD-ALE
    G 61@ 2N7002_SOT23 Close to Socket <37> XD_CD#
    XD_CD# 23 8 MSCLK_XDRE#
    XD_BSY# XD-CD MS-SCLK MSD0_XDD2
    <37> MS_PWREN# S <37> XD_BSY# 25 4
    3

    SDCK_XDWE# 1 MSCLK_XDRE# XD-R/B MS-DATA0 MSD1_XDD6


    2 <37> MSCLK_XDRE# 26 XD-RE MS-DATA1 3
    C678 10P_0402_50V8K XD_CE# 27 5 MSD2_XDD5
    <37> XD_CE# XD-CE MS-DATA2
    61@ SDDA2_XDCL 28 7 MSD3_XDD3
    <37> SDDA2_XDCL XD-CLE MS-DATA3
    MSCLK_XDRE#1 2 6 MS_INS#
    MS-INS MS_INS# <37>
    C679 10P_0402_50V8K 32 2 MSBS_XDD1
    61@ XD-GND MS-BS
    24 XD-GND SD-GND 14
    SD-GND 17
    42 N.C. MS-GND 1
    +VCC_XD 1 2 +VCC_SD 18 N.C. MS-GND 10
    R524 0_0603_5%
    61@ TAITW_R007-530-L3
    61@

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 38 of 55
    A B C D E
    A B C D E

    New Card Power Switch


    New Card Socket (Left)
    U63
    +3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1
    60mils JP24
    +3VS 5 3.3Vin1 3.3Vout1 7 +3VS_CARD1 Imax = 0.275A Imax = 1.35A Imax = 0.75A
    6 3.3Vin2 3.3Vout2 8
    1 GND
    1 1 1 1 1 1 <23> USB20_N0 2 USB_D-
    40mil C680 C681 C682 C683 C684 C685 3
    1 <23> USB20_P0 USB_D+ 1
    +3VALW 21 20 +3VALW_CARD1 CP_USB# 4
    3.3Vaux_in Aux_out 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CPUSB#
    5 RSV
    NC@ 2 2
    0.1U_0402_16V4Z NC@ 2 2
    0.1U_0402_16V4Z NC@ 2 2
    0.1U_0402_16V4Z
    40mil NC@ NC@ NC@
    6 RSV
    +1.5VS 18 1.5Vin1 1.5Vout1 16 +1.5VS_CARD1 <15,36> ICH_SMBCLK 7 SMB_CLK
    19 1.5Vin2 1.5Vout2 17 <15,36> ICH_SMBDATA 8 SMB_DATA
    +1.5VS_CARD1 9 +1.5V
    10 +1.5V
    +3VALW R525 1 NC@ 2 100K_0402_5% CP_USB# 14 <23,36> SB_PCIE_WAKE# 11
    R526 1 NC@ 2 100K_0402_5% CP_PE# CPUSB# WAKE#
    15 CPPE# OC# 23 +3VALW_CARD1 12 +3.3VAUX
    SUSP# 4 PERST1# 13
    <33,35,46,51,53> SUSP# STBY# PERST#
    SYSON 3 22 RCLKEN1 +3VS_CARD1 14
    <33,46> SYSON SHDN# RCLKEN +3.3V
    PCI_RST# 2 9 PERST1# +3VS +3VS 15
    <22,31,36,37,40> PCI_RST# SYSRST# PERST# +3.3V
    CLKREQ1# 16
    CP_PE# CLKREQ#
    17

    GND
    <23> CP_PE#

    NC1
    NC2
    NC3
    NC4
    NC5
    CPPE#

    1
    +3VS 1 18
    <15> CLK_PCIE_CARD# REFCLK-
    R527 C686 19
    <15> CLK_PCIE_CARD REFCLK+
    TPS2231PWPR_PWP24 10K_0402_5% 20

    11

    1
    10
    12
    13
    24
    GND

    1
    NC@ NC@ 0.1U_0402_16V4Z 21
    2 NC@ <12> PCIE_MRX_PTX_N0 PERn0
    R528 22
    <12> PCIE_MRX_PTX_P0

    2
    PERp0

    5
    10K_0402_5% U64 23
    NC@ CLKREQ1# GND
    2 24

    G Vcc
    B <12> PCIE_MTX_C_PRX_N0 PETn0
    4 EXP_CLKREQ# <15> <12> PCIE_MTX_C_PRX_P0 25

    2
    Y PETp0
    1 A 26 GND

    1
    D NC7SZ32P5X_NL_SC70-5 27

    3
    RCLKEN1 2 Q42 NC@ GND
    28 GND
    G 2N7002_SOT23
    +3VS +3VALW +1.5VS S NC@ TYCO_1759056-1

    3
    NC@

    C687
    1
    C688
    1
    C689
    1 (NEW)
    2 2
    10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
    NC@ 2 NC@ 2 NC@ 2

    1 2 1 2
    R821USB@ 0_0402_5% R822 0_0402_5%

    L65 L66
    2 2 1 1 2 2 1 1
    USB20_P1 USB20_P1_R USB20_N2 USB20_N2_R
    <23> USB20_P1 <23> USB20_N2
    USB20_N1 USB20_N1_R USB20_P2 USB20_P2_R
    <23> USB20_N1 <23> USB20_P2
    3 3 4 4 3 3 4 4

    @ WCM2012F2S-900T04_0805 @ WCM2012F2S-900T04_0805

    1 2 1 2
    R823USB@ 0_0402_5% R824 0_0402_5%

    USB Component co-layout

    USB CONN. 1 & 2


    +USB_VCCA +USB_VCCA

    +USB_VCCA
    W=80mils +USB_VCCA
    W=80mils
    1 1
    1 1
    + C690 C692 + C691 C693

    3 150U_D_6.3VM 470P_0402_50V7K 150U_D_6.3VM 470P_0402_50V7K 3


    2 USB@ 2 USB@ 2 2
    2005/09/06 2005/09/06
    JP25 JP26

    USB20_N1_R 1 USB20_N2_R 1
    USB20_P1_R 2 USB20_P2_R 2
    3 3
    4 4
    SUYIN_020173MR004S312ZL SUYIN_020173MR004S312ZL
    USB@

    ECQ60 ECQ60
    +5VALW +USB_VCCA
    U35
    1 8 D23 D24
    GND OUT R530
    2 IN OUT 7 1 GND VCC 4 +USB_VCCA 1 GND VCC 4 +USB_VCCA
    3 6 0_0402_5%
    IN OUT
    1 4 EN# FLG 5 1 2 USB_OC#0 <23>
    C694 USB20_P1 2 3 USB20_N1 USB20_P2 2 3 USB20_N2
    G528_SO8 I/O I/O I/O I/O
    4.7U_0805_10V4Z 1 @ PRTR5V0U2X_SOT143 @ PRTR5V0U2X_SOT143
    2 C695

    USB_EN# 0.1U_0402_16V4Z
    <33,43> USB_EN# 2 @
    SUYIN_020173MR004G533ZR_4P
    SUYIN_020173MR004G533ZR_4P

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 39 of 55
    A B C D E
    A B C D E

    +3VS +2.5VS_1394
    +3VS

    1 1 1 1 1 1 1 1 U36
    C696 C697 C698 C699 C700 C701 C702 C703 1 8
    A0 VCC
    2 A1 WP 7
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 6 EECK
    A2 SCL

    1
    2 2 2 2 2 2 2 2 EEDI
    1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 4 GND SDA 5
    R531
    AT24C02N-10SU-2.7_SO8 510_0402_5%
    @ @

    2
    EECK and EEDI is pull high internal
    1 +2.5VS_1394 +3VS External pull high circuit is unnecessary 1

    20mils L59
    1394@ MBK1608301YZF_0603
    +1394_PLLVDD 1394@ 0.1U_0402_16V4Z 1394@ 0.1U_0402_16V4Z 1 2 +3VS
    1 1 1 1
    C704 C705 C706 C707 When use external EEPROM
    1394@ 4.7U_0805_10V4Z
    Populate U14, R246, R253

    111

    122
    110
    U37 2 2 2 2 Un-populate R261

    46
    30
    21

    99
    36
    17

    87
    86
    73
    72
    62
    59
    5
    1394@ 0.1U_0402_16V4Z

    VDD4
    VDD3
    VDD2
    VDD1
    VCC6
    VCC5
    VCC4
    VCC3
    VCC2
    VCC1

    PVA5
    PVA4
    PVA3
    PVA2
    PVA1
    PVA0
    +3VS

    PCI_AD31 94
    VT6311S EECS 26
    27
    EECS R532 1 2
    1394@ 4.7K_0402_5%
    PCI_AD30 AD31 EEDO EEDI
    PCI_AD29
    95
    96
    AD30
    AD29
    EEPROM SDA/EEDI
    SCL/EECK
    28
    29 EECK
    PCI_AD[0..31] PCI_AD28 97
    <22,26,31,36,37> PCI_AD[0..31] PCI_AD27 AD28 C708 1
    98 AD27 PHYRST# 55 21394@ 1U_0402_6.3V4Z
    PCI_AD26 101 81 R533 1 2 @ 4.7K_0402_5% +3VS
    PCI_AD25 AD26 BJT_CTL I2CEEN R534 1
    102 AD25 I2CEN 43 2 @ 4.7K_0402_5% +3VS
    PCI_AD24 103 32 R535 1 2 1394@ 4.7K_0402_5%
    PCI_AD23 AD24 PWRDET C709 1 2 1394@ 0.1U_0402_16V4Z
    PCI_AD22
    106
    107
    AD23
    AD22
    others REG_FB 84 REG_FB

    3
    PCI_AD21 109 E
    PCI_AD20 AD21 REG_OUT REG_OUT Q43
    113 AD20 REG_OUT 85 2
    PCI_AD19 114 C710 B @ 2SB1197K_SOT23
    PCI_AD18 AD19 R536 1 C
    115 60 21394@ 1K_0402_5% 1394@ 10P_0402_50V8K

    1
    PCI_AD17 AD18 XCPS XREXT R537 1
    116 AD17 XREXT 63 2 1394@ 6.19K_0603_1% 1 2
    2 PCI_AD16 C711 1 2
    117 AD16 10mils 2 1394@ 47P_0402_50V8J

    2
    PCI_AD15 2 57 1394_XI Y5 REG_FB 40mil +2.5VS_1394
    PCI_AD14 AD15 XI 1394@
    PCI_AD13
    3
    4
    AD14
    AD13
    OSCILLATOR XO 58 1394_XO 24.576MHZ_16P_X8A024576FG1H When use external BJT
    PCI_AD12 7 Populate Q35, R279

    1
    PCI_AD11 AD12 TPB0-
    8 AD11 XTPB0M 67 1 2
    PCI_AD10 9 68 TPB0+
    PCI_AD9 AD10 XTPB0P TPA0- C712
    PCI_AD8
    10
    11
    AD9
    AD8
    PHY PORT0 XTPA0M
    XTPA0P
    69
    70 TPA0+ 1394@ 10P_0402_50V8K
    IDSEL:PCI_AD16 PCI_AD7 14 71 TPBIAS0
    PCI_AD6 15
    AD7
    AD6
    PCI I/F XTPBIAS0
    PCI_AD16 1 2 1394_IDSEL PCI_AD5 16 74
    R538 1394@ 100_0402_5% PCI_AD4 AD5 XTPB1M
    18 AD4 XTPB1P 75
    PCI_AD3
    PCI_AD2
    19
    20
    AD3
    AD2
    PHY PORT1XTPA1M
    XTPA1P
    76
    77
    PCI_AD1 24 78
    PCI_AD0 AD1 XTPBIAS1
    25 AD0
    <22,31,36,37> PCI_CBE#3 104 CBE3# NC17 83
    <22,31,36,37> PCI_CBE#2 119 CBE2# NC16 82
    <22,31,36,37> PCI_CBE#1 1 CBE1# NC15 64
    <22,31,36,37> PCI_CBE#0 12 CBE0# NC14 54
    PCI_STOP# 125 53
    <22,31,36,37> PCI_STOP# STOP# NC13
    PCI_PERR# 127 52
    <22,31,36,37> PCI_PERR# PERR# NC12
    PCI_PAR 128 51
    <22,31,36,37> PCI_PAR PAR NC11
    PCI_PIRQE# 88 50
    <22,37> PCI_PIRQE# INTA# NC10
    <22,31,36,37,39> PCI_RST# 89 PCIRST# NC9 49
    CLK_PCI_1394 90 48
    <22> CLK_PCI_1394 PCICLK NC8
    PCI_GNT#0 92 45
    <22> PCI_GNT#0 GNT# NC7
    PCI_REQ#0 93 44
    <22> PCI_REQ#0 REQ# NC6
    1394_IDSEL 105 42
    IDSEL NC5
    34 PME# NC4 41
    PCI _IRDY# 121 40
    3 <22,31,36,37> PCI_IRDY# IRDY# NC3 3
    PCI_TRDY# 123 39
    <22,31,36,37> PCI_TRDY# TRDY# NC2
    PCI_DEVSEL# 124 37
    <22,31,36,37> PCI_DEVSEL# DEVSEL# NC1
    PCI_FRAME# 120 35
    <22,31,36,37> PCI_FRAME# FRAME# NC0
    GNDARX1

    GNDARX2
    GNDATX1

    GNDATX2

    15mils
    GND19
    GND18
    GND17
    GND16
    GND15
    GND10
    GND9
    GND8
    GND7
    GND6
    GND5
    GND4
    GND3
    GND2
    GND1
    GND0

    1
    C713
    VT6311S_LQFP128 R539 R540
    66
    65
    80
    79
    118
    112
    108
    100
    91
    61
    56
    47
    38
    33
    31
    23
    22
    6
    13
    126

    1394@ 54.9_0402_1% 54.9_0402_1% 1394@ 0.33U_0603_10V7K


    1394@ 1394@ 2

    2
    TPBIAS0 JP27
    TPA0+ 4
    CLK_PCI_1394 TPA0- 4
    3 3 6 6
    TPB0+ 2 5
    2 5
    1

    TPB0- 1
    R541 1

    1
    @ 10_0402_5% FOX_UV31413-4R1-TR
    R542 R543 1394@
    54.9_0402_1% 1394@ 54.9_0402_1%
    (ECQ60)
    2

    1 1394@
    C714

    2
    @ 10P_0402_50V8K

    1
    2
    1
    C715 R544
    270P_0402_50V7K 1394@ 4.99K_0402_1%
    1394@
    2

    2
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 40 of 55
    A B C D E
    SUPER I/O SMsC LPC47N207
    +3VS

    0.1U_0402_16V4Z

    1 1 1
    C716 C717 C718
    FIR@ FIR@ FIR@
    0.1U_0402_16V4Z
    2 2 2

    0.1U_0402_16V4Z

    +3VS

    17
    31
    42
    60

    48
    5
    U38

    3.3V
    3.3V
    3.3V
    3.3V
    3.3V

    VTR
    LPC_AD0 64 +3VS
    <22,33> LPC_AD0 LAD0 +3VS
    LPC_AD1 2 27 U65
    <22,33> LPC_AD1 LAD1 GPIO10
    LPC_AD2 4 28
    <22,33> LPC_AD2 LAD2 GPIO11
    LPC_AD3 7 30 1 2 3 15 IRRX
    <22,33> LPC_AD3 LAD3 GPIO12/IO_SMI# VCC IRRX
    32 R545 @ 10K_0402_5% 14 FIR 16 IRTXOUT
    GPIO13/IRQIN1 VCC IRTX IRMODE
    GPIO14/IRQIN2 33 1 2 22 VCC IRMODE/ALT_IRRX 17
    10 34 R546 @ 10K_0402_5%
    LPC_CLK_33 GPIO15
    12 LDRQ1# GPIO16 35
    LPC_DRQ#0 24 36 LPC_FRAME# 7 19
    <22> LPC_DRQ#0 LPC_FRAME# LDRQ0# GPIO17 LPC_DRQ#0 LFRAME# INIT#

    GPIO
    <22,26,33> LPC_FRAME# 14 LFRAME# GPIO30 38 8 LDRQ# SLCTIN# 20
    PM_CLKRUN# LPC_AD0

    LPC I/F

    LPC I/F
    <22,31,36> PM_CLKRUN# 16 CLKRUN# GPIO31 39 2 LAD0 PD0 21
    SERIRQ 19 40 LPC_AD1 4 23
    <22,33,37> SERIRQ CLK_PCI_SIO SERIRQ GPIO32 LPC_AD2 LAD1 PD1
    <22> CLK_PCI_SIO 21 PCI_CLK GPIO33 41 5 LAD2 PD2 24
    NB_RST# 22 43 LPC_AD3 6 25
    <13,16,22,27,33,36> NB_RST#

    PARALLEL I/F
    CLK_14M_SIO PCIRST# GPIO34 LAD3 PD3
    <15> CLK_14M_SIO 23 SIO_14M GPIO35 44 PD4 26
    1 2 SIO_PD# 25 46 NB_RST# 9 27
    +3VS R547 1 SIO_PME# LPCPD# GPIO36 PCI_RESET# PD5
    +3VS 210K_0402_5% 47 IO_PME# GPIO37 61 PD6 28
    R548 @ 10K_0402_5% SIO_PD# 10 29
    LPCPD# PD7
    SLCT 30
    PM_CLKRUN# 11 31
    CLKRUN# PE
    BUSY 32
    SERIRQ 13 33
    RXD1 SER_IRQ ACK#
    63 DLAD0 RXD1 52 ERROR# 34
    TXD1 CLK_PCI_SIO
    SERIAL I/F

    1 DLAD1 TXD1 53 12 PCI_CLK ALF# 35


    3 54 DSR#1 36
    DLAD2 DRSR1# RTS#1 CLK_14M_SIO STROBE#
    6 DLAD3 RTS1#/SYSOPT0 55 1 2 1 CLOCKI
    CTS#1 R549 @ 10K_0402_5%
    DLPC I/F

    CTS1# 56
    57 DTR#1 1 2 +3VS 1 2 BASE_ADDRESS 18 GPIO/SYSOPT1 37
    DTR1#/SYSOPT1 RI#1 R550 @ 10K_0402_5% R802 @ 10K_0402_5% VSS
    9 DLPC_CLK_33 RI1# 58 GROUND PAD
    11 59 DCD#1 1 2
    DLDRQ1# DCD1# R803 10K_0402_5% SIO1036-AEZG_QFN36
    13 DLFRAME#
    15 49 IRTXOUT SIO2@ Base I/O Address SIO2@
    DCLKRUN# IRTX2 IRRX
    18 DSER_IRQ IRRX2 50 1 2 * 0 = 004Eh
    IRMODE R551 FIR@
    IR

    26 DSIO_14M IRMODE/IRRX3 51
    10K_0402_5%
    GND0
    GND1
    GND2
    GND3
    GND4
    GND5

    LPC47N207-JN_STQFP64
    8
    20
    29
    37
    45
    62

    RTS#1
    Base I/O Address
    CLK_14M_SIO CLK_PCI_SIO * 0 = 02Eh
    1 = 04Eh
    2

    R552 R553
    @ 10_0402_5% @ 33_0402_5%
    1

    2 2
    C719 C720 +IR_ANODE
    @ 15P_0402_50V8J @ 22P_0402_50V8J
    1 1
    +3VS 1 FIR@ 2
    R554 0_1206_5%
    1 1 FIR@ 2
    C721 R555 0_1206_5%
    FIR@

    FIR Module 2
    4.7U_0805_10V4Z
    W=60mil
    Place on the BOT side(near MINIPCI conn.)
    IR1
    +5VS 1
    JP28 +IR_3VS IRED_A IRTXOUT
    2 IRED_C TXD 3 T = 12mil
    +3VS IRRX 4 5 T = 12mil IRMODE
    1 RP10 RXD SD/MODE
    2 +3VS 1 FIR@ 2 +IR_3VS 6 VCC MODE 7
    RXD1 DCD#1 1 8 R556 W=40mil 8
    TXD1 3 RI#1 47_1206_5% GND
    4 2 7 1 1
    DSR#1 CTS#1 3 6 C722 C723 TFDU6102-TR3_8P
    RTS#1 5 DSR#1 FIR@ FIR@
    6 4 5 FIR@
    CTS#1 10U_0805_10V4Z 0.1U_0402_16V4Z
    DTR#1 7 4.7K_1206_8P4R_5% 2 2
    RI#1 8 FIR@
    DCD#1 9
    10
    @ ACES_85201-10051

    For SW debug use when no seial port

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    www.laptopfix.vn
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 41 of 55
    A B C D E

    Power ON Circuit
    +3VALW

    2
    C724 +3VALW +3VALW +3VALW
    0.1U_0402_16V4Z
    1

    14

    14

    14

    14
    1 1
    R557 R558 R559
    470K_0402_5% 200K_0402_5% 10_0402_5%

    P
    VLDT_EN 1 2 1 2 3 4 1 2 5 6 9 8 1 2
    <33,46> VLDT_EN I O I O I O I O SB_PWRGD <7,23>

    G
    1 U39A U39B 1 U39C U39D
    SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

    7
    R560 C725 C726
    10K_0402_5% 0.1U_0402_16V4Z 0.47U_0603_16V7K
    2 2
    2

    note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,


    R561
    10_0402_5% SUSP# goes to low after SB_PWRGD goes to low for power
    1 2 NB_PWRGD <13> down.
    T1

    VLDT_EN

    NB_PWRGD

    SB_PWRGD
    T2
    SUSP#
    2 2

    +1.8VS

    ON/OFF switch
    TOP Side
    2 1
    J2 @ JOPEN
    2 1
    J3 @ JOPEN +3VALW
    Bottom Side
    3
    Power Button +3VALW
    3
    2

    R562

    1
    100K_0402_5%
    R563
    Lid Switch
    1

    D25 100K_0402_5%
    2 ON/OFF <33>
    ON/OFFBTN# 1
    <43> ON/OFFBTN#

    2
    3 51ON# Change P/N : SN111000207
    51ON# <47>
    SW7
    DAN202U_SC70 3 1 LID_SW# <33>

    3
    1

    2 4 2
    C727 D27 D26
    MPU-101-81_4P @
    1000P_0402_50V7K RLZ20A_LL34 PSOT24C_SOT23
    1
    2005/09/04
    2

    1
    1

    D
    EC_ON 2 Q44
    <33> EC_ON
    G
    2

    S 2N7002_SOT23
    3

    4 4
    R564

    10K_0402_5%
    1

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 42 of 55
    A B C D E
    R565 LED1
    300_0402_5%
    +5VS 1 2 2 1 PWR_LED#
    PWR_LED# 3

    HT-110UYG_1204

    1
    D
    <33> PWR_LED 2
    G
    S Q45 R566 LED2

    3
    2N7002_SOT23 300_0402_5%
    +5VALW 1 2 2 1 PWR_SUSP_LED# PWR_SUSP_LED# <33>
    3

    HT-110UD_1204

    +5VS +5VS R567 LED3 +5VALW


    300_0402_5%
    +5VALW 1 2 2 1 BATT_GRN_LED# BATT_GRN_LED# <33>
    1

    3 1
    R568 R569 C728
    HT-110UYG_1204 + C729
    300_0402_5% 300_0402_5% 0.1U_0402_16V4Z
    To LED/B Conn. 150U_D_6.3VM
    2

    2
    3
    2

    3
    2

    LED4 LED5
    HT-110UD_1204 HT-110NBQA_BULE_1204 R570 LED6 +5VS
    300_0402_5% JP29
    +5VALW 1 2 2 1 BATT_AMB_LED# BATT_AMB_LED# <33> 1 2 +5VALW
    PWR_LED# 1 2
    3 3 4
    1

    3 4
    <33> MEDIA_LED# 5 5 6 6
    WL_LED# BT_LED# HT-110UD_1204 7 8
    WL_LED# <33> BT_LED# <33> <33> CAPS_LED# 7 8
    9 10 USB20_N3
    <33> NUM_LED# 9 10 USB20_N3 <23>
    <33> E-MAIL_LED# 11 12 USB20_P3
    11 12 USB20_P3 <23>
    <42> ON/OFFBTN# 13 13 14 14
    15 16 USB20_N6
    <33> E-MAIL_BTN# 15 16 USB20_N6 <23>
    17 18 USB20_P6
    <33> IE_BTN# 17 18 USB20_P6 <23>
    <33> USER_BTN# 19 19 20 20
    <33> EMPWR_BTN# 21 21 22 22 USB_EN# <33,39>
    23 23 24 24
    <36> CVBS_IN 25 25 26 26
    <36> S_YIN 27 27 28 28 AUDIO_INL <36>
    29 30

    GND
    GND
    GND
    GND
    GND
    GND
    <36> S_CIN 29 30 AUDIO_INR <36>

    ACES_88018-304G

    31
    32
    33
    34
    35
    36
    BT_SW WL_SW
    5

    2005/09/12 2005/09/12
    1 1
    5

    1 1

    2 2 2 2

    3 3 3 3

    4 BTSW_EN# 4 WLSW_EN#
    4 BTSW_EN# <33> 4 WLSW_EN# <33>
    6

    SW8 SW9
    6

    HSS110_4P HSS110_4P
    +3VALW
    1

    Update Part Number to SCR36236000


    R571
    100_0805_5%
    CIR@ CIR
    2

    IR2
    3 4 RCIRRX
    Vs OUT RCIRRX <33>
    1 GND GND 2
    1
    C730 CIR@ TSOP36236TR_4P 1
    CIR@ C731
    4.7U_0805_10V4Z CIR@
    2 1000P_0402_50V7K
    2

    Geneva 2005/09/04 Grapevine

    KSO16 KSO17 KSO16 KSO17


    KSI0 VOL_UP LEFT
    KSI1 RIGHT VOL_DOWN
    KSI2 PLAY ENTER KSI2 PLAY
    KSI3 STOP KSI3 STOP VOL_UP
    KSI4 NEXT KSI4 NEXT VOL_DOWN
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
    KSI5 REV KSI5 REV ARCADE_TV SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    KSI6 RECORD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    www.laptopfix.vn
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 43 of 55
    A B C D E F G H

    +VDDA
    28.7K for Module Design (VDDA = 4.702)

    1
    R689 +5VAMP (output = 250 mA)
    10K_0402_5% 60mil U34
    +5VS L32 1 2 4 VIN VOUT 5 40mil +VDDA
    KC FBM-L11-201209-221LMAT_0805

    2
    1 1 2 DELAY SENSE or ADJ 6 1 4.85V
    1 2 L33 1 2 C550 C553 R452
    C542 1U_0603_10V4Z KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C558
    ERROR CNOISE

    1
    10U_0805_10V4Z 10U_0805_10V4Z
    R688 2 2
    0.1U_0402_16V4Z 2
    8 3 1

    1
    10K_0402_5% SD GND C548
    1 SI9182DH-AD_MSOP8 1
    R430

    1
    C527 1 2 1 2
    <33> BEEP#

    2
    1U_0402_6.3V4Z C535 2
    560_0402_5% 1 2 MONO_IN R451
    0.1U_0402_16V4Z 10K_0402_1%
    1U_0402_6.3V4Z

    2
    1
    C 1 2
    C528 1 R433 Q19
    <37> PCM_SPK# 2 1 2 2 R687
    1U_0402_6.3V4Z B
    560_0402_5% E 2SC2411K_SC59 2.4K_0402_5%

    3
    C533 1 R438
    <23> SB_SPKR 2 1 2
    1U_0402_6.3V4Z

    1
    560_0402_5%
    D16
    R442 RB751V_SOD323
    10K_0402_5%

    2
    HD Audio Codec
    Modify 11/07 for EMI
    +AVDD_AC97
    20mil 0.1U_0402_16V4Z L74 1 2 +3VS
    FBM-L11-160808-800LMT_0603
    L34 1 2 0.1U_0402_16V4Z 40mil 1 1 1
    +VDDA
    FBM-L11-160808-800LMT_0603 1 1 1 C537 C539 C532
    C545 C559
    2 C549 10U_0805_10V4Z 2
    10U_0805_10V4Z 2 2 2

    25

    38

    9
    2 2 2 U33
    0.1U_0402_16V4Z 0.1U_0402_16V4Z

    AVDD1

    AVDD2

    DVDD1

    DVDD2
    14 35 AMP_LEFT
    LINE2_L FRONT_OUT_L AMP_LEFT <45>
    15 36 AMP_RIGHT
    LINE2_R FRONT_OUT_R AMP_RIGHT <45>
    16 MIC2_L SURR_OUT_L 39

    17 MIC2_R SURR_OUT_R 41

    LINE_L 1 2 LINE_C_L 23 45
    <45> LINE_L LINE1_L SIDESURR_OUT_L
    C556 1U_0603_10V4Z
    LINE_R 1 2 LINE_C_R 24 46
    <45> LINE_R LINE1_R SIDESURR_OUT_R
    C557 1U_0603_10V4Z
    1 2 CD_L_RC 18 43
    C543 @ 1U_0603_10V4Z CD_L CEN_OUT
    1 2 C D_R_RC 20 44
    C546 @ 1U_0603_10V4Z CD_R LFE_OUT
    1 2 CD_AGND_RC19 C538 1 2 22P_0402_50V8J
    C544 @ 1U_0603_10V4Z CD_GND
    BIT_CLK 6 ICH_BITCLK_AUDIO <23>
    MIC1_L 1 2 MIC1_C_L 21
    <45> MIC1_L MIC1_L
    C547 1U_0603_10V4Z
    MIC1_R 1 2 MIC1_C_R 22 8 R443 1 2 33_0402_5% ICH_AC_SDIN0 <23>
    Modify 11/07 for EMI <45> MIC1_R MIC1_R SDATA_IN
    C554 1U_0603_10V4Z
    MONO_IN 12 37
    PCBEEP PIN37_VREFO
    2005/09/12
    LINE1_VREFO 29
    3 3
    1 2 <23> ICH_RST_AUDIO# 11 RESET#
    R826 0_0603_5% 31
    LINE2_VREFO
    <23> ICH_SYNC_AUDIO 10 SYNC 10mil
    MIC1_VREFO_L 28 MIC1_VREFO_L
    1 2 <23> ICH_SDOUT_AUDIO 5 SDATA_OUT
    R827 0_0603_5% 32
    MIC1_VREFO_R MIC1_VREFO_R
    2 GPIO0
    <45> NBA_PLUG 3 GPIO1 MIC2_VREFO 30
    1
    R589
    2
    0_0603_5%
    13 SENSE A AC97_VREF
    10mil
    34 SENSE B VREF 27
    1
    <33> EAPD 47 SPDIFI/EAPD JDREF 40
    1 2 C561

    1
    R590 0_0603_5% L75
    1 2 48 33 10U_0805_10V4Z
    <45> SPDIF FBM-L11-160808-800LMT_0603 SPDIFO VAUX R445 2
    4 26 20K_0402_1%
    DVSS1 AVSS1
    1 2 7 DVSS2 AVSS2 42 @
    R592 0_0603_5%
    2

    ALC883-LF_LQFP48

    DGND AGND
    GND GNDA

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 44 of 55
    A B C D E F G H
    A B C D E

    JP12
    SPKL+ R462 1 2 0_0603_5% SPK_L+
    SPKL- R464 0_0603_5% SPK_L- 1
    1 2 2
    +5VAMP SPKR+ R466 1 2 0_0603_5% SPK_R+
    SPKR- R469 0_0603_5% SPK_R- 3
    1 2 4

    1
    20mil ACES_85204-0400
    R458 Speaker Conn.
    10K_0402_5%
    1 1

    2
    VOL_AMP +5VAMP
    (0.65V -> 10dB ) W=40mil +5VAMP

    1
    R455 R457 1 1

    1
    @ +5VAMP
    5.1K_0402_1% 1.5K_0402_1% C881 C892 R467
    0.1U_0402_16V4Z 4.7U_0805_10V4Z 100K_0402_5% +5VAMP
    1 2

    1
    2 2
    D R468 R698

    2
    SPDIF_PLUG# 2 100K_0402_5% 100K_0402_5%

    3
    S
    Q20 G 1 2 G
    2N7002_SOT23 @ S U56 2 SPDIF_PLUG#
    3

    2
    10 1 EC_MUTE NBA_PLUG
    VDD MUTE EC_MUTE <33> <44> NBA_PLUG
    15 2 Q22
    VDD SHUTDOWN#

    1
    C882 2 D
    1 0.1U_0402_16V4Z D SI2301BDS_SOT23
    9 SPKL- 2 SPDIF_PLUG#

    1
    VOL_AMP LOUT- G Q21
    7 VOLUME
    16 SPKR- S 2N7002_SOT23

    3
    VOLMAX ROUT-
    2
    R690
    1
    0_0402_5%
    8 VOLMAX SPKL+
    +5VSPDIF 20mil
    LOUT+ 11
    NBA_PLUG 13 SE/BTL# SPKR+
    <44> AMP_LEFT 1 2 ROUT+ 14
    C566 1U_0402_6.3V4Z AMP_LEFT_C 6
    AMP_RIGHT_C LIN-
    <44> AMP_RIGHT 1 2 3 RIN-
    C568 1U_0402_6.3V4Z 5
    BYPASS GND
    4 BYPASS GND 12
    20mil
    1 APA2068KAI-TRL_SOP16

    C886
    4.7U_0805_10V4Z
    2 2 2
    2 2
    C563 C562

    330P_0402_50V7K
    S/PDIF Out JACK
    330P_0402_50V7K
    1 1

    JP40
    1
    SPKL+ 2 HPOUT_L_1 HPOUT_L_2 HPOUT_L_3

    +
    1 1 2 1 2 2
    C891 150U_D_6.3VM R702 47_0603_5% L51 FBM-11-160808-700T_0603 6
    SPKR+ 2HPOUT_R_1 HPOUT_R_2 HPOUT_R_3

    +
    1 1 2 1 2 3
    C888 150U_D_6.3VM R699 47_0603_5% L50 FBM-11-160808-700T_0603
    +5VAMP 2 1 SPDIF_PLUG# 5
    R456 100K_0402_5%
    4

    1
    SPDIF 7
    <44> SPDIF
    R651 R652 +5VSPDIF 8
    @ 1K_0402_1% @ 1K_0402_1% 10

    9
    2

    2
    ACES_20234-0101

    LINE-IN JACK
    JP41
    5

    4
    3 L48 FBM-11-160808-700T_0603 3
    LINE_R 1 2 LINE_R_R 3
    <44> LINE_R
    6
    LINE_L 1 2 LINE_L_R 2
    <44> LINE_L
    L49 FBM-11-160808-700T_0603 1
    1 1
    SUYIN_010164FR006G118ZL
    C885 C884
    220P_0402_50V7K 220P_0402_50V7K
    2 2

    MIC1_VREFO_L MIC1_VREFO_R
    MIC JACK
    1

    1
    JP42
    Int MIC Conn. R775 R776
    5

    2.2K_0402_5% 2.2K_0402_5% 4
    2

    2
    JP13 15mil 1 2 FBM-11-160808-700T_0603 MIC1_R_1 3
    <44> MIC1_R
    INT_MIC_L L54 6
    1 MIC1_L_1
    2 <44> MIC1_L 1 2 FBM-11-160808-700T_0603 2
    L35 1
    ACES_85204-0200 1 1
    SUYIN_010164FR006G118ZL
    C569 C876
    220P_0402_50V7K 220P_0402_50V7K
    4 2 2 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 45 of 55
    A B C D E
    A B C D E

    +VDD_CORE
    +1.8VS

    2
    +5VS R843
    470_0402_5% R610
    470_0402_5%

    1
    R614

    1
    1 470_0402_5% 1

    1
    +5VALW +5VS +1.8VALW D
    +5VALW TO +5VS +1.8VALW TO +1.8V

    1
    D
    U43 2 SUSP

    1
    8 D S 1 U44 G 2 SUSP
    7 2 8 1 +1.8V S Q46 G

    3
    D S D S

    1
    D 2N7002_SOT23 Q28
    6 3 1 1 7 2 S

    3
    D S C770 C771 D S
    5 D G 4 2 SUSP 6 D S 3 2N7002_SOT23
    G 5 4 1 1
    SI4800DY_SO8 4.7U_0805_10V4Z 1U_0603_10V4Z Q32 D G C772 C773
    1 S

    3
    2 2 2N7002_SOT23 SI4800DY_SO8

    5VS_GATE3
    C774 1 4.7U_0805_10V4Z 1U_0402_6.3V4Z
    4.7U_0805_10V4Z 2 2
    2 C775 11/17 modify
    R611 4.7U_0805_10V4Z R612
    100K_0402_5% 2 100K_0402_5%
    5VS_GATE0 1 2 +VSB 1 2 +VSB +1.8V
    2 +3VS 2
    1

    1
    C776 D C777 D

    2
    2 SUSP 2 SYSON#

    2
    0.1U_0603_25V7K G 0.1U_0603_25V7K G R613
    1 S Q29 R609 1 S Q30 470_0402_5%
    3

    3
    2N7002_SOT23 470_0402_5% 2N7002_SOT23

    1
    1

    1
    D
    +1.8VALW TO +1.8VS

    1
    D
    2 SYSON#
    2 SUSP G
    2 +3VS G D29 D30 D31 S Q31 2
    +3VALW TO +3VS

    3
    S Q27 CH751H-40_SC76 CH751H-40_SC76 CH751H-40_SC76 2N7002_SOT23

    3
    2N7002_SOT23 +3VS 2 1 2 1 2 1
    1 1
    +3VALW C778 C779

    U46 10U_0805_10V4Z 1U_0402_6.3V4Z +1.8VALW


    2 2
    8 D S 1
    7 2 R615 U45
    D S 100K_0402_5%
    6 D S 3 8 D S 1 +1.8VS
    5 4 5VS_GATE1 1 2 7 2 +5VALW
    D G +VSB D S
    6 D S 3
    SI4800DY_SO8 5 4 1 1
    D G

    2
    C780 C781 +0.9VS
    1

    SI4800DY_SO8 R616

    5VS_GATE4
    1 1
    1

    C783 C784 R617 D 4.7U_0805_10V4Z 1U_0402_6.3V4Z 10K_0402_5%


    1

    2
    @ 1M_0402_1% SUSP 2 2
    2
    10U_0805_10V4Z 0.22U_0603_16V7K G C782 R620

    1
    2 2 S Q33 4.7U_0805_10V4Z R619 470_0402_5% SUSP
    <52> SUSP
    2

    2N7002_SOT23 2 R618 100K_0402_5%

    1
    1 2 1 2 +VSB

    1
    47K_0402_5%
    1

    1
    C785 D D
    100K
    2 SUSP 2 SUSP 2
    <33,35,39,51,53> SUSP#
    0.22U_0603_16V7K G G
    2 S Q34 S Q36

    3
    2N7002_SOT23 2N7002_SOT23 DTC115EKA_SOT23 100K
    Q35

    3
    3 3

    +1.2VS
    +1.2VS TO +1.2V_HT +0.9VS
    U47
    +0.9V TO +0.9VS
    8 D S 1 +1.2V_HT
    7 D S 2 1 1
    6 3 +0.9V C791 C792 +5VALW
    D S +1.2V_HT
    5 D G 4 1 1
    C786 C787 U48 10U_0805_10V4Z 1U_0402_6.3V4Z

    2
    SI4800DY_SO8 2 2
    8 D S 1

    2
    1 4.7U_0805_10V4Z 1U_0402_6.3V4Z 7 2 R627 R622
    2 2 +5VALW D S 100K_0402_5% R623 10K_0402_5%
    6 D S 3
    C788 5 4 5VS_GATE5 1 2 470_0402_5%
    D G +VSB
    4.7U_0805_10V4Z R624

    1
    2

    2 100K_0402_5% SI4800DY_SO8 SYSON#


    <52> SYSON#

    1
    5VS_GATE2 1 2 +VSB R621
    1

    1
    10K_0402_5% 1 1

    1
    C793 C794 R628 D D
    2
    1

    C789 D @ 1M_0402_1% SUSP


    2 2 VLDT_EN#
    1

    2 VLDT_EN# 10U_0805_10V4Z @ 0.22U_0603_16V7K G G


    2 2 100K
    0.1U_0603_25V7K G S Q41 S Q39 SYSON 2
    <33,39> SYSON
    2

    3
    1 S Q40 2N7002_SOT23 2N7002_SOT23
    3

    2N7002_SOT23
    DTC115EKA_SOT23 100K
    Q38

    3
    1

    4 4

    100K
    VLDT_EN 2
    <33,42> VLDT_EN

    DTC115EKA_SOT23
    Q37
    100K Security Classification Compal Secret Data Compal Electronics, inc.
    Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
    3

    SCHEMATIC, M/B LA-3151P


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401412 B
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: 星期四, 三月 09, 2006 Sheet 46 of 55
    A B C D E
    A B C D

    PJP1
    SINGA_2DC-G756-I06 PL1
    ADPIN VIN
    FBMA-L18-453215-900LMA90T_1812
    1 1 2

    1
    PR1
    G 2 10_1206_5%

    12P_0402_50V8J
    560P_0402_50V7K
    G

    12P_0402_50V8J

    560P_0402_50V7K
    1 3 PR2 1

    1 2
    1

    1
    PC1
    1K_1206_5%

    PC2

    PC3

    PC4
    1 2
    PD1 PQ1

    2
    RLZ24B_LL34 TP0610K-T1-E3_SOT23
    PR3
    VIN PD2 1K_1206_5%
    B+

    2
    2 1 1 2 3 1

    RLS4148_LLDS2 PR4
    1K_1206_5%
    1 2

    100K_0402_5%

    100K_0402_5%
    1

    1
    PR5
    PR7

    PR6
    1K_1206_5%

    2
    1 2

    2
    VIN

    1
    PD3
    PD4 RLS4148_LLDS2 PR8

    1
    RB751V_SOD323 100K_0402_5%
    PQ2

    1 1
    2 1 DTC115EUA_SC70

    1 2
    BATT+
    2 PR9 <33,49> ACOFF 2 2

    33_1206_5% VS
    PQ4
    TP0610K-T1-E3_SOT23 PQ3
    2 2 DTC115EUA_SC70

    3
    CHGRTCP 3 1
    0.22U_1206_25V7K
    1

    3
    1

    PR10
    PC5

    100K_0402_5% PC6
    0.1U_0603_25V7K
    2

    PR11
    B+
    2

    22K_0402_5% PR12
    <42> 51ON# 1 2 VL 2.2M_0402_5%
    2 1

    1
    VS PR13
    499K_0402_1%

    1
    1

    PR14

    2
    RTCVREF 100K_0402_1%
    PU1 PR15 PU2A
    3.3V G920AT24U_SOT89 200_0805_5% LM393DR_SO8

    8
    PR16 PD5
    2

    560_0603_5% PR17 <7,48,50> MAINPWON 2 3

    P
    3 3

    +CHGRTC +
    1 2 1 2 3 OUT IN 2 1 1 O

    0.01U_0402_25V7K
    <49> ACON 3 - 2
    1

    1
    4.7U_0805_6.3V6K

    560_0603_5%
    1

    1
    GND
    PC8

    PC9
    32.3
    1000P_0402_50V7K
    PC7 RB715F_SOT323 PR18

    4
    1

    1
    1U_0805_25V4Z PC10 191K_0402_1% PR19
    2

    PC11
    0.1U_0603_25V7K 499K_0402_1%
    2

    2
    2

    PRG++ 2

    2
    ACIN PQ5
    PR20 MF2N7002W-G_SOT323-3 PR21
    Precharge detector

    1
    34K_0402_1% D 47K_0402_5%
    Min. typ. Max. RTCVREF 2 1
    G
    2 2 1
    PACIN <49,50>

    1
    H-->L 14.589V 14.84V 15.243V S

    3
    1
    PQ6
    L-->H 15.562V 15.97V 16.388V @ PR22 DTC115EUA_SC70
    66.5K_0402_1% 2 +5VALW
    BATT ONLY

    2
    Precharge detector

    3
    Min. typ. Max.
    4
    H-->L 6.138V 6.214V 6.359V 4

    L-->H 7.196V 7.349V 7.505V

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/0926 Deciphered Date 2006/0926 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    B B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 47 of 55
    A B C D
    A B C D

    B+
    FBM-L11-322513-151LMAT_1210
    2
    PL2

    PC12 PC13
    1

    0.1U_0603_25V7K 0.1U_0603_25V7K

    2
    1 2 BST5B BST3B 1 2

    1 B+++ PD6 1

    30.6 CHP202UPT_SOT323-3
    2200P_0402_50V7K

    PQ7 VL

    4.7U_1206_25V6K
    8 1

    1
    G2 D2
    7 D1/S2/K D2 2
    1

    2
    PC15

    6 3 DL5
    D1/S2/K G1
    PC14

    5 4 PR23 B+++
    D1/S2/K S1/A

    47_0402_5%
    0_0603_5% B+++ PQ8
    2

    1
    4.7_1206_5%

    4.7_1206_5%

    2200P_0402_50V7K
    AO4916_SO8 1 8
    D2 G2

    4.7U_1206_25V6K
    PR24
    PR27 PC16 2 7

    1
    D2 D1/S2/K

    PR25

    PR26
    0_0603_5% 0.1U_0603_25V7K 3 6

    2
    G1 D1/S2/K

    1
    5HG 1 2 DH5 4 5

    1
    S1/A D1/S2/K

    PC17

    PC18
    @

    1 2

    2
    AO4916_SO8

    2
    1U_1206_25V7K

    2
    PC19

    0.1U_0603_25V7K
    LX5
    VL PR28

    2
    0_0603_5%
    2VREF_1999

    4.7U_0805_10V4Z

    1 PC22
    3HG

    1
    1U_0805_16V7K

    499K_0402_1% 100K_0402_1%

    100K_0402_1%
    1

    2
    PC20

    PR29

    PR30
    1
    BST3A

    PC21
    LX3

    2
    2

    2
    PR31

    2 1

    2 1
    2

    0_0603_5%

    18

    20

    13

    17

    PR32

    499K_0402_1%
    PL3 BST5A 14

    V+
    LD05

    TON

    VCC

    1
    BST5

    PR33
    2 10UH_SIL104R-100PF_4.4A_30% 5 2
    ILIM3 DL3
    16
    +5VALWP DH5
    1

    2
    15 LX5
    19 11 PL4
    DL5 ILIM5
    21 OUT5
    9 PU3 28 10UH_SIL104R-100PF_4.4A_30%
    FB5 BST3
    10.2K_0402_1%

    1 26 DH3
    N.C.MAX8734AEEI+_QSOP28 DH3
    2

    24

    1
    DL3
    PR34

    6 SHDN# LX3 27
    VS 4 22
    1 ON5 OUT3
    1 2 3 ON3
    150U_D_6.3VM

    + @ PR35 7
    1

    FB3
    PC23

    0_0402_5% 12 2 +3VALWP
    SKIP# PGOOD
    2 2VREF_19998

    PRO#

    3.57K_0402_1%
    LDO3
    PZD1 PR37

    GND
    REF
    2

    2
    0_0402_5%

    RLZ5.1B_LL34 47K_0402_5% PR38


    PR36

    @ PR39
    1 2 1 2 1 2

    23

    25

    10
    2

    0.047U_0603_16V7K

    0.22U_0603_16V7K
    100K_0402_5%

    0_0402_5% 1

    150U_D_6.3VM
    PR40

    PC24

    4.7U_0805_10V4Z
    1

    1
    1

    PC26

    PC25
    +
    2

    2
    PC27
    <50> SPOK
    1

    2
    2

    PR42
    0_0402_5%
    PR41
    0_0402_5%

    2
    PR43
    47K_0402_5%

    1
    1 2
    3 3
    1

    PC28
    0.047U_0603_16V7K
    Imax=3.5A +3.3V Iocp =5.36A ~ 9.03A
    2

    Ipeak=4.5A
    Imax=3.5A
    +5V Iocp = 5.35A ~8.65 A Ipeak=4.5A

    MAINPWON <7,47,50>
    1

    PC29
    1U_0603_16V6K
    2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 48 of 55
    A B C D
    A B C D E

    Charger
    Iadp=0~4.5A(90W)

    P2
    PQ9 PQ10 PR44 B+ PL5 CHG_B+ PQ11
    AO4407L_SO8~N AO4407L_SO8~N P3 0.015_2512_1% AO4407L_SO8~N
    FBMA-L18-453215-900LMA90T_1812
    VIN 8
    7
    1
    2
    1
    2
    8
    7
    1 4 1 2 1
    2
    8
    7

    2200P_0402_25V7K
    0.1U_0603_25V7K
    6 3 3 6 2 3 3 6

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    5 5 5

    1
    1 1

    PC30

    PC31

    PC32

    PC33
    4

    4
    1
    PC34 PR45

    2
    1
    0.1U_0603_25V7K PC35 47K_0402_1%

    1
    0.1U_0603_25V7K 1 2
    VIN

    2
    PR46

    2
    1

    10K_0402_1%
    0.1U_0603_25V7K

    SI4810BDY-T1-E3_SO8
    200K_0402_1%

    2
    PR47

    5
    6
    7
    8
    47K_0402_5%

    2
    1

    PR48
    D
    D
    D
    D
    3

    PC36
    PQ13 CSSN
    2

    PQ12
    DTA144EUA_SC70 PD9 CSSP

    1
    47K
    1SS355_SOD323 ACOFF#

    G
    S
    S
    S
    2 47K VIN 2 1

    4
    3
    2
    1

    1
    <50> 6C/8C#

    2
    G
    PC37 PQ14
    0.1U_0603_25V7K PQ15 DTC115EUA_SC70

    SI4810BDY-T1-E3_SO8
    SI2301DS_SOT23~D 3 1 PU4
    1

    2
    1

    ACOFF

    D
    1 DCIN 2 ACOFF <33,47>

    5
    6
    7
    8
    CSSP 27
    PC38

    D
    D
    D
    D

    1
    1U_0603_10V6K 29

    2
    TP

    PQ17
    2 PQ16 2 1 17 @ PC39

    3
    DTC115EUA_SC70 10K_0402_0.1% @ PR49 CELLS 1000P_0402_50V7K
    26

    2
    CSSN

    G
    S
    S
    S
    PR50 0_0402_5%
    2 1 4

    4
    3
    2
    1
    REF
    150K_0402_5%

    25 charger_DHI PR52
    3

    DHI
    1

    3 0.015_2512_1%
    CLS
    PR51

    10UH_SIL104R-100PF_4.4A_30%
    1908LDO BATT+
    1

    D charger_LX
    LX 23 1 2 1 4
    1
    90.9K_0402_0.1%

    2 PQ18 2 1 2 1 12 REFIN
    1

    2 G MF2N7002W-G_SOT323-3 2
    2 3
    2

    2
    PR55

    S PC40 PR53 PR54 21 charger_DLO


    3

    DLO

    4.7U_1206_25V6K

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    PL6
    0.1U_0402_16V7K 9.31K_0402_1% 15K_0402_1% PR56 PC41
    2

    15 0_0402_5% 0.1U_0603_25V7K
    2

    1
    VCTL

    1
    PC42

    PC43

    PC44
    13 24 charger_BST 1 2
    ICTL BST

    1
    11

    2
    ACOK# charger_DLOV PD10
    8 SHDN# DLOV 22
    1

    D PR58 10 ACIN 1SS355_SOD323


    2 PQ19 24.9K_0402_1% 9 2 2 1
    ICHG LDO

    0.01U_0402_25V7K
    G MF2N7002W-G_SOT323-3 2 1

    2
    PC45
    S <33> IREF 28 PR57
    3

    IINP 1908LDO 33_1206_5%


    7

    2
    CCV
    CSIP 19
    1

    2
    PGND
    PD11 18

    GND
    CCS
    CSIN

    CCI
    1N4148_SOD80 PR59 16 PC46
    BATT

    2
    ACOFF# 1 2 100K_0402_1% 1U_0603_10V6K

    1
    10K_0402_1%
    MAX1908ETI+T_QFN28 PC47

    14

    20
    2
    1U_0805_25V4Z
    2

    1
    PR60
    PR61 MAX1908-CCS
    22K_0402_5%

    0.1U_0402_16V7K

    0.01U_0402_25V7K

    0.01U_0402_25V7K
    <47,50> PACIN 1 2

    1
    CSIP

    2
    PC48

    PC49
    1
    PC50

    1
    CSIN
    <47> ACON

    2
    3 BATT+ 3

    PR62
    CP Point: 0_0402_5%
    Charge voltage
    1 2
    <33> FSTCHG VS BATT+
    Iinput=(90.0K/100.9K)*(75/15)=4.504A
    4S CC-CV MODE : 16.8V
    2

    1
    10K_0402_5%

    1
    PR64

    PR65

    0.01U_0402_25V7Z
    PR63 PC51 845K_0603_1%
    100K_0402_5% 0.1U_0402_16V7K
    2

    LI-4S :17.8V--BATT-OVP=1.9758V
    1

    2
    1

    PC52
    +3VALW
    BATT-OVP=0.111*BATT+

    1
    2
    PR66

    1
    300K_0603_0.1%
    IREF=0.832*Icharge PR68 PR67

    8
    PU5A 511K_0402_1% 10K_0402_5%

    2
    IREF=0.73~3.3V 3 1 2

    P
    +
    1

    2
    0
    VS <33> BATT_OVP - 2

    1
    D PQ20

    1
    LM358ADR_SO8 MF2N7002W-G_SOT323-3
    2

    1
    PR69 PC53 G
    2P4S:4800mAH/cell
    8

    PU5B 200K_0402_1% 0.01U_0402_25V7Z S

    1
    D
    0.8C=3.84A 5
    P

    2
    +
    7 2 6C/8C# <50>

    2
    0 G
    - 6
    G

    S PQ21

    3
    4 LM358ADR_SO8 MF2N7002W-G_SOT323-3 4
    4

    OVP voltage :
    LI-3S :17.8V----BATT-OVP=1.9758V
    BATT-OVP=0.111*BATT+ Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 49 of 55
    A B C D E
    A B C D

    PR70
    100K_0402_5%
    1 2
    PH1 under CPU botten side :
    +3VALWP
    BATT+ BATT++ CPU thermal protection at 90 degree C
    PR71
    PL7 1K_0402_5%
    Recovery at 70 degree C

    BATT+
    2 1
    FBMA-L18-453215-900LMA90T_1812 6C/8C# <49>
    1 2 BATT++
    1
    VL 1

    VS VL
    1

    2
    PC54
    0.01U_0402_25V7Z PC55 @PR72

    2
    1000P_0402_50V7K 1K_0402_5%
    2

    1
    PR75 PC56 PR76 PR73
    1K_0402_5% PR74 0.1U_0603_25V7K 442K_0603_1% 150K_0402_1%

    1
    1 2 BATT_TEMP 9.76K_0402_1% 1 2

    2
    BATT_TEMP <33>

    1
    2
    PR77

    8
    82.5K_0603_1% PU2B
    PR78 1 2 5

    P
    7 1K_0402_5% + MAINPWON <7,47,48>
    PJP2 battery connector 6
    2 1 TM_REF1 6
    O 7
    5 -

    G
    100K_0603_1%_TH11-4H104FT
    4

    1
    SM ART PR79 LM393DR_SO8

    4
    3 6.49K_0402_1%
    Batter y: 2

    PH1
    1 1 2 +3VALWP

    1U_0805_16V7K
    1 .GND
    2. SMC

    2
    1

    1
    SUYIN_200275MR007G161ZL

    PC58
    PC57 PR80
    PJP2 PR81 1000P_0402_50V7K 150K_0402_1%
    3.SMD 100_0402_5% 2 1 VL

    2
    4.TS 1 2 EC_SMB_DA1 <33,35>
    5 . B/I
    6. ID

    1
    2 7 .BA TT+ PR83 PR82 2

    100_0402_5% 150K_0402_1%
    1 2 EC_SMB_CK1 <33,35>

    2
    Vin Detector
    Min. typ. Max.
    H-->L 16.976V 17.257V 17.728V
    PQ22 L-->H 17.430V 17.901V 18.384V
    B+ 3 TP0610K-T1-E3_SOT23
    1 +VSBP
    PR84
    1 2
    1

    1
    PR85 VIN 1M_0402_1% VIN
    100K_0402_5% PC59 PC60
    0.22U_1206_25V7K 0.1U_0603_25V7K
    2

    1
    PR88 PR89
    2

    22K_0402_5% PR86 VS PR87 10K_0402_5%


    VL 1 2 84.5K_0402_1% 10K_0402_5% 1 2 AC IN
    ACIN <33>
    PR91

    2
    2

    8
    22K_0402_5% PU6A
    PR90 1 2 3

    P
    3 3

    100K_0402_5% + PACIN
    O 1 PACIN <47,49>

    20K_0402_1%
    2 -

    G
    PR93
    1

    1
    D

    PR92
    0_0402_5% PC61 LM393DR_SO8

    4
    1 2 2 PQ23 1000P_0402_50V7K PC62 PZD2 PR94
    <48> SPOK G MF2N7002W-G_SOT323-3 0.1U_0603_25V7K RLZ4.3B_LL34 10K_0402_5%

    2
    S
    3

    2
    1

    2
    @ PC63
    0.1U_0402_16V7K PR95
    2

    10K_0402_5%
    2 1 RTCVREF

    8
    PU6B
    5

    P
    +
    O 7
    6 -

    G
    LM393DR_SO8

    4
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 50 of 55
    A B C D
    5 4 3 2 1

    D D

    PL8
    FBM-L11-322513-151LMAT_1210
    B+ 1 2

    10U_1206_25VAK
    6269_VCC PHASE_6269

    PC64

    1K_0402_1%
    UG_6269

    2
    PR97

    PR96
    1 2 1 2

    0_0603_5% PC65 0.1U_0603_25V7K


    +5VS

    1
    BOOT_6269
    @PR98
    4.7_0603_5%

    5
    6
    7
    8
    PR99

    17

    16

    15

    14

    13
    4.7_0603_5% PQ24

    D
    D
    D
    D
    2
    1 2 6269_VCC

    PHASE

    BOOT
    UG
    GND

    PGOOD
    PC66

    G
    S
    S
    S
    1 VIN PVCC 12 1 2
    C SI4800BDY-T1-E3_SO8 C

    4
    3
    2
    1
    2.2U_0603_6.3V6K

    6269_VCC 2 11 LG_6269
    VCC LG 1.8UH_SIL104R-1R8PF_9.5A_30%
    PR100 PU7 1 2
    0_0402_5% +1.2VSP
    1

    1 2 3 ISL6269CRZ-T_QFN16 10 PL9
    FCCM PGND

    5
    6
    7
    8
    PC67 1
    PR101 2.2U_0603_6.3V6K PQ25

    D
    D
    D
    D
    2

    100K_0402_5% SI4810BDY-T1-E3_SO8 + PC68


    <33,35,39,46,53> SUSP# 1 2 4 9 ISEN_6269
    1 2 330U_D2E_2.5VM
    EN ISEN

    COMP

    G
    2

    S
    S
    S
    PR102

    FSET
    1

    PC69 15.4K_0402_1%

    VO
    FB

    4
    3
    2
    1
    0.22U_0603_16V7K
    2

    8
    57.6K_0402_1%
    1

    1
    22P_0402_50V8J

    1
    1

    PR104
    PR103 PC70
    PC71

    49.9K_0402_1% 0.01U_0402_25V7K

    2
    2

    2
    B B
    1

    PC72
    6800P_0402_25V7K PR105
    2

    3K_0402_1%
    1 2
    1

    PR106
    3K_0402_1%
    2

    Ipeak=VGA_1.2V+(+1.2V_HT)=2.1A+6.067A=8.167A
    Imax=5.7A
    Iocmin=9.23A
    Iocmax=19.23A

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC, M/B LA-3151P
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 51 of 55
    5 4 3 2 1
    5 4 3 2 1

    +3VALW

    1
    PJP3

    1
    JUMP_43X79
    +1.8VALW

    22

    2
    4.7U_1206_25V6K
    1

    PC73
    PJP4

    1
    D JUMP_43X79 D

    +1.8V +5VALW

    2
    RTCVREF
    PU9

    2
    CM8562IS_PSOP8
    PU8
    1 6 1 8
    VIN VCNTL +3VALW VIN PGND
    2 GND NC 5

    1
    2 VFB AGND 7

    2
    1U_0603_16V6K
    PC74 3 7 PC75
    VREF NC +2.5VSP

    PC76
    10U_1206_25VAK 1U_0603_6.3V6M

    2
    PR107 4 8 3 6

    1
    1K_0402_1% VOUT NC VTT VCCA

    AGND
    10_0603_1%
    9

    2
    TP

    1
    4 VTT REFEN 5

    PR108
    APL5331KAC-TRL_SO8 2 1

    9
    1K_0402_1%

    0.1U_0402_16V7K
    @ PR110 PC77
    +0.9VSP
    1

    2
    D

    0.047U_0402_16V7K
    0_0402_5% MF2N7002W-G_SOT323-3 4.7U_1206_25V6K PR109

    2
    1

    200K_0402_1%
    PQ26

    PR111

    PC78
    1 2 2 60.4K_0402_1%
    <46> SYSON#

    1
    0.1U_0603_25V7K

    PC80
    G

    PR112
    S @ PC79
    3

    PC81
    22U_1206_10V6M
    2

    2
    PQ27 PR113

    1
    D MF2N7002W-G_SOT323-3 100K_0402_5%
    2 1 2 SUSP <46>
    G
    C S C

    1
    PC135
    0.047U_0603_16V7K

    2
    PJP5 PJP6 +1.8VALW
    2 1 2 1
    +3VALWP 2 1
    +3VALW +1.8VALWP 2 1
    +1.8VALW
    JUMP_43X113 JUMP_43X113

    1
    PJP7

    1
    JUMP_43X79
    PJP8 PJP9

    2
    2 1 2 1

    2
    +5VALWP 2 1
    +5VALW +2.5VSP 2 1
    +2.5VS

    2
    4.7U_1206_25V6K
    JUMP_43X113 JUMP_43X113

    PC82

    1
    PJP10 PJP11 +5VALW
    RTCVREF
    2 1 2 1 PU10
    +1.2VSP 2 1
    +1.2VS +1.5VSP 2 1
    +1.5VS CM8562IS_PSOP8
    JUMP_43X113 JUMP_43X113
    1 VIN PGND 8

    B PJP12 PJP14 B
    2 VFB AGND 7

    2
    1U_0603_16V6K
    2 1 2 1
    +0.9VSP 2 1
    +0.9V +VSBP 2 1
    +VSB +1.5VSP

    PC83
    3 6

    1
    JUMP_43X113 JUMP_43X113 VTT VCCA

    AGND
    10_0603_1%
    1
    4 VTT REFEN 5

    PR114
    PJP13 PJP15 2 1

    9
    PC84

    0.047U_0402_16V7K
    2 1 2 1 4.7U_1206_25V6K PR115

    2
    +VGA_CORE_P 2 1
    +VDD_CORE +VGA_CORE_P 2 1
    +VDD_CORE

    51K_0402_1%
    60.4K_0402_1%

    1
    0.1U_0603_25V7K

    PC85
    1
    JUMP_43X113 JUMP_43X113

    PR116
    PC86
    1

    2
    PQ28

    1
    D MF2N7002W-G_SOT323-3
    2 1 2 SUSP <46>
    G
    S PR117

    3
    100K_0402_5%

    1
    PC136
    0.047U_0603_16V7K

    2
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星 薔|, 三月 09, 2006 Sheet 52 of 55
    5 4 3 2 1
    5 4 3 2 1

    PL10
    FBM-L11-322513-151LMAT_1210
    ISL6227B+ 1 2 B+

    10U_1206_25VAK

    2200P_0402_25V7K
    D D

    1
    10U_1206_25VAK

    10U_1206_25VAK

    2200P_0402_25V7K
    1

    10U_1206_25VAK
    1

    1
    PC87

    PC88

    PC89

    PC90
    PR118

    PC91

    PC92
    51_1206_5%

    2
    +5VALW

    1
    PC93

    2
    PQ29 4.7U_0805_6.3V6K

    1
    SI7840DP-T1-E3_SO8 PR119 PC95

    2
    5
    PC94 2.2_0603_5% 2.2U_0805_10V6K
    PD12 0.1U_0603_25V7K

    2
    DAP202U_SOT323

    1
    2

    3
    4
    BST_1.8V

    BST_VGA
    PL11 PC97
    +VGA_CORE_P

    14

    28
    1
    2
    3
    PC96 4700P_0402_25V7K

    8
    7
    6
    5
    1.4U_SSF-13056-1R4_15.5A_20% 2 1 12 17 2 1

    VIN

    VCC
    SOFT1 SOFT2 PQ30

    D
    D
    D
    D
    1 2 PC98 0.01U_0402_25V7Z PR121 PC99 SI4800BDY-T1-E3_SO8
    0.1U_0402_16V7K 0_0603_5% 0.1U_0402_16V7K
    C 1 2 1 1 2BST_VGA-16 BOOT1 BOOT2 23 BST_1.8V-1
    1 2 2 1 C
    8
    7
    6
    5

    8
    7
    6
    5

    G
    S
    S
    S
    PR120
    3

    1
    4.7_1206_5%

    PC100 + 0_0603_5%
    D
    D
    D
    D

    D
    D
    D
    D

    1
    2
    3
    4
    330U_D2E_2.5VM
    +1.8VALWP
    PR122

    DH_VGA 5 24 DH_1.8V PL12


    2 UGATE1 UGATE2 1.8U_SIL104R-1R8_9.5A_30%
    G

    G
    S
    S
    S

    S
    S
    S
    LX_VGA 4 25 LX_1.8V 1 2
    2

    PHASE1 PHASE2
    0.01U_0402_25V7Z

    FDS6676AS_SO8

    FDS6676AS_SO8
    PQ31

    PQ44
    1K_0402_1%

    @ PU11
    1
    2
    3
    4

    1
    2
    3
    4
    1

    PR125 PR126 1
    1

    5
    6
    7
    8
    PR123

    1.5K_0402_1% ISL6227CA-T_SSOP28 1.5K_0402_1% PQ32


    PC101

    680P_0603_50V7K

    PR124 1 2 ISE_VGA 7 22 ISE_1.8V 1 2 SI4810BDY-T1-E3_SO8 + PC103

    D
    D
    D
    D
    ISEN1 ISEN2
    PC102

    0_0402_5%
    @ 0_0402_5% 220U_D2_4VM_R15
    2

    1
    PR127
    DL_VGA 2 27 DL_1.8V PC104
    2

    LGATE1 LGATE2 0.01U_0402_25V7Z 2


    2

    1
    S
    S
    S
    @

    2
    4
    3
    2
    1
    3 26 PR128

    2
    +5VALW PGND1 PGND2 10K_0402_1%

    2
    9 VOUT1 VOUT2 20
    VSE_VGA 10 19 VSE_1.8V
    VSEN1 VSEN2
    5.9K_0402_1%

    1 2 8 21 1@PR130 2
    +3VS EN1 EN2 +3VALW
    2

    @ PR129 10K_0402_1% 15 16
    PG1 PG2/REF

    1
    0.1U_0402_16V7K
    PR132

    PR131 10K_0402_1%

    GND

    DDR

    1
    PC105
    10K_0402_5% 11 18
    OCSET1 OCSET2
    1

    1
    18.2K_0402_1%

    PR137 @ PR134 PR133

    1
    PR136
    0_0402_5%

    100K_0402_5% PR140 0_0402_5% 10K_0402_1%


    1

    1 2

    13

    2
    1

    1
    0.1U_0402_16V7K
    PR135

    PC106

    PR182 1 2 PR138 10K_0402_5%


    <33,35,39,46,51> SUSP#

    2
    10K_0402_5% D PR139 56.2K_0402_1% 1 2
    +5VALW

    2
    B 110K_0402_1% B
    1 22
    2

    2
    PR141 S
    3

    2
    1

    D
    0.01U_0402_25V7Z

    MF2N7002W-G_SOT323-3
    PQ33

    10K_0402_5%
    2 1 2
    PC134

    G
    2

    POWER_SEL <16> S
    3

    MF2N7002W-G_SOT323-3
    1

    0.01U_0402_25V7Z

    PQ34

    For VGA chipset type, that should be dynamic change by everytime load BOM. Ipeak=8.5A
    @ PC107

    Imax=6A
    2

    M52PG M54P M56P Iocpmin=8.76A


    Iocpmax=13.46A
    PR123=1K PR123=1K PR123=1K

    PR135=18.2K PR135=8.87K PR135=18.2K


    Ipeak=16.40A
    PR132=17.8K PR132=8.87K PR132=5.9K
    Imax=12.25A
    Iocpmin=22.07A L=1.000V L=1.102V L=1.102V
    Iocpmax=38.67A
    H=0.949V H=1.001V H=0.949V
    A A

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 53 of 55
    5 4 3 2 1
    5 4 3 2 1

    B+
    CPU_B+
    +5VS
    PL13

    PR142 10_0402_5%
    FBMA-L18-453215-900LMA90T_1812
    +3VS
    1 2

    0.01U_0402_25V7K
    4.7U_1206_25V6K

    4.7U_1206_25V6K

    2200P_0402_50V7K
    1

    100U_25V_M
    1

    1
    PC110

    PC111

    PC112
    +

    PC108

    PC109
    2

    2
    D D

    2
    1
    2

    2.2U_0603_6.3V6K
    10K_0402_5%
    @ PR143

    2
    PC113

    0.01U_0402_25V7K
    2

    5
    PC114

    0.22U_0603_16V7K
    PC115
    2.2U_0603_10V6K
    PU12 PQ35
    SI7840DP-T1-E3_SO8

    1
    2

    PC116
    MAX8774_VCC
    19 25
    VCC VDD
    4

    2
    2 1 31 5 PR146
    <7> VID0 PR144 0_0402_5% D0 THRM 0_0603_5%
    2 1 32 30 1 2 PR148
    <7> VID1 D1 BST1
    PR145 0_0402_5% 0_0603_5% +CPU_CORE

    3
    2
    1
    2 1 33 29 DH1 1 2 PL14
    <7> VID2 PR147 0_0402_5% D2 DH1 0.56UH_ETQP4LR56WFC_21A_20%
    2 1 34 28 LX1 1 2
    <7> VID3 D3 LX1

    SKS30-04AT_TSMA
    680P_0603_50V8J 4.7_1206_5%
    PR149 0_0402_5%

    PR151
    2 1 35 26 DL1
    <7> VID4 D4 DL1

    5
    6
    7
    8

    D 5
    D 6
    D 7
    D 8

    1
    FDS6676AS_SO8

    FDS6676AS_SO8
    4700P_0402_25V7K

    15K_0402_1%
    PR150 0_0402_5%

    PD13
    2 1 36 27

    D
    D
    D
    D
    <7> VID5 D5 PGND1

    1
    PR154
    PQ36

    PQ37
    PR152 0_0402_5% J1 SHORT PADS @

    1 1
    1
    PC117
    1 2 1 2 1 16
    <33> VGATE PR153 0_0402_5% For EC ATE
    PWRGD CSP1

    2
    G

    4 G
    S
    S
    S

    3 S
    2 S
    1 S

    PC118
    +3VS 1 2 17 15 PH2

    2
    PR155 100K_0402_1% PHASEGD CSN1 @ PR156 10KB_0603_ERTJ1VR103J

    4
    3
    2
    1

    1
    PR158 MAX8774_VCC 37 18 AGND 15K_0402_1%
    C 0_0402_5% TWO-PH GND @ PR157 C
    1 2 1 2

    2
    <33> VR_ON 1 2 38 40 PR161 PC119 10_0402_5%
    @ PR159 PR160 71.5K_0402_1% SHDN# IC 2.55K_0603_1% 4700P_0402_25V7K

    PR162
    10_0402_1%
    1 2 2 1 6 11 FB 1 2 1 2 1 2

    2
    PC121 TIME FB PR163 20K_0402_1%
    100K_0402_5% 2 1 8 9 1 2 1 2 PR164 0_0402_5% PC120
    PR165 10K_0402_1% CCV CCI PC122 470P_0402_50V8J 0.033U_0603_25V7K
    1 2
    1 2 150P_0402_50V8J 3 20
    <33> POUT POUT BST2 PR166
    1 2 1 2 MAX8774_REF 10 21 DH2 0_0402_5%
    PC123 PR167 PC124 0.1U_0603_16V7K REF DH2
    1 2
    0.1U_0402_16V7K CPU_B+ 1 2 7 22 LX2
    200K_0402_1% TON LX2
    MAX8774_REF1 2 2 24 DL2
    PR168 OFS DL2
    31.6K_0402_1% PR170 4 23
    VRHOT# PGND2
    1

    MF2N7002W-G_SOT323-3

    0_0402_5%
    PR169 2 1 39 13 CSP2
    169K_0603_1% SKIP# CSP2

    2
    CPU_B+

    0_0603_5%
    CSN2 14
    GNDS

    PR171
    PQ38
    1 2

    EP

    4.7U_1206_25V6K

    4.7U_1206_25V6K

    0.01U_0402_25V7K
    2200P_0402_50V7K
    2 <7> CPU_VCC_SENSE
    +3VS
    41

    12

    1
    G MAX8774GTL+_TQFN40

    PC128
    S
    3

    PC125
    PQ39

    PC126

    PC127
    SI7840DP-T1-E3_SO8

    2
    1

    0.22U_0603_16V7K
    1

    1
    B PR172 PC129 PR173 B

    PC130
    PR174 200K_0402_1% 4700P_0603_50V7K 10_0402_1% 4
    2

    200K_0402_1% PR175

    2
    0_0603_5%
    2

    1 2
    2

    PL15

    3
    2
    1
    1

    D 0.56UH_ETQP4LR56WFC_21A_20%
    2 PQ40 1 2
    1

    4.7_1206_5%
    G MF2N7002W-G_SOT323-3
    PQ41 S
    3

    D 5
    D 6
    D 7
    D 8

    D 5
    D 6
    D 7
    D 8

    2
    SKS30-04AT_TSMA
    FDS6676AS_SO8

    FDS6676AS_SO8

    PR176
    FDV301N_NL 1N SOT23-3

    1
    PR177
    1

    PD14
    PQ42

    PQ43
    <7> PSI# 2 15K_0402_1%
    PR178 @
    10_0402_5%

    1
    4 G

    4 G

    1
    3 S
    2 S
    1 S

    3 S
    2 S
    1 S

    680P_0603_50V8J
    PR179 PH3

    2
    PC131
    15K_0402_1% 10KB_0603_ERTJ1VR103J
    2

    @ PC132 1 2 1 2
    3

    2
    4700P_0402_25V7K @

    1 2 PC133
    <7> CPU_VSS_SENSE 0.033U_0603_25V7K
    1 2

    CSP2
    PR180
    0_0603_5%
    AGND1 2 PR181
    A 1 2 A

    0_0402_5%

    Security Classification Compal Secret Data Compal Electronics, inc.


    Issued Date 2005/09/26 Deciphered Date 2006/09/26 Title
    SCHEMATIC, M/B LA-3151P
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    www.laptopfix.vn
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    401412
    Date: 星期四, 三月 09, 2006 Sheet 54 of 55
    5 4 3 2 1
    5 4 3 2 1

    Version change list (P.I.R. List) Page 1 of 1


    for PWR
    Item Fixed Issue Reason for change Rev. PG# Modify List VER Phase

    D
    1 D

    3
    4

    7
    C C

    10

    11

    B B

    A A

    Compal Electronics, Inc.


    Title
    SCHEMATIC, M/B LA-3151P

    www.laptopfix.vn
    Size Document Number Rev
    401412 B

    Date: 星 薔|, 三月 09, 2006 Sheet 55 of 55


    5 4 3 2 1
    www.laptopfix.vn

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