EE-307

FPGA BASED SYSTEM DESIGN

Spring 2015

Verilog
Combinational Logic in Verilog

Lecture # 05
Today’s Lecture

 Writing simulation module

 Behavior modeling
 Procedural blocks
 Sensitivity list
Verilog -
Half Adder – Testing your design

 module test_halfadder; //no inputs & outputs for simulation module

 reg a_in,b_in; //declare reg for inputs for instantiated module
 wire sum, c_out; //declare wire for outputs of instantiated module
 HA_GateLevel uut( // Instantiate the Unit Under Test (UUT)
 .sum(sum), module HA_GateLevel(
 .c_out(c_out), input a, b ,
 .a(a_in), output c_o, s_o
);
 .b(b_in) xor (s_o,a,b);
 ); and (c_o,a,b);
 initial //This block will execute one time endmodule
 begin // Initial block executes sequentially
 // Initialize Inputs
 a_in = 0;
 b_in = 0;
 #100; // Wait 100 ns
 a_in = 1;
 b_in = 0;
 end
 endmodule
Verilog -- Design Levels

 Gate-Level modelling
 Verilog gate Primitives
 Dataflow Modelling
 Continuous Assignment using assign statement
 Expressions, Operators, Operands
 Behavioural Modelling
 Structured Procedures: Initial & always blocks
 Blocking & Non-blocking statements
 HLL Higher language constructs (if, switch, case, loops)
 Can the life be made even more easier ??


 Assign out = sel[1] ? ( sel[0] ? in3 : in2 ) : ( sel[0] ? in1 : in0 );

case (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: out = in2;
2'b11: out = in3;
endcase
 So We require an always block to be able to use
Higher Level constructs (If-Else, Case, For Loops)

module mux_case(sel,in1,in2,in3,in4,out1);
input [1:0] sel;
input in1,in2,in3,in4;
output reg out1; // LHS in always statement must be “reg”

always @ (sel,in1,in2,in3,in4) // All inputs in paranthesis

begin Sensitivity List
case (sel) // Put the case parameter in brackets
2'b00: out1 = in1;
2'b01: out1 = in2;
2'b10: out1 = in3;
2'b11: out1 = in4;
default : out1 = in1; // Must use default
endcase // Don’t Forget endcase
end
endmodule
Moving to Behavioral Model
 Rule: Input inside a module is always a wire
module Parent_Module (….)
………. reg or wire wire

module Sample_Name (in1, in2, out) Input wire InOut wire

input wire in1,in2;
output reg out;
Intermediate Connections, Wire
Declarations, regs

Instantiation of lower modules

Dataflow Statements Procedural blocks

assign out = in1 & in2 Always/initial blocks
wire out = in1 & in2 (Behavioural statements)

endmodule Output Output can be reg or wire

Signal_From_Sample_Name must be a wire
wire
 Two kind of Assignments
Dataflow & Behavioural (Procedural)
module Sample_Name (a,b,c_o,sum)
output reg c_o, sum ; reg or wire net
input a,b
Input wire InOut wire

Dataflow Statements Behavioural statements

(assign) (always blocks)

LHS must be wire LHS must be reg

wire reg

Output reg or wire

endmodule
net
Behavioural procedural blocks
Initial & always block

 Initial Block  Always block initial

 Non synthesizable  More like HW/ Synthesizable
begin
 Used only in stimulus  Can instantiate multiple . initial &
 Multiple blocks execute always blocks .
concurrently  Simulation #5
 Simulation  executes continuously. at t = 0 and
Starts execution at time t=0 repeatedly thereafter
 .
 Execute until they come to a end
#delay operator; delay & than
resume
always
begin
.
.
.
.
.
end
 A>B A=B A<B A1 B1 A0 B0
Two bit Comparator 0 1 0 0 0 0 0
<CIL> Eg. 4.4, Sec-5.8 0 0 1 0 0 0 1
1 0 0 0 0 1 0
0 1 0 0 0 1 1
Design: 0 0 1 0 1 0 0
Compare two bit numbers A & B 0 0 1 0 1 0 1
0 0 1 0 1 1 0
0 0 1 0 1 1 1
1 0 0 1 0 0 0
1 0 0 1 0 0 1
1 0 0 1 0 1 0
1 0 0 1 0 1 1
0 1 0 1 1 0 0
0 0 1 1 1 0 1
1 0 0 1 1 1 0
0 1 0 1 1 1 1
 Gate Level Model

wire w1, w2, w3, w4, w5, w6, w7;

Data Flow Model
(Continuous Assignment Using relational operators)
Behavioural Model – always block

Note : Reg

Sensitivity List
 Behavioural Model –
<Important……..>
module compare(A_lt_B, A_gt_B, A_eq_B,A,B); // Note the semicolon, Keywords are case sensitive
// There can be multiple modules per verilog file – Don’t do it plz
output reg A_lt_B, A_gt_B, A_eq_B; // Note reg – You will get error if you wont use it !
input [1:0] A,B;

always @ (A or B)
begin
if(A ==B)
begin //begin & end required for multiple lines in if statement
A_lt_B=0; // This (=) is called BLOCKING ASSIGNMENT (Will study later)
A_gt_B=0;
A_eq_B=1;
end
else if(A>B)
begin
A_lt_B=0; A_gt_B=1; A_eq_B=0; // You can write multiple lines separated with semi end
//colon. Not Recommended 
else
begin
A_lt_B=0; A_gt_B=1; A_eq_B=0;
end
end

endmodule // Please note there is no semicolon at the end , Keywords are case sensitive