Institut Supérieure des Sciences Appliquées et de

Technologie de Sousse

Compte rendu
VHDL

Réaliser par  :
NSIR RAMI & SOUABNI YASSIN

FiA1-G02-02
 Partie pratique
1. Transcodeur avec with…select
Entity Transcodeur is
Port (s: in STD_LOGIC_VECTOR (3 downto 0);
t: out STD_LOGIC_VECTOR (6 downto 0));
End Transcodeur;
architecture Behavioral of Transcodeur is
begin
with s select
t<= "0111111" when "0000",--0
"0110000" when "0001",--1
"1101101" when "0010",--2
"1111001" when "0011",--3
"1110010" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110001" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"0000000" when others;
end Behavioral;

2.avec case
entity TranscodeurCase is
Port ( s : in STD_LOGIC_VECTOR (3 downto 0);
t : out STD_LOGIC_VECTOR (6 downto 0));
end TranscodeurCase;

2
architecture Behavioral of TranscodeurCase is
begin
process(s)
begin
case s is
when "0000" => t<="0111111";
when "0001" => t<="0110000";
when "0010" => t<="1101101" ;
when "0011" =>t <= "1111001";
when "0100" =>t <= "1110010";
when "0101" =>t <= "1011011";
when "0110" =>t <= "1011111";
when "0111" =>t <= "1110001";
when "1000" =>t <= "1111111";
when "1001" =>t <= "1111011";
when others => t<= "0000000";
end case;
end process;
end Behavioral;
3.avec when
entity TranscodeurConditionnel is
Port ( s : in STD_LOGIC_VECTOR (3 downto 0);
t : out STD_LOGIC_VECTOR (6 downto 0));
end TranscodeurConditionnel;
architecture Behavioral of TranscodeurConditionnel is
begin
t <= "0111111" when s= "0000" else
"0110000" when s= "0001" else
"1101101" when s ="0010" else

3
 "1111001" when s= "0011" else
"1110010" when s ="0100" else
"1011011" when s= "0101" else
"1011111" when s= "0110" else
"1110001" when s= "0111" else
"1111111" when s = "1000" else
"1111011" when s = "1001" else
"0000000";
end Behavioral;

Ascenceur.vhdl
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity az is

Port ( res : in STD_LOGIC;

etage : in STD_LOGIC_vector(1 downto 0);

ouv : out STD_LOGIC;

ferm : out STD_LOGIC;

app : in STD_LOGIC_vector(1 downto 0);

mont : out STD_LOGIC;

4
 des : out STD_LOGIC;

clk : in STD_LOGIC;

op : in STD_LOGIC;

cl : in STD_LOGIC);

end az;

architecture Behavioral of az is

type state is(attente,monter,descente,ouvrir,fermer);

signal next_state:state;

begin

process (clk,res)

begin

if (res='1') then

mont<='0';

des<='0';

ouv<='0';

ferm<='1';

elsif (clk'event and clk='1') then

case next_state is

when attente=>

mont<='1';

des<='0';

ouv<='0';

ferm<='1';

5
--l'assenceur est en cours d'attente.

if (app>etage) then

next_state<= monter;

--le prochain direction du l'assenceur est de montée

elsif (app<etage) then

next_state<= descente;

--le prochain direction du l'assenceur est de descendre

elsif (app=etage) then

next_state<= ouvrir;

--l'assenceur va être ouvert

end if;

when monter=>

ouv<='0';

mont<='1';

des<='0';

ferm<='1';

if (app>etage) then

next_state<= monter;

--l'assenceur est en cours du montée

else

next_state<= ouvrir;

--l'assenceur est ouvert.

end if;

when descente=>

6
 mont<='0';

des<='1';

ouv<='0';

ferm<='1';

if (app<etage) then

next_state<= descente;

--l'assenceur est en cours du descendre

else

next_state<= ouvrir;

end if;

when ouvrir=>

ouv<='1';

mont<='0';

des<='0';

ferm<='0';

if (op='0') then

next_state<= ouvrir;

else

next_state<= fermer;

end if;

when fermer=>

ouv<='0';

mont<='0';

des<='0';

ferm<='1';

if (cl='0') then

7
 next_state<= fermer;

else

next_state<= ouvrir;

end if;

end case;

end if;

end process;

end Behavioral;

Ascenceur_test_bench.vhdl

Scenario :
clk<='1','0' after 5 ns,'1' after 10 ns,'0' after 15 ns,'1' after 20 ns,'0' after 25 ns,'1' after 30
ns,'0' after 35 ns,'1' after 40 ns,'0' after 45 ns,'1' after 50 ns,'0' after 55 ns,'1' after 60 ns;

op<='0','1' after 30 ns;

res <= '0';--, '0' after 20 ns;

app<="11","00" after 20 ns,"11" after 40 ns;

etage <= "00", "11" after 20 ns,"00" after 40 ns;

END;