To sum up, Figure 3.33 depicts the DC short circuit cur- value of 800V.

rent values Isc as a function of the fault resistance Rsc. Moreover, since Iac1 is lower than in Case 1a (Figure 3.36),

3 Fault analysis
As we can see, with the decrease of Rsc, the short circuit the ESS allows the FEC to reach its maximum AC current
current may reach values up to 10 times the FEC nominal absorption for lower Rsc values. This is better from the
current on the DC side Idcn, As a result, protective devices electronic component current point of view.
are required.
Figure 3.34 – Trend of Vdc voltage during a short circuit on DC side
in Case 1b
Figure 3.33 - DC short circuit current values Isc as a function of the fault
resistance Rsc (FEC contribution, Idcn = 125 A) 900

1400
850

1200 800

1000 750 820

Vdc [V]
800 700 810
Isc [A]

600 650 800

600
400 790

550
200 780
02 03 04 05
500
0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t [s]
100 10 1 0.1 0.01 0.001
Rsc [Ω]
Figure 3.35 – Trend of Isc current during a short circuit on DC side
in Case 1b
3.1.2 Behavior with ESS 10
The same cases of the previous section will be analyzed 9
hereunder in order to see what changes during a short 8
circuit adding the ESS, which is inserted in parallel to the 7
DC-Bus at t = 0.25s, while the fault still occurs at t = 0.5s2. 6

5
Isc [A]

Case 1b 4
For Rsc values such that the FEC is able to maintain the Vdc 3
at the nominal value Vdcn, the fault current Isc = Vdcn/Rsc 2
remains at the same value of Case 1a. 1
Therefore, the presence of the ESS does not contribute 0
to increase the short circuit current. 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t [s]
Nevertheless, since the power amounts delivered to the
load RL and to the fault Rsc are now shared between the
Figure 3.36 – Trend of Iac1 current during a short circuit on DC
FEC and the ESS, the current absorbed from the grid side in Case 1b
Iac1 decreases. 250

200
Since Vdc remains at its nominal value of 800V (Figure
150
3.34), assuming Rsc = 100Ω, the fault current Isc is still
100
8A like in Case 1a (Figure 3.35).
50
The ESS connection causes a transient DC-Bus voltage
Iac [A]

increase over the nominal value (Figure 3.34), but the 0

FEC control intervenes to bring back the Vdc to the set -50

-100

2
See Annex B for the behavior in fault condition of the DC/DC converter that interfaces -150
the ESS with the DC-Bus. In particular, the converter parallel capacitance can be added
-200
to Cdc series in order to have the total capacitance contribution.
-250
0.4 0.45 0.5 0.55 0.6 0.65
t [s]

Faults in LVDC microgrids with front-end converters 23