Network Theorem Trainer

Verification of Kirchoffs Law

Aim:
To verty Kirchotfs voltage law (KVL) and Kirchoffs current law (KCL)
Theory:
ne two basic laws which concern the voltage across and current through the elements of a
ielwork are Kirchhoffs voltage law (KVL) and Kirchhoffs current law (KCL) respectively. These
lews torm the basis of all network analvsis and are applicable to any network whether the
Clements of the network are linear. nonlinear. time-varying or time invariant. The equations
Teoessary to describe a network can be written with the help of KVL and KCL and the V
relations of the circuit elements.

Sign conventions
Polarity of a voltage Source
Ine polarity of a voltage source is fixed and is independent of the direction of current. The
positive (+) terminal is at a higher potential and negative (-) terminal at a lower potential.
Consider avoltage source. When we move from 'a' to 'b' (positive terminal to negative terminal)
there is avoltage drop. When we go from b to a (negative terminal to positive terminal) there is a
voltage rise. A voltage rise indicates a positive voltage and a voltage drop indicates a negative
voltage. Thus, a voltage (equal to -Vs) results when we go from 'a' to 'b' andavoltage (equal to
+Vs) results when we move from b to a.

Fall Rise

Vs

Movement Movement
from a tob- Vs from atob-V
from b to a -Vs from btoa-V
Polarity of avoltage source.
Polarity of a Resistor
ont fows apoint of higher potential to
another point on lower potential. Since the Current I
Aoe from point 'c to point 'd, the point c IS at angher
potential and the point 'd' is at alower
potential. When we move from 'c' to 'd', that is, along the direction of
current, there is a voltage
16
 Network Theorem Trainer

from 'd' to 'c, that is, opposite to

drop V(-R) While going
+RI
Movement e

ww d
R
Movement
-RI

Sian convention for voltage across a resistor

The flow of current, there is avoltage rise Vdc (ER). Wnlle traversing a closed path through a
remembered:
resistor the following rule can easily be
Movement opposite to the flow of current gives positive voltage (i.e., voltage rise)
Another Conversion
We assign a positive (+) sign for the voltage to the terminal of the elenment where the current
enters and anegative () sign to the terminal of the element where the current leaves it. While
traversing adosed path, if we move from + terminal, there is a voltage rise. Avoltage rise
indicates positive voltage anda voltage drop indicates a negative voltage.

If current enters the terminal a of the element. Hence point a is assigned + sign. Since the
current leaves the element at point b, the point b is assigneda (-) sign. While traversing a closed
path through the element between ab, if we move from a to b there is a voltage drop equal to -v.
Conversely, if we move from bto a, there isavoltage rise, equal to +v.

Sign conventions
Kirchhoffs voltage law (abbreviated KVL) is stated as follows

The algebraic sum of allvoltages around a closed path at any instant is zero

Mathematically,

Close Path

The closed path is to be traced in an arbitran specified direction, which may be clockwise or
anticlockwise. In most of the cases we shall choose clockwise direction for traversing the cioSed
path.

Tne votage across elements that are traversedfrom - to + are taken positive and the vOltage
across elements that are traversed from + to -are taken
negatuve.

17
Network Theorem Trainer

An algebraic sum is the one in which the sign of the quantity is taken intoaccount.
b
+
+V
Sign conversion

Kirchhoff's Current Law (KCL)

Kirchhoffs current law (abbreviated KCL) is stated as follows
At any instant of time,the algebraic sum of current at a node is zero.

Mathematically,

)i(0) =0
Node n

If the current entering a node are assigned positive sign, then the currents leaving the node will
be assigned negative sign or vice versa. The choice of the sign conversion is arbitrary, but once
a sign conversion is chosen, it should not be changed with respect to any particular node while
writing KCL equation. In applying KCL let us adopt the sign conversion that the incoming currents
are positive and the outgoing currents are negative.
Consider a portion of some network as shown in Fig Current i, (t), iz(t) and ia(t) are entering the
node n. Hence they are assigned positive sign. Currents i(t), is(t) and is(t) are leaving n and
hence they are assigned negative sign. Applying KCL at node n we get
i{(e) + i,() - iz() + is(t) - is() is(t) =0 ..1)

from Eq. (1)

i{(t) + i2() + i4(0) = i(t) + i_(t) + i,(t) ...2)

or
 Network Theorem Trainer

is(t)
i0)

i(t) i,(t)

llustration of KCL

Sum of the incoming current=sum of the outgoing currents.

Thus, as alternative from of KCL can be stated as follows:

At anyinstant of time, the sum of all the currents flowing into a node is equal to the sum of all the
Currents leaving the same node.

Kirchhoffs current law (KCL) is based on the conservation of charge at a node. According to the
law of conversion of charge, the charge flowing out of the node. The current law given by Eg.
Then folows directly by diferentiation with respect to time, (since i =dq / dt).
Traversing of meshes in clockwise direction

A
R1 Vs3
B

R2 R4
Vst

Vs2
wt D
R3

IMustrating Example

19
Network Theorem Trainer

(a) KVL in mesh A-B-F-G-H-A

We have to traverse the mesh fromA to B. toFF to G. G to H and H to A

(1) From Ato B, since we are moving along the current I, there is a voltage drop- ""
(2) From Bto Fagain we move along the current l,. therefore. there is avoltage drop= h22
(3) From F to G(- to +) there is a rise of voltage+Vs2
(4) From G to H, because of the movement along the curent l. there is a voitage oro
Rgl.
(5) From Hto A(- to +) there is avoltage rise + Vs1:

By KVL the algebraic sum of allthese voltages is zero

1
VAB +VF+ VFG +VGH +VHA =0
(-R1,)+(Rzlh)+(+Vs2)+(-Rgl,)+(+Vs1) =0
-Ryl,-Rol2+Vsz-R3l+Vs =0
(b) KVL in mesh B-C-D-G-F-B
4
VBC + Vcp + VoG t VGF + VEB =0
(Vsg) +(-Ral3) +(0) +(-Vs2) +(Ral2) =0
5
-Vs3 -R4l4 - Vs2 + Rgl2 =0

Traversing of meshes in anticlockwise direction

(c) KVL in mesh A-H-G-F-B-A

6
VAH + VHG + VGF + VGB +VBA =0
(-Vs1) + (+Rgl) + (-Vsz) +(+Rgl2) + (+R|4) =0
7
-Vs1 t Rgl-Vs2 +Rl, Rql =0
get
Multiplying Eq. (9) by -1 on both the sides and rearranging the terms we
8
- Ryl-Ral2 +Cs2 - Rgl3 + Vs1 0
It is seen that Egs, (3) and (8) are indentical. This shows that the choice of direction round a
mesh is immaterial to write KVL equation
 Network Theorem Trainer
(d) KVL in mesh B-F-G -D-C-B
0
VBF +VEG +Vep +Voc+ VCB .....9

Hl2)+(+Vs) +(0) +(+Ral,) +(+Vs3) =0

-Rgl, +Vs +Rala t Vs3 =0 ....10

Multiplying Eq. (10) by -1 on both the sides and rearranging the terms
- Vs3 - R3 - Vs t Rgl, =0 11

Itis observed that Egs. (5) and (11) are identical. Thus, the choice of direction round a meek
IS Immaterial to write KVL equation.
Theoretical Circuit Diagram
R1 R2
1502 (R11) B 47092 (R21)
W
Vi V2 C
A
R3 RA
22092 (R15) D 56082 (R25)
W
V3 l2 V4
12V

Apparatus required for KVL &KCL Theorem

1. Resistors 1500, 4700, 2200, 5609
2. Variable Supply 12V
3. Bread Board

4. Multimeter (from lab)

5. Connecting Wires

Procedure for KVL Theorem

1. Make a circuit with the help of resistances and voltage sources so that all the
component ale
connected in the close loop (as shown in Circuit Diagram).
2. Now Consider the loop ABCA &measure the voltages across R, with the help of
muiti-meiel
which is Vy.

21
 22
MULTIMETER
COM A
BANK POTENTIorE
TER
JPL-NTT-12 NETHo VA
100K IK
3
2
RESISTANCE
BANK
183000
730
R33470KO
70KQ R2 KI RA UPEDU
ERIDGE INOUCTANCE
BANK CPICITOR
ENNK GNS
220KN R51 2K20 R39 Z200 R:5 100H L8
150KO R50 2KO 32 2000 R14
15CKO 49 LKS R31 43200Q 10 L6
a21500
100XQ R48
LKO
LK
R30
R29 A11500

:0: 10 L5
100KA R47 lH L4
1K
R28 R:O1200
9200 D7 1200 9 260uH 2
7KO 5
680 R26 100Q R8 260 u
33KN R44
2X 43 560 RZ5 eKe
K
15KQ R42 550Q R24 1000 RS
1000 R
50R22 SOURCE CURRENT SECTI
ON PURER SECTION-1 POAER BANK TANOE CAACI
1OK RO W P3
10K RH 70 R21
3309 g20
470 R2
1OK R33
L334
330O 919 100 1
W 12 11
SUPPLY-2 POLER SUPPLY-1 PO-ER
SUOPLY-3 POAER -1201 "251
-12v2 2512 12+ 1+
GNO3 -12v3 253 GO
U7
follows: ascircuit
is above the diagram
for Connection
12V
+
V A
C (R21) 470s2 (R11)B 15092
R2 R
Trainer Theorem Network
 Network TheoremTrainer
multi-meter
3 Nowconsider the loop ABCA &measure the votages across R2 With the help of
which is V,
R1 R
15002 (R11) B 4709) (R2)
W C

A V2

12V

Connection diagram for the above circuit isas follows:

124 *25U1 -1201 -12/2 2510 -12v3

POuER SUPPLY-1 PCuER SUPLY-2 POLER SUPDLY-3
12

109 19 T90G

R2 479

.0 ca'a42 214700

CAPACI TNCE A POUCR SCCTION-1 ouER SECTION-2 CLRREN SOURCE R40 10Ka

RZOB6O 4: 12a
LEOY
Rs 1009 R2450n R2 15Ka
LED2
43 22Ka

R8 1000 R26 B0a

R9 1200
R27 0200 45 47KO

L3 1H
R10 1200

R11 1802 R29 LKO R47 100A

R3O 1K R48 100Kn

M
RA3 2002 R3L 1KA 49 150xa

R14 200 R32 RSO I5OKA

R15 2200
ANG CAACI TOR GA INOJCTANCE BAK JPEDU) BRIDGE
R33 2K20 RS: 220KG

RI6 2200 R34 3K3n 32 470xO

17 3009 R53470KO

R16 2000 R36 K79

RESISTANCE BAN

3 3

J00K

NP NETHo JPL-NTT-12 poTENTIOrE TER BANK

>
A COM V

MULTIMETER
Network Theorem Trainer

4. Now taking the sum of allthe voltages V, &V, we willfind that sum is equal to V
V,= Vit V2
5. Nowconsider the loop ADCA &measure the voltages across Ra with the help of mult-meter
which is V3
A
|R3 22062 (R15) R4 56092 (R25)
D
W
V3 V4

Connection diagram for the above circuit is as follows:

Lz
-1201
POMER SUPPLY-1 POER SUpDLY-2 PONER SupPLY
12
co
C1ga R20 1100 RO0 10K0

A39 10
9214g
P
R22 500)
cAPNCI TANCE DNK POMCR SECTION-1 POLER SECTION-2 cuRRCNT soURCE
R20 540n

RS 100Q R24 540 942 15)

W 4 22NO

LI 260
W
R9 1200

L3 J t 1O1200

029 LKOa 471000

L6 10H 2160Q ROO IKS R40 100n

Q
13 200 Q49 190O

100M 14 2000

GANG CAPACI TOR BANK INDUCTANCE BAN UPEDU) W

173 470CKA
G
grsISTNCE 9NK

Ve NETWO jPL-NTT-12/

A COM
MULTIMETER
 Network Theorem Trainer

across Ra with the help of multi-meter

the voltages
& measure
6. Now Consider the loop ADCA
which is Va
R4 56052 (R25)
R3 22082 (R1s) D
W W
V4
V3

follows:
above circuit is as
Connection diagram for the

A S2 -1201 1203
POLER spp_Y POLER SUDPLY-2 cCLER SUPPLY
1T. 2 2

R19 2300a

203:

Lo047
n20
csac P3 R22500
POLSR SCIION-1
CAORCI TANCE BAN 223 560
GK KE
R6 1009 R42 1SKQ

-O

101200

R1900

12 1500
Q12 B4e 100KQ

R49150KO

RI4 200

R5 200
100H
INOUCIANOE BNK
JPEDU) BRIDGE
GANG CAACI TOQ BAK

R7 3000

m82000
RESISTANCE BN
2

3 1

10

V2 NETHO JPL-NTT-12 PoTEMTIKTER BA

A COM

MULTIMETER

7. Now find out V, = V3+ V4

Result V, = Vo

This verifies that the algebraic sum of the voltage around any closed path is zero.

25
Network Theorem Trainer

Procedure for KCL

1. Make a circuit with the help of resistances and voltage sources so that all componernt ale
connected in the close loop (as shown in figure).
R1 15002 (R11) R2 47092 (R21)
B
W
A
R3 2202 (R15) R4 56092 (R25)
D
W

Connection Diagram for the above circuit is as shown below:

-1203

PONER SsuppLY-2 pavCR SUPPLY-3

POAER SUpPLY-)
12

R20 3902

RZ14700

22500
CAPACITCE N POMER SECTION-1 POMER SECrig-2 cURENT sOURCE

D LCO R24so
LED2
RZS600
1000
-
L2 260H 200
R28 IX)

R12 1800

46 10I a2000

RÊ 200Q

a13 2200

GANG CNCI TOR DNK INOUCTANCE BAN UPEDU 8R10GC

R5347n

12o

RESISTANCE BANK

10N 1COK

JPL-NTT-12
VA NETHo POTENTIarE rER CA

<
COM V

MULTIMETER

Note down the current in the meter as I

 Network Theorem Trainer
RË 15002 (R11) R2 47092 (R21)
A
W
R3 22062 (R15) Ra 560s2 (R25)
D C
W W

Loop ADCA
Connection Diagram for the above circuit is as shown below:

12 "31 -12V1 GNOS

2602
-122 GNO2
POUER SUPPLY-I -1243 GM
POER SUPPLY-2
POMER SUPPLY-3
LH334 R1S 33O0
R37 4K>0o
R2 470
G1'a 47U R20 380o
R39 10Ko
R3 479
P2 R21 420o
CAPACI TANCE BANK R39 10
POMER SECTION-1 POHER SECTIN-2
cuggENT SOURCE R4 560
R22 500n
R40 10
R5 1000
LED R23 560 W

pf Ko LED• R24 S60

42 16Kn
16
R2 100o
R28 B60n R42 22KQ
22
L1 260M R3

L2 260H
R9 1200
R22 8200 Q4542
4x0

RO 120
R29 1K0 R46 82XO
L4 H
R29 1Kg 47100oKo
L5 10M
PA2 150
LE 10mH R48 100KO
RA3 200Q
RA9 IOKO
100M GW
4200a
00 150KO
L 100
GAHS CAPACITOR BANK JNDUCTANCE BAK UEDU) BRIDOE
RIS 220 a33 Z 220Ko
R16 220Q
RS2 47KO

R17 3000 R3S 3K39 RS3 470n

R1 S00
RESTSTANCE PANK
2 2
1 3
Gt K
00

VP NETHO JPL-NTT-12 POTENTIorETER BAK

COM

MULTIMETER
Note down the current in the meter as I

27
Network Theorem Trainer

RË 1500 (R) R2 47099 (R21)

A
R3 2202 (R15) Ra 5606O (R26)

Loop ABCA
Connection Diagram for the above circuit is as shown below:

124 25U1 12V1 2502 12V2 GNC2 N3 -1203

a "a TIT DOuCR CUPPLY-1 POLER SUPPLY-2 POUER SuPDLY-3

12
R19 330n
aola
R20 330Q R38 10KQ

RZ1 470Q RA9 1OKs

CADACITANCE NK DOLR SKCTION-1 pOER SLCTIO-2 R4 560 RZ2500Q RA0 10KO
DENT SOURCE

K R8 1000 R41 12A

LCO
R6 1009 R42 15K
04

Q7 100 R43 22KA

LI 260
R9 1000 Q44 33<O

L2 260
R920Q R45 47Kn

R10 1200
L4 l
11500 R47 100KO

12 160Q R30 1KQ R48 100Kn

R3 2000 49 150KA

L7 100t
R14 2000 R32 2Ka R5O 150Ka
LO 100
R15 220S9 R33 2K20Q R1220K
ONO CAPACITOR BANK INOUCTANCE BANK (UPED BRIOGE
R16 2209a R34 3K30 R2 470K

RI7 300N R35 3K3Q RS3 470K

RI0 300g R9S K7Q

RESISTNCE BANK
2 2

1 3 1

10 4 100K

Ne NETWO þPL-NTT-12 POTENTI0HETER BANK

COM

MULTIMETER

Note down the current in the meter as l,

28
 Network Theorem Trainer
2 Now consder the loop ABCA, ADCA and measure the current I, &l, in both arms with the
help of muti meter.
3. Now take sum of both currents I &I, The total current Iflows in circuit is equal to the sum.

This verifies sum of the currents at any node is zero.

Observation Table for KVL (from loop area)

S.No.
Measured Loop
ABCA
V2 V=V+V2 Error

Similarty verify for loop ADCA.

Observation Table for KCL (fromn loop area)

ADCA Loop ABCA Loop Total (ABCA+ADCA) Error
S.No. ((2) ()
(4)

and Voltage Low are verified.

Thus Kirchoffs Current Law
Network Theorem Trainer

Super Position Theorem

Aim:
To verify the superposition theorem and determine the current following tnro9
resistance.

Theory
or the
In alinear circuit containing more than one source, the current that flows at any point
voltage that exists between any two points is the algebraic sum of the currents or ne v a
hat would have been produced by each source taken senarately with all other sources remoyu.

Theoretical Circuit Diagram

R1 R2

10092 (R6) w 4702 (R21)

24V R3 1KQ (R28) 12V

Apparatus required:
1. Variable supply - 24V
2. Resistance used 1000,1K9, 4702
3. Multimeter (from lab)
4. Connecting Wires
Procedure:
1. Connections are made as per the circuit diagram.
2. Set 12V supply by rotating the Pot at Power Section, use multimeter to check.
3. Check your connections before switch ON the supply.
4. Determine the current through the load resistance (1k2) Tas measured by multimeter.
5. Now one of the sources is shorted and the current flowing through the resistance (1k0) ,
measured by multimeter.
6 Similary, the other source is shorted and the current flowing through the resistance (1kQ) ,
measured by multimeter.
7. Compare the value obtained with the sum of l,&l,
should equal to.
8. Switch OFF the supply.
9. Disconnect the circuit.

30
 Network Theorem Trainer

acting
To find I when two sources are
R1 R2

10092 (R6) 4702 (R21)

R3 1KQ (R28)
24V 12V

below:
Connection Diagram for the above circuit is as shown

LM3L7
OF -121
2790 -12/3
TZ PO ER SUPPLY-1 POMER SpoLY-2 POLER SPPLY-3

100 R19 3300

LR334

R20 3300Q R09 1OKQ

R214700 R39 10KQ

2
POHER SECTION-1 POHER SECTIEN-2 URRENT sOURCE R22 B0OQ
CAPRCITANCE BANK R40 10KQ
5 1009 R23 560 R41 12K0
LEO
D6 100Q R24 9600 42 19Q

1000 R23 S600

260uH 29 100
D44 33KO
2 260uH
R27 200 547K9
W
L3 1aH
R10 1200
G
R42 100K
L5 10
R42 1900
-
L6 1OH
R13 2000
m D49 190O

R4 2000Q
-
GANG CAOACI TOR BANK INDUCTANCE BANK UPEDO BRIDGE
45 220
R5: 220a

R16 2202 5270xo

G
R17 300a R33470rn

RESISTANCE BA

tK 100K

VP NETHOR
PL-NTT-12 POTENTIOEIR GANK

<
A
COM

MULTIMETER
Nework Teorm 1veiner
lo find I, when 24V source is acting alone

R1
H,w R

1009(Re) 4702 (R21)

R3 1K9 (R28)
24V

Connection Diagram for the above circuit is as shown below:

L
PER SeNLY-POUR SUPLY-2 POMER SPLY-3

LAIN
2 40 a8 10K

R40 10K
AOAER SECTION-2 hopENr succ

R236s09 1 12K

R13 22x
MA
433KR

S01200 246 82K

229 IK

8100Kn
R49 150K

R32 X0 REO 1506Q

E19 220
INOLCIANOT ANK UEOU)
62200

83470

Rt9 3000
RESTTANCE RAK
2

foK 4X 100X

Ve NETHOR PL-NTT-12 POTENTIONCTER SANK

<
COM
MULTIMETER
 alone
acting
sOurceis R2
When12V
To find l, R1
47052(R21)
10062(Rs)
1KS)(Rz8)
12V
R3

as shownbelow:
is
theabovecircuit
Diagramfor
Connection -12/1
2 -142
GD2299 -12V
PONER UPPLY-3
+255 POHER SUPPLY-2
POER SUPPLY-1

12 R19 330n

P20 33cn
R2 479

R21 470@
HO 10
R22 S000
CURRENT sOURCE R1 12KO
SECTIO2 R5 1000 23 5
POAERSECTION-1 G R42 15K0
CAPACI TANCE BANK
P3 22
R7 1000
e, K R26 680A
R4 33K2

L1 260uH
R5 474Q
31209

L2 260uH R20120Q R28 1KS

R29 K
R47 100K

02150Q R30 1KO

L5 R9 150Kn
R13200 RO1 1K
6 10aH
ReO 150A
RI4 200Q
C
R5 2202
LO 100

GANG CAPACITOQ BNK

INDUCTANCE BANK UPEDU) BRI0GE
16 2200 R34 33
R2 47oxA

P17 20o R35 330 R3 470

W
R18300 RESISNCE BAK

2 2 2

47% 100K

NP NETHOR PL-NTT-12 POTENT!OHE TER BAK

cOM
MULTIMETER
Network Theorem Trainer

Tabulation:

Practical I(mA) 4 (mA) I2 (mA)

Calculation:
We foundthat l=l4+tl2
Thus the superposition theorem is verified.