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Toshiba A30 La 1931 Dbl10 Sapporo X
Toshiba A30 La 1931 Dbl10 Sapporo X
COMPAL CONFIDENTIAL
1
MODEL NAME : DBL10 -- Sapporo X 1
2 2
2003-09-19 v1.0
3 3
4 4
+3VALW
page 24 page 22 +5VS +5VCD ALC202 RJ11
+5VALW -> +VDDA
Super I/O Embedded Controller page 26 page 26 +3VS page 28 Cable
LID Hibernation
+5VALW +RTC_VREF
page 36 Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401264
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期三, 九月 24, 2003 Sheet 2 of 49
A B C D E
5 4 3 2 1
Device Address
+CPU_CORE
D D
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
C8
D7
D9
A8
B7
B9
JCPU1A
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#[3..31] HD#[0..63]
<7> HA#[3..31] HD#[0..63] <7>
HA#3 K2 B21 HD #0
HA#4 A#3 D#0 HD #1
K4 A#4 D#1 B22
HA#5 L6 A23 HD #2
HA#6 A#5 D#2 HD #3
K1 A25
HA#7 L3
A#6
A#7
POWER D#3
D#4 C21 HD #4
HA#8 M6 D22 HD #5
HA#9 A#8 D#5 HD #6
L2 A#9 D#6 B24
HA#10 M3 C23 HD #7
HA#11 A#10 D#7 HD #8
M4 A#11 D#8 C24
HA#12 N1 B25 HD #9
HA#13 A#12 D#9 H D#10
M1 A#13 D#10 G22
HA#14 N2 H21 H D#11
HA#15 A#14 D#11 H D#12
N4 A#15 D#12 C26
HA#16 N5 D23 H D#13
HA#17 A#16 D#13 H D#14
T1 A#17 D#14 J21
HA#18 R2 D25 H D#15
HA#19 A#18 D#15 H D#16
P3 A#19 D#16 H22
HA#20 P4 E24 H D#17
HA#21 R3
A#20
A#21
HOST D#17
D#18 G23 H D#18
HA#22 T2 F23 H D#19
C
HA#23
HA#24
U1
P6
A#22
A#23
ADDR D#19
D#20 F24
E25
H D#20
H D#21 C
HA#25 A#24 D#21 H D#22
U3 A#25 D#22 F26
HA#26 T4 D26 H D#23
HA#27 A#26 D#23 H D#24
V2 A#27 D#24 L21
HA#28 R6 G26 H D#25
HA#29 A#28 D#25 H D#26
W1 A#29 D#26 H24
HA#30 T5 M21 H D#27
HA#31 A#30 D#27 H D#28
U4 L22
V3
W2
Y1
A#31
A#32
A#33
Northwood-MT HOST
D#28
D#29
D#30
J24
K23
H25
H D#29
H D#30
H D#31
A#34 D#31 H D#32
<7> H_REQ#[0..4]
H_REQ #[0..4]
H_REQ#0
AB1 A#35
Prescott-MT ADDR D#32
D#33
D#34
M23
N22
P21
H D#33
H D#34
H D#35
J1 REQ#0 D#35 M24
H_REQ#1 K5 N23 H D#36
H_REQ#2 REQ#1 D#36 H D#37
J4 REQ#2 D#37 M26
H_REQ#3 J3 N26 H D#38
H_REQ#4 REQ#3 D#38 H D#39
H3 REQ#4 D#39 N25
H_ADS# G1 R21 H D#40
<7> H_ADS# ADS# D#40
P24 H D#41
D#41 H D#42
D#42 R25
+CPU_CORE AC1 R24 H D#43
V5
AP#0
AP#1
CONTROL D#43
D#44 T26 H D#44
AA3 T25 H D#45
R15 BINIT# D#45
1 2 56_0402_1% AC3 IERR# D#46 T22 H D#46
T23 H D#47
D#47 H D#48
D#48 U26
H6 U24 H D#49
B <7> H_BREQ0# BR0# D#49 B
D2 U23 H D#50
<7> H_BPRI# BPRI# D#50
G2 V25 H D#51
<7> H_BNR# BNR# D#51
G4 U21 H D#52
<7> H_LOCK# LOCK# D#52
V22 H D#53
D#53 H D#54
V24
<14> CLK_CPU_BCLK
CLK_CPU_BCLK AF22
BCLK0
CLK D#54
D#55 W26 H D#55
CLK_CPU_BCLK# AF23 Y26 H D#56
<14> CLK_CPU_BCLK# BCLK1 D#56
W25 H D#57
D#57 H D#58
CON D#58
D#59
Y23
Y24 H D#59
F3 Y21 H D#60
<7> H_HIT# TROL
HIT# GND POWER D#60 H D#61
BOOTSELECT
<7> H_HITM# E3 HITM# D#61 AA25
E2 AA22 H D#62
<7> H_DEFER# DEFER# D#62
AA24 H D#63
D#63
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AD1
F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12
FOX_PZ47803-274A-42_Prescott
+CPU_CORE
2 1 BOOTSEL
A BOOTSELECT <44> A
R8
@0_0402_5% R_C
Pop: Northwood
Depop: Prescott
Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom
401264
D ate: ¬P 期三, 九月 24, 2003 Sheet 4 of 49
5 4 3 2 1
5 4 3 2 1
G ND H_SKTOCC#
1
R320 R321
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AF10
AF12
AF14
AF16
AF18
AF20
AF26
@33_0402_5% H_DPSLPR# 1 0_0402_5%
2
AE7
AE9
AF1
AF6
AF8
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
H_DPSLP# <8,17>
B10
B12
B14
B16
B18
B20
B23
B26
E11
E13
E15
E17
E19
E23
E26
F10
F12
F14
F16
F18
F22
F25
C2
C5
C7
C9
D3
D6
D8
B4
B8
E1
E4
E7
E9
F2
F5
JCPU1B H_GH I# 1 2 PM_CPUPERF# <18>
2
+CPU_CORE R55
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
SKTOCC#
0_0402_5%
H_RS# [0..2]
<7> H_RS#[0..2]
+H_GTLREF
H_RS#0 F1 J26
RS#0 DP#0 C33
1 2ITP_BPM#0 H_RS#1 G5 RS#1 DP#1 K25
R49 51_0402_5% H_RS#2 F4 K26 1 2
D
1 2ITP_BPM#1 AB2
RS#2
RSP#
GROUND DP#2
DP#3 L25
D
C
2
R21
1ITP_TRST#
680_0402_5%
<18> H_THERMTRIP# H_THERMTRIP# A2 THERMTRIP#
MAL DSTBN#0
DSTBN#1 K22 H_DSTBN#1
H_DSTBN#2 C
VIDPWRGD
R82 61.9_0603_1% COMP1 NC5
GTL Reference Voltage
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VCCVID
1 2 Layout note :
VID0
VID1
VID2
VID3
VID4
VID5
R20 61.9_0603_1%
1. Place R_A and R_B near CPU (Within 1.5").
Comp0/1 need keep 25
F8
G21
G24
G3
G6
J2
J22
J25
J5
K21
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
AE5
AE4
AE3
AE2
AE1
AD3
AD2
AF4
mils trace width +1.2V
+CPU_CORE
CPU _VID0
CPU _VID1
CPU _VID2
CPU _VID3
CPU _VID4
CPU _VID5
FOX_PZ47803-274A-42_Prescott
1
CPU Temperature Sensor +3VS
C276
0.1U_0402_10V6K
H_THERMTRIP#
Reserve Pop: Prescott R56
2 51.1_0603_1%
Depop: Northwood
for EMI. R270 1 2 10K_0402_5%
3
1
1 2 @SM05_SOT23 R16 1 2 10K_0402_5% 1
200_0402_5% D46 R59 C34
1 H_VID_PW RGD <35>
1
H_THERMDA C27 2
2
0.1U_0402_10V6K R48
3
2 10K_0402_5%
1
2
A U6 A
C24
2200P_0603_50V7K 2 1
2 D+ VDD1 @SM05_SOT23
H _THERMDC 3 6
D- ALERT# D47
<32> EC_SMC2 8 4
Compal Electronics, Inc.
1
SCLK THERM#
7 5 Title
<32> EC_SMD2 SDATA GND
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
ADM1032ARM_RM8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom
401264
D ate: ¬P 期三, 九月 24, 2003 Sheet 5 of 49
5 4 3 2 1
A B C D E F G H I J
+CPU_CORE
Layout note :
Layout note : 1 1 1 1 1
Place close t o CPU, Use 2~3 vias per PAD.
1 Place 22uF caps x31 pcs, populated 14pcs. Place close to CPU power and + C20 + C30 + C11 + C40 + C26 1
470U_D4_2.5VM 470U_D2_2.5VM @470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM
gr ound pin as possible
(<1inch) 2 2 2 2 2
+CPU_CORE
+CPU_CORE
1 1 1
+ C319 + C325 + C329
1 1 1 1 1 1 470U_D4_2.5VM 470U_D4_2.5VM 470U_D4_2.5VM
3 3
+CPU_CORE
Please place these cap on the socket north side
1 1 1 1 1
C338 C335 C336 C345 C337
@22U_1206_6.3V6M 22U_1206_6.3V6M @22U_1206_6.3V6M @22U_1206_6.3V6M @22U_1206_6.3V6M
2 2 2 2 2
4 4
+CPU_CORE
1 1 1 1 1 1
C343 C344 C339 C340 C341 C342
@22U_1206_6.3V6M @22U_1206_6.3V6M @22U_1206_6.3V6M @22U_1206_6.3V6M 22U_1206_6.3V6M @22U_1206_6.3V6M
2 2 2 2 2 2
5 5
6 6
7 7
8
Title
Compal Electronics, Inc. 8
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401264
Date: 星期三, 九月 24, 2003 Sheet 6 of 49
A B C D E F G H I J
5 4 3 2 1
HA#[3..31] 1.Place R337 and R338 within 0.5" of U77 pin K28
HA#[3..31] <4> HXSWING and HYSWING Ref. Voltage
H_REQ #[0..4] 2.Place R387 and R392 within 0.5" of U77 pin B18
H_REQ#[0..4] <4>
HD#[0..63] +CPU_CORE +CPU_CORE 3.+HYSWING, +HXSWING 10mil trace, 20mil space.
HD#[0..63] <4>
1
U26A R337 R387
301_0402_1% 301_0402_1%
D
Montara-GT D
1 2
HA#3 P23 K22 HD #0 +HYSW ING +HXSWING
HA#4 HA#3 HD#0 HD #1
T25 HA#4 HD#1 H27 1 1
1
HA#5 T28 K25 HD #2 R338 R392
HA#6 HA#5 HD#2 HD #3 C387 C447
R27 HA#6 HD#3 L24
HA#7 U23 J27 HD #4 150_0402_1% 150_0402_1%
HA#8 HA7# HD#4 HD #5 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
U24 G28
2
HA#9 HA#8 HD#5 HD #6
R24 L27
2
HA#10 HA#9 HD#6 HD #7
U28 HA#10 HD#7 L23
HA#11 V28 L25 HD #8
HA#12 HA#11 HD#8 HD #9
U27 HA#12 HD#9 J24
HA#13 T27 H25 H D#10
HA#14 HA#13 HD#10 H D#11
V27 K23
HA#15 U25
HA#14
HA#15
HD#11
HD#12 G27 H D#12 Host data Ref. Voltage
HA#16 V26 K26 H D#13
HA#17 HA#16 HD#13 H D#14 +CPU_CORE
Y24 HA#17 HD#14 J23
HA#18 V25 H26 H D#15 1.Place R385 and R376 within 0.5" of U77 pin K21 J21 J17
HA#19 HA#18 HD#15 H D#16
V23 HA#19 HD#16 F25
1
HA#20 W25 F26 H D#17 2.Place C423 C456 C424 C457 in order from U77 to divider
HA#21 HA#20 HD#17 H D#18 R385
Y25 HA#21 HD#18 B27
HA#22 AA27 H23 H D#19 49.9_0603_1% 3.+HVREF 10mil trace, 20mil space.
HA#23 HA#22 HD#19 H D#20
W24 HA#23 HD#20 E27
HA#24 W23 G25 H D#21
1 2
HA#25 HA#24 HD#21 H D#22 + HVREF
W27 HA#25 HD#22 F28
HA#26 Y27 D27 H D#23 1 1 1 1
HA#27 HA#26 HD#23 H D#24 R376
AA28 HA#27 HD#24 G24
HA#28 W28 C28 H D#25 100_0603_1% C423 C456 C424 C457
HA#29 HA#28 HD#25 H D#26 1U_0402_6.3V4Z 0.1U_0402_10V6K @0.1U_0402_10V6K @0.1U_0402_10V6K
AB27 HA#29 HD#26 B26
C HA#30 H D#27 2 2 2 2 C
Y26 G22
2
HA#31 HA#30 HD#27 H D#28
AB28 HA#31 HD#28 C26
E26 H D#29
H_REQ#0 HD#29 H D#30
R28 HREQ#0 HD#30 G23
H_REQ#1 P25 B28 H D#31
H_REQ#2 HREQ#1 HD#31 H D#32
R23 HREQ#2 HD#32 B21
H_REQ#3 R25 G21 H D#33
H_REQ#4 T23
HREQ#3
HREQ#4 HOST
HD#33
HD#34 C24 H D#34 Host Address Ref. Voltage
T26 C23 H D#35
<5> H_ADSTB#0 HADSTB#0 HD#35 +CPU_CORE +CPU_CORE
AA26 D22 H D#36
<5> H_ADSTB#1 HADSTB#1 HD#36
C25 H D#37
CLK_MCH_BCLK# AD29 HD#37 H D#38
<14> CLK_MCH_BCLK# BCLK# HD#38 E24
1
CLK_MCH_BCLK AE29 D24 H D#39
<14> CLK_MCH_BCLK BCLK HD#39
+HYSW ING K28 G20 H D#40 R384 R334
R331 27.4_0402_1% +HXSWING HYSWING HD#40 H D#41 49.9_0603_1% 49.9_0603_1%
B18 HXSWING HD#41 E23
1 2 +HYRC OMP H28 B22 H D#42
+HXRCOMP HYRCOMP HD#42 H D#43
1 2 B20 B23
2
R367 27.4_0402_1% HXRCOMP HD#43 H D#44 + HAVREF +HCC VREF
HD#44 F23
K21 F21 H D#45
HDVREF0 HD#45
1
J21 C20 H D#46 1 1 1 1
+ HVREF HDVREF1 HD#46 H D#47 R383 R335
J17 HDVREF2 HD#47 C21
+HCC VREF Y28 G18 H D#48 100_0603_1% 100_0603_1%
+ HAVREF HCCVREF HD#48 H D#49 C427 C390
Y22 HAVREF HD#49 E19
H D#50 2 C418 2 2 C389 2
E20
2
H_DSTBN#0 HD#50 H D#51 0.1U_0402_10V6K 0.1U_0402_10V6K
J28 HDSTBN#0 HD#51 G17
H_DSTBN#1 C27 D20 H D#52
H_D STBN#[0..3] H_DSTBN#2 HDSTBN#1 HD#52 H D#53 1U_0402_6.3V4Z 1U_0402_6.3V4Z
<5> H_DSTBN#[0..3] E22 HDSTBN#2 HD#53 F19
H_DSTBN#3 D18 C19 H D#54
H_DSTBP#0 HDSTBN#3 HD#54 H D#55
K27 HDSTBP#0 HD#55 C17
B B
1
H_D BI#3 G19 D16 H D#62
DINV3# HD#62 H D#63 H_BREQ0# R455
HD#63 C18 2 1
F15 220_0402_5% R35 80.6_0402_1%
<5> H_RESET# CPURST#
H_PD[0..10] H _PD0 U7
<17> H_PD[0..10]
2
H _PD1 HL_0
U4 HL_1
H _PD2 U3 L28 + HUB_PSW ING
HL_2 ADS# H_ADS# <4>
H _PD3 V3 M25 1 1
HL_3 HTRDY# H_TRDY# <5>
H _PD4 W2 N24 C588 C593
HL_4 DRDY# H _ D R DY# <5>
1
H _PD5 W6 M28 0.01U_0402_25V7Z 0.1U_0402_10V6K
HL_5 DEFER# H_DEFER# <4>
H _PD6 V6 N28 R491
HL_6 HITM# H_HITM# <4> 2
H _PD7 W7 N27 51.1_0603_1% 2
H_HIT# <4>
HUB I/F
2
H_PD10 HL_9 BREQ0# + HUB_VREF
V4 HL_10 BNR# N25 H_BNR# <4>
W3 HLSTB BPRI# P28 H_BPRI# <4>
1
<17> HUB_PSTRB V2 HLSTB# DBSY# M26 H_DBSY# <5> 1 1
T2 N23 H_RS#0 C592 R490 C591
<17> HUB_PSTRB# HLRCOMP RS#0 0.01U_0402_25V7Z 0.1U_0402_10V6K
+1.5VS 1 2 HLRCOMP U2 P26 H_RS#1
+ HUB_PSW ING PSWING RS#1 H_RS#2 40.2_0603_1%
W1 HLVREF RS#2 M27
R492 + HUB_VREF 2 2
2
48.7_0603_1% H_RS# [0..2]
H_RS#[0..2] <5>
A
RG82G4350MA1_uFCBGA732_MONTARA-GT A
DAC
D 6 3 M DVICLK N5 H10 R450 D
DVOBD6/GAD8 HSYNC INTCRT_HSYNC <16>
5 4 MDVIDATA P2 J9 127_0603_1%
DVOBD7/GCBE0# VSYNC INTCRT_VSYNC <16>
N2 DVOBD8/GAD10 REFSET E8 1 2
2.2K_0804_8P4R_5% N3 B6
DVOBD9/GAD9 DDCACLK INTDDCCK <16>
M1 DVOBD10/GAD12 DDCADATA G9 INTDDCDA <16>
M5 DVOBD11/GAD11
+1.5VS_DVO
P3 DVOBCLK/GADSTB0
P4 DVOBCLK#/GADSTB0# IYAM0 G14 LCD_A0- <16>
T6 DVOBHSYNC/GAD0 IYAM1 E15 LCD_A1- <16>
T5 DVOBVSYNC/GAD1 IYAM2 C15 LCD_A2- <16>
1 2 DVO BCINTR# L2 C13
R470 100K_0402_5% DVOB_FLDSTL DVOBBLANK#/GCBE1# IYAM3
M2 DVOBFLDSTL/GAD14 IYAP0 F14 LCD_A0+ <16>
IYAP1 E14 LCD_A1+ <16>
DVO BCINTR# G2 C14
DVOBCINTR#/GAD30 IYAP2 LCD_A2+ <16>
D VOBC_CLKINT M3 B13
<15> DVOBC_CLKINT DVOBCCLKINT/GAD13 IYAP3
D VOBC_CLKINT H12
IYBM0 LCD_B0- <16>
<15> TV_CLK J3 DVOCCLK/GADSTB1 IYBM1 E12 LCD_B1- <16>
1
LVDS
R465 R465 = 50K; DVOCHSYNC/GAD17 IYBM3
<15> TV_VSYNC L5 DVOCVSYNC/GAD16 IYBP0 G12 LCD_B0+ <16>
@22_0402_5% C578 = 50K. L3 E11
DVOCBLANK#/GAD18 IYBP1 LCD_B1+ <16>
DVOC_FLDSTL H5 C11 LCD_B2+ <16>
2
DVOCFLDSTL/GAD31 IYBP2
IYBP3 G10
W/ TV-OUT D14
ICLKAM LCD_ACLK- <16>
C578 De-Pop M I2CCLK K7 E13
@10P_0402_50V8K <15> MI2CCLK MI2CCLK/GIRDY# ICLKAP LCD_ACLK+ <16> +3VS
MI2CDATA N6 E10
<15> MI2CDATA MI2CDATA/GDEVSEL# ICLKBM LCD_BCLK- <16>
M DVICLK N7 F10
MDVICLK/GTRDY# ICLKBP LCD_BCLK+ <16>
MDVIDATA M6
MD DCCLK MDVIDATA/GFRAME# R483 1
C P7 MDDCCLK/GSTOP# DDCPCLK B4 2 2.2K_0402_5% C
MDDCDATA T7 C5 R476 1 2 2.2K_0402_5%
MDDCDATA/GAD15 DDCPDATA CLK_M CH_DISPLAY CL K_VCH
PANELBKLTCTL G8
1
D VOC_TV_D[0..11] DVOC_TV_D0 K5 F8 ENBKL
<15> DVOC_TV_D[0..11] DVOCD0/GAD19 PANELBKLTEN ENBKL <32>
1
DVOC_TV_D1 K1 A5 ENVDD <16>
DVO
+1.5VS DVOC_TV_D2 DVOCD1/GAD20 PANELVDDEN R443 R405
K3 DVOCD2/GAD21
DVOC_TV_D3 K2 R444 1.5K_0603_1% @33_0402_5% @33_0402_5%
DVOC_TV_D4 DVOCD3/GAD22
J6 A10 1 2
2
DVOCD4/GAD23 LIBG
1
+1.5VS DVOC_TV_D5 J5
2
R468 DVOC_TV_D6 DVOCD5/GCBE3#
H2 DVOCD6/GAD25 RSVD3 D12 1 1
DVOC_TV_D7 H1 F12 C552
1K_0402_5% DVOC_TV_D8 DVOCD7/GAD24 RSVD4 C470
H3 DVOCD8/GAD27 RSVD5 B12
R486 DVOC_TV_D9 H4 @10P_0402_25V8K @10P_0402_25V8K
2
CLKS
DREFSSCLK
1
H9 CLK_VCH <14>
+GVREF LCLKCTLA LCLKCTLB
C6 1 2
D
LCLKCTLB +3VS
R456 1K_0402_5%
Q34 E5 LCLKCTLB H:1.2V
BSS138_SOT23 ADDID0/GSBA0
R471 Close to Ball F1
F5
E3
ADDID1/GSBA1
AA22
PSB Voltage Select
ADDID2/GSBA2 DPWR#
G
MISC
PCIRST# <15,17,20,21,22,23,25,26,31,32>
2
D1 DVO_GRCOMP NC0 B1
CLK_MCH_66M Y3 AH1
<14> CLK_MCH_66M GCLKIN NC1
1
R464 A2
@33_0402_5% R489 NC2
F2 GSBSTB NC3 AJ2
F3 A28
2
U26C
SDQ67 AG16
R395 DDR_SMAB1 AD16 AH14
<12> DDR_SMAB1 SMAB1 SDQ68
150_0603_1% DDR_SMAB2 AC12 AE15
<12> DDR_SMAB2 SMAB2 SDQ69
DDR_SMAB4 AF11 AF16
<12> DDR_SMAB4 SMAB4 SDQ70
DDR_SMAB5 AD10 AF17
<12> DDR_SMAB5
2
U26D
C1 VSS0 VSS91 R17
G1 VSS1 VSS92 U17
L1 AB17 +CPU_CORE
VSS2 VSS93 +1.5VS
U1 VSS3 VSS94 AC17
AA1 F18 U26E
VSS4 VSS95 C419
AE1
R2
VSS5 VSS96 J18
AA18
CLOSE TO VCC 0.1U_0402_10V6K
D AG3
VSS6 VSS97
AG18 C442 C479 J15
Montara-GT G15 1 1 1
1
D
VSS7 VSS98 C400 1 0.1U_0402_10V6K 0.1U_0402_10V6K VCC0 VTTLF0 + C357
AJ3 VSS8 VSS99 A19 1 P13 VCC1 VTTLF1 H16
D4 D19 150U_D2_6.3VM 1 1 1 1 1 T13 H18 150U_D2_4VM
VSS9 VSS100 + + VCC2 VTTLF2
G4 VSS10 VSS101 H19 N14 VCC3 VTTLF3 J19
C428 2 2 2 2
K4 VSS11 VSS102 AB19 R14 VCC4 VTTLF4 H20
N4 AE19 U14 L21 C420 C429
VSS12 VSS103 C3582 2 C461 2 2 2 2 2
0.1U_0402_10V6K VCC5 VTTLF5 0.1U_0402_10V6K 10U_1206_6.3V7K
T4 VSS13 VSS105 F20 P15 VCC6 VTTLF6 N21
W4 J20 150U_D2_6.3VM 10U_1206_6.3V7K C540 T15 R21
VSS14 VSS106 0.1U_0402_10V6K VCC7 VTTLF7
AA4 VSS15 VSS107 AA20 AA15 VCC8 VTTLF8 U21
AC4 AC20 N16 H22 0.1U_0402_10V6K
VSS16 VSS108 VCC9 VTTLF9
AE4 VSS17 VSS109 A21 R16 VCC10 VTTLF10 M22 1 1
B5 D21 +1.5VS U16 P22 C443 C368
VSS18 VSS110 L37 VCC11 VTTLF11
U5 VSS19 VSS111 H21 P17 VCC12 VTTLF12 T22
Y5 M21 KC FBM-L11-201209-221LMAT_0805 CLOSE TO VCCHL T17 V22
VSS20 VSS112 VCC13 VTTLF13 2 2
Y6 VSS21 VSS113 P21 1 2+VCCADPLLA AA17 VCC14 VTTLF14 Y29
AG6 T21 1 C572 AA19 K29 0.1U_0402_10V6K
VSS22 VSS114 VCC15 VTTLF15
C7 V21 CLOSE TO PIN 1 +1.5VS C561 0.1U_0402_10V6K W21 F29
VSS23 VSS115 + 0.1U_0402_10V6K VCC16 VTTLF16
E7 VSS24 VSS116 Y21 H14 VCC17 VTTLF17 AB29
G7 AA21 C525 C562 1 1 1 1 A26 C417 1 2 0.1U_0402_10V6K
VSS25 VSS117 220U_D2_4VM 0.1U_0402_10V6K VTTLF18
J7 VSS26 VSS118 AB21 VTTLF19 A20
2 2 C406 1
M7 VSS27 VSS119 AG21 V1 VCCHL0 VTTLF20 A18 2 0.1U_0402_10V6K
R7 VSS28 VSS120 B24 Y1 VCCHL1
AA7 F22 1 2 +VCCADPLLB C480 2 2 2 2
W5 A22 C380 1 2 0.1U_0402_10V6K
VSS29 VSS121 L28 10U_1206_6.3V7K C600 VCCHL2 VTTHF0
AE7 VSS30 VSS122 J22 1 1 U6 VCCHL3 VTTHF1 A24
AJ7 L22 KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K U8 H29 C379 1 2 0.1U_0402_10V6K
VSS31 VSS123 + VCCHL4 VTTHF2
H8 VSS32 VSS124 N22 W8 VCCHL5 VTTHF3 M29
K8 R22 V7 V29 C378 1 2 0.1U_0402_10V6K
VSS33 VSS125 C4782 VCCHL6 VTTHF4
Montara-GT
POWER
R9 F24 0.1U_0402_10V6K AB6
VSS42 VSS134 VCCSM7
2
L35 2 2 2 2 2 2 2 2
U9 VSS43 VSS135 H24 +1.5VS_DVO E1 VCCDVO_0 VCCSM8 AF6
W9 K24 FLM1608081R8K_0603 L31 J1 Y7
VSS44 VSS136 VCCDVO_1 VCCSM9 C394 C528 0.1U_0402_10V6K
AB9 VSS45 VSS137 M24 BLM21A601SPT_0805 N1 VCCDVO_2 VCCSM10 AA8
AG9 P24 +1.5VS_DAC E4 AB8 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS46 VSS138 VCCDVO_3 VCCSM11
C10 T24 J4 Y9
2
1
VSS48 VSS140 C534 VCCDVO_5 VCCSM13 C529 C477
AA10 VSS49 VSS141 AA24 1 E6 VCCDVO_6 VCCSM14 AJ9
AE10 AG24 C501 0.01U_0402_25V7Z
1 1 1 C544 H7 AB10 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS50 VSS142 + VCCDVO_7 VCCSM15 0.1U_0402_10V6K
D11 VSS51 VSS143 A25 1 1 1 1 J8 VCCDVO_8 VCCSM16 AA11 1 1 1 1 1 1
F11 D25 + 0.1U_0402_10V6K L8 AB12 C381 C426
VSS52 VSS144 @220U_D2_4VM C579 C618 VCCDVO_9 VCCSM17
H11 VSS53 VSS145 AA25 M8 VCCDVO_10 VCCSM18 AF12
2 2 2 0.1U_0402_10V6K 150U_D2_6.3VM
AB11 VSS54 VSS146 AE25 N8 VCCDVO_11 VCCSM19 AA13
C535 2 2 C513 2 2 C543 2 2 2 2 2 2 2
AC11 VSS55 VSS147 G26 R8 VCCDVO_12 VCCSM20 AJ13
AJ11 J26 0.1U_0402_10V6K 10U_1206_6.3V7K 0.1U_0402_10V6K K9 AB14 C455 C499
VSS56 VSS148 +1.5VS_DLVDS VCCDVO_13 VCCSM21 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
J12 VSS57 VSS149 L26 M9 VCCDVO_14 VCCSM22 AF15
AA12 VSS58 VSS150 N26 1 1 1 P9 VCCDVO_15 VCCSM23 AB16
AG12 VSS59 VSS151 R26 VCCSM24 AJ17
A13 U26 1 C580 AB18 C771 & C772 change to 100u
VSS60 VSS152 0.1U_0402_10V6K C546 C545 VCCSM25 next Reversion
D13 VSS61 VSS153 W26 1 +1.5VS_DAC A9 VCCADAC0 VCCSM26 AF18
C468 + 2 2 2
F13 VSS62 VSS154 AB26 B9 VCCADAC1 VCCSM27 AB20
H13 A27 47U_6.3V_M C491 0.1U_0402_10V6K 0.1U_0402_10V6K B8 AF21 1 1 1 1 0.1U_0402_10V6K
1 1
VSS63 VSS155 22U_1206_6.3V6M VSSADAC VCCSM28 C506 C388 C587 C519 C558 C542
N13 VSS64 VSS156 F27 VCCSM29 AJ21
B 2 2 + + B
R13 VSS65 VSS157 AC27 +1.5VS_ALVDS VCCSM30 AB22
U13 AG27 A11 AF24 0.1U_0402_10V6K
VSS66 VSS158 +1.5VS +1.5VS_ALVDS +1.5VS +1.5VS_DLVDS VCCALVDS VCCSM31 150U_D2_4VM 2 2 2 2
AB13 VSS67 VSS159 AJ27 B11 VSSALVDS VCCSM32 AJ25
2 2
AE13 VSS68 VSS160 AC28 L32 L29 VCCSM33 AF27
J14 AE28 AC29 150U_D2_4VM 0.1U_0402_10V6K 0.1U_0402_10V6K
VSS69 VSS161 VCCSM34
P14 VSS70 VSS162 C29 1 2 1 2 +1.5VS_DLVDS G13 VCCDLVDS0 VCCSM35 AF29
T14 E29 FLM1608081R8K_0603 1 1 FLM1608081R8K_0603 1 B14 AG29
VSS71 VSS163 C521 VCCDLVDS1 VCCSM36
AA14 VSS72 VSS164 G29 J13 VCCDLVDS2
AC14 J29 C512 C500 B15 +2.5V_QSM +2.5V
VSS73 VSS165 0.1U_0402_10V6K 0.01U_0402_25V7Z 0.1U_0402_10V6K VCCDLVDS3 C547 R429
D15 VSS74 VSS166 L29 L39
2 2 2 0.1U_0402_10V6K 0_0805_5%
H15 VSS75 VSS167 N29
N15 VSS76 VSS168 U29 +2.5V_TXLVDS F9 VCCTXLVDS0 1 2 1 2
R15 VSS77 VSS169 W29 B10 VCCTXLVDS1 VCCQSM0 AJ6 1 1
U15 AA29 D10 AJ8 KC FBM-L11-201209-221LMAT_0805
VSS78 VSS170 VCCTXLVDS2 VCCQSM1 C560
AB15 VSS79 VSS171 AJ10 A12 VCCTXLVDS3
AG15 AJ12 R493 +VCC_GPIO VCC_ASM 4.7U_1206_10V7K
VSS80 VSS172 0_0603_5% 2 2 +1.5VS
F16 VSS81 VSS173 AJ18 VCCASM0 AD1
J16 VSS82 VSS174 AJ20 +3VS 1 2 A3 VCCGPIO_0 VCCASM1 AF1 L40
P16 C22 C484 C520 A4
VSS83 VSS176 L33 22U_1206_16V4Z_V1 VCCGPIO_1
T16 D28 0.1U_0402_10V6K 1 1 1 2
VSS84 VSS177 C609 KC FBM-L11-201209-221LMAT_0805
AA16 VSS85 VSS178 E28 +2.5V 1 2 +2.5V_TXLVDS 1
AE16 L6 FLM1608081R8K_0603 10U_1206_6.3V7K C585 RG82G4350MA1_uFCBGA732_MONTARA-GT 1
VSS86 VSS179 0.1U_0402_10V6K + C612
A17 VSS87 VSS180 T9 1 1 1 1 1 2 2 C597 100U_D_16VM
D17 VSS88 VSS181 AJ26
H17 AJ1 C465 +
VSS89 VSS182 47U_6.3V_M 0.1U_0402_10V6K 2 2
N17 VSS90 2 2 2 2
2 C505 C530
A
0.1U_0402_10V6K 0.1U_0402_10V6K A
RG82G4350MA1_uFCBGA732_MONTARA-GT
+2.5V
RP100 10_0404_4P2R_5% RP68 10_0404_4P2R_5% +SDREF_DIMM DDR _DQ[0..63]
DDR_SDQ0 DDR_DQ0 DDR_SDQ27 DDR_DQ27 +2.5V DDR_DQ[0..63] <12>
1 4 1 4
DDR_SDQ1 2 3 DDR_DQ1 DDR_SDQ29 2 3 DDR_DQ29 JP21 R523 DDR _DQS[0..7]
DDR_DQS[0..7] <12>
1 VREF VREF 2 2 1 +SDREF
3 4 0_0402_5% D DR_DM[0..7]
DDR_DQ4 VSS VSS DDR_DQ0 DDR_DM[0..7] <12>
RP101 10_0404_4P2R_5% RP70 10_0404_4P2R_5% 5 6
DDR_SDQ4 DDR_DQ4 DDR_SDQ30 DDR_DQ30 DDR_DQ5 DQ0 DQ4 DDR_DQ1 R524
1 4 1 4 7 DQ1 DQ5 8 1
DDR_SDQ5 2 3 DDR_DQ5 DDR_SDQ26 2 3 DDR_DQ26 9 10 2 1
VDD VDD +SDREF_DIMM0
DDR_DQS0 11 12 DDR_DM0 @0_0402_5%
DDR_DQ3 DQS0 DM0 DDR_DQ7 C637 DDR_SMAA[6..12]
13 DQ2 DQ6 14 DDR_SMAA[6..12] <12>
RP97 10_0404_4P2R_5% RP56 10_0404_4P2R_5% 15 16 2 0.1U_0402_10V6K
DDR_SDQ3 DDR_DQ3 DDR_SDQ37 DDR_DQ37 DDR_DQ2 VSS VSS DDR_DQ6
1 4 1 4 17 18
DDR_SDQ2 DDR_DQ2 DDR_SDQ33 DDR_DQ33 DDR_DQ8 DQ3 DQ7 DDR_DQ12 DDR_SMAA0
2 3 2 3 19
DQ8 DQ12
20 DDR_SMAA0 <12>
21 22 +2.5V
1 DDR_DQ13 VDD VDD DDR_DQ9 DDR_SMAA3 1
23 24 DDR_SMAA3 <12>
RP95 10_0404_4P2R_5% RP54 10_0404_4P2R_5% DDR_DQS1 DQ9 DQ13 DDR_DM1
25 26
DQS1 DM1
1
DDR_SDQ7 1 4 DDR_DQ7 DDR_SDQ32 1 4 DDR_DQ32 27 28
DDR_SDQ6 DDR_DQ6 DDR_SDQ36 DDR_DQ36 DDR_DQ15 VSS VSS DDR_DQ10 R525
2 3 2 3 29 30
DDR_DQ14 DQ10 DQ14 DDR_DQ11 +SDREF_DIMM0 @10K_0603_1%
31 32
DQ11 DQ15
33 34
RP94 10_0404_4P2R_5% RP47 10_0404_4P2R_5% VDD VDD
35 36
2
DDR_SDQ8 DDR_DQ8 DDR_SDQ39 DDR_DQ39 <9> DDR_CLK0 CK0 VDD
1 4 1 4 <9> DDR_CLK0# 37
CK0# VSS
38
DDR_SDQ13 2 3 DDR_DQ13 DDR_SDQ35 2 3 DDR_DQ35 39 40
VSS VSS
1
DDR_SMA0 2 1 DDR_SMAA0
R526 R168 10_0402_5%
RP92 10_0404_4P2R_5% RP49 10_0404_4P2R_5% DDR_DQ18 41 42 DDR_DQ20 @10K_0603_1%
DDR_SDQ12 DDR_DQ12 DDR_SDQ38 DDR_DQ38 DDR_DQ16 DQ16 DQ20 DDR_DQ17
1 4 1 4 43 DQ17 DQ21 44
DDR_SDQ9 2 3 DDR_DQ9 DDR_SDQ34 2 3 DDR_DQ34 45 46
2
DDR_DQS2 VDD VDD DDR_DM2
47 DQS2 DM2 48
DDR_DQ21 49 50 DDR_DQ22 DDR_SMA3 2 1 DDR_SMAA3
RP88 10_0404_4P2R_5% RP43 10_0404_4P2R_5% DQ18 DQ22 R170 10_0402_5%
51 VSS VSS 52
DDR_SDQ15 1 4 DDR_DQ15 DDR_SDQ40 1 4 DDR_DQ40 DDR_DQ23 53 54 DDR_DQ19
DDR_SDQ14 DDR_DQ14 DDR_SDQ44 DDR_DQ44 DDR_DQ25 DQ19 DQ23 DDR_DQ24
2 3 2 3 55 DQ24 DQ28 56
57 VDD VDD 58
DDR_DQ31 59 60 DDR_DQ28
RP86 10_0404_4P2R_5% RP45 10_0404_4P2R_5% DDR_DQS3 DQ25 DQ29 DDR_DM3 DDR_SMA6 DDR_SMAA6
61 DQS3 DM3 62 2 1
DDR_SDQ10 1 4 DDR_DQ10 DDR_SDQ41 1 4 DDR_DQ41 63 64 R171 10_0402_5%
DDR_SDQ11 DDR_DQ11 DDR_SDQ45 DDR_DQ45 DDR_DQ27 VSS VSS DDR_DQ30 DDR_SMA7 DDR_SMAA7
2 3 2 3 65 DQ26 DQ30 66 2 1
DDR_DQ29 67 68 DDR_DQ26 R176 10_0402_5%
DQ27 DQ31 DDR_SMA8 DDR_SMAA8
69 VDD VDD 70 2 1
RP80 10_0404_4P2R_5% RP38 10_0404_4P2R_5% 71 72 R177 10_0402_5%
DDR_SDQ18 DDR_DQ18 DDR_SDQ43 DDR_DQ43 CB0 CB4 DDR_SMA9 DDR_SMAA9
1 4 1 4 73 CB1 CB5 74 2 1
DDR_SDQ16 2 3 DDR_DQ16 DDR_SDQ47 2 3 DDR_DQ47 75 76 R183 10_0402_5%
VSS VSS DDR_SMA10 2 DDR_SMAA10
77 DQS8 DM8 78 1
79 80 R160 10_0402_5%
RP84 10_0404_4P2R_5% RP40 10_0404_4P2R_5% CB2 CB6 DDR_SMA11 2 DDR_SMAA11
81 VDD VDD 82 1
2 DDR_SDQ20 DDR_DQ20 DDR_SDQ46 DDR_DQ46 R184 10_0402_5% 2
1 4 1 4 83 CB3 CB7 84
DDR_SDQ17 2 3 DDR_DQ17 DDR_SDQ42 2 3 DDR_DQ42 85 86 DDR_SMA12 2 1 DDR_SMAA12
DU DU/RESET# R188 10_0402_5%
87 VSS VSS 88
89 CK2 VSS 90
RP75 10_0404_4P2R_5% RP34 10_0404_4P2R_5% 91 92
DDR_SDQ21 DDR_DQ21 DDR_SDQ52 DDR_DQ52 CK2# VDD
1 4 1 4 93 VDD VDD 94
DDR_SDQ23 2 3 DDR_DQ23 DDR_SDQ50 2 3 DDR_DQ50 DDR_CKE1 95 96 DDR_CKE0
<9> DDR_CKE1 CKE1 CKE0 DDR_CKE0 <9>
97 98
DDR_SMA12 DU/A13 DU/BA2 DDR_SMA11
99 100
RP82 10_0404_4P2R_5% RP36 10_0404_4P2R_5% DDR_SMA9 A12 A11 DDR_SMA8
101 102
DDR_SDQ19 DDR_DQ19 DDR_SDQ48 DDR_DQ48 A9 A8
1 4 1 4 103
VSS VSS
104 Layout note
DDR_SDQ22 2 3 DDR_DQ22 DDR_SDQ53 2 3 DDR_DQ53 DDR_SMA7 105 106 DDR_SMA6
DDR_SMA5 A7 A6 DDR_SMA4
107
A5 A4
108 Place these resistor
DDR_SMA3 109 110 DDR_SMA2
RP73 10_0404_4P2R_5% RP30 10_0404_4P2R_5% DDR_SMA1 111
A3 A2
112 DDR_SMA0 close by DIMM0,
DDR_SDQ25 DDR_DQ25 DDR_SDQ51 DDR_DQ51 A1 A0 all trace length
1 4 1 4 113 114
DDR_SDQ31 DDR_DQ31 DDR_SDQ54 DDR_DQ54 DDR_SMA10 VDD VDD DDR_SBS1
2 3 2 3 115 116 Max=1.4"
DDR_SBS0 A10/AP BA1 DDR_SRAS#
117 118
DDR_SWE# BA0 RAS# DDR_SCAS#
119 120
RP78 10_0404_4P2R_5% RP28 10_0404_4P2R_5% DDR_SCS#0 WE# CAS# DDR_SCS#1
<9> DDR_SCS#0 121 122 DDR_SCS#1 <9>
DDR_SDQ24 DDR_DQ24 DDR_SDQ49 DDR_DQ49 S0# S1#
1 4 1 4 123 124
DDR_SDQ28 DDR_DQ28 DDR_SDQ55 DDR_DQ55 DU DU +1.25VS
2 3 2 3 125 126
DDR_DQ32 VSS VSS DDR_DQ37
127 128
DDR_DQ36 DQ32 DQ36 DDR_DQ33
129 130
RP24 10_0404_4P2R_5% RP21 10_0404_4P2R_5% DQ33 DQ37
131 132
DDR_SDQ60 DDR_DQ60 DDR_SDQ62 DDR_DQ62 DDR_DQS4 VDD VDD DDR_DM4
1 4 1 4 133 134 RP15
DDR_SDQ61 DDR_DQ61 DDR_SDQ63 DDR_DQ63 DDR_DQ39 DQS4 DM4 DDR_DQ38 DDR_CKE0 1
2 3 2 3 135
DQ34 DQ38
136 4
137 138 DDR_CKE1 2 3
DDR_DQ35 VSS VSS DDR_DQ34
139 140
RP26 10_0404_4P2R_5% RP19 10_0404_4P2R_5% DDR_DQ40 DQ35 DQ39 DDR_DQ41 56_0404_4P2R_5%
141 142
DDR_SDQ57 DDR_DQ57 DDR_SDQ58 DDR_DQ58 DQ40 DQ44
1 4 1 4 143 144
DDR_SDQ56 DDR_DQ56 DDR_SDQ59 DDR_DQ59 DDR_DQ44 VDD VDD DDR_DQ45
2 3 2 3 145 146
3 DDR_DQS5 DQ41 DQ45 DDR_DM5 3
147 148 RP9
DQS5 DM5 DDR_SCS#1 1
149 150 4
DDR_DQ43 VSS VSS DDR_DQ46 DDR_SCS#0 2
151 152 3
DDR_DQ47 DQ42 DQ46 DDR_DQ42
153 154
DQ43 DQ47 56_0404_4P2R_5%
155 156
VDD VDD
157 158 DDR_CLK1# <9>
VDD CK1#
159 160 DDR_CLK1 <9>
DDR_SDQS0 DDR_DQS0 DDR_SDM0 DDR_DM0 VSS CK1
2 1 2 1 161 162
R507 10_0402_5% R506 10_0402_5% DDR_DQ52 VSS VSS DDR_DQ48
163 164
DDR_SDQS1 DDR_DQS1 DDR_SDM1 DDR_DM1 DDR_DQ50 DQ48 DQ52 DDR_DQ53
2 1 2 1 165
DQ49 DQ53
166
R500 10_0402_5% R498 10_0402_5% 167 168
DDR_SDQS2 DDR_DQS2 DDR_SDM2 DDR_DM2 DDR_DQS6 VDD VDD DDR_DM6
2 1 2 1 169 170
R459 10_0402_5% R475 10_0402_5% DDR_DQ51 DQS6 DM6 DDR_DQ49
171 172
DDR_SDQS3 DDR_DQS3 DDR_SDM3 DDR_DM3 DQ50 DQ54
2 1 2 1 173 174
R440 10_0402_5% R449 10_0402_5% DDR_DQ54 VSS VSS DDR_DQ55
175 176
DDR_DQ57 DQ51 DQ55 DDR_DQ60
177 178
DDR_SDQS4 DDR_DQS4 DDR_SDM4 DDR_DM4 DQ56 DQ60
2 1 2 1 179 180
R361 10_0402_5% R363 10_0402_5% DDR_DQ56 VDD VDD DDR_DQ61
181 182
DDR_SDQS5 DDR_DQS5 DDR_SDM5 DDR_DM5 DDR_DQS7 DQ57 DQ61 DDR_DM7
2 1 2 1 183 184
R343 10_0402_5% R345 10_0402_5% DQS7 DM7
185 186
DDR_SDQS6 DDR_DQS6 DDR_SDM6 DDR_DM6 DDR_DQ62 VSS VSS DDR_DQ58
2 1 2 1 187 188
R333 10_0402_5% R332 10_0402_5% DDR_DQ63 DQ58 DQ62 DDR_DQ59 DDR_SBS0
189 190 <9> DDR_SBS0 2 1 DDR_BS0 <12>
DDR_SDQS7 DDR_DQS7 DDR_SDM7 DDR_DM7 DQ59 DQ63 R158 10_0402_5%
2 1 2 1 191 192
R330 10_0402_5% R329 10_0402_5% VDD VDD DDR_SBS1
<12,14,17> SMDATA 193 194 <9> DDR_SBS1 2 1 DDR_BS1 <12>
SDA SA0 R159 10_0402_5%
<12,14,17> SMCLK 195 196
SCL SA1 DDR_SRAS#
197 198 <9> DDR_SRAS# 2 1 DDR_RAS# <12>
+3VS VDD_SPD SA2 R157 10_0402_5%
199 200
VDD_ID DU DDR_SCAS#
<9> DDR_SCAS# 2 1 DDR_CAS# <12>
DD R_SDQ[0..63] R152 10_0402_5%
DDR_SDQ[0..63] <9>
KLINK_5746-2-111 DDR_SWE# 2 1
DD R_SDQS[0..7] <9> DDR_SWE# DDR_WE# <12>
R153 10_0402_5%
DDR_SDQS[0..7] <9>
4 4
DDR_SDM[0..7] Layout note
DDR_SDM[0..7] <9>
Place these resistors
DDR_SMA[1..2]
DDR_SMA[1..2] <9,12> close to DIMM0,
DDR_SMA[4..5] all trace length<500 mil
DDR_SMA[4..5] <9,12>
DDR_SMA[6..12] DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE# Compal Electronics, Inc.
DDR_SMA[6..12] <9>
Title
DDR_SMA0
SCHEMATIC, M/B LA-1931
DDR_SMA0 <9> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DDR_SMA3 401264 1B
DDR_SMA3 <9> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 11 of 49
A B C D E F G H
A B C D E
1
DDR_DQ1 2 3 3 2 DDR_DQS3 3 2 DDR_DQ51 DDR_DQ4 5 6 DDR_DQ0
DDR_DQ5 DQ0 DQ4 DDR_DQ1 R529
7 DQ1 DQ5 8
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 9 10 @10K_0603_1%
RP99 DDR_DQS0 VDD VDD DDR_DM0
RP71 RP32 11 12 1
DDR_DQ4 DQS0 DM0
1 4 4 1 DDR_DQ28 4 1 DDR_DM6 DDR_DQ3 13 14 DDR_DQ7
2
DDR_DQ5 DQ2 DQ6
2 3 3 2 DDR_DM3 3 2 DDR_DQ49 15 16 C227 +SDREF_DIMM0
DDR_DQ2 VSS VSS DDR_DQ6 0.1U_0402_10V6K
17 18
DQ3 DQ7
1
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% DDR_DQ8 19 20 DDR_DQ12 2
RP93 DQ8 DQ12 R530
RP66 RP27 21 22
1 DDR_DM0 VDD VDD 1
1 4 4 1 DDR_DQ27 4 1 DDR_DQ54 DDR_DQ13 23 24 DDR_DQ9 @10K_0603_1%
DDR_DQ7 DQ9 DQ13
2 3 3 2 DDR_DQ29 3 2 DDR_DQ57 DDR_DQS1 25
DQS1 DM1
26 DDR_DM1
27 28
2
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% DDR_DQ15 VSS VSS DDR_DQ10
29 30
DDR_DQ14 DQ10 DQ14 DDR_DQ11
RP67 RP29 31 32
DDR_DQS0 1 RP96 DQ11 DQ15 +1.25VS
4 4 1 DDR_DQ30 4 1 DDR_DQ55 33
VDD VDD
34
DDR_DQ3 2 3 3 2 DDR_DQ26 3 2 DDR_DQ60 35 36
<9> DDR_CLK3 CK0 VDD
<9> DDR_CLK3# 37 38
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% CK0# VSS
39 40
VSS VSS
RP90 RP57 RP23 1 2 DDR_SMAA12
DDR_DQ6 1 4 4 1 DDR_DQ32 4 1 DDR_DQ56 R182 56_0402_5%
DDR_DQ12 2 3 3 2 DDR_DQ36 3 2 DDR_DQS7 DDR_DQ18 41 42 DDR_DQ20
DDR_DQ16 DQ16 DQ20 DDR_DQ17 RP64 56_0404_4P2R_5%
43 DQ17 DQ21 44
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 45 VDD VDD 46 4 1 DDR_SMAA11
RP91 RP53 RP20 DDR_DQS2 47 48 DDR_DM2 3 2 DDR_SMAA9
DDR_DQ2 DQS2 DM2
1 4 4 1 DDR_DQ37 4 1 DDR_DQ62 DDR_DQ21 49 50 DDR_DQ22
DDR_DQ8 DQ18 DQ22
2 3 3 2 DDR_DQ33 3 2 DDR_DQ63 51 VSS VSS 52
DDR_DQ23 53 54 DDR_DQ19 RP63 56_0404_4P2R_5%
DDR_DQ25 DQ19 DQ23 DDR_DQ24
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 55 DQ24 DQ28 56 4 1 DDR_SMAA7
RP87 RP48 RP25 57 58 3 2 DDR_SMAA8
DDR_DQ9 VDD VDD
1 4 4 1 DDR_DQS4 4 1 DDR_DQ61 DDR_DQ31 59 DQ25 DQ29 60 DDR_DQ28
DDR_DM1 2 3 3 2 DDR_DQ39 3 2 DDR_DM7 DDR_DQS3 61 62 DDR_DM3
DQS3 DM3 RP60 56_0404_4P2R_5%
63 VSS VSS 64
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% DDR_DQ27 65 66 DDR_DQ30 4 1 DDR_SMAA6
DDR_DQ29 DQ26 DQ30 DDR_DQ26
RP89 RP51 RP22 67 68 3 2 DDR_SMAA3
DDR_DQ13 1 DQ27 DQ31
4 4 1 DDR_DM4 4 1 DDR_DQ58 69 VDD VDD 70
DDR_DQS1 2 3 3 2 DDR_DQ38 3 2 DDR_DQ59 71 72
CB0 CB4 RP58 56_0404_4P2R_5%
73 CB1 CB5 74
56_0404_4P2R_5% 56_0404_4P2R_5% 56_0404_4P2R_5% 75 VSS VSS 76 4 1 DDR_SMAA10
RP85 RP44 77 DQS8 DM8 78 3 2 DDR_SMAA0
DDR_DQ15 1 4 4 1 DDR_DQ35 79 80
DDR_DQ14 2 CB2 CB6
3 3 2 DDR_DQ40 81 VDD VDD 82
2 2
83 CB3 CB7 84
56_0404_4P2R_5% 56_0404_4P2R_5% 85 86
DU DU/RESET# DDR_SMA1
RP83 RP46 87 88 2 1
DDR_DQ10 1 DDR _DQS[0..7] VSS VSS
4 4 1 DDR_DQ34 DDR_DQS[0..7] <11> 89 CK2 VSS 90 R169 56_0402_5%
DDR_DQ11 2 3 3 2 DDR_DQ41 91 92 2 1 DDR_SMA2
DDR _DQ[0..63] CK2# VDD R167 56_0402_5%
DDR_DQ[0..63] <11> 93 VDD VDD 94
56_0404_4P2R_5% 56_0404_4P2R_5% DDR_CKE3 95 96 DDR_CKE2
D DR_DM[0..7] <9> DDR_CKE3 CKE1 CKE0 DDR_CKE2 <9>
RP79 RP41 DDR_DM[0..7] <11> 97 98
DDR_DQ18 1 DU/A13 DU/BA2
4 4 1 DDR_DQ44 DDR_SMAA12 99
A12 A11
100 DDR_SMAA11 RP59 56_0404_4P2R_5%
DDR_DQ16 2 3 3 2 DDR_DQS5 DDR_SMAA9 101 102 DDR_SMAA8 4 1 DDR_SMAB1
A9 A8
103
VSS VSS
104 3 2 DDR_SMAB2
56_0404_4P2R_5% 56_0404_4P2R_5% DDR_SMA[1..2] DDR_SMAA7 105 106 DDR_SMAA6
DDR_SMA[1..2] <9,11> A7 A6
RP81 RP42 DDR_SMAB5 107 108 DDR_SMAB4
DDR_DQ20 1 DDR_SMA[4..5] A5 A4
4 4 1 DDR_DQ45 DDR_SMA[4..5] <9,11>
DDR_SMAA3 109 110 DDR_SMAB2 RP13 56_0404_4P2R_5%
DDR_DQ17 2 A3 A2
3 3 2 DDR_DM5 DDR_SMAB1 111
A1 A0
112 DDR_SMAA0 4 1 DDR_SMA4
113 114 3 2 DDR_SMA5
56_0404_4P2R_5% 56_0404_4P2R_5% DDR_SMAA10 VDD VDD DDR_BS1
115 116 DDR_BS1 <11>
DDR_SMAA[6..12] DDR_BS0 A10/AP BA1 DDR_RAS#
RP76 RP37 DDR_SMAA[6..12] <11> <11> DDR_BS0 117 118 DDR_RAS# <11>
DDR_DQS2 1 BA0 RAS#
4 4 1 DDR_DQ43 <11> DDR_WE#
DDR_WE# 119 120 DDR_CAS#
DDR_CAS# <11>
RP61 56_0404_4P2R_5%
DDR_DQ21 2 WE# CAS#
3 3 2 DDR_DQ47 <9> DDR_SCS#2
DDR_SCS#2 121
S0# S1#
122 DDR_CS#3
DDR_SCS#3 <9> 4 1 DDR_SMAB4
DDR_SMAA0 123 124 3 2 DDR_SMAB5
DDR_SMAA0 <11> DU DU
56_0404_4P2R_5% 56_0404_4P2R_5% 125 126
DDR_SMAA3 DDR_DQ32 VSS VSS DDR_DQ37
RP77 RP39 DDR_SMAA3 <11> 127 128
DDR_DM2 1 DQ32 DQ36
4 4 1 DDR_DQ46 DDR_DQ36 129 130 DDR_DQ33 RP12 56_0404_4P2R_5%
DDR_DQ22 2 DQ33 DQ37
3 3 2 DDR_DQ42 131 132 4 1 DDR_WE#
DDR_DQS4 VDD VDD DDR_DM4
133 134 3 2 DDR_BS0
56_0404_4P2R_5% 56_0404_4P2R_5% DDR_DQ39 DQS4 DM4 DDR_DQ38
135 136
DQ34 DQ38
RP72 RP33 137 138
DDR_DQ23 1 VSS VSS
4 4 1 DDR_DQ52 <9> DDR_SMAB1
DDR_SMAB1 DDR_DQ35 139 140 DDR_DQ34 RP55 56_0404_4P2R_5%
DDR_DQ25 2 DQ35 DQ39
3 3 2 DDR_DQ50 DDR_DQ40 141 142 DDR_DQ41 4 1 DDR_RAS#
DQ40 DQ44
143 144 3 2 DDR_CAS#
56_0404_4P2R_5% 56_0404_4P2R_5% DDR_SMAB2 DDR_DQ44 VDD VDD DDR_DQ45
<9> DDR_SMAB2 145 146
3 DDR_DQS5 DQ41 DQ45 DDR_DM5 3
RP74 RP35 147 148
DDR_DQ19 1 DQS5 DM5
4 4 1 DDR_DQ48 149
VSS VSS
150
DDR_DQ24 2 3 3 2 DDR_DQ53 DDR_SMAB4 DDR_DQ43 151 152 DDR_DQ46 1 2 DDR_BS1
<9> DDR_SMAB4 DDR_DQ47 DQ42 DQ46 DDR_DQ42
153 154 R389 56_0402_5%
56_0404_4P2R_5% 56_0404_4P2R_5% DQ43 DQ47
155 156
DDR_SMAB5 VDD VDD
<9> DDR_SMAB5 157 158 DDR_CLK4# <9>
VDD CK1#
159 160 DDR_CLK4 <9>
VSS CK1 +1.25VS
Layout note 161
VSS VSS
162
DDR_DQ52 163 164 DDR_DQ48
DDR_DQ50 DQ48 DQ52 DDR_DQ53
Place these resistor 165
DQ49 DQ53
166
closely DIMM1, 167 168
DDR_DQS6 VDD VDD DDR_DM6
169 170 RP62
all trace DDR_DQ51 DQS6 DM6 DDR_DQ49 DDR_CKE3 1
171 172 4
DQ50 DQ54 DDR_CKE2 2
length<=800mil 173 174 3
DDR_DQ54 VSS VSS DDR_DQ55
175 176
DDR_DQ57 DQ51 DQ55 DDR_DQ60 56_0404_4P2R_5%
177 178
DQ56 DQ60
179 180
DDR_DQ56 VDD VDD DDR_DQ61
181 182 RP10
DDR_DQS7 DQ57 DQ61 DDR_DM7 DDR_SCS#2 1
183 184 4
DQS7 DM7 DDR_SCS#3 2
185 186 3
DDR_DQ62 VSS VSS DDR_DQ58
187 188
DDR_DQ63 DQ58 DQ62 DDR_DQ59 56_0404_4P2R_5%
189 190
DQ59 DQ63
191 192
VDD VDD
<11,14,17> SMDATA 193
SDA SA0
194
+3VS
Layout note
<11,14,17> SMCLK 195 196
SCL SA1
+3VS
197
VDD_SPD SA2
198 Place these resistor
199 200 close by DIMM1,
VDD_ID DU
all trace length
DDR-SODIMM_200_STD_H4.0 Max=0.8"
4 4
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401264
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期三, 九月 24, 2003 Sheet 12 of 49
A B C D E
A B C D E
+2.5V +2.5V
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
+ C333 C82 C88 C107 C94 C156 C73 C139 C166
1 + C334 C135 C97 C80 C70 C196 C164 C195 C98 150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 1
150U_D2_6.3VM 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C162 C151 C178 C167 C72 C179 C134 C86 C117 C194 C193 C183 C175 C115 C81 C170 C181 C74
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
C228
+ + C643
150U_D2_6.3VM 150U_D2_6.3VM
2 2
Layout note :
Place one cap close to every 2 pull up resistors termination to
2 +1.25VS 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C431 C421 C413 C409 C405 C402 C398 C392 C384 C377
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C440 C444 C450 C476 C483 C503 C539 C550 C557 C511
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1
C617 C619 C622 C625 C628 C629
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
3 2 2 2 2 2 2 3
+1.25VS
1 1 1 1 1 1 1 1 1 1
C141 C160 C142 C155 C464 C566 C367 C498 C627 C366
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C517 C350 C360 C526 C576 C356 C615 C584 C355 C616
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2 2 2 2 2
+1.25VS
4 4
1 1 1 1 1 1
C590 C354 C603 C596 C352 C607
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 2 2 2 2 2
1 1
+3VS +3V_CLK
L6
* CPU Frequency Select Table (Based on H_BSEL0) KC FBM-L11-201209-221LMAT_0805
1 2
SEL[2:0] CK-408 Speed
1 1 1 1 1 1
L7 +3V_48M
001 100 MHZ BLM21A601SPT_0805 C65 C362 C361 C364 C62 C60
+3VS 1 2 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
011 133 MHZ 1 1
C76 C68
4.7U_0805_10V4Z 0.1U_0402_16V4Z +3VS
2 2
14
19
32
37
46
50
1
8
1 2 U17
R129 0_0402_5% BLM21A601SPT_0805
VDD_PCI_0
VDD_PCI_1
VDD_REF
VDD_3V66_0
VDD_3V66_1
VDD_CPU_0
VDD_CPU_1
VDD_48MHZ
L8
+3V C96 @10P_0402_50V8K
1 2 XTALIN 2 26 +3V_VDD 1 2
+3VS +3VS XTAL_IN VDDA
1
1 1 1 1
X2 C90
5
1
U21 C363 C63 C91
1
1 R94 14.31818MHZ_20P 0.1U_0402_16V4Z 10U_1206_10V4Z
P
2
<18,32> PM_SLP_S3# IN1 CLK_PWD# 2 2 2 2
4 1 2 R83 20K_0402_5%
O R128 @0_0402_5% 20K_0402_5% XTALOUT 0.1U_0402_16V4Z
0.1U_0402_16V4Z
<18,32> PM_SLP_S1# 2 IN2 1 2 3 XTAL_OUT VSSA 27
G
C101 @10P_0402_50V8K
2
@SN74AHC1G08HDCK_TSSOP5 45 CPU_BCLK 1 2
3
2
CPUCLKT2 CLK_CPU_BCLK <4>
54 R100 33_0402_1%
H_SEL0 SEL0 R90 49.9_0402_1%
<5> H_BSEL0 2 1 55 SEL1
2 R95 0_0402_5% 2
1 2 40 SEL2 1 2
R85 1K_0402_5% 1 2
R91 49.9_0402_1%
CLK_PWD# 25 44 CPU_BCLK# 1 2
+3VS PWR_DWN# CPU_CLKC2 CLK_CPU_BCLK# <4>
34 R101 33_0402_1%
<18> PM_STPPCI# PCI_STOP#
53 49 MCH_BCLK 1 2
<18,44> PM_STPCPU# CPU_STOP# CPUCLKT1 CLK_MCH_BCLK <7>
R98 33_0402_1%
1
R88 49.9_0402_1%
R437 1 2
10K_0402_5% VTT_PWRGD# 28 1 2
VTT_PWRGD# R89 49.9_0402_1%
2
D 10K_0402_5% CPU_ITP
52 1 2 CLK_CPU_ITP <5>
CPUCLKT0 R96 33_0402_1%
<18,35,44> VGATE 1 2 2 2 1
R445 0_0402_5% G Q13 R76 @1K_0603_1% R86 49.9_0402_1%
+CPU_CORE 1 2 S 2N7002_SOT23 29 1 2
3
23
R75 3V66_4 MCH_66M
1 2 475_0402_1% 42 22 R125 1 2 33_0402_5%
CLK_MCH_66M <8>
IREF 3V66_3 ICH_66M R124 1 33_0402_5%
21 2 CLK_ICH_66M <17>
3V66_2
3 3
<18> CLK_ICH_48M
R102 1 2 33_0402_5% ICH_48M 39
48MHZ_USB PCICLK_F2
7 PCI_ICH R117 1 2 33_0402_5%
CLK_PCI_ICH <17>
6
PCICLK_F1
5
PCICLK_F0
<8> CLK_MCH_DISPLAY
R103 1 2 33_0402_5% MCH_DISPLAY 38
48MHZ_DOT
18
PCICLK6 PCI_1394 R123 33_0402_5%
17 1 2 CLK_PCI_1394 <20>
PCICLK5 PCI_LAN R122 33_0402_5%
16 1 2 CLK_PCI_LAN <23>
PCICLK4
<18> CLK_ICH_14M
R105 1 2 33_0402_5% ICH_14M 56 13 PCI_PCM R121 1 2 33_0402_5%
CLK_PCI_CB <21>
REF PCICLK3 PCI_MINI R120 33_0402_5%
12 1 2 CLK_PCI_MINI <25>
PCICLK2
GND_3V66_0
GND_3V66_1
GND_48MHZ
R106 1 2 33_0402_5% 11 PCI_SIO R119 1 2 33_0402_5%
GND_PCI_0
GND_PCI_1
<31> CLK_SIO_14M PCICLK1 CLK_PCI_SIO <31>
GND_IREF
GND_CPU
PCI_LPC
GND_REF
10 R118 1 2 33_0402_5%
PCICLK0 CLK_LPC_EC <32>
1 1 1 1
C57 C58 C372 C371
@10P_0402_50V8K @10P_0402_50V8K CY28346ZCT-2 @10P_0402_50V8K @10P_0402_50V8K
4
9
15
20
31
36
41
47
2 2 2 2
4 4
CH-7011A U5
21
22
24
25
27
28
30
31
DVOC_TV_D[0..11]
<8> DVOC_TV_D[0..11] DVOC_TV_D11 50 9
NC
NC
NC
NC
NC
NC
NC
NC
DVOC_TV_D10 D11 NC
51 D10
DVOC_TV_D9 52 47
DVOC_TV_D8 D9 BCO
53 D8
DVOC_TV_D7 54 48
DVOC_TV_D6 D7 C/H Sync R293 75_0402_5%
55
DVOC_TV_D5 D6
58 36 1 2
DVOC_TV_D4 D5 CVBS
59
1 DVOC_TV_D3 D4 LUMA 1
60 37
DVOC_TV_D2 D3 Y/G
61
DVOC_TV_D1 D2 CRMA +3VS_7011_DVDD
62 38
DVOC_TV_D0 D1 C/R/V R63 0_0603_5%
63
D0 COMPS
39 1 2 +3VS
CVBS/B/U
<8> TV_CLK# 56 1 1 1 1
XCLK* C35 C29 C23 C36
<8> TV_CLK 57 1
XCLK DVDD0
12
DVDD1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_1206_16V4Z_V1
2 49
NC DVDD2 2 2 2 2
<8> DVOBC_CLKINT 46 6
Pout/DET# DGND0
DGND1 11
4 H DGND2 64
<8> TV_HSYNC
5 V
2N7002_SOT23 <8> TV_VSYNC 45 +3VS_7011_AVDD
Q29 DVDDV +1.5VS R298 0_0603_5%
<8,17,20,21,22,23,25,26,31,32> PCIRST# 13 RESET*
NC 23 1 2 +3VS
S
<8> MI2CDATA 3 1 14 29 1 1 1
SD NC C311 C288 C294
15 SC NC 20
2N7002_SOT23 26
GPIO1 NC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_1206_16V4Z_V1
G
7 32
2
GPIO1 NC 2 2 2
S
3 1 GPIO0 8
<8> MI2CCLK +3VS GPIO0 +3VS_7011_VDD
R47 18
AVDD0 R299
2 1 10 AS AVDD1 44
1
16 1 1 +3VS
2
AGND0
2
R34 @10K_0402_5% 35 17 0_0603_5%
ISET AGND1
1
2
R540 R309 10K_0402_5% 19 33 0.1U_0402_16V4Z 22U_1206_16V4Z_V1
NC VDD 2 2
XI/FIN
I2C Address = 1110110X 330_0402_5% R289 34
2
XO
3 40
1
VREF GND1
1
140_0402_5%
2
42
43
2 2
+3VS
Pull Low: Default NTSC
10K_0402_5%
( For Power on default )
2
1
+1.5VS
1
R282
Y1
R300
+3VS
1
4.7K_0402_5% 1 2
R51 @10K_0402_5%
2
2
10K_0402_1% 14.318MHZ
1 1
C22 C38 GPIO1 GPIO0
2
22P_0402_50V8J 22P_0402_50V8J
1
2 2
1
1
1 C305 R303
C28 R54
0.1U_0402_16V4Z 330_0402_5%
0.1U_0402_16V4Z 10K_0402_1% 2
2
2
2
3
TV-OUT CONN. 3
1
D7 D6
V-PORT-0603-220 M-V05_0603 V-PORT-0603-220 M-V05_0603
2
C8 1 2 @33P_0402_50V8J
L3 FBM-11-160808-121-T_0603
LUMA 1 2
JP14
C9 1 2 @33P_0402_50V8J 1
1
2
L4 FBM-11-160808-121-T_0603 2
3
CRMA 3
1 2 4
COMPS 4
SUYIN_030008FR004T100ZL
1
R305 R25
75_0402_1% 75_0402_1% R24 1 1
75_0402_1% C12 C7
2
100P_0402_50V8K 270P_0402_25V8K
2
2 2
4
1 4
C10
1
C13 270P_0402_25V8K
2
100P_0402_50V8K
2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 15 of 49
A B C D E F G H
A B C D E
+CRT_VCC
+3VS +3VS
1
R11 R17
2
+5VS +R_CRT_VCC 2.2K_0402_5% 2.2K_0402_5%
D9 F1 R29 R27
2 1 1 2 2.2K_0402_5% 10K_0402_5%
2
1A_6VDC_MINISMDC110 +CRT_VCC
1
CH491D_SOT23 R18
10K_0402_5%
Q1
2
1 2N7002_SOT23 1
1
1
DDC_DATA 1 3 INTDDCDA <8>
C6
S
1
1
0.1U_0402_16V4Z
2
2 Q2
G
D24
1 1 1 V-PORT-0603-220 M-V05_0603 D23 DDC_CLK 1 3 INTDDCCK <8>
C277 C278 C279 V-PORT-0603-220 M-V05_0603
S
D22 2N7002_SOT23
2
3.3P_0402_50V8C 3.3P_0402_50V8C 3.3P_0402_50V8C V-PORT-0603-220 M-V05_0603 JP12
2 2 2 6
L22 FCM2012C-800_0805 11
1 2 CRT_R 1
<8> INTCRT_R
7
L21 FCM2012C-800_0805 12
1 2 CRT_G 2
<8> INTCRT_G
8
L20 FCM2012C-800_0805 13
1 2 CRT_B 3
CRT Connector
<8> INTCRT_B
9
1
+5VS 1 1 1 14
R276 R277 R278 4
C262 C261 C260 10
75_0402_1% 75_0402_1% 75_0402_1% 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 15
2 2 2 5
2
5
SUYIN_070549MR015S200ZU
OE#
P
2 4 H S YNC 1 2 CR T_HSYNC
<8> INTCRT_HSYNC A Y L1
G
CHB1608B121_0603
U1
3
2 CRT_VSYNC 2
1 2
SN74AHCT1G125GW_SOT353-5 L2 1 1
CHB1608B121_0603
2
C3 C4
R28 27P_0402_50V8J 27P_0402_50V8J
2 2
1K_0402_5%
1
5
1 1 1
OE#
P
2 4 VSYNC C259 C2 C5
<8> INTCRT_VSYNC A Y 100P_0402_50V8J 100P_0402_50V8J
G
2 2 2
U2
3
SN74AHCT1G125GW_SOT353-5 100P_0402_50V8J
B+ Protect for EC
+3VS
+3VALW
1 1
1
C290 C282
R290
4.7K_0402_5% 0.1U_0603_50V4Z 10U_1210_35V4Z B+
1
2 2 L24 CHB2012U170_0805
1 2 D42
2
3 D30 RB751V 3
1
1 2 DISPOFF# 1 2 JP1
<32> BKOFF# IB+
L23 R519 D43
2
1
1
2 R301 CHB2012U170_0805 1 2 BRIG RB751V
2 <32> DAC_BRIG
RB751V C296 D44
BRIG 3 1K_0402_5% RB751V
2
1000P_0402_50V7K @0_0402_5% PWM 4
1 DISP_OFF# 5 R520
2
+3V 6 PWM
<32> INVT_PWM 1 2
7
+LCDVDD 8 1K_0402_5%
<8> LCD_B0+ 9
1 <8> LCD_B0- 10 R521
<8> LCD_B1+ 11 DISPOFF# DISP_OFF#
C301 1 2
4.7U_1206_16V6K <8> LCD_B1- 12
+12VALW
<8> LCD_B2+ 13
1
2 1K_0402_5%
+3VS <8> LCD_B2- 14
D
15
2
Q28
<8> LCD_BCLK+ 16
R317 SI2302DS_SOT23 RP18
<8> LCD_BCLK- PID0 17
<31> PID0 18
+LCDVDD 100K_0402_5% 8 1 PID0 PID1
<31> PID1 19
G
<8> LCD_A1+ 24
2
1 <8> LCD_A1- 25
100_0402_5% R312 200K_0402_5% 1000P_0402_50V7K 1 C303
2 <8> LCD_A2+ 26
C302
1 2
<8> LCD_A2- 27
10K_0402_5% 4.7U_1206_16V6K
28
G
Q30 D 2
0.1U_0402_16V7K
I
1
2 <8> LCD_ACLK+ 29
2 1 R314 2
2
4 <8> LCD_ACLK- 30 4
2N7002_SOT23 G 47K_0402_5%
1
S IPEX_20143-030E
3
Q31
DTC124EK_SC59
G
I
<8> ENVDD
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 16 of 49
A B C D E
A B C D
+RTCVCC +3VALW
2
+3VS +3VS +3VALW SMB_CLK 1 2
RP8 R378 +3VALW R398 4.7K_0402_5%
U25A
100K_0402_5%
1
PCI_FRAME# 1 10 SMB_DATA 1 2
PC I_TRDY# 2 9 PCI_LOCK# ICH4-M R397 4.7K_0402_5%
1
PCI_STOP# 3 8 PCI_DEVSEL# PCI_AD0 H5 W6 SM_INTRUDER# R154
PCI_SERR# PCI_PERR# PCI_AD1 AD0 INTRUDER# SMLINK0 4.7K_0402_5% 1
4 7 J3 AD1 SMLINK0 AC3 2 R149 100K_0402_5%
5 6 PCI_IR DY# PCI_AD2 H3 AB1 SMLINK1 4.7K_0402_5% 1 2 R145
2
PCI_AD3 AD2 SMLINK1 SMB_CLK +3VS
8.2K_1206_10P8R_5% PCI_AD4
K1
G5
AD3 SM I/F SMB_CLK
AC4
AB4 SMB_DATA
PCI_AD5 AD4 SMB_DATA ICH _ACIN
J4 AA5
1 PCI_AD6 AD5 SMB_ALERT#/GPI11 ACIN <32,34,38> 1
H4
+3VS +3VS PCI_AD7 AD6 Place R481 close SMCLK
J5 1 2
RP14 PCI_AD8 AD7 R517 4.7K_0402_5%
K2 to pinAA21
PCI_AD9 AD8 SMDATA 1
G2 Y22 GATEA20 <32> 2
PCI_REQ#3 PCI_AD10 AD9 A20GATE R518 4.7K_0402_5%
1 10 L1 AB23 H_A20M# <5> 1 2 +CPU_CORE
PCI_REQB# PCI_REQ#2 PCI_AD11 AD10 A20M# R481 56_0402_1%
2 9 G4
AD11 DPSLP#
U23 H_DPSLP# <5,8>
PCI_REQ#4 3 8 PCI_REQ#1 PCI_AD12 L2 AA21 H_FERR#
PCI_REQA# PCI_REQ#0 PCI_AD13 AD12 FERR# H_FERR# <5>
4 7 H2
AD13 IGNNE#
W21 H_IGNNE# <5>
5 6 SERIRQ PC I_AD[0..31] PCI_AD14 L3 V22 +3VS
<20,21,23,25> PCI_AD[0..31] AD14 INIT# H_INIT# <5>
PCI_AD15
8.2K_1206_10P8R_5% PCI_AD16
F5
F4
AD15 CPU I/F INTR
AB22
V21
H_INTR <5>
PCI_AD17 AD16 NMI H_NMI <5>
N1 AD17 CPU_PWRGOOD Y23 H_PWRGD <5>
PCI_AD18 E5 U22
AD18 RCIN# KBRST# <32>
2
+3VS
G
+3VS PCI_AD19 N2 U21
PCI_AD20 AD19 SLP# H_SLP# <5>
RP50 E3 W23
AD20 SMI# H_SMI# <5>
PCI_AD21 N3 V23 SMCLK 3 1 SMB_CLK
PIRQD# PCI_AD22 AD21 STPCLK# H_STPCLK# <5> <11,12,14> SMCLK
D
1 10 E4 AD22
PIRQC# 2 9 PIRQE# PCI_AD23 M5
PIRQB# PIRQF# PCI_AD24 AD23 Q40
3 8 E2 AD24
PIRQA# 4 7 PIRQH# PCI_AD25 P1 L19 H_PD0 2N7002_SOT23
PIRQG# PCI_AD26 AD25 HI0 H_PD1 H_PD[0..10]
5 6 E1 AD26 HI1 L20 H_PD[0..10] <7>
PCI_AD27 P2 M19 H_PD2
AD27 HI2
2
G
8.2K_1206_10P8R_5% PCI_AD28 D3 M21 H_PD3
+3VS PCI_AD29 AD28 HI3 H_PD4
R1 AD29 HI4 P19
PCI_AD30 D2 R19 H_PD5 SMDATA 3 1 SMB_DATA
AD30 HI5 <11,12,14> SMDATA
PCI I/F
PCI_AD31 H_PD6
D
P4 AD31 HI6 T20
R20 H_PD7
HI7 H_PD8 Q41
HI8 P23
R436 2 1 8.2K_0402_5% INT_IRQ14 C/BE#0 J2 L22 H_PD9 2N7002_SOT23
<20,21,23,25> PCI_C/BE#0 C/BE#0 HI9
C/BE#1 H_PD10
R461 2 1 8.2K_0402_5% INT_IRQ15 <20,21,23,25> PCI_C/BE#1 C/BE#2
K4
M4
C/BE#1 HUB I/F HI10 N22
K21 R480 1 2 56_0402_1%
<20,21,23,25> PCI_C/BE#2 C/BE#3 C/BE#2 HI11
<20,21,23,25> PCI_C/BE#3 N4 C/BE#3
2 R407 2 PCIRST# CLK_ICH_66M 2
1 @8.2K_0402_5% CLK66 T21 CLK_ICH_66M <14>
PCI_REQ#0 B1
<20> PCI_REQ#0 REQ#0
1
PCI_REQ#1 A2 P21 HUB_PSTRB
PCI_PAR <25> PCI_REQ#1 PCI_REQ#2 REQ#1 HI_STB HUB_PSTRB <7>
R372 2 1 @100_0402_5% <21> PCI_REQ#2 B3 REQ#2 HI_STB# N20 HUB_PSTRB# HUB_PSTRB# <7>
+1.5VS R478
PCI_REQ#3 C7 @22_0402_5%
<23> PCI_REQ#3 PCI_REQ#4 REQ#3 HUB_RCOMP_ICH
B6 R23 1 R218
2
REQ#4 HICOMP +ICH_HI_VREF 48.7_0603_1%
M23
2
PCI_GNT#0 HUB_VREF +ICH_HI_VSWING
Note:
<20> PCI_GNT#0 PCI_GNT#1
C1
E6
GNT#0 HUB_VSWING
R22
Place R218 within 0.5" of ICH4 ball R23,
1 Reserve
<25> PCI_GNT#1 GNT#1
In ICH4, PCI_GNT[0..4] don't need external pullup <21> PCI_GNT#2
PCI_GNT#2
PCI_GNT#3
A7
GNT#2 APICCLK
use thick trace C595
@10P_0402_25V8K H_PWRGD
for EMI.
<23> PCI_GNT#3 B7 J19
GNT#3 APICCLK APICD0 2 Near SB
D6 H19
GNT#4 APICD0 APICD1
K20
Interrupt I/F
APICD1
2
CLK_PCI_ICH P5 D5 PIRQA#
<14> CLK_PCI_ICH PCICLK PIRQA#
1
C2 PIRQB#
R406 FRAME# PIRQB# PIRQC#
<20,21,23,25> PCI_FRAME# F1 B4
@22_0402_5% DEVSEL# FRAME# PIRQC# PIRQD#
<20,21,23,25> PCI_DEVSEL# M3 A3
IR D Y# DEVSEL# PIRQD# PIRQE# @SM05_SOT23
<20,21,23,25> PCI_IRDY# L5 C8
IRDY# PIRQE#/GPI2 PIRQF# D48
G1 D7
2
1
C451 LOCK# PIRQH#/GPI5 IRQ14
<32> ICH_WAKE_UP# W2 AC13 INT_IRQ14 <26>
@10P_0402_25V8K PCIRST# PME# IRQ14 IRQ15
U5 AA19 INT_IRQ15 <26>
2 <8,15,20,21,22,23,25,26,31,32> PCIRST# SERR# PCIRST# IRQ15 SERIRQ
K5 J22 SERIRQ <21,31,32>
<21,23,25> PCI_SERR# STOP# SERR# SERIRQ
<20,21,23,25> PCI_STOP# F3
TR DY# STOP#
<20,21,23,25> PCI_TRDY# F2
TRDY#
D10
PCI_REQA# EE_CS
B5
REQA#/GPI0 EEPROM I/F EE_IN
D11 R185
PCI_REQB# A6 A8 1 2 APICCLK
GNTA# REQB#/GPI1/REQ5# EE_OUT APICD0
<26> PIDERST# E8 C12
GNTA#/GPO16 EE_SHCLK @1K_0402_5% APICD1
<26> SIDERST# C5
GNTB#/GPO17/GNT5#
2
3 3
A10
LAN_RXD0 R474 R473 R467
A9
LAN_RXD1 10K_0402_5% 10K_0402_5% 0_0402_5%
A11
LAN_RXD2
B10
LAN_TXD0
C10
1
LAN I/F LAN_TXD1
LAN_TXD2
A12
C11
LAN_CLK R408
B11
HUB I/F REF VOLTAGE LAN_RSTSYNC
LAN_RST#
Y5 1 2
+1.5VS 10K_0402_5%
Topology 1:
ICH4-M Pop : RP52 and R393
2
C216 C215
R217 0.01U_0402_25V7Z @0_1206_8P4R_5% Trace:PIRQA#
0.1U_0402_16V4Z 51.1_0603_1% 2
2 Use IRQA
CardBus
1
+ICH_HI_VREF
1 1
2
C218 Trace:PIRQF#_LAN
R219 C217 RP52 LAN Use IRQF
4 0.1U_0402_16V4Z 40.2_0603_1% 0.01U_0402_25V7Z PIRQH# PIRQD#/H# 4
1 8 PIRQH#_MINI_2 <25>
2 2 PIRQG# 2 7 PIRQC#/G# PIRQG#_MINI <25>
PIRQF# 3 6 PIRQB#/F#/D# PIRQF#_LAN <23> Trace:PIRQG#
1
+3VALW +3VS
1 2 EC_SWI# 1 2 AGP_BUSY#
1
R138 10K_0402_5% R142 10K_0402_5%
R143
2 1 V_GATE
1 2 SYSRST# R462 10K_0402_5% 10K_0402_5%
R139 10K_0402_5%
2
1 U25B 1
2
R172
1
100K_0402_5%
SYS_PWROK
<8> AGP_BUSY#
AGP_BUSY# R2
AGPBUSY#
ICH4-M GPI7
R3
SYSRST# Y3 V4
SYSRST# GPI8 EC_SMI# <32>
2 1 EC_RSMRST# PM_BATLOW# AB2 V5 SCI#
BATLOW# GPI12 EC_SCI# <32>
R179 100K_0402_5% T3 W3
CLKRUN# C3_STAT# GPI13 EC_LID_OUT# <32>
2 1 PM_DPRSLPVR <21,23,25,31,32> PM_CLKRUN# PM_DPRSLPVR
AC2
V20
CLKRUN# GPIO GPIO25
V2
W1
FLASH# <33>
<44> PM_DPRSLPVR DPRSLPVR GPIO27
R482 100K_0402_5% AA1 W4
<32> PBTN_OUT# SYS_PWROK PWRBTN# GPIO28
AB6
<8,35> SYS_PWROK EC_SWI# PWROK
Y1 RI#
<32> EC_SWI# EC_RSMRST#
+3VALW <32> EC_RSMRST#
AA6
W18
RSMRST# PM AA13 PDA0
<14,32> PM_SLP_S1# SLP_S1# PDA0 PDA1 IDE_PDA0 <26>
<14,32> PM_SLP_S3# Y4 SLP_S3# PDA1 AB13 IDE_PDA1 <26>
SLP_S4# Y2 W13 PDA2
SLP_S5# SLP_S4# PDA2 PDCS1# IDE_PDA2 <26>
AA2 SLP_S5# PDCS1# Y13 IDE_PDCS1# <26>
5
GPIO34 +VBIAS
routing next to G20
GPIO35 CLOCK VBIAS
Y6 1 2 +R_VBIAS 1 2
clock pin. F21
GPIO36 RTCX1 0.047U_0603_16V7K 1K_0603_5%
H20 AC7
GPIO37 RTCX1 R186
F23
GPIO38 RTCX2
H22
G23
GPIO39 GPIO RTCX2
AC6 1 2
GPIO40 10M_0603_5%
H21
GPIO41 SPKR X3 R421 R401
F22 H23 ICH_SPKR <30>
GPIO42 SPKR
E23 1 2 2 1
GPIO43
MISC THRMTRIP# W20
2
1 32.768KHZ 1 10M_0603_5% @22M_0603_5%
IAC_BITCLK CLK_ICH_14M CLK_ICH_48M 2 1 R418
+3VS
R220 @10K_0402_5% C485 C518 @2.4M_0603_1%
1
1
@22_0402_5% @22_0402_5% @22_0402_5% Place R502 near to
H_THERMTRIP#
Reserve U12 pinW20 R502
2
4 4
1 1 1 for EMI. 1 2 +CPU_CORE
C165 C220 C602 Near SB. 56_0402_5%
@10P_0402_25V8K @10P_0402_25V8K @10P_0402_25V8K THRMTRIP#
2 2 2 H_THERMTRIP# <5>
@SM05_SOT23
D49
Title
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 18 of 49
A B C D
A B C D E F G H
U25C +3VS
+3VALW
D22 VSS0
ICH4-M VCC3.3_0 A5 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
E10 VSS1 VCC3.3_1 AC17
E14 AC8 1 1 1 1 1 1 1 1 1 1 1
VSS2 VCC3.3_2 C199 C109 C565 C582 C508 C573 C507 C516 C537 C496 C482
E16 B2
VSS3 VCC3.3_3
E17 H18
1 VSS4 VCC3.3_4 1
E18 H6
VSS5 VCC3.3_5 2 2 2 2 2 2 2 2 2 2 2
E19 J1
VSS6 VCC3.3_6 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
E21 J18
VSS7 VCC3.3_7
E22 K6
VSS8 VCC3.3_8
F8 M10
VSS9 VCC3.3_9
G19 P12
VSS10 VCC3.3_10 +3VS
G21 P6
VSS11 VCC3.3_11
G3 U1
VSS12 VCC3.3_12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
G6 V10
VSS13 VCC3.3_13
H1 V16
VSS14 VCC3.3_14
J6 V18 1 1 1 1 1 1 1 1 1 1
VSS15 VCC3.3_15 +3VALW C122 C497 C571 C474 C434 C433 C460 C510 C575 C522
K11 VSS16
K13 VSS17
K19 VSS18 VCCSUS3.3_0 E11
2 2 2 2 2 2 2 2 2 2
K23 VSS19 VCCSUS3.3_1 F10
K3 F15 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS20 VCCSUS3.3_2
L10 VSS21 VCCSUS3.3_3 F16
L11 VSS22 VCCSUS3.3_4 F17
L12 F18 +1.5VALW
VSS23 VCCSUS3.3_5
L13 VSS24 VCCSUS3.3_6 K14
L14 V7 10U_1206_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS25 VCCSUS3.3_7
L21 VSS26 VCCSUS3.3_8 V8
M1 VSS27 VCCSUS3.3_9 V9 1 1 1 1 1 1 1 1
M11 C207 C202 C523 C481 C583 C536 C471 C594
VSS28 +1.5VS
M12 VSS29
M13 GND POWER 0.1U_0402_16V4Z
VSS30 2 2 2 2 2 2 2 2
M20 VSS31 VCC1.5_0 K10
M22 K12 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS32 VCC1.5_1
N10 VSS33 VCC1.5_2 K18
N11 VSS34 VCC1.5_3 K22
N12 VSS35 VCC1.5_4 P10
N13 T18 +1.5VS
2 VSS36 VCC1.5_5 2
N14 VSS37 VCC1.5_6 U19
N19 V14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_1206_16V4Z_V1
VSS38 VCC1.5_7 +1.5VALW
N21 VSS39
N23 VSS40 1 1 1 1 1 1 1 1
N5 E12 C623 C605 C509 C524 C606 C210 C553 C589
VSS41 VCCSUS1.5_0
P11 VSS42 VCCSUS1.5_1 E13
P13 E20 0.1U_0402_16V4Z
VSS43 VCCSUS1.5_2 2 2 2 2 2 2 2 2
P20 F14
VSS44 VCCSUS1.5_3 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
P22 G18
VSS45 VCCSUS1.5_4
P3 R6
VSS46 VCCSUS1.5_5
R18 T6
VSS47 VCCSUS1.5_6 +1.5V_LAN +3V_LAN +1.5VS_PLL
R21 U6
VSS48 VCCSUS1.5_7
R5
VSS49
T1
VSS50 +VCC5REF
T19 E7
VSS51 VCC5REF1
T23 V6 1 2 1 2 1 2
VSS52 VCC5REF2 C473 C492 C504 C493 C604 C613
U20
VSS53 +VCC5REFSUS
V15 E15
VSS54 VCC5REFSUS1 +1.5VS 0.1U_0402_16V4Z 0.01U_0402_25V4Z 0.1U_0402_16V4Z 0.01U_0402_25V4Z 0.1U_0402_16V4Z 0.01U_0402_25V4Z
V17
VSS55 2 1 2 1 2 1
V3
VSS56
W22 L23
VSS57 VCCHI_0
W5 M14
VSS58 VCCHI_1
W8 P18
VSS59 VCCHI_2
Y19 T22
VSS60 VCCHI_3
Y7
VSS61 +CPU_CORE
A16
VSS62
A18 AA23
VSS63 VCC_CPU_IO_0 +RTCVCC +CPU_CORE
A20 P14
VSS64 VCC_CPU_IO_1
A22 U18
VSS65 VCC_CPU_IO_2
A4
VSS66 +1.5VS_PLL +1.5VS
AA12
VSS67 R225 1
AA16 C22 2 0_0805_5% 1 1 1 1
3 VSS68 VCCPLL C462 C549 C611 C567 3
AA22
VSS69
AA3
VSS70 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V6K
AA9 AB5 +RTCVCC
VSS71 VCCRTC 2 2 2 2
AB20
VSS72
AB7
VSS73 +3V_LAN +3V
AC1
VSS74 R423 1
AC10 E9 2 0_0805_5%
VSS75 VCCLAN3.3_0
AC14 F9
VSS76 VCCLAN3.3_1
AC18
VSS77 +1.5V_LAN +1.5V
AC23
VSS78 R420 1
AC5
VSS79 VCCLAN1.5_0
F6 2 0_0805_5%
B12 F7
VSS80 VCCLAN1.5_1
B16
VSS81
B18
VSS82
B20
VSS83 +3VS +5VS +3VALW +5VALW
B22
VSS84
B9
VSS85
C15
VSS86
1
C17
VSS87 R424 R431
C19
VSS88 D36 1K_0603_5% D37 1K_0603_5%
C21
VSS89 1SS355 1SS355
C23
VSS90
C6
2
VSS91 +VCC5REF +VCC5REFSUS
D1
VSS92
D12
VSS93
D15 1 1 1 1
VSS94 C494 C495 C569 C568
D17
VSS95
D19
VSS96 0.1U_0402_16V4Z 1U_0603_10V6K 0.1U_0402_16V4Z 1U_0603_10V6K
D21
VSS97 2 2 2 2
D23
VSS98
D4
VSS99
D8 VSS100
4 4
A1 VSS101
ICH4-M
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 19 of 49
A B C D E F G H
5 4 3 2 1
+3VS
1 1 1 1 1 1 1 1 1
PC I_AD[0..31] +3VS C191 C190 C189 C208 C214 C223 C188 C209 C204
<17,21,23,25> PCI_AD[0..31]
0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2
110
122
111
100
108
118
126
112
2
46
36
99
17
32
21
30
31
47
91
13
23
33
22
38
5
6
U29 L41 +3VS
U28
PVD
PVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCI_AD0 25 FCM2012C-800_0805 1 8
PCI_AD1 AD0 +3V_1394 A0 VCC
24 2 7 1 2
PCI_AD2 AD1 A1 WP
20 3 6 EECK_1394 R446
1
PCI_AD3 AD2 A2 SCL
19 4 5 EEDI_1394 560_0402_5%
PCI_AD4 AD3 0.1U_0402_16V4Z GND SDA
18 59
PCI_AD5 AD4 PVA AT24C02N-10SI-2.7_SO8
16 62 2 2 2 2
AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
15
14
11
AD6
AD7
AD8
Power PVA
PVA
PVA
PVA
72
73
86
1
C633
1
C626
1
C635
1
C634
0.1U_0402_16V4Z
10 AD9 PVA 87
PCI_AD10 9 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS
PCI_AD11 AD10
8 AD11
PCI_AD12 7 AD12
2
PCI_AD13 4 61
PCI_AD14 AD13 GND R224
3 AD14 GND 65
PCI_AD15 2 66
PCI_AD16 AD15 GND 1K_0402_5%
117 AD16 GND 79
PCI_AD17 116 80
1
PCI_AD18 AD17 GND XREXT XCPS
115 AD18 GND 56
PCI_AD19 114 AD19
2
PCI_AD20 113
PCI_AD21 AD20 R222
109 AD21
PCI_AD22 107 AD22
IEEE 1394 EECS 26
1
PCI_AD23 1K_0402_5%
PCI_AD24
106
103
AD23 EEPROM EEDO 27
28 EEDI_1394 R505
2
1
AD24 EEDI/SDA
PCI_AD25
PCI_AD26
102 AD25 I/F EECK/SCL 29 EECK_1394
6.34K_0402_1%
C630
101 47P_0402_50V8J
PCI Bus
AD26 1
PCI_AD27 98
VT6301S
2
C PCI_AD28 97
AD27
AD28
PM & Test C
PCI_AD29 96 34
PCI_AD30 AD29 PME# 1394_PME# <32>
95 AD30
PCI_AD31 94 60 XCPS
AD31 XCPS
12 63 XREXT
<17,21,23,25> PCI_C/BE#0 CBE0# XREXT
Differential Pairs
1 JP23
<17,21,23,25> PCI_C/BE#1 CBE1#
119 67 XTPB0- 1
<17,21,23,25> PCI_C/BE#2 CBE2# TPB0M XTPB0+ 1
<17,21,23,25> PCI_C/BE#3 104 68 2
CBE3# TPB0P XTPA0- 2
69 3
PCI_AD16 TPA0M XTPA0+ 3
1 2 R216 105
IDSEL TPA0P
70 4
4
100_0402_1%120 71 XTPBIAS0 SANTA_360302
<17,21,23,25> PCI_FRAME# FRAME# TPBIAS0
<17,21,23,25> PCI_IRDY# 121
IRDY#
1
<17,21,23,25> PCI_TRDY# 123
TRDY# R230 R231
124
<17,21,23,25> PCI_DEVSEL# DEVSEL#
<17,21,23,25> PCI_STOP# 125
STOP# 54.9_0402_1% 54.9_0402_1%
<17,21,23,25> PCI_PERR# 127
PERR#
128
2
<17,21,23,25> PCI_PAR PAR
1
<17> PCI_REQ#0 93
REQ# R228 R229
92
<17> PCI_GNT#0
<17> PIRQE#_1394 88
89
GNT#
INTA# NC 55 54.9_0402_1% 54.9_0402_1%
,17,21,22,23,25,26,31,32> PCIRST# CLK_PCI_1394 90
PCIRST#
OSC PHYRESET#
2
CARDEN
2
<14> CLK_PCI_1394 PCICLK
1
I2CEN
C624 1
1
1394
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R232
XO
0.1U_0402_16V4Z 1
XI
43
44
57
58
2 270P_0402_25V8K
2
2
1
2
XO
C226 XI
B @22P_0402_50V8J B
2 Note:These components need to close to chip pins.
R210
+3VS 2 1
4.7K_0402_5% X4
XI 1 2 XO
24.576MHz_16P_3XG-24576-43E1
1 2
2 2
R227
C221 1M_0402_5% C225
10P_0402_25V8K 10P_0402_25V8K
1 1
A A
D +3V D
+3V
<22> VPPD0
<22> VPPD1 1 2
<22> VCCD0#
C359
<22> VCCD1#
0.1U_0402_16V4Z
126
138
122
102
74
73
72
71
44
18
90
86
50
30
14
63
U11
VCCI
VCCD1#
VCCD0#
VPPD1
VPPD0
VCCP0
VCCP1
VCCSK0
VCCSK1
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
PC I_AD[0..31]
<17,20,23,25> PCI_AD[0..31]
36 101 S1_A13
<17,20,23,25> PCI_PAR PAR CPAR/A13
1 123 S1_INPACK#
10K_0402_5% <17> PCI_REQ#2 REQ# CREQ#/INPACK# S1_WE# S1_INPACK# <22>
<17> PCI_GNT#2 2 106 S1_WE# <22>
R438 CLK_PCI_PCM GNT# CGNT#/WE# A16_CLK 1 S1_A16
<14> CLK_PCI_CB 21 108 2
PCLK CCLK/A16 R81 33_0402_5%
2
59 135 S1_BVD1
<32> PCM_PME# RI_OUT#/PME# CSTSCHG/BVD1 S1_BVD1 <22>
1 2 70 136 S1_WP
<28,32,33,37,43> SUSP# SUSPEND# CCLKRUN#/WP S1_WP <22>
PCI_AD20 1 2 PCM_ID 13 103 S1_A19
D19 R327 100_0402_1% IDSEL CBLOCK#/A19
RB751V_SOD323 60 132 S1_RDY#
<17> PIRQA#_PCM MFUNC0 CINT#/READY S1_RDY# <22>
61
MFUNC1 PCM_SPK#
64 62 PCM_SPK# <30>
MFUNC2 SPKOUT S1_BVD2
<17,31,32> SERIRQ 65 134 S1_BVD2 <22>
MFUNC3 CAUDIO/BVD2
67
MFUNC4
68 137 S1_CD2# <22>
MFUNC5 CCD2#/CD2#
RSVD/D14
RSVD/A18
PM_CLKRUN# 69 75
RSVD/D2
66 131 S1_VS1
<22,25> CBRST# VCC/GRST# CVS1/VS1# S1_VS1 <22>
1
R328 1 2
@33_0402_5% CB1410_LQFP144 C348 0.1U_0402_16V4Z
6
22
42
58
78
94
114
130
84
100
143
1 2
C84 0.1U_0402_16V4Z
2
A S1_D2 A
1
S1_A18
C353 S1_D14
@10P_0402_50V8K
2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 21 of 49
5 4 3 2 1
PCMCIA Power Controller
+12VALW +S1_VCC
1
+S1_VPP
U12 1
C78
1U_0805_25V4Z 13 C67
2 AVCC1 0.1U_0402_16V4Z
12 1 1
AVCC2 2
9 11
12V AVCC3 +S1_VPP C145 C146
0.01U_0402_25V4Z 4.7U_1206_16V4Z
+5VALW 2 2
1
10
AVPP C79
1
5 1U_0805_25V4Z
C66 5V_1 2
6 5V_2
0.1U_0402_16V4Z
2 1 +S1_VCC
VCCD0# VCCD0# <21>
VCCD1# 2 VCCD1# <21>
+3VALW 15
VPPD0 VPPD0 <21>
VPPD1 14 VPPD1 <21> 1 1
S1_A[0..25]
<21> S1_A[0..25]
3 C147 C150
3.3V_1 0.1U_0402_16V4Z 10U_1206_16V4Z
4 8
1 3.3V_2 SHDN# OC# 2 2 S1_D[0..15]
GND
16
CardBus Socket
CBRST#
JP18
1 1 2 2
S1_D3 3 4 S1_CD1#
S1_D4 3 4 S1_D11 S1_CD1# <21>
5 5 6 6
S1_D5 7 8 S1_D12
S1_D6 7 8 S1_D13
9 9 10 10
+3VALW +5VALW S1_D7 11 12 S1_D14
S1_CE1# 11 12 S1_D15
13 13 14 14
<21> S1_CE1# S1_A10 S1_CE2#
1 1 15 15 16 16
S1_OE# S1_VS1 S1_CE2# <21>
17 17 18 18
C61 C75 <21> S1_OE# S1_A11 S1_IORD# S1_VS1 <21>
19 20
10U_1206_16V4Z 10U_1206_16V4Z S1_A9 19 20 S1_IOWR# S1_IORD# <21>
21 22
2 2 S1_A8 21 22 S1_A17 S1_IOWR# <21>
23 24
S1_A13 23 24 S1_A18
25 26
S1_A14 25 26 S1_A19
27 28
S1_WE# 27 28 S1_A20
<21> S1_WE# 29 30
S1_RDY# 29 30 S1_A21
<21> S1_RDY# 31 32
31 32
+S1_VCC 33 34 +S1_VCC
33 34
+S1_VPP 35 36 +S1_VPP
S1_A16 35 36 S1_A22
37 38
S1_A15 37 38 S1_A23
39 40
S1_A12 39 40 S1_A24
41 42
S1_A7 41 42 S1_A25
43 44
S1_A6 43 44 S1_VS2
45 46
S1_A5 45 46 S1_RST S1_VS2 <21>
47 48
S1_A4 47 48 S1_WAIT# S1_RST <21>
49 50
S1_A3 49 50 S1_INPACK# S1_WAIT# <21>
51 52
S1_A2 51 52 S1_REG# S1_INPACK# <21>
53 54
S1_A1 53 54 S1_BVD2 S1_REG# <21>
55 56
S1_A0 55 56 S1_BVD1 S1_BVD2 <21>
57 58
S1_D0 57 58 S1_D8 S1_BVD1 <21>
PCMRST# <32> 59 60
S1_D1 59 60 S1_D9
61 62
S1_D2 61 62 S1_D10
63 64
S1_WP 63 64 S1_CD2#
65 66
+3V <21> S1_WP 65 66 S1_CD2# <21>
67 68
67 68
69 70
+3V GND GND
71 72
GND GND
1
73 74
R116 GND GND
75 76
10K_0402_5% GND GND
14
77 78
GND GND
1
S1_A23 1 2 79 80
R150 +S1_VCC GND GND
81 82
OE#
P
R113 +S1_VCC
U16A 22K_0402_5%
7
S1_CE1# 1 2
R197 +S1_VCC
43K_0402_5%
S1_CE2# 1 2
R195 +S1_VCC
43K_0402_5%
S1_RST 1 2
R135 +S1_VCC
43K_0402_5%
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 22 of 49
5 4 3 2 1
R382
+2.5V_LAN_1 TRACE=20mil 2 1 +2.5V_LAN
2
2 0_0805_5%
D C123 D
0.1U_0402_16V4Z C437
U18 1 0.1U_0402_16V4Z
PCI_AD0 1
47 AD0 VDD25 48
PCI_AD1 46 94 RTL8101L has internal
PCI_AD2 AD1 VDD25 +2.5V generator at pin58
45 AD2
PCI_AD[0..31] PCI_AD3 43 58 +2.5V_LAN TRACE=20mil
<17,20,21,25> PCI_AD[0..31] AD3 AVDD25 +2.5V_LAN
Power
PCI_AD4 42
PCI_AD5 AD4 +3V_LAN_VDD1 TRACE=20mil
41 AD5 AVDD 59 1 2 +3V
PCI_AD6 40 LQG21N4R7K10_0805 L30
PCI_AD7 AD6 +3V_LAN_VDD2 TRACE=20mil
39 AD7 AVDD 70 TRACE=30mil
PCI_AD8 36
PCI_AD9 AD8 +3V_LAN_VDD3 TRACE=20mil
35 AD9 AVDD 75
PC I_AD10 34
PC I_AD11 AD10 R178 5.6K_0402_5% Place closed to +3V
33 AD11 1 2
PC I_AD12 32 1 2 C161 22U_1206_16V4Z_V1 RTL8101L pin58
AD12 +3V
PC I_AD13 30 U27 1 2
PC I_AD14 AD13 LAN_EEDO C441 0.1U_0402_16V4Z
29 AD14 EEDO 52 4 DO GND 5
PC I_AD15 28 53 LA N_EEDI 3 DI +3V
PC I_AD16 AD15 EEDI LAN_EECLK NC 6
15 AD16 EESK 54 2 SK NC 7 1 2 1 1 1
PC I_AD17 14 55 LAN_EECS 1 CS C452 0.1U_0402_16V4Z
PC I_AD18 AD17 EECS VCC 8 C410 C446 C127
13 AD18 1 1 2
PC I_AD19 12 78 AT93C46-10SI-2.7_SO8 C454 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PC I_AD20 AD19 LED0 C171 2 2 2
11 AD20 LED1 77 1 2
PC I_AD21 10 76 ACTIVITY# ACTIVITY# <24> 0.1U_0402_16V4Z C453 0.1U_0402_16V4Z
PC I_AD22 AD21 LED2 LINK10_100# 2
9 AD22 LINK10_100# <24>
PC I_AD23 8 72
LAN I/F
PCI I/F
PC I_AD24 AD23 TXD+ LAN_TD+
96 AD24 TXD- 71 LAN_TD+ <24>
PC I_AD25 93 LAN_TD- +3V
AD25 LAN_TD- <24>
C PC I_AD26 92 68 LAN_RD+ C
AD26 RXIN+ LAN_RD+ <24>
PC I_AD27 91 67 LA N_RD-
AD27 RXIN- LAN_RD- <24>
PC I_AD28 89
PC I_AD29 AD28 LAN_X1
87 AD29 X1 61 1 1 1
PC I_AD30 86
PC I_AD31 AD30 C382 C114 C383
85 AD31
60 LAN_X2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_C/BE#0 X2 2 2 2
<17,20,21,25> PCI_C/BE#0 38 C/BE#0 1 2 +3VS
1
PCI_C/BE#1 27 64 R189 1K_0402_5%
<17,20,21,25> PCI_C/BE#1 C/BE#1 LWAKE
PCI_C/BE#2 17
<17,20,21,25> PCI_C/BE#2 C/BE#2
PCI_C/BE#3 84 74 1 2 R193 R192
<17,20,21,25> PCI_C/BE#3 C/BE#3 ISOLATE# R190 15K_0402_5% 49.9_0603_1% 49.9_0603_1%
PC I_AD17 1 2 L AN_IDSEL 98 65 1 2
2
R130 100_0402_5% IDSEL RTSET R374
24 63 5.6K_0603_1% 1
<17,20,21,25> PCI_PAR PAR RTT3
<17,20,21,25> PCI_FRAME# 18 FRAME#
19 56 C169
<17,20,21,25> P C I_ IRDY# IRDY# VCTRL 0.1U_0402_16V4Z
<17,20,21,25> PCI_TRDY# 20 TRDY# 2
21 1
AC-Link
C LK_PCI_LAN
37
49
90
VDD
VDD
Power DGND5
AGND1
88
62
66
1
C174
1
C173
VDD AGND2 27P_0402_50V8J 27P_0402_50V8J
95 VDD AGND3 73
1
2 2
RTL8101L_LQFP100
R133
@10_0402_5%
2
1
C99
@10P_0402_50V8K
2
A A
Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 23 of 49
5 4 3 2 1
5 4 3 2 1
1
H0013
R308 R307 RJ45_TX- 2
49.9_0603_1% R287 R288 PR1-
49.9_0603_1% SHLD2 14
75_0402_5% 75_0402_5% RJ45_TX+ 1 PR1+
1 13
2
2
SHLD1
10 Green LED-
C316
1 0.1U_0402_16V4Z RJ45_GND +Green_LED T=10mil 9
2 Green LED+
C312 SANTA_130401-1
0.1U_0402_16V4Z
2
2
R283 R284
75_0402_5% 75_0402_5%
1
C C
3
I
1 1
DTA114YKA_SC59 C15 C16
Q26 @0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2
O
1
R285
1 2 +Amber_LED
B B
300_0402_5% Termination plane should be copled
to chassis ground and also depends
on safety concern
+3V
3
I
DTA114YKA_SC59
Q25
O
1
R281
1 2 +Green_LED
300_0402_5%
A A
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 24 of 49
5 4 3 2 1
+3V
C104
1 2
0.1U_0402_16V4Z
PC I_AD[0..31]
PCI_AD[0..31] <17,20,21,23>
5
U22
1 MINI_PCI SOCKET
P
<32> WL_OFF# B
Y 4
<32,34> KILL_SW# 2 A
G
TC7SH08FU_SSOP5 JP19
3
TIP 1 2 RING
1 2
KEY KEY PCIRST#
3 3 4 4 1 2 PCIRST# <8,15,17,20,21,22,23,26,31,32>
LAN RESERVED 5 6 R127 0_0402_5%
5 6 MINI_RST#
7 7 8 8 1 2 CBRST# <21,22>
RB751V_SOD323 9 10 LAN RESERVED R126 @0_0402_5%
D15 9 10
11 11 12 12
+3VS_MINIPCI INTB# 1 2 13 13 14 14
15 15 16 16
L11 PIRQH#_MINI W=30mils +3VS_MINIPCI
<17> PIRQH#_MINI_2 17 17 18 18 +5VS_MINIPCI
1 2 W=40mils 19 20 PIRQG#_MINI_2 INTA#
+3V 19 20 PIRQG#_MINI <17>
21 21 22 22
CHB1608B121_0603 23 24 W=40mils
23 24 MINI_RST# +3V
25 26 L12
<14> CLK_PCI_MINI 25 26 W=40mils
27 27 28 28 1 2
CHB1608B121_0603 +3V
<17> PCI_REQ#1 29 29 30 30 PCI_GNT#1 <17>
2 2 31 31 32 32
C105 C108 PCI_AD31 33 34 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z PCI_AD29 33 34 WLANPME# <32> C93 C144 +3VS_MINIPCI
35 35 36 36
37 38 PCI_AD30 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+5VS_MINIPCI 1 1 PCI_AD27 37 38
39 39 40 40
PCI_AD25 41 42 PCI_AD28 1 1
41 42 1 1
43 44 PCI_AD26
43 44 PCI_AD24 C138 C143
<17,20,21,23> PCI_C/BE#3 45 46
PCI_AD23 45 46 MINI_IDSEL1 0.1U_0402_16V4Z 10U_0805_10V4Z
47 48 2 PCI_AD18
47 48 R174 100_0402_5% 2 2
49 50
PCI_AD21 49 50 PCI_AD22
51 52
PCI_AD19 51 52 PCI_AD20
1 1 1 1 53 54
C85 C187 C182 53 54
55 56 PCI_PAR <17,20,21,23>
C200 PCI_AD17 55 56 PCI_AD18
57 58
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 57 58 PCI_AD16
<17,20,21,23> PCI_C/BE#2 59 60
2 2 2 2 59 60
61 62
<17,20,21,23> PCI_IRDY# 61 62
63 64 PCI_FRAME# <17,20,21,23>
63 64
65 66 PCI_TRDY# <17,20,21,23>
1000P_0402_25V8K <18,21,23,31,32> PM_CLKRUN# 65 66
67 68 PCI_STOP# <17,20,21,23>
<17,21,23> PCI_SERR# 67 68
69 70
69 70
<17,20,21,23> PCI_PERR# 71 72 PCI_DEVSEL# <17,20,21,23>
71 72
73 74
<17,20,21,23> PCI_C/BE#1 PCI_AD14 73 74 PCI_AD15
75 76
75 76 PCI_AD13
77 78
PCI_AD12 77 78 PCI_AD11
79 80
PCI_AD10 79 80
81 82
81 82 PCI_AD9
83 84
PCI_AD8 83 84
85 86
CLK_PCI_MINI PCI_AD7 85 86 PCI_C/BE#0 <17,20,21,23>
87 88
87 88 PCI_AD6
89 90
89 90
1
PCI_AD5 91 92 PCI_AD4
R144 91 92 PCI_AD2
93 94
33_0402_5% PCI_AD3 93 94 PCI_AD0
95 96
W=30mils 95 96
+5VS_MINIPCI 97 98
PCI_AD1 97 98
99 100
2
99 100
101 102
101 102
1 103 104
C130 103 104
105 106
10P_0402_50V8K 105 106
107 108
107 108
109 110
2 109 110
111 112
111 112
113 114
113 114
115 116
115 116
117 118
117 118
119 120
119 120
121 122
W=30mils 121 122 W=20mils
+5VS 1 2 123 124 +3V
L18 0_0603_5% 123 124
2
KEYLINK_5305-4-211 C177
0603 0.1U_0402_16V4Z
+5VS_MINIPCI 1
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 25 of 49
IDE Module CONN. C254 +5VS
@0.1U_0402_16V4Z
+3VS 2 1
ID E_PDD[0..15]
<18> IDE_PDD[0..15]
5
U37
1 2 IDE_PD IORDY PCIRST# 1
P
<8,15,17,20,21,22,23,25,31,32> PCIRST# B
JP10 R262 4.7K_0402_5% 4 PIDE_RST#
PIDE_RST# Y
1 2 <17> PIDERST# 2 A
G
IDE_PDD7 IDE_PDD8
IDE_PDD6 3 4 IDE_PDD9 @TC7SH08FU_SSOP5
3
IDE_PDD5 5 6 IDE_PDD10 IDE_PDD7
7 8 1 2
IDE_PDD4 IDE_PDD11 R264 @10K_0402_1%
IDE_PDD3 9 10 IDE_PDD12
IDE_PDD2 11 12 IDE_PDD13 IDE_PDDREQ
13 14 1 2
IDE_PDD1 IDE_PDD14 R263 @5.6K_0402_5%
IDE_PDD0 15 16 IDE_PDD15 1 2
17 18 R541 0_0402_5%
IDE_PDDREQ 19 20
<18> IDE_PDDREQ 21 22
<18> IDE_PDIOW# 23 24
<18> IDE_PDIOR# IDE_PD IORDY 25 26 PCSEL
27 28 1 2
<18> IDE_PDIORDY R265 470_0402_5%
<18> IDE_PDDACK# INT_IRQ14 29 30
<17> INT_IRQ14 31 32
1 2 +5VS
<18> IDE_PDA1 33 34 R256 0_0402_5%
<18> IDE_PDA0 35 36 IDE_PDA2 <18>
<18> IDE_PDCS1# 37 38 IDE_PDCS3# <18>
<32> PHDD_LED# 39 40
+5VS 41 42 +5VS 1 1 1 1
1 2 43 44
+5VS R254 100K_0402_5% C257 C255 C256 C258
1000P_0402_25V8K 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z
SUYIN_200138FR044G242ZL 2 2 2 2
JP25
<28> INT_CD_L 1 2 INT_CD_R <28>
5
1 1 2 IDE_SDD7 U36
<28> CD_AGND SIDE_RST# 3 4 IDE_SDD8 PCIRST# 1
R247 @10K_0402_1%
P
C248 IDE_SDD7 5 6 IDE_SDD9 B SIDE_RST#
4
@12P_0402_50V8J IDE_SDD6 7 8 IDE_SDD10 IDE_SDDREQ Y
9 10 1 2 <17> SIDERST# 2
A
G
2 IDE_SDD5 IDE_SDD11 R242 @5.6K_0402_5%
IDE_SDD4 11 12 IDE_SDD12 @TC7SH08FU_SSOP5
3
IDE_SDD3 13 14 IDE_SDD13
IDE_SDD2 15 16 IDE_SDD14
IDE_SDD1 17 18 IDE_SDD15
IDE_SDD0 19 20 IDE_SDDREQ
21 22 IDE_SDDREQ <18>
23 24 IDE_SDIOR# <18>
<18> IDE_SDIOW# 1 2
IDE_SD IORDY 25 26 R542 0_0402_5%
<18> IDE_SDIORDY 27 28 IDE_SDDACK# <18>
<17> INT_IRQ15 29 30
<18> IDE_SDA1 1 2 +5VS
31 32 R240 100K_0402_5%
<18> IDE_SDA0 33 34 IDE_SDA2 <18>
<18> IDE_SDCS1# 35 36 IDE_SDCS3# <18> +5VS
<32> SHDD_LED# 37 38 +5VS
39 40
+5VS 41 42
+5VS 1 2 SHDD_LED#
R248 100K_0402_5% 43 44
45 46 W=80mils
47 48 2
49 50 1 1 1 1
1
C234
SUYIN_800189MB050S105ZL 0.1U_0402_16V4Z C238 C247 C236 C237
R243 1 1000P_0402_25V8K 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z
470_0402_5% 2 2 2 2
2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 26 of 49
+USB_VCCA
+USB_VCCB +3V
1
1
C273 +
150U_D2_6.3VM C275
470P_0603_50V8J
1
+USB_VCCA 2 2
R33 USB
100K_0402_5% 100K_0402_5% USB_CGND
+5V R32 CONNECTOR
2
U3
1 8 1 2 JP13
GND OC1# OVCUR#2 <18>
2 7 R31 47_0402_5% 1 2
IN OUT1 <18> USBP2- USB2- 1
3 6 R273 0_0402_5%
EN1# OUT2 USB2+ 2
1 4 5 1 2 OVCUR#4 <18> <18> USBP2+ 1 2
C17 EN2# OC2# R22 47_0402_5% R274 0_0402_5% 3
0.1U_0402_16V4Z 4
1 TPS2042ADR_SO8 Keep 20 mils minimum spacing 5
2 1 1 6
C283 C19 C14 1 2 USB4-
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z <18> USBP4- 7
R268 0_0402_5%
2 USB4+ 8
<18> USBP4+ 1 2
2 2 R269 0_0402_5% TYCO_1470713-1
+USB_VCCB
1
1
C284 +
150U_D2_6.3VM C274
470P_0603_50V8J
2 2
USB_BGND
+USB_VCCC +3V
+USB_VCCC
1
1
1
R261 R260 C646 +
100K_0402_5% 100K_0402_5% 150U_D2_6.3VM C647
+5V 470P_0603_50V8J
2 2
2
U32 USB
1 8 1 2 USB_AGND
2
GND OC1#
7 R259 47_0402_5%
OVCUR#3 <18> CONNECTOR
IN OUT1
1 3 6
C231 EN1# OUT2 JP26
4 5
0.1U_0402_16V4Z EN2# OC2#
1 <18> USBP3- 1 2 1
1
1 TPS2042ADR_SO8 C250 R255 0_0402_5% USB3- 2
2 0.1U_0402_16V4Z USB3+ 2
<18> USBP3+ 1 2 3
3
C645 R253 0_0402_5% 4
10U_0805_10V4Z 2 4
2 TYCO_1470712-1
1 1 1 1 1 1
C271 C272 C269 C270 C251 C241
@10P_0402_50V8K @10P_0402_50V8K @10P_0402_50V8K @10P_0402_50V8K @10P_0402_50V8K @10P_0402_50V8K
2 2 2 2 2 2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 27 of 49
5 4 3 2 1
1
R342 0_0402_5% 2 6
LINEIN_R L9 DELAY SENSE or ADJ
1 2 C140 C128
<30> LINE_IN_R 4.7U_0805_10V4Z
R336 0_0402_5% 1 2 7 1 R151 1
+VDDA 2 2 ERROR CNOISE
CHB2012U170_0805 69.8K_0603_1%
1 1 1 1 8 3 1 C133
2
SD GND
1
0.1U_0402_16V4Z 4.7U_0805_10V4Z
1
R344 C111 C102 C152 C448 SI9182DH-AD_MSOP8 C100 2
1
@68K_0402_5% 0.1U_0402_16V4Z 10U_0805_10V4Z 10U_0805_10V4Z SUSP# 0.1U_0402_16V4Z
2 2 2 2 <21,32,33,37,43> SUSP# 2
D R340 R137 D
2
@68K_0402_5% 24K_0402_1%
25
38
2
9
U45
2
AVDD1
AVDD2
DVDD1
DVDD2
14 35 LINEL 1 2 LINE_OUT_L LINEL 1 2
AUX_L LINE_OUT_L LINE_OUT_L <29,30>
C131 4.7U_0805_10V4Z C120 1000P_0402_25V8K
INT_CD_L 2 1 CD_L 15 36 LINER 1 2 LINE_OUT_R LINER 1 2
<26> INT_CD_L AUX_R LINE_OUT_R LINE_OUT_R <29,30>
R380 20K_0402_5% C132 4.7U_0805_10V4Z C121 1000P_0402_25V8K
INT_CD_R 2 1 C D_R 16 37 1 2 MD_MIC
<26> INT_CD_R VIDEO_L MONO_OUT
R351 20K_0402_5% C129 1U_0402_6.3V4Z
17 VIDEO_R TRUE_LOUT_L 39
1
1
LINEIN_L 2 1 23 41
R379 R349 C399 1U_0402_6.3V4Z LINE_IN_L TRUE_LOUT_R
20K_0402_5% 20K_0402_5% LINEIN_R 2 1 24 R402 22_0402_5%
C386 1U_0402_6.3V4Z LINE_IN_R IAC_BITCLK IAC_BITCLK
BIT_CLK 6 1 2 IAC_BITCLK <18> 1 2
CD_L 2 1 18 C466 @22P_0402_50V8J
2
2
CD_GNA 2 1 19
C422 1U_0402_6.3V4Z CD_GND R404
MIC 2 1 C_MIC 21 @1M_0402_5% X5
R411 <30> MIC MIC1 XTL_IN XTL_OUT
C404 1U_0402_6.3V4Z 2 1
MD_SPK 1 2 C_MD_SPK 2 1 22 3 XTL_OUT 1 1
1
C125 0.1U_0402_16V4Z MIC2 XTL_OUT
10K_0402_5% C_MD_SPK 2 1 13 29 1 2 C489 24.576MHz_16P_3XG-24576-43E1 C490
C445 1U_0402_6.3V4Z PHONE AFILT1 C118 1000P_0402_25V8K 22P_0402_50V8J 22P_0402_50V8J
1
12 30 1 2 2 2
1 1 <30> MONO_IN PC_BEEP AFILT2
C R413 C119 1000P_0402_25V8K C
C467 C458 2.4K_0402_5% 28
IAC_RST# 1 VREFOUT +AUD_VREF
<18> IAC_RST# 2 11 RESET#
0.1U_0402_16V4Z 2 2 R410 100_0402_5% 27 +AUD_VREF
2
1
CD_GNA 2 2 2 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 1 GPIO1
44 1 2
<26> CD_AGND 48 R161@0_0402_5% C385 2 2
R362 SPDIFO R339 1U_0402_6.3V4Z
40
NC
1
20K_0402_5% 4 26 2
R358 DVSS1 AVSS1 AGND
7 42
2
R370 DVSS2 AVSS2
@0_0402_5% 20K_0402_5% @1K_0402_5%
ALC202 E_LQFP48
2
DGND
1
L36
2
0_0805_5%
MDC Connector
1 2 AGND
L19 0_0805_5% JP17
2 2 1 2
1 2 MD_SPK
L10 0_0805_5% C684 C685 3 4
5 6 L25
@4.7U_0805_10V4Z 10U_0805_10V4Z 7 8
1 1 +5VS_MDC
1 2 1 2 +5VS
B L42 0_0805_5% 9 10 CHB1608B121_0603 B
11 12 R313
+3V 1 2 13 14
DGND AGND R66 0_0402_5% +3VS_MDC_R 1 2
+3V_MDC 15 16 +3VS
1 2 10K_0402_5%
+3VS 17 18
L5
CHB1608B121_0603 +3VS_MDC 19 20 IAC_SYNC
+5VALW IAC_SDATAO 21 22
1 2 IAC_SDATAI1 <18>
+5VCD +5VALW B+ IAC_RST# 23 24 R316 0_0402_5%
+5VALW TO +5VCD 25 26 R318 22_0402_5%
27 28 IAC_BITCLK
29 30 1 2
5
6
7
8
@1U_0603_10V4Z
@1U_0603_10V4Z
@22U_1206_10V4Z
@22U_1206_10V4Z
R319 22_0402_5%
1
1
1 1 1 1
D
D
D
D
2 2 2 2
S
S
S
2
R208 S D
2 7
4
3
2
1
S D
3 6
1
S D 2
1 2 4 5
240K_0402_5% G D @2N7002_SOT23
1
SI4425DY-T1_SO8 Q45
C205
2
@1U_0805_25V4Z
@4.7U_0805_10V4Z
@4.7U_0805_10V4Z
@22U_1206_10V4Z
@0.1U_0402_10V6K
@0.1U_0402_10V6K
@150U_D2_6.3VM
R207 2 R538
K
G
1
S
@1U_0603_10V4Z
@1U_0603_10V4Z
10K_0402_5% 1 1 1 1 1 1 1
1 @3.9K_0603_1% C679 C678 C677 C676 C675 C674 C673 + C672
2
10U_1206_16V4Z A
2
2
R
1
@2N7002_SOT23 2 2 2 2 2 2 2
1
O
A Q46 R539 A
D45
Q15
DTC124EK_SC59 @4.99K_0603_1%
2
G
S
I
2
SUSP#
SUSP#
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 28 of 49
5 4 3 2 1
5 4 3 2 1
+5VCD
1
BY-PASS EQ CIRCUIT == W/O EQ +5VCD
R426
+2.5VOP_REF
4
@100K_0402_1%
LINE_OUT_L 2 1 AMP_LEFT 9
V+
2
<28,30> LINE_OUT_L R164 0_0402_5% - R544
O 8
LINE_OUT_R 2 1 AMP_RIGHT 10 2 1 1 2
V-
<28,30> LINE_OUT_R R165 0_0402_5% + L44 0_0805_5%
U48C 0_0805_5%
11
1
2 @LMV824MTX_TSSOP14 1 2
D C556 R435 L45 0_0805_5% D
2
+5VCD
4
13
V+
-
14
O
12
V-
+
U48D
11
@LMV824MTX_TSSOP14
GNDA-EQ
+5VCD +5VCD
+5VCD
1 2
C158 2
C154 C555 C574 @100P_0402_50V8K
@4.7U_0805_10V4Z @0.1U_0402_16V4Z 2 1
2 1 @0.1U_0402_16V4Z
1 1 2
R452 @2.26K_0603_1%
4
4
C C153 C
2
V+
LINE_OUT_L EQ_L_IN1# - AMP_LEFT
2 1 1 2 2 - 1
V+
V-
@0.018U_0603_16V7K EQ_L_IN1 O R425 @4.32K_0603_1% +
2 1 3 +
V-
C486
C157 C548 U48A
11
1
R173 @LMV824MTX_TSSOP14
@143K_0402_1% 1 2 @5.62K_0402_1% 1 2 @1800P_0402_50V7K LEFT CHANNEL
R181 R175 @2.87K_0603_1% 1 2
+5VCD +5VCD R433 @1.05K_0603_1%
2
+2.5VOP_REF 2 2 +5VCD
C488 C163 2
@3300P_0402_50V7K C531
4
4
@2700P_0603_50V7K
1 6
V+ 1 9 @1200P_0603_50V7K 13
V+
V+
- EQ_L_OUT2 - EQ_L_OUT3 1 -
7 8 14 EQ_L_OUT4
EQ_L_IN2 O EQ_L_IN3 O EQ_L_IN4 O
5 10 12
AUDIO LEFT CHANNEL
V-
V-
V-
+ + +
1
U46B U46C U46D
11
11
11
1
1
@LMV824MTX_TSSOP14 @LMV824MTX_TSSOP14 R432 @LMV824MTX_TSSOP14
R166 R187 @162K_0402_1%
@100K_0402_1% @162K_0402_1%
2
+2.5VOP_REF
GNDA-EQ
2
2
+2.5VOP_REF +2.5VOP_REF
+5VCD
1 1 +5VCD
C103 C116
B @4.7U_0805_10V4Z @4.7U_0805_10V4Z B
2 C430 @100P_0402_50V8K
2 2 C126 2 1
@0.1U_0402_16V4Z 1 2
1 R373 @2.26K_0603_1%
+5VCD
4
4
C149 6
V+
LINE_OUT_R EQ_R_IN1# - AMP_RIGHT
2 1 1 2 2 - 7
V+
V-
@0.018U_0603_16V7K EQ_R_IN1 O R368 @4.32K_0603_1% +
2 1 3 +
V-
11
1
R148 @LMV824MTX_TSSOP14
@143K_0402_1% 1 2 @5.62K_0402_1% 1 2 @1800P_0402_50V7K
R346 R341 @2.87K_0603_1% 1 2
+5VCD +5VCD R360 @1.05K_0603_1%
2
+2.5VOP_REF 2 +5VCD
C407 OUTPUT TO AMPLIFIER
2 2
@3300P_0402_50V7K C396
RIGHT CHANNEL
4
4
C435
1 6 @2700P_0603_50V7K 9 @1200P_0603_50V7K 13
V+
V+
V+
- 1 - 1 -
7EQ_R_OUT2 8 EQ_R_OUT3 14 EQ_R_OUT4
AUDIO RIGHT CHANNEL EQ_R_IN2 5
O EQ_R_IN3 10
O EQ_R_IN4 12
O
V-
V-
V-
+ + +
1
U44B U44C U44D
11
11
11
1
2
+2.5VOP_REF
2
+2.5VOP_REF +2.5VOP_REF
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 29 of 49
5 4 3 2 1
A B C D E
1
W/O EQ R385=R386= 1.3K Ohm
C537=C539= 0.47U R454 R513 4.3K 4.3K 1 2 +5VCD
+5VCD 100K_0402_5% R513 4.3K_0402_5%
2 1 OUT_L R = R385, R386
1.3K_0402_5% R441 C = C537, C539 W=40Mil R504 3.6K 3.6K
2
2 1 OUT_R SHUTDOWN#
4
1.3K_0402_5% R196 fo=1/(2*3.14*R*C)=260Hz 1 1 Q33
1
D 2N7002_SOT23
R=1.3K / C=0.47U R503 6.2K 3.6K
2 1 VOL_AMP C180 C185 2 +5VCD VR - C-Type
4.7U_0805_10V4Z EAPD <28>
0.1U_0402_16V4Z C172 0.1U_0402_16V4Z G
4 2 2 +5VCD VOL_AMP 4
S SPK SPK 2 5
3
1 2 NBA_PLUG Bias
@100K_0402_5% R534 0.687 V 0.560 V
(Gain)
2
R430 10 dB 12 dB VR1
3
HIGH PIN 10,4 ACTIVE 100K_0402_5% R512 10K
U47 100K_0402_5%
Pin 22
LOW PIN 9,5 ACTIVE 7 22 HP HP
1
PVDD SHUTDOWN# NBA_PLUG
18 15 2 1
1
PVDD SE/BTL# C650 0.1U_0402_16V4Z
19
VDD PC-BEEP
14 1.006 V 1.006 V
11 R503 3.6K_0402_5%
BYPASS
2
NBA_PLUG INTSPK_L2 D
2 PC-ENABLE LOUT- 9 -2 dB -2 dB 2N7002
VOL_AMP 3 16 INTSPK_R2 2 R504
INTSPK_L1 VOLUME ROUT- G Q38 3.6K_0402_5%
4 LOUT+ LIN 10
INTSPK_R1 21 8 2N7002 S
3
ROUT+ RIN
1
AMP_LEFT 1 OUT_L D Q36
2 1 2 5
1
<29> AMP_LEFT C570 0.47U_0603_16V4ZC564 0.47U_0603_16V4Z LLINEIN NBA_PLUG 2
23 RLINEIN GND 1
AMP_RIGHT 1 2 OUT_R 1 2 6 12 G
<29> AMP_RIGHT C514 0.47U_0603_16V4ZC532 0.47U_0603_16V4Z LHPIN GND
20 13 2 1 1 S
3
RHPIN GND
GND 24
17 CLK
LINE_OUT_L 1 2 HP_L C563 C533 C551
<28,29> LINE_OUT_L C581 0.47U_0603_16V4Z 1 2 2 0.47U_0603_16V4Z
LINE_OUT_R 1 2 HP_R TPA0232 0.47U_0603_16V4Z
<28,29> LINE_OUT_R C515 0.47U_0603_16V4Z
0.47U_0603_16V4Z
HP won't C651 (0.47U~1U) +AUD_VREF
implement 0.047U_0402_16V4Z
EQ.
MICROPHONE
R162
IN JACK
1
3 2.2K_0402_5% 3
R163 JP3
@2.2K_0402_5%
Speaker Connector 5
2
JP4 3
INTSPK_L1 L15 6
INTSPK_L2 1 MIC MIC-1
2 <28> MIC 1 2 2
INTSPK_R1 1
INTSPK_R2 3 FBM-11-160808-700T_0603
4 FOX_JA6033L-5S1-TR
1
ACES_85204-0400
C159
220P_0402_50V8K
2
2
SM05_SOT23
D34
1 LINE IN JACK
3
JP2
5
4
SM05_SOT23 L13
D33 1 2 LINE_IN_R-1 3
2 <28> LINE_IN_R 2
1 FBM-11-160808-700T_0603 6
1 2 LINE_IN_L-1 2
System Sound <28> LINE_IN_L
L14
FBM-11-160808-700T_0603
1
+VDDA 1 1 FOX_JA6033L-5S1-TR
+3V +3V
<32> BEEP#
C136 C110
1
330P_0402_50V7K 330P_0402_50V7K
1
C192 R203 2 2
R206 1 2 10K_0402_5%
100K_0402_5%
0.1U_0402_16V4Z
2
14
2
4
U16B U31A 1
1
5 6 1 2 1 2 1 2 1 2 R204 10U_1206_16V4Z
I O 8.2K_0402_5% I O 10K_0402_5%
G
1U_0402_6.3V4Z 560_0402_5% 2
1 HEADPHONE
SN74LVC125APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7
1U_0402_6.3V4Z
NBA_PLUG 4
C
R221 L16
C219 Q16 INTSPK_R1 1
+
2 1 2 3
1 2 1 2 MONO_IN_I 2SC2411K_SC59 R205 C148 150U_D2_6.3VM FBM-11-160808-700T_0603 6
<21> PCM_SPK# 2.4K_0402_5% INTSPK_L1 1
+
2 1 2 2
B
FBM-11-160808-700T_0603 1 1
2
+3V FOX_JA6033L-5S1-TR
C186 C176
1 330P_0402_50V7K 330P_0402_50V7K 1
2 2
14
<18> ICH_SPKR 3 I O 4 1 2 1 2
G
1U_0402_6.3V4Z 560_0402_5%
1
SN74LVC14APWLE_TSSOP14
Compal Electronics, Ltd.
7
R211
D20 Title
10K_0402_5% RB751V_SOD323 SCHEMATIC, M/B LA-1931
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 30 of 49
A B C D E
A B C D E
GPIO17 DSR2#
1 57 GPIO20 TXD2 96
C49 R302 100K_0402_5% 58 95 1 2
GPIO21 RXD2 DCD#2 R311 1K_0402_5%
+3VS 1 2 59 GPIO22 DCD2# 94
@15P_0402_50V8J 6 92 R I#2
2 FIR_EN# GPIO24 RI2#
32 GPIO30
33 89 DTR#1
GPIO31 DTR1# CTS#1
34 GPIO32 CTS1# 88
35 87 RTS#1
GPIO33 RTS1# DSR#1
36 86
37
38
GPIO34
GPIO35
DSR1#
TXD1 85
84
TXD1
RXD1 1 2
Serial Port
PCLK_SIO GPIO36 RXD1 DCD#1 R50 1K_0402_5%
39
40
GPIO37
GPIO40
DCD1#
RI1#
91
90 R I#1 for Debug
2
41 GPIO41
R60 42 63 IRMODE
@33_0402_5% GPIO42 IRMODE/IRRX3 IRRX
43 GPIO43 IRRX2 61 1 2
44 62 IRTX R296 1K_0402_5%
GPIO44 IRTX2
45
1
GPIO45 RDATA#
1 46 GPIO46 RDATA# 16
C31 47 10 WDATA# +5V
2 GPIO47 WDATA# WGATE# 2
WGATE# 11
@22P_0402_50V8J 2 1 51 12 HDSEL#
2 R294 10K_0402_5% GPIO13/IRQIN1 HDSEL# FDD IR# +3VS JP16
52 GPIO14/IRQIN2 DIR# 8
2 1 64 9 STEP# 1
R297 10K_0402_5% GPIO23/FDC_PP STEP# DRV0# 1
DS0# 5 2 2
18 13 INDEX# RXD1 3
+3VS VTR INDEX# 3
2
4 DSKCHG# TXD1 4
DSKCHG# WP# R42 DSR#1 4
1 53 15 5
C289 VCC WRTPRT# TRACK0# RTS#1 5
65 14 @10K_0402_5% 6
0.1U_0402_16V4Z VCC TRK0# MTR0# CTS#1 6
93 3 7
VCC MTR0# DTR#1 7
1 1 1 8
1
C326 2 C320 DRVDEN0 R I#1 8
7 9
0.1U_0402_16V4Z VSS DCD#1 9
31
VSS DRVDEN1
2 * Base I/O Address 10
10
4.7U_0805_10V4Z 1 60 0 = 02Eh
2 2 C328 VSS @E&T_96212-1011S
76
VSS GPIO11/SYSOPT
49 1 = 04Eh
2
R46
2 LPC47N227 B_TQFP100 1K_0402_5%
0.1U_0402_16V4Z
1
RP3
Parallel Port LPTACK# 6 5 +5V_PRN
3
LPTBUSY
LPTPE
7
8
4
3
AFD#/3M#
LPTERR#
+5V_PRN
FIR Module 3
LPTSLCT 9 2 LPTINIT# D1
10 1 LPTSLCTIN# 2 1
+5V_PRN +5VS
1
RB420D_SOT23 +IR_ANODE
2.7K_1206_10P8R_5% R2 +3VS 1 2
CP7 2.2K_0402_5% R53 3.3_1206_5%
1 8 LPTSLCTIN# 1 2 60mil
2 7 LPTINIT# R3 C1 FIR_EN# R58 @3.3_1206_5%
2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 31 of 49
A B C D E
5 4 3 2 1
123
136
157
166
161
2 2 2 2 1 1 0.1U_0402_16V4Z
16
34
45
95
7 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 2 U24 8 EC_URXD
8 EC_UTXD
9
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VBAT
VDD
AVCC
9 EC_USCLK
10 10
+EC_AVCC +3VALW
L38 BATT_TEMPB @E&T_96212-1011S
1 2 7 81 BATT_TEMP
<17,21,31> SERIRQ SERIRQ AD0 VBATTA BATT_TEMPA <39>
CHB1608U800_0603 1 2 8 82
D <18> LPC_DRQ#0 LDRQ# AD1 ADP_I <40,43> D
1 R391 @0_0402_5% 9 83
<18,31> LPC_FRAME# LPC_AD0 LFRAME# AD2 VBATTB BATT_OVP <40>
C554 15 84
LPC_AD1 LAD0 Host interface AD3
14 87 ALI/MH# <39,43>
0.1U_0402_16V4Z LPC_AD[0..3] LPC_AD2 LAD1 IOPE0AD4 CP6
<18,31> LPC_AD[0..3] 13 88 EMAIL# <34>
2 LPC_AD3 LAD2 IOPE1/AD5 KSO15
ECAGND
10
18
LAD3 AD Input IOPE2/AD6
89
90
MODE# <34> KEYBOARD CONN. KSO14
5
6
4
3
<14> CLK_LPC_EC EC_RST# LCLK IOPE3/AD7 AD_BID0 INTERNET# <34> KSO10
19 93 7 2
RESET1# DP/AD8
1
22 94 JP9 KSO11 8 1
R416 SMI# DN/AD9 NUM_LED#
23
PWUREQ# 34 PADS_LED# 100P_1206_8P4C_50V8
@33_0402_5% 99 DAC_BRIG <16>
DA0 33 CAPS_LED# R235
100 EN_DFAN2 <34>
+3VS EC_SCI# DA output DA1 32 +3VS CP5
31 101 1 2
2
<18> EC_SCI# IOPD3/ECSCI# DA2 IREF <40> 31 KSO15 KSO8
DA3 102 EN_DFAN1 <34> 30 5 4
1 KSO14 300_0402_5% KSO9 6 3
EC_GA20 INVT_PWM 29 KSO10 KSO13
5 GA20/IOPB5 IOPA0/PWM0 32 INVT_PWM <16> 28 7 2
2
R388 1K_0402_5%
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
KBA2
NC10
R458 R136 1 2
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
17
35
46
122
159
167
137
96
11
12
20
21
85
86
91
92
97
98
1 X1
R453 C559
4 56K+-1% 32.768KHZ_12.5PF_CM155 1 2
1
Rb 0_0402_5%
2
0.1U_0402_16V4Z
5 100K+-1% 1 1 PC87591L-VPCN01 A2_LQFP176 L34
C124 C106 ECAGND1 2 @1U_0402_6.3V4Z
1
6 200K+-1%
2
10P_0402_50V8K
2
12P_0402_50V8J
Title
Compal Electronics, Ltd.
CHB1608U800_0603
Analog Board ID definition, SCHEMATIC, M/B LA-1931
Please see page 3. PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 32 of 49
5 4 3 2 1
+5VALW
C51
1 2
0.1U_0402_16V4Z
U9
20
+3VALW
ADB0 3 2
VCC
ADB1 D0 Q0 CDON_LED# <34>
+3VALW 4 5
ADB2 D1 Q1 MP3_LED# <34>
C395 7 6
D2 Q2 E-MAIL_LED# <34>
2
1 2 ADB3 8 9
D3 Q3 PWR_LED# <34>
R350 ADB4 13 12
ADB5 D4 Q4 WL_BT_LED# <34>
0.1U_0402_16V4Z 100K_0402_5% 14 15
D5 Q5 BATT_LOW_LED# <34>
ADB6
14
17 16 BATT_CHGI_LED# <34>
U15A ADB7 D6 Q6
18 19
1
KBA2 D7 Q7 CD_FDD_LED# <34>
1
P
A AA
3 11
GND
SELIO# O LARST# CP
2 B 1 MR
<32> SELIO#
G
SN74LVC32APWLE_TSSOP14 SN74HCT273PW_TSSOP20
7
10
C52
+5VALW 1 2 1 2
R73 1U_0805_25V4Z
20K_0402_5%
5 28
U15B KBA6 A7 A13 KBA8
3 6 27
S FLASH# <18> KBA5 A6 A8 KBA9
4 7 26
P
2
C230
1 2 R244
2
100K_0402_5%
C48 R236 R237 0.1U_0402_16V4Z
0.1U_0402_16V4Z 4.7K_0402_5% 4.7K_0402_5% U34
1
1 2 +3VALW 8 VCC
A0
1
U43 U41 7 WP 2
1
A1
<32,39> EC_SMC1 6 SCL 3
KBA11 FR D# KBA11 FR D# A2
1 32 1 32 <32,39> EC_SMD1 5 SDA 4
KBA9 A11 OE# KBA10 FRD# <32> KBA9 A11 OE# KBA10 GND
2 31 2 31
KBA8 A9 A10 FSEL# KBA8 A9 A10 FSEL# AT24C16N-10SI-2.7_SO8
3 30 3 30
KBA13 A8 CE# ADB7 FSEL# <32> KBA13 A8 CE# ADB7
4 29 4 29
KBA14 A13 DQ7 ADB6 KBA14 A13 DQ7 ADB6
5 28 5 28
A14 DQ6 A14 DQ6
2
KBA17 6 27 ADB5 KBA17 6 27 ADB5
FWE# A17 DQ5 ADB4 FWE# A17 DQ5 ADB4 R241
7 26 7 26
WE# DQ4 ADB3 WE# DQ4 ADB3 100K_0402_5%
8 25 +3VALW 8 25
KBA18 VCC DQ3 KBA18 VCC DQ3
9 24 9 24
KBA16 A18 VSS ADB2 KBA16 A18 VSS ADB2
10 23 10 23
1
KBA15 A16 DQ2 ADB1 KBA15 A16 DQ2 ADB1
11 22 11 22
KBA12 A15 DQ1 ADB0 KBA12 A15 DQ1 ADB0
12 21 12 21
KBA7 A12 DQ0 KBA0 KBA7 A12 DQ0 KBA0
13 A7 A0 20 13 A7 A0 20
KBA6 14 19 KBA1 KBA6 14 19 KBA1
KBA5 A6 A1 KBA2 KBA5 A6 A1 KBA2
15 A5 A2 18 15 A5 A2 18
KBA4 16 17 KBA3 KBA4 16 17 KBA3
A4 A3 A4 A3
@SST39VF040_TSOP @29F040_TSOP
KBA[0..18]
<32> KBA[0..18]
AD B[0..7] Title
Compal Electronics, Ltd.
<32> ADB[0..7]
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 33 of 49
5 4 3 2 1
+3VALW +3VALW
SW BOARD Connector +5VALW LID_SW# Kill SWITCH
(Top contact)
Touch Pad Connector
1
SW6
2
JP6 R23
R522 <32> TP_CLK TP_CLK 1
10K_0402_5% TP_DATA 1 100K_0402_5% 1 R68
<32> TP_DATA 2 SW1
1 100K_0402_5%
2
3
6 2
1
4 LID_SW# 2
5 <32,36> LID_SW# 2
SUSP_LED# 5 3
+5VS 6 3 KILL_SW# <25,32>
1 3
1
D C608 ACES_85201-0602 DS-1208_3P
4
<32> PWR_SUSP_LED 2
G Q43 1U_0603_10V6K D8 ESE24MV1T_6P D10
D S 2N7002_SOT23 2 V-PORT-0603-220 M-V05_0603 V-PORT-0603-220 M-V05_0603 D
3
+5VALW
2
1
C652 C614
JP8 51ON#
1U_0603_10V6K 1 C653 100P_0402_50V8K
TV-OUT BUTTON WIRELESS ACTIVE AMB LED
1000P_0402_50V7K 2 MODE# 1 MODE#
<32> MODE# 2
51ON# 2 C654 100P_0402_50V8K
<38> 51ON# 3
4
3 KSO17 SMT1-05_4P HP HSMG-C170 AMB 0805 D11 R109
4 C649 100P_0402_50V8K SW5
5 5 1 2 2 1 +3VALW
6 EC_REVBTN# 1 3
+5VALW 6
7 C655 100P_0402_50V8K 120_0402_5%
+5VALW 7
3
+3VS 8 EC_FRDBTN# KSO17 2 4
+5VALW KSO17 8 TV_OUT_EN# <32>
<32> KSO17 9 C656 100P_0402_50V8K
EC_REVBTN# 9 EC_PLAYBTN# E
10 47K
6
5
<32> EC_REVBTN# 10
2
1
R494 EC_PLAYBTN# 12 EC_STOPBTN# WL_BT_LED# 2
<32> EC_PLAYBTN# 12 <33> WL_BT_LED#
2
1
<33> PWR_LED# SUSP_LED# 16
17 C660 100P_0402_50V8K
1
2
17
2
BATT_LOW_LED# 18 SUSP_LED#
<33> BATT_LOW_LED# BATT_CHGI_LED# 18 *
19 C648 1000P_0402_50V7K
<33> BATT_CHGI_LED# HDD_LED_OUT# 19 BATT_LOW_LED#
<32> HDD_LED# 3 1 20 20
Q35 CD_FDD_LED# 21 C661 100P_0402_50V8K
MMBT3904_SOT23 <33> CD_FDD_LED# 21 BATT_CHGI_LED#
22 22
CDON_LED# 23 C662 100P_0402_50V8K
<33> CDON_LED# MP3_LED# 23 HDD_LED#
<33> MP3_LED# 24 24 Internet Button +3VALW User Button & E-MAIL SW
C E-MAIL_LED# C663 100P_0402_50V8K C
<33> E-MAIL_LED# 25 25
26 CD_FDD_LED# 51ON#
26 C664 100P_0402_50V8K
E&T_6901-26 CDON_LED# R7 2 1 100K_0402_5% EMAIL#
1
C665 *
220P_0402_50V8K
MP3_LED# R275 R280 2 1 100K_0402_5% INTERNET#
FAN CONN. 1
2
C666 100P_0402_50V8K 1N4148_SOT23 EMAIL#
EMAIL# <32>
E-MAIL_LED# Q22 0_0603_5% D3
G
S
+12VALW C667 *
220P_0402_50V8K
2
2
For EMI D28 INTERNET# 1 D4
1 1 INTERNET# <32>
D
C642 +5VALW NDS352AP_SOT23 2 1N4148_SOT23 1N4148_SOT23
0.1U_0402_16V4Z C640 3
2
0.1U_0402_16V4Z 1
2 2
8
3 D25
1
1
2
100_0402_5% 1SS355 2
1
G
6
5
3
2
B
10K_0402_5% C620
4
0.1U_0402_16V4Z 1 JP22 D5
2
6
5
1 PSOT24C_SOT23
1
1 2
2
1
1000P_0402_50V7K 3 PSOT24C_SOT23
C636 3 D26
1 2 4
1
R514 8.2K_0402_5% D39 4
1N4148_SOT23 2 ACES_85205-0400
1
B +3VS B
Power Button
3
2
2
R516 1
10K_0402_5% C639
ON/OFF# <36>
2
3
1000P_0402_50V7K
RTC BATT
1
2
<32> FAN_SPEED1
D27 +3VALW
2
PSOT24C_SOT23
+5VALW D29 R286 +RTCBATT
FAN CONN. 2 - +
1
1
ON/OFF <32>
U49B 2 4 1
1
FMMT619_SOT23 1 51ON#
1
6
5
1
7 1 2 D40 +3VALW
OUT
1
2 1 6 2 10U_1206_16V4Z 1000P_0402_50V7K D21
-IN 100_0402_5% 1SS355 2 Q24 BAS40-04_SOT23
O
2
2
1
R509 LM358A_SO8 C292
2
B
JP24 1
G
R292
I
1 1
1
2
1
1
3
2 <32> EC_ON +CHGRTC
1 2 D41 C641 3 1
R511 8.2K_0402_5% 3 33K_0402_5% C222
4 4
A 2 DTC124EK_SC59 A
+3VS ACES_85205-0400 0.1U_0402_16V4Z
2
1
D
2
Q23 2
3
2N7002_SOT23 G
R354 1 S
3
10K_0402_5% C644
Compal Electronics, Ltd.
1
1000P_0402_50V7K Title
2
<32> FAN_SPEED2 SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 34 of 49
5 4 3 2 1
A B C D E
1
FD4 FD5 FD6
FIDUCAL FIDUCAL FIDUCAL
1
1 1
+3V +3V
13
14
14
U16D U31C U31D
R479
OE#
P
<14,18,44> VGATE 12 11 1 2 5 6 9 8
1
I O I O I O SYS_PWROK <8,18>
G
20K_0402_5% 2 CF16 CF8 CF21 CF7 CF11 CF9 CF4
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80
7
SN74LVC125APWLE_TSSOP14 C610
1U_0805_25V4Z
1
1
CF6 CF5
SMD40M80 SMD40M80
1
VID_PWRGD
+3V
H1 H2 H3 H10 H14
1
1
2
VID_PWRGD <44>
1 2 ENLL <44>
R131 0_0402_5% H29 H30 H33 H34 H35
10
<5> H_VID_PWRGD 8 9
O I
1
SN74LVC125APWLE_TSSOP14
+3V POWER
H4 H9 H5 H8
H_C315D142 H_C315D142 H_C315D142 H_C315D142 H41
H_C118D118N
1
H6 H23
H_S315D181 H_S315D181 H7 H12 H11 H26
H_C276D142 H_C276D142 H_C197D91 H_C197D91
3 3
1
+3VALW +3VALW H13 H27 H15
+3V +3V H_C126D110 H_C126D110 H_S315D118 H17 H22
H_C276D91 H_C276D91
14
14
U15C U15D
14
14
1
U31E U31F 9 12
P
1
A A
8 11
P
O O
11 10 13 12 10 13
I O I O B B
G
G
G
SN74LVC32APWLE_TSSOP14 SN74LVC32APWLE_TSSOP14
7
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7
1
4 H16 H21 H20 H24 H28 H32 4
H_O85X118D85X118N H_C63D63N H_O63X102D63X102N H_C85D85N H_O201X162D201X162N H_O315X236D315X236N
1
1
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 35 of 49
A B C D E
A B C D E
1 1
RTCVREF
1
C59 0.1U_0402_16V4Z
R110 R107 R115 1 1 2
10K_0402_5% 100K_0402_5% 620K_0402_5%
2
1
D Q10
1 2 2 4 1 2 2
C71 1U_0805_25V4Z R112 10K_0402_5% G 2N7002_SOT23
U13 S
3
D12 NC7SZ14M5X
3
1
2 D Q7 2
<32,34> LID_SW# 1 2 2
G 2N7002_SOT23
S
1
RB751V D Q8
<32,37,42> SYSON 2
G 2N7002_SOT23
RTCVREF S
3
1 2 C83 1 2
R111 10K_0402_5%
1U_0805_16V7K
RTCVREF
U14
1 14
CD1# VCC
1
D Q11
2 13 1
D1 CD2# 0.1U_0402_10V6K
<32> S4_LATCH 3 12 2
CP1 D2 C681 G 2N7002_SOT23
RTCVREF 1 2 4
SD1# CP2
11
R543 1 5 10 S
3
Q1 SD2#
1
10K_0402_5% C680 2
6 09
R535 Q1# Q2
7 08
10K_0402_5% +3VALW @1U_0805_16V7K GND Q2#
2
74LCX74
1 2
2
R114 10K_0402_5%
D14
2 1 D_SET_S4
<32> S4_DATA
RB751V
3 3
4 4
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 36 of 49
A B C D E
A B C D E
1
R252 R223
+1.5VALW +1.5V +1.5VALW +1.5VS 470_0402_5% 1K_0402_5%
U38 U39
8 1 4.7U_0805_10V4Z 8 1 4.7U_0805_10V4Z
1 2
1 2
D S D S
7 D S 2 1 1 1 7 D S 2 1 1 1 D D
6 3 C266 C265 6 3 C264 C268 C267
D S ON_GATE C263 D S +5VS_GATE SYSON# 2 SUSP
5 D G 4 5 D G 4 2
1 1U_0603_10V4Z 4.7U_0805_10V4Z 1 1U_0603_10V4Z 4.7U_0805_10V4Z G Q20 G Q17
C280SI4800DY_SO8 2 2 2 C286SI4800DY_SO8 2 2 2 S 2N7002_SOT23 S 2N7002_SOT23
3
1 4.7U_0805_10V4Z 4.7U_0805_10V4Z 1
2 2
+3VALW To +3V Transfer +3VALW To +3VS Transfer +3V & +3VS Discharge +3V +3VS
1
+3VALW +3V R201 R77
U19 +3VALW +3VS 470_0402_5% 1K_0402_5%
8 1 U10
D S 10U_1206_16V4Z 10U_1206_16V4Z 10U_1206_16V4Z
7 2 1 8 1
1 2
1 2
D S C92 D S
6 D S 3 1 7 D S 2 D D
5 D G 4 6 D S 3 1 1 1 1 1
4.7U_0805_10V4Z C87 5 4 C54 C46 C50 C41 C43 SYSON# 2 SUSP 2
SI4800DY_SO8 2 1U_0805_25V4Z D G G Q14 G Q3
1 2
C89 1 SI4800DY_SO8 1U_0603_10V4Z 10U_1206_16V4Z S 2N7002_SOT23 S 2N7002_SOT23
3
C55 2 2 2 2 2
4.7U_0805_10V4Z ON_GATE
2 4.7U_0805_10V4Z +5VS_GATE
2 2 2
+5VALW To +5V Transfer +5VALW To +5VS Transfer +5V & +5VS Discharge
1
1 4.7U_0805_10V4Z 1U_0805_25V4Z
C233 SI4800DY_SO8 2 2 SI4800DY_SO8 4.7U_0805_10V4Z 4.7U_1206_25VFZ 4.7U_1206_25VFZ 4.7U_1206_25VFZ R239 R92
1 2 2 2 2 2
C232 470_0402_5% 1K_0402_5%
4.7U_0805_10V4Z
3 2 4.7U_0805_10V4Z 3
+12VALW
1 2
1 2
ON_GATE 2 +5VS_GATE
+12VALW 1 2 2 1 D D
R251 100K R246 100K
1
1
D SYSON# 2 SUSP
1 1 2
1
R249 C242 SYSON# R245 C240 D G Q18 G Q5
2
G 2 SUSP S 2N7002_SOT23 S 2N7002_SOT23
3
1M_0402_5% S Q19 1M_0402_5% G
3
2 2N7002_SOT23 2 S Q21
2
3
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2N7002_SOT23
+5VALW +5VALW
1
R108 R104
10K_0402_5% 4.7K_0402_5%
2
SYSON# SUSP
1
4 D D 4
2 SUSP# 2
<32,36,42> SYSON <21,28,32,33,43> SUSP#
G Q6 G Q9
S 2N7002_SOT23 S 2N7002_SOT23
3
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 37 of 49
A B C D E
A B C D
V IN
VS
PF2 12A_65VDC_451012 PL14 V IN
PCN1 1 2 1 2
1 2
1 1 C8B BPH 853025_2P
6 G PR128 1M_0603_1%
1
5 G
1
4 2 PR130 VS 1 2
G 2 A C IN <17,32,34>
1
3 PC114 PC115 84.5K_0603_1% PR129 PR131 1K_0603_5%
G
1
PD28 PC113 100P_0603_50V8J 5.6K_0603_5%
2
1000P_0603_50V7K
8
SINGA_2DC-S113L200 EC10QS04_SOD106 PC112 100P_0603_50V8J PU14A
2
1 2 3
P
1 1
G
1
1
1
PR133 LM393M_SO8 PD1
1
1000P_0603_50V7K PC116 20K_0603_1% PC117
1000P_0603_50V7K 0.1U_0603_50V4Z PR134
Vin Detector
2
RLZ4.3B_LL34 10K_0603_1%
2
SINGA_2DC-S133L200 120W
2
2 1 RTCVREF High 18.764 17.901 17.063
SINGA_2DC-S726B201 90W PR135 10K_0603_1%
3.3V Low 17.745 16.903 16.038
V IN
2
PZD2 PD29
BATT+ 2 1
1N4148_SOD80 1 2
RB751V_SOD323
1
PR136 1K_1206_5%
2 2
1
PQ46
PR151 TP0610T_SOT23 PR137 PD31
CH GRTCP 1 2 N1 33_1206_5% 2 1 N3 1 2
VS VIN B+
3 1N4148_SOD80 PR138 1K_1206_5%
2
200_0603_5% S
1
PC118 1
D
1
0.22U_1206_25V7K
2
2 G 1 2
PR139
100K_0603_5% 1 PR140 1K_1206_5%
1
2
PC119 PR144
1 2 0.1U_0603_50V4Z 499K_0603_1%
<34> 51ON#
2
VL 1 2 2 1
PR141 22K_0603_5%
6.0V
2
PR142 10K_0603_1% PR143 1M_0603_1%
RB715F_SOT323
8
2 PU14B
<39,41> MAINPWON
1
+ 5
P
PR145 1 7
RTCVREF 200_0603_5% O
- 6
1
PU15 3
<40> ACON
1
S-81233SGUP-T1_SOT89 LM393M_SO8 PR146
3.3V
2
4
1
1
PR147 499K_0603_1% PC120
3 PR152 PR149 PD32 PC121 10K_0603_1% PR148 1000P_0603_50V7K 3
2
1 2 1 2 3 2 1000P_0603_50V7K PC122 215K_0603_1%
+CHGRTC
2
3 2 0.1U_0603_50V4Z
1
200_0603_5% 200_0603_5%
2
1
1
PD4 RTCVREF
1
1
PC123
3.3V
1
PC124 RLZ16B_LL34
2
10U_1206_10V4Z 1U_0805_25V4Z
D
2
PQ47
2N7002_SOT23
G
S
Precharge detector
2
2 1P ACIN
PJP2 PJP3 15.34 15.90 16.48 PR150 47K_0603_5%
+2.5VP 1 2 +2.5V (8.5A,340mils ,Via NO.= 142) +1.25VSP 1 2 +1.25VS 13.13 13.71 14.20
1
PAD-OPEN 3x3m PAD-OPEN 2x2m
O
PJP6 (900mA,40mils ,Via NO.= 2) PQ48
2 1 +1.5VALW (4A,160mils ,Via NO.= 8) DTC115EKA_SC59
+1.5VALWP
G
PJP5
I
PAD-OPEN 3x3m
+1.2VP 2 1 +1.2V
2
+5VALWP
4 PJP7 PAD-OPEN 2x2m 4
10K_TSM1A-103(F4D3R)_0603_1%
2
VMB
PCN2 PR109
1
1 PF1 PL13 47K_0603_1%
BATT+ MAINPW ON <38,41>
1
2 1 2 1 2 PC105
BATT+ BATT+
1
3 BLI/N IMH# 2 1 PH1 0.1U_0603_50V4Z
1
ID B B/I PR110 1K_0603_5% 12A_65VDC_451012 +3VALWP C8B BPH 853025_2P
4
O
2
B/I TS
5 1 2
2
TS
1
6 EC_SMDA 1 2 PQ45
SMD EC_SMCA PC106 PC107 PR112 DTC115EKA_SC59
SMC 7
1
10 8 PR111 47K_0603_5% 1000P_0603_50V7K 0.01U_0603_50V7K 47K_0603_1%
2
GND GND-
G
1
8
PR116 PU13A
I
11 GND GND- 9
PR113 1K_0603_5% 1 2 3 PD23
3
SUYIN_200275MR009G116ZL 100_0603_5% PR115 16.9K_0603_1% +
3 O 1 2 1
TM_REF1 2
2
-
G
1 PD22 1SS355_SOD323
2
@ BAS40-04_SOT23 LM393M_SO8
4
1
2
PR114
100_0603_5%
1
PR117
1
2
PC108 3.32K_0603_1%
ALI/MH# <32,43>
2 1 VL
2
0.22U_1206_25V7K
2
1 2 PR118 100K_0603_1%
+3VALWP
1
PR119 25.5K_0603_1% PC109
1
1
2 2
2
PR121 PR120
1K_0603_5% 100K_0603_1%
2
2
3
PD24 1000P_0603_50V7K
1
@ BAS40-04_SOT23
2
PD25
PD26 VL
@ BAS40-04_SOT23
@ BAS40-04_SOT23 VL
2
PR122
47K_0603_1%
3
1
3 3
PH2
1
10K_TSM1A-103(F4D3R)_0603_1%
+5VALWP
1 2
2
PR123 47K_0603_1%
8
PU13B
1 2 5 PD27
P
PR124 16.9K_0603_1% +
O 7 2 1
TM_REF2 6 -
G
1SS355_SOD323
1
LM393M_SO8
4
PR126
3.92K_0603_0.5%
2
1
2 1 VL
PC110
PR125 100K_0603_1%
1
0.22U_1206_25V7K
PC111 PR127
2
100K_0603_1%
2
1000P_0603_50V7K
4 4
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 39 of 49
A B C D
A B C D
PQ39
1
6 3 3 6 0.01_2512_1% C8B BPH 853025_2P PC84 3 5
D S S D PC85
5 D G 4 4 G D 5
1
1
1 4.7U_1210_25V6K PC86 1
2
PR80 PR81 SI4825DY_SO8
4
10K_0603_1% SI4825DY_SO8
200K_0603_1% 4.7U_1210_25V6K 4.7U_1210_25V6K
2
2
PR82 PR83
AC OFF# 1 2 1 2 V IN
10K_0603_1% 47K_0603_5%
1
PR84 PU11
150K_0603_1% 1 24 PR85
<32,43> ADP_I -INC2 +INC2
3
2
1
0_0603_5%
1 2 PQ40
1
2 1 2 23 SI4835DY_SO8
PQ42 OUTC2 GND N18 4
O
PD19 2N7002_SOT23 PR86 100K_0603_1% PC87
D
AC OFF#1 2 3 22 CS 1 2 PQ41
+INE2 CS DTC115EKA_SC59
1SS355_SOD323 0.022U_0603_25V7K
G
1
I
4 -INE2 VCC(o) 21 1 2
G
PC89 PR89
5
6
7
8
2
1
PR87 10K_0603_1% PR88 PC90 PR90 10K_0603_5% PC88 0.1U_0603_50V4Z
2
2
3K_0603_5% 4700P_0603_50V7K PC91
6 19 1 2 LXCHRG
VREF VH
1
AC ON PC93 PR91 1K_0603_5% 0.1U_0603_50V4Z PC94
<38> ACON
2 PC92 1 2 1 2 7 18 1 2 2
1
CS 0.02_2512_1%
PR97 PC96 10K_0603_1% 47K_0603_5% 1500P_0603_50V7K 22UH_SPC-1205P-220A_2.8A_20%
+3VALWP 100K_0603_1% 0.1U_0603_50V4Z 11 14 AC ON
2
OUTD CTL
1
1
PC97 PC98 PC99
PD21
O
12 13 4.7U_1210_25V6K
2
-INC1 +INC1
1
PQ43 RB051L-40_SOD106~D
PR99 DTC115EKA_SC59
2
47K_0603_5% MB3887_SSOP24
G
I
2
4.7U_1210_25V6K
1
4.7U_1210_25V6K
O
PR100
PQ44 1 2
4.2V 2 1
DTC115EKA_SC59
95.3K_0603_1% PR101 143K_0603_1%
G
I
3 3
PR2
2
1 2
95.3K_0603_1%
<32> FSTCHG
VMB
120W 90W
VS
1
PC100
0.1U_0603_50V4Z PR103
(BAT_OVP=0.1111 *VMB)
2
PU12A
3
P
+
1
<32> BATT_OVP 0
2
-
G
1
4
LM358A_SO8 PR153
4 105K_0603_0.5% PC104 4
1
PC103 0.01U_0603_50V7K
2
PR107
2
@ 0.1U_0603_16V4Z 2.2K_0603_5%
2
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 40 of 49
A B C D
A B C D
PC61
1 N4 1 2 1
1
4.7U_1210_25V6K
2
PC62 PD14
470P_0805_100V7K
PC63 EC11FS2_SOD106
1
1 2 BST31 BST51 PR64
2
B+++ S NB 2 1 FLYBACK
PL9 0.1U_0603_50V4Z
2
1 2 22_1206_5%
B+
3
HCB4532K-800T90_1812
1
3
4.7U_1210_25V6K PQ35 PR65 DAP202U_SOT323
2
2
2 7 PD16
1
D1 S1/D2 0_0603_5%
3 G2 S1/D2 6
4.7U_1210_25V6K 4 5 PLX3 +12VALWP
S2 S1/D2 1SS355_SOD323
SI4814DY_SO8 PC67 PC68
1
1
4.7U_1210_25V6K
PC69
2
1
PC70 4.7U_1206_16V4Z 4.7U_1210_25V6K
1
PDL3
0.1U_0603_50V4Z PC71 PQ36
2
1
4.7U_1206_16V4Z
PDH3
1 8
2
PC72 D1 G1
2 2 D1 S1/D2 7 2
PL10 47P_0603_50V8J 3 6
2
PD H5 P DH51 G2 S1/D2
1 2 4 S2 S1/D2 5
10UH_SPC-1205P-100_4.5A_20%
PR66 0_0603_5% SI4814DY_SO8
2
1
22
21
PU10 PC73
25 4 PDL5 47P_0603_50V8J
VL
V+
2
BST3 12OUT
VDD 5
2
27 18 CS H5
DH3 BST5
1
PR67 16
PR68 1M_0603_1% DH5 PLX5
26 LX3 LX5 17
1
0.012_2512_1% 24 19
DL3 DL5
1
+3VALWP 20 PR69
1
CS H3 CSH5 0.012_2512_1%
1 CSH3 CSL5 13
2 12
2
CSL3 FB5
3 15
2
FB3 SEQ
1 1 <38,40,43> PACIN 1 2 10 SKIP# REF 9 2.5VREF
1
23 SHDN# SYNC 6
1
1
PC74 PC76 7
EP10QY03 TIME/ON5 PC77
+5VALWP
2
2 2 3.57K_0603_1% 4.7U_1206_16V4Z
28
GND
2
2
RUN/ON3
1
1
1
1
150U_D2_6.3VM MAX1632_SSOP28 1
8
1
@150U_D2_6.3VM 100P_0603_50V8J PC125 PR73 PC81 + PC80 PD18
2
2
10K_0603_1% 2
2
1
2
POK <42>
PR75
1
1
47K_0603_5%
PR77
PR78 @150U_D2_6.3VM
2
2 1 10K_0603_1%
VL
2
47K_0603_1%
1
PC83
0.047U_0603_25V7M
2
4 4
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 41 of 49
A B C D
A B C D
1
+2.5V/+1.5V 1
PL15
1 2 B+
HCB4532K-800T90_1812
2
1
PC126 PR154
0_0603_5%
4.7U_1210_25V6K +5VALWP
1
1
1
PC127 PC130
1
4.7U_1206_16V4Z PC128 4.7U_1210_25V6K
5
6
7
8
PC131 PC129
2
1U_0805_25V4Z PQ49
D
D
D
D
2
DAP202U_SOT323 4.7U_1210_25V6K 4.7U_1210_25V6K
IRF7811A_SO8
PD33
G
S
S
S
PR155
4
3
2
1
PQ50 2 1
1 D1 G1 8 +2.5V
1
2 7 PC132 20_0603_5% +2.5VP
2
+1.5V 3
4
D1 S1/D2
G2 S1/D2 6
5
1U_0603_10V6K
PR156
PC133 0.1U_0603_25V7K PL16
2.2H_SPC-1205P-2R2B_+40-20%
2
2
S2 S1/D2
1 2 2 1 1 2
+1.5VALWP SI4814DY_SO8
22
4
1
4700P_0603_50V7K PC134 PR157 PU17 0_0603_5% 1 PC135 1
5
6
7
8
1
2 1 2 1 1 2 25 21 PD34 220U_D2_4VM 1 1
VCC
UVP
V+
PL17 0_0603_5% BST1 VDD + + PD35
5UH_SPC-06704-5R0_2.9A_30% 0.1U_0603_25V7K 26 19 EC31QS04 + +
DH1 BST2
1
2
DH2
2
PD36 2 2 PC136
27 17
2
EP10QY03 + LX1 LX2 220U_D2_4VM2 2 @ 220U_D2_4VM
24 20 4
2
OUT1 OUT2
1
5.1K_0603_1% 14
3
2
1
FB2 PR159 PC141
2 FB1 ON2 12
2
7 15K_0603_1% 4700P_0603_50V7K
PGOOD
1
1
TON
1
PC142 PR160 1 2 11
10K_0603_1% <41> POK PR161 0_0603_5% ON1
ILIM2 13
2200P_0402_50V7K 3
SKIP
GND
OVP
REF
2
ILIM1
2 1 S Y SON S YSON <32,36,37>
2
1
PR162 0_0603_5%
1
PC143
23
10
MAX1845EEI_QSOP28 PR163
PR164 2200P_0402_50V7K
2
2 1 10K_0603_1%
2
42.2K_0603_1%
3 3
PR165
2 1
75K_0603_1%
1
PC144 PR166
PR167
0.22U_0805_16V7K 100K_0603_1% 100K_0603_1%
2
2.5V OCP > 13A
4 4
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 42 of 49
A B C D
5 4 3 2 1
+3VALWP +3VALWP
2
PR168
0_1206_5%
1
PR169
1
22K_0603_5% PR170
D 1 2 D
2
5.1_0603_5%
1
PC145
1
PC146
0.1U_0603_16V7K 4.7U_1206_16V4Z
2
2
PU18 +1.25VSP
1 8 PL18
VIN PVIN
2 GND LX 7 1 2
PR171 3 6
SD PGND 5UH_SPC-06704-5R0_2.9A_30%
+2.5VP 2 1 4 VREF VFB 5
1
105K_0603_1% CM3718_PSOP8 PR172
1 PQ52 1 2 + PC147
PC148 D 100K_0603_5% 220U_D2_4VM
1
1 2 1 2
2
PR174
G
1K_0603_5% 470P_0603_50V8J
105K_0603_0.5% 2N7002_SOT23
2
3
2
C C
1
2
D
PQ53 PR175
2N7002_SOT23 100K_0603_5%
1
G
S
2
PR176
<21,28,32,33,37> SUSP# 1 2 PR226
120W 90W 1 2 H_PROCHOT# <5>
0_0603_5%
64.9K_0603_1% 84.5K_0603_1% @ 1M_0603_1% VL
PR227
VS
1
PR229 249K_0603_1% 200K_0603_1%
D
1
PR223 PQ1
1
PC2
@47K_0603_1% @2N7002_SOT23
S
@ 0.1U_0603_25V7K
2
VS
8
PR227 PU6A
3
1 2 3 PD7
P
<32,40> ADP_I +
@ 84.5K_0603_1% 1 2 1
PR229 O
VL 1 2 2 -
G
B +2.5V @ 1SS355_SOD323 B
@ 200K_0603_1%
1
+SDREF @ LM393M_SO8
1
4
1
1
C42 PC1
0.1U_0603_50V4Z PC3
1
PR228 @ 10P_0603_50V8J
2
2 R72 @ 1000P_0603_50V7K
2
10K_0603_1%
8
U8A
P
1 -IN 2
R71 C47
G
1
C39 10K_0603_1% 0.1U_0603_16V7K
10U_1206_10V4Z LM358A_SO8 2 PR232
4
2 @ 200K_0603_1%
2
8
PU6B
5 PD8
P
R348 +
O 7 2 1
1
1 2 6 -
G
1
@ 1SS355_SOD323
@0_0603_5% PQ2 PR233
D
4
@ 100K_0603_1% @ LM393M_SO8
2
G
A @ 2N7002_SOT23 A
U8B
<38,40,41> P ACIN
2
<32,39> ALI/MH#
+IN 5
7 OUT
-IN 6
LM358A_SO8 Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 43 of 49
5 4 3 2 1
A B C D
1
PR177
2
Forward
2
PC150 PR178
1U_0603_10V6K 80.6K_0603_1%
2
2
PR179 PU2
1
PR181 @ 0_0603_5% 32 7 2 1
VCC RAMPS PR180 10K_0603_1%
1 2
1 39 VGATE <14,18,35>
<5> CPU_VID4
1
@ 0_0603_5% VID4 PGOOD
<5> CPU_VID3 2 VID3
<5> CPU_VID2 3 VID2
1
4 25 PWM1 <45>
<5> CPU_VID1 VID1 PWM1
PR182 5
<5> CPU_VID0 VID0 ISEN1+ <45>
@ 0_0603_5% 6 24
<5> CPU_VID5 VID12.5 ISEN1+
ISEN1- 23
34 ISEN1- <45>
<35> ENLL
2
ENLL
1 2 33 26 PWM2 <45>
<18> PM_DPRSLPVR DRSEN PWM2
PR183 0_0603_5%
27 ISEN2+ <45>
ISEN2+
<14,18> PM_STPCPU# 2 1 35 DSEN# ISEN2- 28
ISEN2- <45>
PR184 0_0603_5%
20 PWM3 <45>
PWM3
2
10 OCSET
PR185 21 ISEN3+ <45>
ISEN3+
2
PC151 ISEN3- 22 2
1
69.8K_0603_1% SOFT
PWM4 31 2 1 +5VALWP
357_0603_1% PR188 0_0603_5%
0.047U_0603_25V7M PC152 PR189
30
2
ISEN4+
9 DSV ISEN4- 29 2 1 1 2
Frequency Select
2200P_0603_50V7K 20K_0603_1%
PU12B PC153
1
+ 5 36 FS COMP 15 2 1
1
PR190 7
20.5K_0603_1% 0 22P_0603_50V7K
- 6
PC154 37 13
2
100P_0603_50V8J DRSV FB
2
PR193 17
PR194 100K_0603_1% VSEN
12 GND VRTN 18
2
10K_0603_1% @ 220P_0603_50V8J PR195 2.8K_0603_1%
+5VALWP
2
1
PC156 PH3 19 8 1 2
GND OFS
2
Place close to IC
1
1
PR196 ISL6247_MLFP40
2
@ 330KB_0402_5%_ERTJ0EV334J PR197 PQ54
1
2
2
@ 10K_0603_1% 1.2M_0603_5% 3 2N7002_SOT23
S
1
PR198 PC157
1
1
45.3K_0603_1% PR199 0.1U_0603_16V7K PC158 1 2 1
1
3 32.4K_0603_1% D 3
2
2 PR200 16.2K_0603_1%
1
2
G
1
Panasonic ERTJ0EV334J (0402)
2
2
PQ55 PR201 1U_0603_10V6K Remote
D
Locate this NTC resistor on PR202 5.1K_0603_1%
Sensing
2
PCB between phase 2 and 3 PR204
1
340K_0603_1% PR203 2 1
for thermal compensation. +CPU_CORE
1
27K_0603_5% 0_0603_5%
1
G
S
TP0610T_SOT23
D
1
2N7002_SOT23 PR205 @ 0_0603_5%
Place near +VCC_CORE
<35> VID_PW RGD PR206
output capacitor
G
1
S
2 1
+3VALWP PU5 PQ57
D
3
PR207 0_0603_5%
2 1 1 5 +1.2VP 2N7002_SOT23
IN OUT
1
PR209 2 PR208 1 VSSSENSE <5>
0_0603_5% 4 2 1
C
PG <4> BOOTSELECT
G
1
S
@ 0_0603_5%
1
PC159 3 2 22K_0603_5%
3
EN GND
1
4.7U_1206_16V4Z PC160
2
4.7U_1206_16V4Z PR210
2
E
MIC5258_SOT23-5 100K_0603_5% PQ58
2 1 MMBT3904_SOT23
<32> VR_ON
2
3
2
2
1 2 B+
+5VALWP
PL1 C8B BPH 853025_2P
5
6
7
8
5
6
7
8
1
PC162 PC163
PC161
PR234 PQ59 4.7U_1210_25V6K 4.7U_1210_25V6K 1
D
D
D
D
D
D
D
D
1 2 2 1
2
1
2.2_0603_1% IRF7811A_SO8 + PC164
PC165 220U_25V_M
0.22U_0805_16V7K
G
S
S
S
S
S
S
PQ60
2
4.7U_1210_25V6K 2
4
3
2
1
4
3
2
1
PU1 IRF7811A_SO8
6 VCC BOOT 2
1 PR213 1
5
6
7
8
5
6
7
8
PR214 0_0603_5% 4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE PQ61 PQ62
D
D
D
D
D
D
D
D
2
1
PR215 PC166 ISL6207CB-T_SO8 SI4362DY_SO8
499K_0603_1% PC168
PC167 SI4362DY_SO8 PD2
0.1U_0603_16V7K 1U_0805_25V4Z EC31QS04 2 1 2 1
1
G
S
S
S
S
S
S
PR217 32.4K_0603_1%
4
3
2
1
4
3
2
1
2
0.01U_0603_16V7K
CPU_DRIVE_EN
<44> ISEN1-
<44> ISEN1+ 2 1
CPU_B+ PH4 820B_0603_5%_ERAV33J821V
PC170
Local Transistor
PR235 Swtich Decoupling
1 2 1 2
5
6
7
8
5
6
7
8
2.2_0603_1% PQ63 PQ64
1
PC171 PC172
D
D
D
D
D
D
D
D
0.22U_0805_16V7K PC173
2 4.7U_1210_25V6K 4.7U_1210_25V6K 4.7U_1210_25V6K 2
2
G
G
S
S
S
S
S
S
PU3
6 2 IRF7811A_SO8 IRF7811A_SO8
4
3
2
1
4
3
2
1
VCC BOOT PR218
<44> PWM2 3 PWM UGATE 1 1 2
1_0603_1% PL3
7 EN PHASE 8 1 2
2
4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE
5
6
7
8
5
6
7
8
PC174
1
1U_0805_25V4Z ISL6207CB-T_SO8 PQ66
D
D
D
D
D
D
D
D
1
EC31QS04
PR220 SI4362DY_SO8 2 1 2 1 +CPU_CORE
G
S
S
S
S
S
S
499K_0603_1% PR221 32.4K_0603_1%
2
4 0.01U_0603_16V7K
3
2
1
4
3
2
1
1
1
PD6
EC31QS04
2
<44> ISEN2-
<44> ISEN2+ 2 1
PH5 820B_0603_5%_ERAV33J821V
3
CPU_B+ 3
PC177
PR236
1 2 1 2
5
6
7
8
5
6
7
8
2.2_0603_1%
0.22U_0805_16V7K
1
PQ67 PQ68
D
D
D
D
D
D
D
D
2
G
G
S
S
S
S
S
S
PU4
6 2 PR222
4
3
2
1
4
3
2
1
VCC BOOT
4 5 0.6U_HK_AE26A0R6_26A_25%
GND LGATE
2
5
6
7
8
5
6
7
8
PC181
PR224 ISL6207CB-T_SO8 PQ70 PD5
D
D
D
D
D
D
D
D
PR225 32.4K_0603_1%
PC182 SI4362DY_SO8
1
0.01U_0603_16V7K
G
G
S
S
S
S
S
S
1U_0805_25V4Z
1
4
3
2
1
4
3
2
1
4 4
<44> ISEN3-
<44> ISEN3+ 2 1
PH6 820B_0603_5%_ERAV33J821V
Local Transistor
Swtich Decoupling
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: ¬P 期三, 九月 24, 2003 Sheet 45 of 49
A B C D
REV 0.1
Date Page Description
04/10 21 Delete Power interface short line.
04/13 21, 22 Change Card Bus controller as one slote CB1410
11, 12 Swap RAM data signals.
04/16 29 Add EQ circuit
43 Add throutoling circuit.
26, 31 Add FIR and Remove SW DJ cicuit
04/24 17 Add R569 and R570 for Layout Request. Move Signal IRQE#~H# from RP92 to RP91 and del RP92.
14 CLK-GEN. pin 1(VDD_REF) and pin 46(VDD_CPU_0) change power plan as +3V_VDD. Suggestion from ICS
C249 and C251 change power plane as +3VDD
04/25 45 PL4 swap pin1 and pin2.
6 Change CPU Decoupling CAP. from 22U_1210_6.3V6M to 22U_1206_6.3V6M ( H=1.6 )
32 1. EC GPIO signal HDD_LED# move from pin114 to pin119.
2. Add signal PM_SLP_S1# on EC GPIO pin115.
28 Q44 for +5VCD change part name as U55
04/28 8 Del R73, cause it duplicate pull high.
27 Change C478 and C488 from 150U to 10U
36 Change R480 from 560K to 620K Ohm
4 Add R571 for BOOTSELECT
5 Add R573 for OPTIMIZED/COMPAT#
18 Add R572 for signal PM_DPRSLPVR
04/29 Rename from Layout
04/30 33 R73 0402 -> 0603 and C52 0805 -> 0603
16 C2, C5, C259, C3, C4, C6, C260, C261 and C262 Link CIS.
5 Thermal Sensor : Del R62, R61 8.2K-->200Ohm and power +5VS -> +3VS, C27 value 0.1U -> 1U, Sensor power rout direction : +3VS -> R61 -> C27.1 -> U6.1
17 Add Q40 and Q41, R517 and R518 for SMBus isolate solution.
05/01 8 Change CRT_HSYNC -> INTCRT_HSYNC and CRT_VSYNC -> INTCRT_VSYNC on MGCH terminal.
05/02 33 Remove dummy net on SUSP#.
16 R28, C277, C278 and C279 modify P/N for CIS link
17 C215 and C217 modify P/N for CIS link
22 C145 modify P/N for CIS link
20 Remove dummy net on XI
14 R83 and R94 modify P/N for CIS link
05/03 32 CP4 pin2 add connected to GND
05/05 42 PR151 pin1 SYSON signal --> MAINPWON
8 Swap U26.B6 (INTDDCDA) and U26.G9 (INTDDCCK) --> U26.B6 (INTDDCCK) and U26.G9 (INTDDCDA)
9 +SDREF circuit move to page 44
6 Modify Cap.s location same with Layout
14 Change R129 net from PM_SLP_S3# to PM_SLP_S1#
16 Add R519 and R520 for EC protect
05/06 20 EEDI_LAN --> EEDI_1394; EECK_LAN --> EECK_1394
27 Remove R26. Delete USBEN# and U3.3, U3.4, U32.3 and U32.4 connect to GND.
Delete R30, R279, R258 and R257.
Change C273, C284 and C646 220U -->150U.
42 PR151 pin1 SYSON signal --> POK; PU10 pin 11 output POK.
5 R324 size 0603 -> 0805
32 U24.175 ATF_INT# --> EC_THERM#
05/07 28 Add L42 between GND and AGND by EMI request.
17 R408, remove @ for Intel comment.
5 R56 60.4_0603_1% --> 51.1_0603_1%; R59 102_0603_1% -> 86.6_0603_1%
05/08 35 H19 GNDA -> GND; H31 GND -> GNDA
37 C242 0.01U -> 0.1U.
11 JP21 DDR-SO-DIMM link with CIS.
29 De-pop EQ components, add @ symbol on components.
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 46 of 49
REV 0.2
Date Page Description
05/12 35 Change H31 GND --> AGND and H19 AGND --> GND
37 R104 and R108 power plane changed, +3VALW --> +5VALW
05/29 40 Change PR100 47.5K-->95.3K
PR100 47.5K-->95.3K;PQ37,PQ38,PQ39 SI4835DY-->SI4825DY
PR79 0.015-->0.01; PR86 10K-->100K ;PR90 4.7K-->10K; PR88 29.4K-->33.2K
Add PR2 95.3K
38 Change PCN1 90W-->120W
20 U29 Pin 37 pull up with 4.7K Ohm --> U29 Pin 43
change X4 footprint same as X2
16 Add Protect circuit for EC (Add D42, D43 ,D44 and R521)
32 PWR_SUSP_LED# --> PWR_SUSP_LED
34 Add reverse circuit for PWR_SUSP_LED (Add Q43 and R522).
23 change Y2 footprint same as X2
36 change J1 ~ J6 footprint from JUMP_2MM to 2MM
05/30 35 Add H41 and change H13 H27 size.
06/02 38 Change PL14 value
39 Change PL13 value
45 Change PL1 value
40 Change PQ39 and PL11 value
11 Add R523, R524, R525 and R526, Del R515
12 Add R527, R528, R529 and R530
06/03 6 Delete C281, C287, C300, C309, C317, C324, C327 and C330.
06/05 34 Add C648 and C649 for EMI request
32 Add R531 and R532 for EC floating issue
8 Add R533 for DVO device detect
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 47 of 49
REV 0.3
Date Page Description
06/12 25 Swap IRQG#_MINI2 and IRQH#_MINI
06/30 30 Change sound resource, cause Headphone without EQ.
07/01 40 Modify PQ38 direction
28 Add regulator : Add Q44, Q45, Q46, D45 and R536 ~ R539.
Change C95, C129, C385, C386, C399, C404, C441, C422, C438 and C445 size : 0603 -> 0402.
29 Change R166, R357, R426, R435, R148, R173, R187, R347, R352, R432, R181 and R346 size
: 0603 -> 0402.
30 Change amplifier from TPA6011A4 to TPA0232.
Add R534, C651 and C650
Delete R202, R199, R434 and R442.
Change C563 1U to 0.47U
Change VR type from A-Curve to C-Curve.
Change C184, C212, C213, C219 size 0603 -> 0402.
14 R129 change net from PM_SLP_S1# to PM_SLP_S3#
Q13 : 2SC2411K --> 2N7002
R445 : 10K --> 0 Ohm
10 Change C491 size : 1210 -> 1206; Change C465 and C468 size : 1210 --> D type
35 Change SYS_PWROK control signal
25 SWAP PIRQG#_MINI and PIRQH#_MINI_2
07/09 14 U21 and R128 add '@', and R129 remove '@' CLK_PWD#.
26 U36, U37, C253 and C254 --> @; Add R541 and 542 --> 0 Ohm
28 Change Q44 --> U59; Add decoupling CAPs., C668 ~ C679.
35 Change H13 and H27 size
30 Change ESD diode type near speaker connector. Change D35 and D33 type, Del D34 and D32.
07/10 36 Change S4 resume function power plane +RTC_VCC -> RTCVREF
Add R543, C680 and C681
32 Add C682, reserve for PC97551.
07/16 5 R270 R271 R272 R267 R266 R16 R220 1K_0402_5% --> 10K_0402_5%
32, 8 Delete R412 R399 R369 R390 R485 R306
16 R304, R314, R317, R310, C318 1_0603_5% -> 1_0402_5%
18 R422 1_0603_5% -> 1_0402_5%
07/16 5 Add D46 and D47 for EMI solution
17 Add D48 for EMI solution
19 Add D49 for EMI solution
10 C491 C_1210 -> C_1206
30 MONO_IN GNDA --> GND
07/18 28 Delete L36, L19, L10 and L42
07/21 30 D33, D34 GND --> GNDA
07/22 35 H31 GNDA --> Non-PDH hole.
29 EQ-1 and EQ-2 GNDA --> GNDA-EQ
Add R544 for GNDA <-> GNDA-EQ
Add L44 L45 for EMI request GND <-> GNDA-EQ
28 Add L36, L19, L10 and L42 for EMI request GNDA <-> GND
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 48 of 49
REV 1.0
Date Page Description
08/04 28 Reserve C683, C684 and C685 for Audio noise issue
R370 --> @
C467 and C458 change as 0.1U for Audio noise issue
08/18 44 PC151 0.033U -->0.047U; PC152 1000P --> 2200P; Add PC153 22P
09/19 44 PR195 2.26K --> 2.8K
09/22 45 PR217 PR221 PR225 48.4K -->32.4K
Title
Compal Electronics, Ltd.
SCHEMATIC, M/B LA-1931
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 401264 1B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期三, 九月 24, 2003 Sheet 49 of 49