Curs MS

Content
Preface IX
Introduction XI
1. The Fundamental Equations of The Semiconductor Theory 1
1.1. Preliminary 1
1.1.1. Semiconductors Internal Structure 2
1.1.2. Electric Carriers in Semiconductors 3
1.1.3. Energy Bands Representation. Carriers 4
Concentration
1.2. The Fundamental Equations of the Semiconductor 7
Devices Theory
1.2.1. Currents Equations 8
1.2.2. Continuity Equations 9
1.2.3. The Fundamental Equations of the 10
Semiconductor Theory
Problems 11
2. P-N Diode 17
2.1. Preliminary 18
2.1.1. Structure and Symbol 18
2.1.2. Principle of Operation 19
2.1.3. Methods of Mathematical Description 21
2.2. Quasi-Static Large-Signal Behavior 22
2.2.1. Backgrounds 23
2.2.2. Ideal Diode Equation 23
2.2.3. Non-Ideal Diode Effects 35
2.2.4. Piecewise-Linear Models for P-N Diodes 41
2.2.5. "I-V" Characteristic. SPICE Model 42
2.3. Dynamic Large Signal Behavior 44
2.3.2. C-V Characteristic 45
2.3.3. SPICE Model 46
2.4. Quasi-Static Small-Signal Behavior 47
V
2.4.1. The Small-Signal Condition 47
2.4.2. Quasi-Static Small-Signal Parameters 50
2.4.3. Quasi-Static Small-Signal Model 50
2.5. Dynamic Small-Signal Behavior 51
2.5.2. Dynamic Small-Signal Model 51
2.6. Classes of Diodes 52
2.6.1. Rectifier Diode 53
2.6.2. Zener Diode 53
2.6.3. Varactor Diode 54
2.6.4. PIN Diode 54
2.6.5. Step Recovery Diode 55
Problems 56
3. Circuit Applications of P-N Diodes 63
3.1. By Hand Large-Signal Analysis 64

3.1.1. Algorithm Presentation 64
3.1.2. Example 65
3.2. By Hand Small-Signal Analysis 67
3.2.1. Algorithm Presentation 68
3.2.2. Example 68
3.3. Rectifiers 72
3.3.1. Half-Wave Rectifier 73
3.3.2. Full-Wave Rectifier 77
3.3.3. Filtering 81
3.3.4. Split Rectifier 85
3.3.5. Voltage Multipliers 86
3.4. Clipping Circuits 88
3.4.1. Clipping-down Circuits 89
3.4.2. Clipping-up Circuits 92
3.5. Clamping Circuits 94
Problems 96
4. Bipolar Junction Transistor 115
4.1. Preliminary 116

4.2.1. Ebers-Moll Models 126
4.2.2. Ebers-Moll SPICE Models 135
4.2.3. Non-Ideal Effects 138
VI
4.2.4. I-V Characteristics for Common Emitter 144
Connection
4.2.5. I-V Characteristics for Common Base 145
Connection
4.2.6. Piecewise Linear Models for Active Mode 146
4.3.1. Charge-Control Model 148
4.3.2. Gummel-Poon SPICE Model 154
4.4.1. Conductances Model 162
4.4.2. Hybrid- π Model. SPICE Model 164
4.4.3. H-Parameter Model 165
4.5.1. Hybrid π Model. SPICE Model 165
4.5.2. Cut-off Frequency 167
4.6. Cut-off Frequency 171
4.6.1. Quiescent point 171
4.6.2. Usual Biasing Circuit 172
Problems 179
5. The Fundamental Bipolar Transistor Circuits 197
5.1. The Common Emitter Connection 198

5.1.1. Common Emitter Amplifier 200
5.1.2. Common Emitter Inverter 208
5.2. The Common Collector Connection 210
5.3. The Common Base Connection 221
5.4. By Hand Large-Signal Analysis 228
5.5. By Hand Small-Signal Analysis 231
Problems 236
6. The Field Effect Transistors 253
6.1. Preliminary 254

6.2.1. Currents Derivation 266
6.2.2. Non-Ideal Effects 272
6.2.3. "I-V" Characteristics 273
6.2.4. Approximate Quasi-Static Large-Signal Models 276
6.2.5. SPICE Models 278
VII
6.4.2. Simplified Models 287
6.5.2. Simplified Models 289
6.6. D.C. Biasing 289
6.6.1. Quiescent Point Positioning 289
6.6.2. Quiescent Point Stabilization 290
6.6.3. Usual Biasing Circuit 291
Problems 299
7. The Fundamental Field Effect Transistor Circuits 323
7.1. The Common Source Connection 324

7.1.1. Common Source Amplifier 328
7.1.2. Common Source Inverter 333
7.2. The Common Drain Connection 333
7.3. The Common Grill Connection 342
7.4. FET Incremental Resistances 348
7.4.1. Resistance Seen Looking into the Grill 348
7.4.2. Resistance Seen Looking into the Source 349
7.4.3. Resistance Seen Looking into the Drain 350
Problems 352
References 365
VIII
Preface
The aim of this book is to offer the essential tools for the circuit analyst.
Generally specking, the electronic circuits may be treated as electric circuits,
and by consequence, the whole mathematical construction dealing with
electrical circuit theory may be applied to the electronic circuit analysis. In fact,
this is the way followed by the automatic calculation. In the same time, it must
be said that, in many cases - practical situation - by hand analysis is useful. For
such situation approximate model devices must be developed. In truth, the
more complex model is the more accurate analysis is. That is why the central
point of this book is the electrical model concept, because of the device
modeling process. The models are developed according to the electrical
regime of the operation, and more, the essential techniques used in the circuit
analysis theory related to these models are exposed. Both the so-called "by
hand" and computer analysis (SPICE) is presented. In fact, the SPICE
simulation is used in order to validate by hand analysis.
The book covers the principal devices such as: p-n junction, bipolar transistor
and field effect transistor. The approaches used for modeling procedure are the
classical ones. The large signal models are derived starting from the
fundamental semiconductor equations. The small signal models are derived
using linearisation techniques. In the same time, it must be added that for
quasi-static large signal regime the piece wise linear models are exposed.
Last but not least, the book contains a number of applications that covers the
theoretical approach. These applications are presented at the end of each
chapter. For each application at least one possible solution is presented. When
more than one solution is presented, a correlation among them is exposed.
In closing, it must be said that the book is addressed to the electrical
engineering students, but the models derived for quasi-static regimes are also
useful for the students from other engineering fields.
Hoping that the readers will find this book useful, the author wants to thank his
daughter and his wife for the support they offered.
Author
IX
X
Introduction
Generally, three steps must be followed in the electronic circuit analysis:

1. Modeling of electronic devices. At this step, the electronic device is
replaced by its model. The electronic circuit becomes an electrical
circuit. This new circuit is usually named modeled circuit. One says that
electronic problem is reduced to an electrical problem.
2. The modeled circuit is analyzed according to the operation regime with
the convenient technique (Kirchhoff, Laplace, etc…). One obtains a
system of equations. One says that electrical problem is reduced to an
algebraic problem
3. One solves the algebraic problem
Two observations must be made:
The electronic device model must be chosen according to the
operating conditions.
The complexity of the electronic device model must be chosen
according to the level of approximation required by the purpose of the
analysis.
Mathematical Model; Electrical Model
The present book exemplifies this approach for the p-n diodes, bipolar
transistors and field effect transistors. The modeling process is focused on the
two important directions:
the developing of a mathematical model,
the deriving of an electrical model (the equivalent circuit diagram).
A mathematical model - in general - may be found starting from the from the
fundamental semiconductor equations or from the electrical characteristics of
the device. In this book the large signal models - except the piece-wise linear
models - are treated using the first way, while the small signal models are
derived through the linerisation of the large signal characteristics. The
mathematical model is represented by a system of equations whose dimension
is strictly linked with the number of the terminals of the device. Because this
book deals with classical devices (diodes and transistors), only two and three
terminals are mentioned in the following:
XI
Two Terminals Device; one and only one equation is necessary to describe
completely this type of device.
symbol is presented in figure 1. v
where: i
D
i the current through the device
v the drop voltage across the device Figure 1
D the device
description;
The equation follows the form of the equation numbered (1) and is
called "characteristics equation".
 di dn i dv dmv 
E ∫ idt , i , , K , n , v , ,K , m , θ1, K , θp  = 0 (1)
 dt dt dt dt 
 
where:
θ1, K, θp non-electric parameters.
Three Terminals Device; only two "characteristics equations" are needed in

order to describe completely this type of device.
The electrical model was found interpreting the mathematical equations. The
approach used is presented in the following: The expression numbered (1)
presents the general form of a typical equation of the mathematical model.
Starting from this equation three observations may be made:
1. For resistors this equation becomes:
( )
E i ,v = 0 (2)
and for linear resistors:

v=const × i (3)
and "const" is the resistance ("R")
2. For bobbins (1) becomes:
 di 
E ,v = 0 (4)
 dt 
In the case of linear bobbins:
di
v = const. × (5)
dt
and the "const." is the inductance ("L").
3. For capacitors (1) becomes:
XII
 dv 
E i ,  = 0 (6)
 dt 
and linear capacitors:
dv
i = const. × (7)
dt
where "const" is the capacitance (C)
Regime of Operation
The equation numbered (1) is very general. In real applications it may be
simplified having in mind two criteria:
1. the speed of the signal variation, and
2. the magnitude of these variations.
According to the first criterion three important regimes of operation are defined:
Static Regime (DC regime); The signals are constant. All the derivates from
(1) must equal zero. It becomes:
E ( i , v , θ1,K, θp ) = 0 (8)
Quasi-Static Regime (low frequency regime); Due to the small speed of the
signal variation all the signals the derivates from (1) may be approximated as
zero. The mathematical description of this regime of operation is given by
characteristic equations similar to (8).
Dynamic Regime (high frequency regime); in this case the speed of variation
for the signal is very high. The equations follow the form presented by (1).
Even in this case, some more simplification may be made. If the speed of
variation is not enough high, only the first order derivates may be taken into
account. In these conditions (1) becomes:
 di dv 
E i , , v , , θ1,K, θp  = 0 (9)
 dt dt 
This book treats this case.
According to the second criterion two important regimes of operation are
defined:
Small Signal Regime. The signal variations are so small that the non-linear
behavior of the device becomes insignificant.
Large Signal Regime. The signal variations are high enough to emphasize the
non-linear behavior of the device.
The Outline of the Book
The book has seven chapters as follows:
XIII
First chapter presents the fundamental equations of the semiconductor
theory. It has two sections. The first section treats the intrinsic and
extrinsic conduction using The Energy Band Approach. In the
following, Fermi Level is defined and, therefore, the charge carriers
distribution is calculated. Based on these facts, in the second section
the field current equations, the diffusion current equations and the
continuity equations are derived. Finally, a complete system of seven
equations is presented.
The second chapter is dedicated to pn diode. It has six sections. The
first one, whose title is “Preliminary”, presents structure, symbol and
the principle of operation. The second section is dedicated to quasi-
static large signal behavior of p-n diode. The seven-equation system,
mentioned above, is integrated in quasi-static conditions and the “I-V
characteristic” is developed (current related to voltage). Starting from
this representation, some approximate diode models are presented.
The third section develops mathematical and electrical models for
dynamic large signal conditions. Both Q-V and C-V characteristics are
derived. The fourth section presents quasi-static small-signal model.
The models are derived using Taylor approximation. The small signal
condition for p-n junction is also developed. The next section
introduces dynamic small-signal models. This time capacitive effects
are considered. In closing, a classification - according to the
operational regime - is made.
The third chapter deals with typical diode circuits. The first two sections
present by hand analysis techniques. Both large-signal analysis and
small-signal analysis are exposed. The sections numbered three four
and five treats rectification circuits (half-wave rectifier, full-wave
rectifier, filtering power supply, split power supply, voltage multiplier),
clipping circuit and clamping circuits.
The fourth chapter is dedicated to bipolar transistor. The first section,
whose title is “Preliminary”, presents structure, symbol, the principle of
operation and methods of mathematical description related to the
operation regime. The second section is dedicated to quasi-static large
signal behavior of bipolar transistor. The fundamental semiconductor
equations are integrated in quasi-static conditions and Ebers-Moll
models (including SPICE model) are developed. In addition, non-ideal
effects such as: series resistance, high injection, generation-
recombination phenomenon, base-width modulation, junction
breakdown, temperature dependence and thermal run-away are
treated. In the following, “I-V characteristics” both for common emitter
connection and for common base connection are presented. Finally,
piecewise linear models for active model are derived. The third section
develops mathematical and electrical models for dynamic large signal
conditions. One discusses about charge control models. Gummel-Poon
XIV
SPICE model is also presented. The fourth section presents quasi-
static small-signal model. Three different models are showed:
conductances model, hybrid π model, or fundamental models (and
SPICE model as a consequence) and in closing, ‘h”-parameter model.
The fifth section introduces dynamic small-signal models. The dynamic
small signal model presented in this section completes the hybrid
model by adding the capacitive effects. Estimation for cut-off frequency
is also presented. The sixth section is dedicated to DC bias circuits.
One defines quiescent point and a usual biasing circuit is treated.
The fifth chapter treats the fundamental bipolar transistor circuits. The
first section is dedicated to common emitter connection. The second
section presents the common collector connection. The third section
analyses the common base connection. For each circuit transfer
characteristic is developed and, based on it, amplification and
commutation applications are presented. For amplification circuits,
voltage gain, input and output resistances are computed. The
frequency response is also treated. Finally, the fourth section presents
an analysis technique dedicated to DC regime. This technique uses
first order approximation model for the transistor. The fifth section
exposes a procedure for evaluation of the incremental resistaces of the
transistor. The incremental resistances are useful for the small signal
analysis.
The field effect transistors are presented in the sixth chapter. Following
the pattern of the presentation from the second and fourth chapters, the
first section of this chapter presents structure, symbol, the principle of
operation and methods of mathematical description related to the
operation regime. In the following the second section is dedicated to
quasi-static large signal behavior of the junction field effect transistor.
The expression for drain current is derived for all types of field effect
transistor. In addition, non-ideal effects such as: effective channel
length, channel length modulation, parasitic resistances, body effect
and junction breakdown are treated. In the following, “I-V
characteristics” are presented. From these characteristics, some
approximate models are derived. Finally SPICE models are exposed.
dynamic large signal conditions. One considers the effects of the
parasitic capacitors. SPICE model is presented. The fourth section
presents quasi-static small-signal model. Both SPICE models and
simplified models are presented. The fifth section introduces dynamic
small-signal models. This section treats also SPICE models and
simplified models useful for by hand analysis. The sixth section is
dedicated to DC bias circuits. One defines quiescent point and a usual
biasing circuit is treated.
XV
In closing the seventh chapter deals with the fundamental application
of the field effect transistors. The first section is dedicated to common
source connection. The second section presents the common drain
connection. The third section analyses the common grill connection.
For each of these circuits the transfer characteristic is developed and
based on it, amplification and commutation applications are presented.
For amplification circuit, voltage gain, input and output resistances are
computed. The frequency response is also treated. In addition for the
common drain connection the behavior of the input impedance in
respect with the frequency is treated. The fourth section is dedicate to
FET,s incremental resistances.
XVI
• Preliminary
• Fundamental Equations of The
Semiconductor Devices Theory
Chapter 1
The Fundamental Equations of
the Semiconductor Theory
In the "Introduction" was pointed out that the aim of the Semiconductor Devices
Theory is the developing of different mathematical models – and subsequently
circuit models – for electronic devices in different functional duties. Generally
speaking, the start point of any approach to device modeling is the physical
phenomenon. That’s why the Fundamental Equations of Semiconductor
Devices must be discussed first. Taking into account that these equations give
emphasis to electric field – or electric potential – related to internal structure of
the semiconductor, the outline of this chapter will be:
The first chapter is entitled "Preliminary". The intrinsic and extrinsic
conduction are described according to Energy Band Approach. Fermi
Level is defined and, therefore, the charge carriers distribution is
calculated.
The second chapter deals with the field current equations, the diffusion
current equations and the continuity equations. Finally, a complete
system of seven equations is presented.
1.1 Preliminary
The semiconductors are usually defined as materials whose conductibility is

between the isolators (air, ceramics, wood, rubber, etc.) and conductors
(copper, silver, salt water, etc.). Keeping in mind that electric conduction is a
quantum phenomenon defined as ordered movement of electric carriers under
17
Device Modeling for Circuit Analysis
certain forces, becomes obvious that the present analysis must be focused on
two topics:
movable electric carriers and their statistic;
forces able to flow movable electric carriers.
So, in this chapter, it will be discussed:
1. Semiconductors internal structure;
2. Electric carriers in semiconductors;
3. Energy band representation. Carriers concentration.
The analysis will be focused on silicon – a tetra-valent semiconductor – widely
used in semiconductor devices.
1.1.1 Semiconductors Internal Structure
From the very beginning, it must be reminded that semiconductors are crystals
and by consequence they present a crystal lattice structure. As it is well known,
the semiconductor technologies use mostly impure semiconductors, the so-
called doped semiconductors. From this point of view, one can discuss about:
intrinsic (pure) semiconductor;
extrinsic (impure) semiconductor; according to the valence of the
substance use for impurification, one can discuss also about:
• n-type semiconductor;
• p-type semiconductor
For a better understanding of the conduction phenomenon in semiconductor
substances, it is necessary to analyze both intrinsic and extrinsic
semiconductors internal structure.
a.) Intrinsic semiconductor. Figure 1.1 presents the simplified structure of
silicon. One can observe that positive ions are joined together with two parallel
+4 +4 +4
Positiv Ion
Electron
+4 +4 +4
Covalent
bond
+4 +4 +4
Figure 1.1
lines – covalent bonds. The electrons that form this covalent bond are valence
18
The Fundamental Equations of the
electrons. So, each atom of silicon is bounded by four neighboring electrons

and shares four electrons with them.
b.) Extrinsic semiconductor. As it has been said, there are two classes of
doted semiconductors. Figure 1.2 presents such structures:
+4 +4 +4 +4 +4 +4
Extra Positiv Ion Positiv Ion

Electron
Electron Hole Electron
+4 +5 +4 +4 +3 +4
Covalent Covalent
bond bond
+4 +4 +4 +4 +4 +4
Figure 1.2
One can observe that:

N-type semiconductor;. A silicon atom was replaced with a penta-
valent atom (phosphorus and arsenic). An "extra-electron" appeared.
P-type semiconductor; A silicon atom was replaced with a trivalent
atom (boron). A "lack-electron" appeared. From now on this lack-
electron will be referred as "hole". It will be considered as an electric
carrier with unity positive charge.
1.1.2. Electric Carriers in Semiconductors
As a consequence of the above discussion, one can identify the electrical
charge carriers in semiconductors:
fixed carriers:
- positive ions
- negative ions
free charges
- electrons
- holes
Some observations must be made:
1. The semiconductor conductibility approach deals with two types of
free electric charges.
2. According to this approach, both electrons and holes are fictive
particles. They are useful to simplify the theoretical representations.
19
1.1.3. Energy Bands Representation. Carriers Concentration

Intrinsic semiconductor. Figure 1.3 presents energy diagram for intrinsic
silicon.
In fact, only the last two bands are represented: conduction band and valence
band.
Energy
e
conduction band
F(E)
bandgap
valence band
Figure 1.3
Where:
1
F(E ) = (1.1)
 E − EF 
1 + exp  
 kT 
and: k Boltzman constant
EF Fermi Level – the probability to find an electron with this
energy level is 0.5
T absolute temperature
0
At T=0 K there is no free electron because they are kept by the parent atom.
This statement is correct for both intrinsic and extrinsic semiconductors. At
higher temperatures, lattice vibration will cause breaking of some covalent
bones. Free electrons and in the same time free holes will be generated, thus
enabling electric current to flow. This process is referred as generation -
recombination process and is presented in figure 1.4.
Energy
electron
e
conduction band
F(E)
bandgap
valence band
hole
Figure 1.4
20
One can observe:

in the conduction band there are electrons;
in the valence band there are holes.
According to Fermi-Dirac statistic the concentration of electrons and holes is:
 E − EF 
n 0 = NC exp − C  (1.2)
 kT 
 E − EC 
p 0 = N V exp − F  (1.3)
 kT 
where: no electrons concentration in steady-state condition
po holes concentration in steady-state condition
NC constant (it depends of temperature according to 3/2 law).
NV constant (it depends of temperature according to 3/2 law).
There is also another possibility to rewrite no and po expressions:
 E − Ei 
n 0 = n i exp − F  (1.4)
 kT 
 E − EF 
p 0 = n i exp − i  (1.5)
 kT 
with:
E C − E V kT N C
Ei = − + ln (1.6)
2 2 NV
ni2 = n 0 p 0 (1.7)
where ni represents the so called intrinsic concentration. For unstationary
situations, (1.2.) and (1.3.) becomes:
 E − Ei 
n = n i exp − Fn  (1.8)
 kT 
 Ei − EFp 
p = n i exp −  (1.9)
 kT 
with: EFn Fermi quasi-level for electrons;
EFp Fermi quasi-level for holes.
Extrinsic semiconductors.
N-type semiconductor; Figure 1.5 presents the energy band representation for
a n-type semiconductor. One can observe that penta-valent impurity introduces
a new energy level (noted ND in the figure). This level is in the neighborhood of
0
the conduction band. At 0 K the extra-electrons are kept by the parent atoms. If
the temperature is increased, the crystal lattice will vibrate. Therefore, the
extra-electrons will jump in the conduction band enabling the electric current.
At room temperature, the concentration of electrons in the conduction band is
21
equal to the concentration of the atoms of the impurity. Because this kind of
impurities generates electrons in the conduction band, they are referred as
donor impurities.
Energy
e electron
F(E) conduction band
ND bandgap
valence band
Figure 1.5
P-type semiconductor; Figure 1.6 presents the energy band representation for a
p-type semiconductor. One can observe that trivalent impurity introduces also a
new energy level (noted NA in the figure). This time, the energy level
corresponding to the impurity is in the neighborhood of the valence band. If the
temperature is increased, because the gap between the top of the valence
band the impurity level is small, the silicon valence electron will jump on this
new free level.
Therefore, holes will appear in the valence band, enabling the electric current.
At room temperature, the concentration of holes in the valence band is equal to
the concentration of the atoms of the impurity. Because this kind of impurities
generates holes in the valence band, they are referred as acceptor impurities.
Energy
e
conduction band
hole
NA bandgap
F(E)
valence band
Figure 1.6
The concentration of the mobile carriers in an extrinsic semiconductor.

The calculus of the concentration of the electric carriers must be made taking
into account the concentrations of the impurities. Let's denote:
NA concentration of atoms of acceptor impurity, and
ND concentration of atoms of donor impurity
22
At room temperature, all atoms of impurities are ionized. By consequence, the

neutrality condition is:
po-no+ND-NA=0 (1.10)
Equations (1.10) and (1.7) form a system of two equations with two unknowns
(n0, p0) that must be solved. It must be said that the solutions for n-type,
respectively p-type semiconductors are interesting. So:
N-type semiconductor The impurities concentrations must respect the following
conditions:
ND>>ni (1.11)
NA=0 (1.12)
Under these circumstances, one obtains:
no=ND (1.13)
n i2
p0 ≅ (1.14)
ND
P-type semiconductor In this case the impurities concentrations must respect

the following conditions:
NA>>ni (1.15)
ND=0 (1.16)
and by consequence :
po=NA (1.17)
n i2
n0 ≅ (1.18)
NA
1.2 The Fundamental Equations of The

The central problem of the semiconductor theory is to determine the current

that flows in a certain semiconductor structure, for definite conditions.
Generally speaking, two factors may cause current flow:
electric field that generates the so called field current or drift current,
and
gradient of concentration impurities that generates diffusion current
23
This chapter will fill out the equations that describe these connections. The
outline will be:
1. Currents equations. Both field and diffusion equations will be derived
2. Continuity equations
3. The fundamental equations of the semiconductor theory
The one-dimensional approach will be presented.
1.2.1. Currents Equations
a.) Field currents. According to Ohm's law:
j=σE (1.19)
where:
j current density
σ conductibility
E electric field
For σ one can find the expression:
σ=q(µpp+µnn) (1.20)
and:
q elementary charge;
µp holes mobility;
µn electrons mobility.
Introducing (1.20) in (1.19), the expression of the density of current becomes:
j= q(µpp+µnn)E (1.21)
Keeping in mind that:
j=jn+jp (1.22)
with:
jn holes current density;
jp electrons current density.
From (1.21) and (1.22) one can write:
jn= qµnnE (1.23)
jp= qµppE (1.24)
b.) Diffusion currents. The usual approach is based on Fick's Laws. So, the
density of diffusion current for electrons becomes:
∂n
jnd = qDn (1.25)
∂x
and for holes:
24
∂p
jpd = qDp (1.26)
∂x
where:
j nd electrons current density according to the diffusion theory
j pd holes current density according to the diffusion theory
and:
kT
Dn = µn (1.27)
q
kT
Dp = µp (1.28)
q
are Einstein's relations.
c.) Currents equations. Now one can derive the complete equations for the
current:
Electrons current. From (1.23) and (1.25) results:
∂n
jn = qµ n nE + qDn (1.29)
∂x
Holes current. From (1.24) and (1.26)
∂p
j p = qµ p pE − qD p (1.30)
∂x
The total current is represented by the sum of these two components.
j = jn + j p (1.31)
According to Maxwell's equations one more term must be added: the
deplacement current. Finally, one obtains:
∂E
j = jn + j p + ε (1.32)
∂t
1.2.2. Continuity Equations
The analysis presented above considered that the variation of the free charge
concentration is due only to the variation of the impurity concentration. In fact,
there are three different causes:
1. External factors; They provoke the generation phenomenon. There
are two types of mechanisms:
electron generation – an electron jumps from donor level to
conduction band;
25
hole generation – an electron jumps from valence band to

acceptor level
2. External factors; They provoke also the generation phenomenon
but the mechanisms are different. The simpler is represented by
the jumps of the electrons between the valence and the conduction
bands.
3. Transport phenomena. It was just discussed.
The equations that relate the time variation of the free electric carrier
concentration to the generation-recombination phenomenon are generally
referred as continuity equations. These equations may be written as:
∂n n − no 1 ∂jn
=− + (1.33)
∂t τn q ∂x
∂p p − p o 1 ∂jp
=− + (1.34)
∂t τp q ∂x
where:
τn electrons time-life
τp holes time-life
1.2.3 The Fundamental Equations of the Semiconductor
Theory
There are six equations. These equations are:
Current equations:
∂n
jn= qµnnE +qDn (1.35)
∂x
∂p
jp= qµppE −qDp (1.36)
∂x
∂E
j = jn + j p + ε (1.37)
∂t
Continuity equations:
∂n n − no 1 ∂jn
=− + (1.38)
∂t τn q ∂x
∂p p − po 1 ∂jp
=− + (1.39)
∂t τp q ∂x
Poisson equation:
∂ 2V q
2
= − (p − n + ND* − N*A ) (1.40)
∂t ε
26
where V (electric potential) is defined by:

∂V
E=− (1.41).
∂x
27
Problems
Problem 1. This problem is regarding the atom concentration in pure Si. Find
3
the number of atoms existing in 1dm of Si and Ge. Si density is: 2330 Kg m3
and Ge density is 5350 Kg m3 .
Solution The relation between Avogadro number and the atoms concentration
is:
A
NA = na (1)
ρ
where:
 moleculs 
NA = 6.02 × 1023  , Avogadro number;
 mol × g 
 atoms number 
na   atoms concentration;
 m3 
 Kg 
ρ  3 density;
m 
A atomic mass
One finds:
28 -3
nSi= 5 × 10 dm
28 -3
nGe= 4.41 × 10 dm
Problem 2 This problem is regarding the free electron and hole concentration in
3 0
pure Si. Find the number of free electrons existing in 1m of Si, at T=300 K
(room temperature).
Solution The number of free electrons in a semiconductor is given by:
3
n0 =2
(2πkTm e ) 2  E − EF 
exp − c  (2)
8 π2 h 3  kT 
p 0 = n0
where:
n0 electron concentration at thermal equilibrium;
k Boltzman constant
me effective mass of electron;
28
h Plank constant “h”, divided by π

The result is:
16 -3
n0=p0=1.5 × 10 cm
Problem 3 This problem is regarding the free electron and hole concentration in
3
doped Si. Find the number of free electrons and holes existing in 1m of Si,
18 -3 10 -3
doped with NA=10 cm , at room temperature. Assume that ni=10 cm .
Solution:
18 -3
p ≅ NA =10 cm (3)
n2
n≅ i =
(
1010 )
2
= 102 cm−3 (4)

NA 1018
Problem 4 This problem is regarding the resistivity of pure Si. Find the intrinsic
cm2 cm2
resistively of Is at 3000K. Assume that: µn = 800 , µp = 300 ,
V V
ni = 1010 cm−3
Solution
σ = e(nµn + pµp ) (5)
n=p=ni (6)
1
ρ= (7)
σ
Solving the system one determines: ρ = 231 Ωcm
Problem 5 This problem is regarding the resistivity of doped Si. Find the
18 -3
resistivity of a piece of Si doped with NA=10 cm , at room temperature.
Solution Electron and hole concentration is calculated in problem 3. These
results must be introduced in (5) and the outcome in (6). One finds:
ρ ≈ 0.1 Ωcm
Problem 6 This problem is regarding the current equations. The hole

concentration into a semiconductor is presented in figure 1. Sketch hole current
assuming that no external electric field is applied.
29
p(x) jp (x)
p(0) − p 0
p(0) qDp
W
p0
0 w x 0 w x
Figure 1 Figure 2
Solution:
Hole current due to hole distribution is:
dp( x )
jp ( x ) = −qDp (8)
dx
Hole distribution according to figure 1 is:
 p(0) − p0
 p(0) − x if x<w
p( x ) =  w (9)
p0 if x≥w
Replacing (9) in (8) one obtains:
 p(0) − p0
 qD if x<w
ip ( x ) =  p w (10)
0 if x≥w
Figure 2 shows this solution.
Problem 7 This problem is regarding the electric field calculation. Find the
internal electric field into a semiconductor whose internal distribution of holes
respects conditions from figure 1, assuming that j p(x) =0.
Solution:
From (1.36) equation follows:
dp( x ) dp( x )
Dp
dx = kT dx
E= (11)
µp p( x ) q p( x )
Replacing (9) in (11):
30
 p(0) − p0
 kT w
− if x<w
E( x ) =  q p(0 ) − p0 (12)
 p(0) − x
w
0 if x≥w

Figure 3 displays this solution:
jp (x)
E(x)
0 w x p(0) − p 0
qDp
W
0 w x
Figure 3 Figure 4
Problem 8 This problem is regarding the drop voltage field calculation. Find the
drop voltage between the points x=0 and x=w of the structure presented in
p(0)
problem 6. Assume that = 103 .
p0
Solution:
The relation electric field and drop voltage is:
B
VAB = ∫ E( x )dx (13)
A
Replacing (12) in (13) one finds:

p(0 ) − p0
W
kT w
V0 w = ∫− dx = 180 mV (14)
q p(0) − p 0
0 p(0) − x
w
31
• Preliminary
• Quasi-static Large Signal Behavior
• Dynamic Large Signal Behavior
• Quasi-Static Small Signal Behavior
• Dynamic Small Signal Behavior
• Classes of Diodes
Chapter 2
P-N Diode
The term diode refers - historically speaking - to those vacuum tubes, with two
electrodes: cathode and anode used for rectifying alternative current. The term
“p-n diode” refers to semiconductor diodes constructed using p-n junctions. This
chapter deals with this type of diodes. Being structured into seven sections, the
outline of its content is:
The first section whose title is “Preliminary” presents structure, symbol
the principle of operation and general methods of mathematical
description related to the regime of operation;
The second section is dedicated to quasi-static large signal behavior of
p-n diode. The seven-equation system (1.35) ÷ (1.41) is integrated in
quasi-static conditions and the “I-V characteristic” is developed (current
related to voltage). Starting from this representation, some
approximate diode models are presented.
dynamic large signal conditions. Both Q-V and C-V characteristics are
derived.
The fourth section presents quasi-static small-signal model. The small
signal condition for p-n junction is also developed
The fifth section introduces dynamic small-signal models
The sixth section presents some usual types of diodes
2.1 Preliminary
This section treats:

1. Structure and symbol;
2. Principle of operation
31
3. Methods of mathematical description related to the regime of

operation;
2.1.1 Structure and Symbol
The structure of a p-n diode is the structure of a p-n junction. Figure 2.1
presents such a structure.
metallurgical
junction
anode cathode
p ≅ NA n ≅ ND
Figure 2.1
Figure 2.2 shows the electrical symbol of a diode,
vA
A C
iA
Figure 2.2
where:
A anode
C cathode
vA diode voltage drop (total instantaneous value)
iA current through the diode (total instantaneous value)
One can see that a p-n junction consists of two adjacent semiconductor regions
Aj Cathode
SiO2
Epitaxial n+
growth
aprox. p
Substrate p+
aprox.100µm
Metal
Anode
Figure 2.3
32
P-N Diode
of opposite type. The region on the left is p-type with NA acceptor density. The
right region is n-type with ND donor density.
The contact to p-type region is called anode, and the contact to n-type region is
called cathode.
Figure 2.3 shows the composition of a diode. One can observe that a p-n
junction is fabricated from a single slice of semiconductor. Cathode is diffused
into p-type epitaxial layer grown on a p-substrate (the anode).
2.1.2 Principle of Operation
The goal of this section is to present a simple explanation of the so-called
diode effect – the unilateral conduction. Basically, in a diode the current flows
from anode to cathode. This manifestation seems to be a little bit unusual,
because both in p-type semiconductor region and in n-type semiconductor
region, the current flows in any
direction. Which is the phenomenon that E
does not allow the current flowing in any ---- +++++
---- +++++
p n
direction through a p-n junction? ---- +++++
---- +++++
---- +++++
Figures 2.4, 2.5 and 2.6 may be useful
for the explanation. Figures 2.4 show
p-type neutral transition p-type neutral
the p-n structure in condition of thermal region region region
equilibrium. One can observe the
existence of three regions: the p-type
quasi-neutral region, the transition Figure 2.4 a
region and the n-type quasi-neutral ρv
region. The reason why these regions -lpo +qND
exist is the strong variation of the
impurity density nearby the junction. As -qNA
+lno
a consequence of diffusion
phenomenon, the electrons from n-type
Figure 2.4 b;
region are pushed into p-type region
and holes from p-type region to n-type E
region. Taking into account that both -l po +l no
holes and electrons are electric charges,
an electric field appears. The diffusion
phenomenon is stopped when electric
forces equal diffusion forces. So, the Figure 2.4 c;
electrons and holes distribution is
disturbed only nearby metallurgical v
distribution. This domain is called
transition region. The most important Φ BO
characteristic of this region is the lack of
-lpo +lno
mobile charge carriers. That’s why this
region is sometimes referred as
depletion region. The technical Figure 2.4 d
33
literature recommends also the denomination of space charge region for this
domain, because of the presence of positive and negative ions in crystal lattice.
The existence of these ions is the direct consequence of electrons or holes
migration.
Figure 2.4a, emphasizes these meanings. The sign “+” denotes positive ion
and the sign “-“ denotes negative ion. Figure 2.4b shows the charge distribution
due to these ions. Figure 2.4c presents the electric field distribution generated
by the charge distribution. Figure 2.4d E
exposes the potential distribution ---- +++++
---- +++++
produced by electric field. Φ B is 0
p ---- +++++
n
---- +++++
generally designated as built-in voltage. ---- +++++
In fact, this built-in voltage is the key of

the explanation for unidirectional p-type neutral depletion p-type neutral
region region region
conduction in p-n junctions
Figures 2.5 show the p-n structure in Figure 2.5 a
condition of forward potential
ρv
difference (the p region made positive
-lpo -lp
with respect to n region). Comparing
these figures with figures 2.4 one can +ln +lno
notice:
the equilibrium condition is Figure 2.5 b;
disturbed; E
the width of the depletion region -lp +l n
is reduced (figure 2.5a)
the internal electric field is also
reduced (figure 2.5c);
the junction potential reduces to
Figure 2.5c;
Φ B 0 − v A (figure 2.5d), so that v
the electrons in n-type can fall Φ BO
down the potential barrier to p-
type and the holes in p-type ΦBO-vA
likewise fall down to n-type. This
phenomenon is referred as
charge carrier injection. These Figure 2.5 d
injected carriers are absorbed
due to recombination occurrence. A net current flow from p-type to
n-type appears. This current is due to recombination
phenomenon, which can occur within quasi-neutral region,
transition region, or at metal semiconductor contact.
Figures 2.6 show the p-n structure in condition of reverse potential difference
(the p region is made negative with respect to n region). Comparing these
figures with figures 2.4, one can notice:
34
P-N Diode
the equilibrium condition is also disturbed;

the width of the depletion region is increased (figure 2.6a)
the internal electric field is also increased (figure 2.6c);
the junction potential is increased to Φ B0 + v A (figure 2.6d), so that the
electrons in n-type and the holes in p-type regions are repelled further
from the junction and they can not cross the junction. The only current
present is that due to thermally generated minority carriers (holes
in n-type region and electrons in E
n-type region. A net flow current - - - - - - -+ + + + + + +
- - - - - - -+ + + + + + +
from n-type region to p-type p - - -- - - - + + + + + + + n
- - - - - - -+ + + + + + +
region appears. This current is - - - - - - -+ + + + + + +
--- --- +++++++
called leakage current. It is a
-9 -12
very small current (10 ÷ 10 A) p-type depletion region p-type
neutral neutral
In conclusion, in forward bias condition, Figure 2.6 a
the internal potential barrier is moved
ρv
downward and an injection phenomenon
-lp -lpo
appears. The holes from p-type region
are pushed into n-type region where they +lno +l n
recombine, and electrons from n-type
region are pushed into p-type region,
Figure 2.6b
where also a recombination process E
-l p + ln
appears. These phenomena explain the
existence of the forward current in p-n
diode. In reverse bias condition, the
internal potential barrier is moved
upwards and essentially no charge carrier
can pass through it. Therefore, no current Figure 2.6 c;
flows.
v
2.1.3 Methods of Mathematical
Φ BO +v R
Description
The complete mathematical description of Φ BO
the diode is made using one and only one
equation. The general form of this Figure 2.6 d
equation – known as characteristic
equation – is:
 di dn i dv dm v 
E ∫ iA dt , iA , A ,K, nA , v A , A ,K, mA , θ1,K, θp  = 0 (2.1)
 dt dt dt dt 
where: θ1, K , θp are non-electric parameters.
Related to the regime of operation this equation will be simplified as follows:
35
1. large-signal quasi-static regime; equation (2.1) becomes:

E(i A , v A ) = 0 (2.2)
or:
iA=i A(v A) (2.3)
under this form the equation is known as static characteristic equation;
usually this equation is referred as “I-V characteristic”; the “I-V
characteristic” represents the most important tool used in practical analyses
of quasi-static conditions.
2. large-signal dynamic regime; equation (2.1) becomes:
 dv A 
E ∫ i A dt , i A , v A , =0 (2.4)
 dt 
from this equation the so called Q-V and C-V characteristics may be
derived; the “C-V characteristic” is the most helpful tool used in high
frequencies studies.
3. small-signal dynamic regime; equation (2.1) becomes:
dv a
ia = ga v a + C (2.5)
dt
-where:
ia small signal current (instantaneous value);
va small signal voltage drop (instantaneous value);
ga equivalent conductance;
C equivalent capacitance;
4. small-signal quasi-static regime; equation (2.1) becomes:
ia = ga v a (2.6)
2.2 Quasi-Static Large-Signal Behavior
“I-V” characteristic related to (2.4) equation will be developed in this section. It

treats:
1. Backgrounds;
2. Ideal diode equation;
3. Non-ideal diode effects;
4. Piecewise-linear models for p-n diodes;
36
P-N Diode
5. "I-V" characteristic. SPICE model.

2.2.1 Backgrounds
The only way that allows the current derivation implies the integration of the
seven equations system (1.35) ÷ (1.41) in quasi-static condition.
∂n
j n = qµ n nE + qD n (2.7)
∂x
∂p
j p = qµ p pE − qD p (2.8)
∂x
j = jn + jp (2.9)
n − n 0 1 ∂j n
0=− + (2.10)
τn q ∂x
p − p 0 1 ∂j p
0=− + (2.11)
τp q ∂x
∂E q
= − (p − n + ND − N A ) (2.12)
∂x ε
∂2v q
= − (p − n + ND − N A ) (2.13)
∂x 2 ε
The system contains seven unknown variables {n, p, din, JP, j E, v}. One
considers that {NA, ND} are known. This system of seven non-linear equations
can not be solved analytically. A very interesting approach was developed by
Shockley. Historically this was the first attempt. Shockley approach divided the
structure into three regions as figure 2.4a shows and treated these three
regions separately. He found the boundary conditions using physical condition.
A similar approach will be presented below and an ideal diode equation will
be derived.
2.2.2. Ideal Diode Equation
The next five simplifying assumptions will be made:
1. abrupt charge density profile; one suppose that there is a clear cut
distinction between p-type region and n-type region (figure 2.4a);
2. full depletion approximation; the full depletion approximation assumes
that the depletion region around the metallurgical junction has well defined
edges with an abrupt transition between the fully depleted region where no
carriers are present and quasi-neutral regions where the carriers density is
37
close to the doping density; one reminds that the depletion region is also called
space charge region.
3. small level of injection; this means that for quasi-neutral regions one can
assume:
minority carriers density is much smaller than majority carriers density
n(-lp)<<ppo (2.14)
p(l n)<<nno (2.15)
majority carriers density remains unchanged
p(x ≤ -lp)≅ppo (2.16)
n(x ≥ ln)≅ nno (2.17)
where:
n(-lp) electron concentration at the edge depletion region into
p-type region
p(l n) holes concentration at the edge depletion region into n-
type region
n(x ≥ l n) electron concentration into n-type region
p(x ≤ -l p) holes concentration into p-type region
nno electron concentration into n-type region at equilibrium
ppo holes concentration into p-type region at equilibrium
Equations (2.16) and (2.17) show that in quasi-neutral regions, the majority
carrier density may be considered constant, and therefore no diffusion forces
will appear. That means that the only cause that might be responsible for
majority charge carriers movement is the electric field (there are only two
causes responsible for electric current presence in semiconductors: field and
diffusion). In conclusion, it must be an electric field in quasi-neutral regions. On
the other hand, the electric field into these regions must be zero according to
neutrality hypothesis. The solution of this dilemma is to accept that the real
value of the electric field is enough important to produce the current due to
majority carriers, but not enough to produce any considerable effect on minority
carriers. By consequence, one accepts that:
the current due to majority carriers is produced by electric field;
the current due to minority carriers is produced by diffusion;
In conclusion, the diffusion phenomenon may be considered the only
phenomenon responsible for the current flowing through the quasi-
neutral regions. This may be written as follows:
jp(x ≤ -l p)≅ jpd (2.18)
jn(x ≥ l n)≅j nd (2.19)
38
P-N Diode
where:
j p(x ≤ -lp) holes current through p-type quasi-neutral region
j n(x ≥ ln) holes current through p-type quasi-neutral region
j pd holes current due to diffusion
j nd electrons current due to diffusion
4. quasi-equilibrium conditions (law of the junction); one assumes the
holes density “p” multiplied by electrons density “n” is still constant but its value
is different from ni2
 E Fn − E Fp 
pn = n 2i exp  = const.
 (2.20)
 kT 
and
EFn(ln)-EFp(-l p)=qv A (2.21)
Introducing (2.21) in (2.20) one obtains,
 qv  v 
pn = ni2 exp A  = ni2 exp A . (2.22)
 kT   VT 
where:
EFn -Fermi quasi-level for electrons in n-type region
EFp -Fermi quasi-level for electrons in p-type region
VT thermal voltage defined as:
kT
VT = (2.23)
q
5. “long diode”; a so called diode is a diode with infinite quasi-neutral regions;
in fact the length of quasi-neutral regions must be much bigger then diffusion
length.
The figure 2.7 presents "a general picture" of the procedure that must be
followed to obtain the ideal diode equation.
For reasons of clarity, the presentation will follow the next steps:
1. The total current density will be written as the sum of the minority
carrier diffusion current at the two limits of the space charge region.
Thus, the expressions of the minority carrier diffusion current become
important.
2. The diffusion equations for minority carriers will be derived taking into
account current equations and continuity equations.
3. The distribution of the minority carriers will be determined by
integrating diffusion equations.
39
4. The minority carrier current will be derived from the distribution of the
minority carriers according to current equation.
In addition, it must be added:
The boundary conditions for diffusion equation are given by the law of
junction and the long diode approximation.
Fermi level is constant at

equilibrium
Built-in voltageΦ BO
Poisson equation Boundary conditions

vA(-lp)=0; vA(ln)=Φ BO -v A
Long diode approximation Limits of space charge region

lp, and ln + Law of the junction
Diffusion equations Boundary conditions

np(-lp), np(-∞), pn(ln), pn(∞)
Distribution of minority carriers Current equations

inside neutral regions
Minority diffusion current at

boundaries of depletion region
Current expression
Figure 2.7
The limits of the space charge region are calculated writing Poisson
equation for depletion region. The boundary conditions are obtained
taking into account the relation between built-in voltage and external
voltage. The built-in voltage is determined form the assumption that
Fermi level is constant.
1. The Total Current Density.
Figure 2.8 shows a physical model of the current existing in structure. One can
observe that there are three currents:
diffusion hole current due to p-type region
diffusion electron current due to n-type region
generation-recombination current due to depletion region
40
P-N Diode
According to “full depletion approximation”, the generation-recombination

current due to depletion region may be ignored. Thus, only two currents are
meaningful:
the diffusion hole current due to p-type region that recombines into n-
type region and
the diffusion electron current due to n-type region that recombines into
p-type region.
diffusion hole current

due to p-type region
-Ln -lp ln Lp
anode cathode
p-type region n-type region
generation-recombination diffusion electron current

current due to depletion region; due to n-type region
(this current will be ignored in
the first step of the analysis)
Figure 2.8
The total current will be the sum of these two components.

j=jpd(x)+j nd(x) (2.24)
where:
i the density of current through the structure;
-lp ln
hole electron
anode current current cathode
electron
current
Ln Lp
Figure 2.9
41
Figure 2.9 shows the distribution of the hole, respectively electron, diffused
currents, into the structure.
Returning at diffusion currents, it may be observed that:
j pd ( −l p ) = j pd (l n ) (2.25)
j nd ( −l p ) = j nd (l n ) (2.26)
Usually one chooses

x=ln (2.27)
and (2.24) becomes:
j=jpd(l n)+j nd(l n) (2.28)
Taking into account (2.25), (2.28) may be rewritten:
j=jpd(l n)+j nd(-l p) (2.29)
2. The Diffusion Equations
It must be noticed that (2.29) is really important because it states that the total
diffusion current may be derived considering only current due to minority
diffused carriers (jpd, jnd) at the edge of depletion region. In other words,
current and continuity equations must be integrated only for quasi-static
regions. So (2.7), (2.8) current equations, and (2.10), (2.11) continuity
equations, become:
∂p n
j p = − qD p (2.30)
∂x
∂n p
jn = qDn (2.31)
∂x
p n − pn0 1 ∂j p
0=− + (2.32)
τp q ∂x
n p − n p0 1 ∂j n
0=− + (2.33)
τn q ∂x
Observing that:
jp≅jpd (2.34)
jn≅jnd (2.35)
42
P-N Diode
and introducing (2.30) into (2.32) and (2.31) into (2.33) one obtains:
d 2p n p n − p no
− =0 (2.36)
dx 2 L2p
for holes. For electrons:
d 2n p n p − n po
− =0 (2.37)
dx 2 L2n
Where:
Lp diffusion length for holes
τp life time for holes
Ln diffusion length for electrons
τn life time for electrons
and
L p = Dp τp (2.38)
L n = Dn τ n (2.39)
These equations are usually named diffusion equations.

3. The Distribution of the Minority Carriers
The general solution of the diffusion equation for holes in quasi-neutral n-type
regions is given by:
 − ( x − ln )   ( x − ln ) 
p n ( x ≥ l n ) = p no + A exp   + B exp   (2.40)
 L p   L p 
The boundary conditions are:
v 
p n (x = lp ) = pn0 exp  A  (2.41)
 VT 
p( x → ∞) =pn0 (2.42)
Where:
p( x → ∞) represents the density of holes in the neighborhood of
the anode according to long diode concept.
p(ln) represents the density of holes at the edge of the n-
type quasi-neutral region.
43
Introducing (2.41) and (2.42) in(2.43) the expression of holes distribution in n-

type region becomes:
 v    − (x − l n ) 
p n ( x ≥ ln ) = p n0 + p n0 exp A  − 1 exp   (2.43)
 L 
  VT    p 
The general solution of the diffusion equation for electrons in quasi-neutral p-
type region is given by:
 − ( x + lp )   (x + lp ) 
n p ( x ≤ −l p ) = n po + C exp   + D exp   (2.44)
 Ln   Ln 
The boundary conditions for p-type quasi-neutral region are:
v 
n p (x = −ln ) = np 0 exp A  (2.45)
 VT 
n( x → −∞) = n p0 (2.46)
Where:
n( x → −∞) represents the density of electrons in the neighborhood
of the cathode according to long diode concept.
n(-lp) represents the density of electrons at the edge of the p-
type quasi-neutral region.
Introducing (2.45) and (2.46) in (2.44) the expression of electrons distribution in
p-type region becomes:
 v    ( x + lp ) 
n p (x ≤ −l p ) = n p0 + n p0 exp A  − 1 exp  (2.47)
  VT    Ln 
v  v 
The expressions p n ( x = l p ) = p n0 exp A  and n p (x = −ln ) = np 0 exp A  called
 VT   VT 
Shockley conditions will be calculated in next section. Figure 2.10 shows the
minority carriers distribution according to (2.43) and (2.47) relations.
44
P-N Diode
v  v 
np0 exp A  p n0 exp A 
 VT   VT 
n(x ≤ -lp) p(x ≥ ln)
np0 pn0
-Ln -lp ln Lp
Figure 2.10
4. The Minority Carrier Current

The diffusion current densities in quasi-neutral regions due to minority carriers
may be derived from the derivative of (2.43) and (2.47) relations
D p p n0   vA    − (x − l n ) 
jp ( x ≥ l n ) = q exp   − 1 exp   (2.48)
L p   L 
 VT    p 
D nn p0   vA    (x + l p ) 
jn ( x ≤ −l p ) = q exp   − 1 exp   (2.49)
L n   VT    LN 
Introducing (2.48) and (2.49) in (2.29), one obtains the final formula:
 D n n p0 D p p n0  v  
j = q +  exp  A
V  − 1 (2.50)
 L Lp 
 n   T  
Taking into account that:
i A= j A (2.51)
where A is the junction surface, and noting:
 D n n p0 D p p n0 
IS = qA +  (2.52)
 L Lp 
 n 
the expression of the ideal diode current becomes:
 v  
i A = IS exp A  − 1 (2.53)
  VT  
5. Boundary Conditions for Diffusion Equations;
The boundary conditions for diffusion equations may be found into two steps:
1. The calculation of space charge edges l p an ln;
45
2. The calculation of mobile charge carrier densities at these points, pn(l n)

and np(-lp)
The calculation of the space charge edges, lp an ln
These limits may be obtained from the electrostatic analysis of the depletion
region. This analysis starts by setting up Gauss and then Poisson equations,
(2.12) and (2.13) respectively. According to full depletion approximation the
charge density may be expressed as (figure 2.4a):
 − qN A for − l po < x ≤ 0
ρ= (2.54)
+ qND for 0 < x < l no
where lpo, lno are the edges of depletion region at thermal equilibrium. Gauss
equation changes to:
∂E  − qN A for − l po < x ≤ 0
= (2.55)
∂x + qND for 0 < x < l no
The boundary conditions are:

E(x=-l po)=0 (2.56)
for p-type region, and
E(x=l no)=0 (2.57)
for n-type region. The integration result is:
 − qN A
 ( x + l po ); for − l po < x ≤ 0
E( x ) =  ε (2.58)
− qND
 (l no − x ) for 0 < x < l no
 ε
Figure 2.4c represents (2.58) relation. At this point of the analysis, it must be
observed that the electric field must satisfy the continuity condition:
E(-0)=E(+0) (2.59)
Introducing this condition into (2.59) relation one obtains:
NAlpo=NDlno (2.60)
The expression (2.60) is called the neutrality condition.
In the conditions discussed above, Poisson equation is
∂ 2 v  − qN A for − lpo < x ≤ 0

= (2.61)
∂x 2 + qND for 0 < x < l no
and the boundary condition are:
46
P-N Diode
v(x=lpo)=0; (2.62)
v(x=lno)=Φ BO (2.63)
and Φ BO is, the built-in voltage The expression of built-in voltage will be
developed in next section. Integrating (2.61) results:
 − qNA
 (x + l po ) 2 ; for − l po < x ≤ 0
v( x ) =  ε (2.64)
− qND
 Φ BO − (lno − x ) 2 for 0 < x < l no
 ε
Figure 2.4d shows this parabolic curve. Taking into account that the potential
must be continuos in origin:
v(-0)=v(+0) (2.65)
and adding to this the neutrality condition, the width of space charge region
may be obtained:
2ε  1 1
l0 =  +  ΦBO (2.66)
q  ND N A 
where:
l o=l po+l no (2.67)
Also must be noted that:
2ε N A  1 1 
l n0 =  + Φ BO (2.68)

q ND  N D N A 

2ε N D  1 1 
l p0 =  + Φ BO (2.69)

q N A  ND N A 

The approach, presented above, considers that the equilibrium conditions are
satisfied. When an external voltage v A is applied to p-n diode, the total
potential across the semiconductor must equal the difference between the built-
in potential and the applied voltage. In other words Φ B0 becomes Φ B0 -v A, and
by consequence the width of the depletion region is changing. In fact, the new
edges of space charge region are:
2ε N A  1 1 
ln =  + (Φ BO − v A ) (2.70)
q ND  ND N A 
47
2ε ND  1 1 
lp =  + (Φ BO − v A ) (2.71)
q NA N
 D N A 
The calculation of mobile charge carrier densities at the edges of

depletion regions, pn(ln) and np(-lp)
Both hole and electrons density, pn(l n) and np(-l p) may be calculated taking into
account two simplifying assumptions made in the beginning of this analysis:
small signal condition that consider majority carriers density unchanged
(2.16) and (2.17) equations;
law of the junctions
For holes one obtains:
n(l n)≅nno (2.72)
v 
p(l n )n(ln ) = n i2 exp A . (2.73)
 VT 
From (2.72), (2.73) and (1.7) comes into view:
n i2 v  v 
p(ln ) = exp A  = p no exp A . (2.74)
nn0  VT   VT 
For electrons one obtains:
p(-lp)≅ppo (2.75)
v 
( )( )
p − l p n − l p = n i2 exp  A . (2.76)
 VT 
and finally:
ni2 v  v 
n(− lp ) = exp  A  = np0 exp  A . (2.77)
pp 0  VT   VT 
6. Boundary Conditions for Poisson Equation;
Φ BO evaluation starts from the assumption that Fermi level is constant in a
structure that is in equilibrium conditions. Figure 2.11 shows the energy bands
in a p-n diode. One can observe that:
EC (lno ) − EC ( −lpo )
Φ BO = − (2.78)
q
where:
48
P-N Diode
EC(-lp0) the bottom of conduction band into p-type region

EC(l n0) the bottom of conduction band into n-type region
Keeping in mind that that the carriers densities may be expressed:
 E (l ) − EF 
nno = NC exp − C no  (2.79)
 kT 
 EC ( −lpo ) − EF 
n po = NC exp −  (2.80)
 kT 
Introducing (2.79) and (2.80) in (2.78) follows:

kT nno
Φ BO = ln (2.81)
q npo
p-type region n-type region
conduction band Φ B0
p(x ≥ l )
Fermi level
Φ B0
-lp0 ln0
valence band
Figure 2.11
Again, the carriers densities may be expressed related to impurity

concentrations as follows:
ni2
p po ≅ N A npo ≅ (2.82)
NA
ni2
nno ≅ ND nno ≅ (2.83)
ND
Associated to (2.82) and (2.83), (2.81) may be rewritten:

kT N A ND
Φ BO = ln (2.84)
q ni2
2.2.3 Non-Ideal Diode Effects.

The approach presented above ignored some phenomena such as:
series resistance;
49
high injection;
generation-recombination phenomenon in depletion region;
junction breakdown;
thermal breakdown;
short diode effect
temperature dependence
The impact of these phenomena is presented below.
Series resistance.
Contact resistances and the resistances of the neutral regions are usually
referred as series resistance. Considering its effect, the (2.53) formula
becomes:
 v −i R  
i A = IS exp A A S  − 1 (2.85)
  VT  
where RS series resistance.
High injection
Condition (2.14) ÷ (2.17) are not realized. In fact, "high injection" occurs at high
forward bias, when the excess minority carrier density exceeds the doping
density in the material. The neutrality condition demands a similar increase of
majority carrier density. In fact, the excess electron density must equal the
excess hole density, because no net charge may exist. If there is a net charge,
the electric field causes the carriers to move and the neutrality condition is re-
established.
The aim of this section is to find the influence of the excess carrier density
related to the diode current expression (2.53). The present analysis will be
focused on n-type neutral region. Let's note:
nn=nn0+ns (2.86)
pn=pn0+ps (2.87)
where:
nn0=ND (2.88)
N
pn0 = D2 (2.89)
ni
and:
nn electron density at the boundary of n-type region;
nn0 electron density in n-type region at thermal equilibrium;
ns excess electron density at the boundary of n-type region;
pn hole density at the boundary of n-type region;
pn0 hole density in n-type region at thermal equilibrium;
50
P-N Diode
ps excess hole density at the boundary of n-type region.

In the same time the neutrality condition requires:
ps=ns (2.90)
Taking into account (2.86) ÷ (2.90) and the "law of junction"
v 
p n nn = ni2 exp A  (2.91)
 VT 
one obtains a system of six equations with six unknown variables (nn, pn, nn0,
pn0, ns, ps ). The solution for ps is:
  v   
 4n i2 exp  A  − 1 
N    VT   
p s = D  1+ − 1 (2.92)
2  ND2 
 
 
The associated current to this excess charge is diffusion current and it may be
obtained using the same procedure to that for calculating the ideal diode
current. One obtains the following hole current:
  v   
 4n i2 exp A  − 1 
Dpps D p ND    VT   
i p = qA = qA  1+ − 1 (2.93)
Lp 2L p  ND2 
 
 
If:
 v   N
n p 0 exp  A  − 1 << D (2.94)
  VT   4
that means that the density of the excess minority carriers is much smaller than
one quarter of the doping density, the current expression becomes:
D p np0   vA  
i p ≅ qA exp  − 1 (2.95)
L p   VT  
If:
 v   N
np 0 exp A  − 1 >> D (2.96)
  VT   4
51
that means high injection, the current expression becomes:

D p ni  v 
i p ≅ qA exp A  (2.97)
Lp  2VT 
The electron current due to diffusion of electrons in p-type neutral region has a
similar expression:
  v   
 4ni2 exp A  − 1 
Dn D N    VT   
i n = qA n s = qA n A  1 + − 1 (2.98)
Ln 2L n  N 2A 
 
 
In conclusion, the total current at high injection condition must be

 v 
proportional with exp A 
 2VT 
 v 
i A ⇒ exp A  (2.99)
 2 VT 
Generation-recombination phenomenon in depletion region;
The approach presented above ignored the current due to the generation-
recombination phenomenon in the depletion region. This current may be
evaluated using Shockley-Read-Hall model. In fact, generation-recombination
processes seek to restore thermal equilibrium. Therefore, in reverse bias
conditions, characterized by a lack of charge carriers ( pn < n i2 ), the generation
process is significant. On the other hand, in forward bias conditions,
characterized by an excess of charge carriers ( pn > n i2 ), the recombination
process is significant. According to this model, the current density may be
expressed as:
ni   v  
jGR = q
2τ 0
(l p + l n )exp A  − 1 (2.100)
  2VT  
where τ 0 is the effective lifetime within the depletion region. In real situation
(2.101) formula may be used.
  v  
i GR = ISR exp A  − 1
 (2.101)
  n R VT  
where
52
P-N Diode
nR emission coefficient for generation recombination current;

ISR generation recombination current parameter.
Junction breakdown;
Figure 2.12 presents a typical shape of an "I-V" characteristic for a real diode.
It must be observed that for forward bias region and reverse bias region,
different scales were used. This is the significance of the dotted line. The
iA
VBR knee voltage
leakage
Vγ ≅0.7 V
vA
breakdown
reverse bias forward bias

region region
Figure 2.12
reason why such an artifice was used is that breakdown voltage is hundreds of
time greater then knee voltage. As one can observe, the breakdown means, in
fact, the sharp increases in the inverse current. It may be caused by two
mechanisms:
avalanche breakdown and
tunneling breakdown
Avalanche breakdown occurs typically at higher voltages in lightly doped
junction. It is caused by impact ionization. In this process an electron or a hole,
acquires enough energy from the electric field, to break a bond and promote
another electron from the valence band into the conduction band creating an
electron-hole pair. The electrons and holes created by impact ionization, are
accelerated by the electric field and may create more electron-hole pairs. This
will lead to an uncontrolled rise of current caused by impact ionization. If this
current is not limited by an external load, the diode burns out.
Tunneling breakdown occurs typically at lower voltages in highly doped
junction. It is caused by the tunnel effect. The width of the depletion region
becomes so small that electrons from occupied states in the valence band on
the p-side, may jump to the empty states in the conduction band on the n-side.
The current in the breakdown region is usually expressed as:
i R=MIS (2.102)
where:
iR reverse current
M multiplication factor whose expression is:
53
1
M= n
(2.103)
 v 
1 −  R 
 VBR 
and VBR breakdown voltage
vR reverse bias voltage
Thermal breakdown;
It is provoked by a large power dissipation in a reverse biased junction.
Thermal breakdown leads to a run-away increase in the reverse current, and to
an S-type negative differential resistance. It is especially important in diode
made from narrow-gap materials (ex. Ge).
Short diode effect;
This effect appears when lengths n-type and p-type are smaller than the
diffusion lengths. As the quasi-neutral regions are much smaller than the
diffusion lengths, the carrier density varies linearly throughout these regions.
Taking into account this new fact, the current through the diode still follows the
(2.53) formula, but IS becomes:
 D nn p0 D pp n0 
IS = qA +  (2.104)
 X Xp 
 n 
where:
Xn width of the n-type quasi-neutral region;
Xp width of the p-type quasi-neutral region;
Temperature Dependence
One can discuss about the temperature dependency of any of the parameters
mentioned above, but only two important parameters are generally mentioned:
1. saturation current, whose variation related to temperature may be
considered as being:
X ti
 T  n  qE g0 qE g0 
IS ( T) = IS (T0 )  
 exp  −  (2.105)
 T0   nkT0 nkT 
2. and built-in voltage:

1.5
T  T  1 T 
Φ B = Φ B0 − 2VT ln 
 −  E g0 − E g (T) (2.106)
T0  T0  q  T0 
54
P-N Diode
where:
Xti gamma temperature effect exponent (usually 3)
Eg band gap voltage; its law of variation is:
αT 2
E g (T ) = E g0 − (2.107)
β+T
for Si α = 702 • 10 −6 and β = 1108
2.2.4 Piecewise-Linear Models for P-N Diodes

The (2.53) equation is a non-linear equation and can not be used in practical
analyses. For these kind of situations, piecewise-linear techniques must be
applied. This section presents three possibilities and correspondingly three
models are developed.
First order approximation
Figure 2.13 shows how the static characteristic is approximated. One can
observe that knee voltage is considered zero.
iA
A C
diode conducting
A C
First order Real A C
diode non-conducting
approximation characteristic
vA
Figure 2.13 Figure 2.14
Mathematical model is:

v A=0 for i A>0 (2.108)
i A =0 for v A<0 (2.109)
Electrical model is presented in figure 2.14
Second order approximation
Figure 2.15 reveals another possibility of approximation. One can observe that
knee voltage Vγ is considered different of zero (usually 0.7 V). This
approximation is more accurate than the previous one.
55
iA Vγ
Real A C
characteristic diode conducting
A C
A C
Second order diode non-conducting
approximation Knee voltage
vA

v A=constant (usually 0.7V) for iA>0 (2.110)
iA =0 for v A< Vγ (2.111)
Third order approximation
Figure 2.17 exposes a more accurate approximation. This time a bulk
resistance was introduced.
v A − Vγ
iA = for v A ≥ Vγ (2.112)
rB
iA =0 for v A < Vγ (2.113)
iA
iA2
Vγ rB
v − v A1 Third order A C
rB = A 2 diodeconducting
approximation A C
iA 2 − iA1
A C
diodenon-conducting
iA1 vA
vA1 vA2

Observation: rB is bulk resistance of the diode forward biased. Its value is very
small (ohms or tenth of ohms), and may be estimated as figure 2.17 shows.
56
P-N Diode
2.2.5 "I-V" Characteristic. SPICE Model

Figure 2.19 presents non-ideal effects related to ideal characteristic of a diode
forward bias.
One can observe that two important deviations from ideal diode I-V
characteristic exists:
low currents (less than 1nA) due to generation in transition region;
high currents (more than 1mA) due to ohmic voltage drop in neutral
regions)
According to the correction introduced in SPICE the current through the diode
follows:
i A=KHIiD+i GR-i B (2.114)
where:
  qv  
i D = IS exp I  − 1 (2.115)
  nkT  
lg(iA)
ideal diode
series resistances
real diode
high injection
diffusion
high injection
knee current
generation-recombination
vA
Figure 2.19
 IKF
 for IKF > 0
K HI =  IKF + i D (2.116)
 0 otherwise

M
 v 
2
2   vI  
i GR = ISR 1 − I  + 0.001
 exp   − 1
 (2.117)
 Φ B0     n R VT  
 
  v + qVBR  
i B = IBV exp − I  − 1
 (2.118)
  nVT  
and
57
IBV reverse breakdown knee current;

iD diffusion current;
IKF high injection knee current;
IS saturation current;
KHI correction for high injection effects;
M grading coefficient (M=0.5 for abrupt junction and M=0.33 for
linear junction);
n emission (ideality) factor;
nR emission coefficient for generation recombination current;
vI junction voltage drop;
As a result of (2.114) equation, SPICE model of the diode (figure 2.20)
embodies a single linear resistor RS that represents both the external contact
resistance and any voltage drop in the neutral n and p regions and other three
non-linear resistances that embodies the rest of the effects. It must be
observed that RD has the symbol of the diode because it has the same
behavior as an ideal diode (the current is varying exponential related to
vA
vI
RB
iB
RS RD
iA iD
Anode Cathode
RG/R
i G/R
Intrinsic
diode
Figure 2.20
voltage).
2.3 Dynamic Large Signal Behavior
C-V characteristic related to (2.4) equation will be developed in this section. It

treats:
1. Backgrounds;
2. C-V Characteristic
3. SPICE model
58
P-N Diode
2.3.1 Backgrounds
The dynamic high signal conditions are characterized by large variation of
the electrical parameters (current or voltage) at high speed. In fact one can
distinguish:
the switching conditions (the current and the voltage are varying as
impulses)
the high frequencies conditions (the current and the voltage are
varying similar to sinusoidal signals).
This section will analyze both possibilities.
The key of this study is the charge stored in the diode. In fact this is another
important characteristic of diodes. In steady-state conditions this feature does
not matter. It becomes important when transitions between different state are
studied, and that means, in fact, dynamic behavior.
There are two components to the charge stored in a diode. The first is due to
the ions “fixed” in transition region. The amount of this charge depends on the
applied bias since the size of the depletion region varies with the voltage. This
component is significant in reverse bias conditions. It is called depletion
charge In respect with depletion charge a junction capacitance may by
defined (2.121). The second component of stored charge in a diode is due to
mobile (“injected”) carriers (figure 2.20).
np0
pn0
-Ln -lp ln Lp
Figure 2.20
During forward bias (and immediately afterward) this charge can be much
larger than the depletion charge. In fact this component is considerable only in
forward bias conditions. Its name is diffusion charge. Related to it, a
diffusion capacitance is defined. In fact, as (2.123) formula shows the
diffusion charge is determined by τ - transit time.
Both junction and diffusion capacitance are small signal parameters. They are
valid only for small signal changes around the bias point. The relation between
59
the values of the capacitance and the bias voltage, in both cases, is non-linear.
In practical situation, piecewise linear diode capacitance models are used.
2.3.2 C-V Characteristic
As it has been told, the total diode capacitance is the sum of the junction and
diffusion capacitance
C=CJ+CD (2.119)
where:
CJ depletion region (junction) capacitance;
CD diffusion capacitance.
The junction capacitance
The charge stored in the transition depletion region is:
Φ B0
QJ = ∫C
0
J
( v I )dv I (2.120)
and so :
dQ J
CJ = (2.121)
dv I QP
where QP is the quiescent point. According to the junction profile, different

formulas may be developed for this capacitance. SPICE uses (2.122)
expression:
  vI 
−m
 
C J 0 1 −  v I ≤ f C Φ B0
  Φ B 0 
CJ =  (2.122)
C (1 − f ) − (1+ m ) 1 − f (1 + m ) + m v I  v I > f C Φ B0
 J0 C  C 
  Φ B0 
and:
fC forward bias depletion capacitance coefficient. fC ∈ (0,1)
m the exponent of the voltage factor for v j
CJ0 depletion capacitance at zero bias.
The diffusion capacitance
The diffusion capacitance is defined as:
diD
CD = τ (2.123)
dv I QP
60
P-N Diode
and τ is the so called transit time.
2.3.3 SPICE Model

This time the current through the diode is:
dQD dv
i A=KHIiD+i GR-i B+ + CJ I (2.124)
dt dt
The SPICE model is presented in figure 2.21. This model includes all the
effects discussed above. One can observe that non linear resistors are
symbolized as diodes.
vA
vI CD
CJ
RB
iB
RS RD
iA iD
Anode Cathode
i G/R
Intrinsic RG/R
diode
Figure 2.21
2.4 Quasi-Static Small-Signal Behavior

1. Small-Signal Condition;
2. Quasi-static Small-Signal Parameters.
3. Quasi-static Small-Signal Model;
2.4.1 The Small-Signal Condition
As it has been said, the I-V characteristic - for any electronic device - is
profound non-linear. A common approach to hand analysis of signal processing
circuits is to find the DC operating point using device large-signals
characteristics, and then linearize the characteristics around the DC bias
operating point in order to examine what happens with signals that vary around
the DC bias point.
61
Figure 2.22 explains this piecewise linear procedure. Related to this procedure
the next problem may be formulated: how large the signal ( ∆ v) may be, so that
the device can be considerate as operating linear. The solution to this problem
is referred as small signal condition. Mathematically, linearization of the
device characteristics amounts to taking a Taylor expansion of the device non-
linear characteristic at DC bias operating point and retaining only the linear
terms in the expansion. In other words, the current may be expanded as:
2
di ( VQ ) 1 d i ( VQ )
i = IQ + ( v − VQ ) + (v − VQ )2 + K (2.125)
dv 2 dv 2
and observing that:

∆i = i − IQ (2.126)
and
∆v = v − VQ (2.127)
(2.125) may be rewritten as follows:

d i( VQ ) 1 d2 i( VQ )
∆i = ∆v + ( ∆v )2 + K (2.128)
dv 2 dv 2
Non-linear
Characteristic
i
Linear
Region
∆i
Q(VQ, IQ)
v
∆ v
Figure 2.22
If:
d i( VQ ) 1 d2 i( VQ )
∆v >> (∆v )2 (2.129)
dv 2 dv 2
or:
62
P-N Diode
d i( VQ )
∆v << dv (2.130)
1 d2 i( VQ )
2 dv 2
(2.128) may be approximate as:

d i( VQ )
∆i ≅ ∆v (2.131)
dv
The (2.130) relation is called small-signal condition.
d i( VQ )
On the other hand, is a differential conductance calculated in Q point,
dv
and by consequence it may be noted as follows:
d i( VQ )
g= (2.132)
dv
and hence:
∆i ≅ g ∆v (2.133)
Finally one can say: if ∆v accomplishes the small signal condition, the relation
between current variation and voltage variation may be considered linear:
The (2.130) constriction may be applied for an ideal diode. In this case the I-V
characteristic is:
 v  
i A = IS exp A  − 1 (2.134)
  VT  
and by consequence:
d iA ( VQ ) 1 V 
= IS exp Q  (2.135)
dv A VT  VT 
and
d2 iA ( VQ ) 1 V 
= IS 2 exp Q  (2.136)
dv 2A VT  VT 
Introducing (2.135) and (2.136) in (2.130) one obtains:
∆v A << 2VT (2.137)
In real situations ∆v A represents a sinusoidal signal:
63
v a = Va sin ωt (2.138)
with restriction:
∆v ≤ 2Va (2.139)
Taking into account (2.137) and (2.139) the small-signal condition may be
rewritten as:
Va << VT (2.140)
In real situations it is considered that any signal smaller than 10 mV

satisfies the small-signal condition.
2.4.2 Quasi-Static Small-Signal Parameters

The only parameter that characterizes the diode behaviour in quasi-static
small-signal condition is its differential conductance defined by (2.229) formula.
For practical reasons this formula is approximated as:
∆i A
ga = (2.141)
∆v A QP
and hence:
Ia
ga = (2.142)
Va QP
if small-signal values are used. In fact, under this last form this conductance is
referred as small signal conductance.
The expression of differential conductance may be derived from (2.132) and
(2.134)
V    VQ  
IS exp Q  IS exp  − IS  + IS

d i (V )  VT  =   VT   I +I
ga = A Q = = A S (2.143)
dv A VT VT VT
In many cases
IA >> IS (2.144)
so that ga is usually approximated as:
64
P-N Diode
IA
ga ≅ (2.145)
VT
Remembering that:
VT ≅ 25 mV (2.146)
the final expression for ga becomes:

ga [mS] = 40 IA [mA ] (2.147)
2.4.3 Quasi-Static Small-Signal Model

The mathematical model may be developed starting from (2.133) relation. The
finite differences must be approximate by small signal values as follows:
∆i → i a (2.148)
∆v → v a (2.149)
and
g → ga (2.150)
Finally the mathematical model becomes:

i a=gav a (2.151)
The electrical model associated to this mathematical model is represented in
figure 2.23
va
ga
ia
Anode Cathode
Figure 2.23
2.5 Dynamic Small-Signal Behavior
This section presents a dynamic small signal model of a diode. It treats:

1. Backgrounds;
2. Dynamic small signal model
2.5.1 Backgrounds
65
Many ways are useful to develop small-signal dynamic models. Two of them
are simpler:
linearization of dynamic large-signal models.
embedding of second order effects (capacitive effects) in quasi-static
small-signal models
This section presents the second possibility.
2.5.2 Dynamic Small-Signal Model
Mathematical model is introduced by (2.152) formula:
dv a
ia = ga v a + C (2.152)
dt
where C represents the equivalent capacity of the diode. The definitions (2.122)
and (2.124) are useful from this point of view.
Starting from this mathematical model the electrical model may be developed
as figure 2.24 shows:
va
ga
ia
C
Anode Cathode
Figure 2.24
2.6 Classes of Diodes
There are two important criteria used in diodes classification:

1. frequency of the signal processed;
2. range of the signal processed.
According to the first criteria one discusses about:
a.) DC and low frequencies and here one finds – generally - two classes:
rectifier diodes;
Zener diodes and;
b.) high frequencies and microwave diodes, such as:
varactor diodes
PIN diodes,
66
P-N Diode
step recovery diodes

mixer diodes,
detector diodes,
GUNN diodes,
IMPATT diodes,
LSA diodes,
TRAPATT diodes,
parametric amplifier diodes
tunnel diodes
According to the second criteria one discusses about:
low power diodes;
medium power diodes and
power diodes.
In this section, a brief discussion regarding general problems related to these
classes of diodes will be presented, but only rectifier diodes, Zener diodes
varactor diodes PIN diodes and step recovery diodes will be exposed.
2.6.1 Rectifier Diode

In many cases the term rectifier is replacing the term diode. In fact, a lot of
scientific papers use the term diode for very low power devices with current
typically in the milliamp. range. The term rectifier covers power devices
conducting from 1 to 1000 amps. The rectifier diodes are useful in power
electronics, and, more specific, in energy conversion (AC to DC or DC to AC).
This means that they are working at low frequency and medium or high power
conditions. That’s why their most important specifications are:
1. Forward Voltage Drop, Vf The forward voltage drop, Vf, is specified at
a forward current If. It must be noted that the diode conducts a small
current in the forward direction up to a threshold voltage, 0.3 V for
germanium and 0.7 V for silicon. Generally, the maximum forward
voltage drop is specified.
2. Leakage Current . It is specified at a voltage less than the breakdown
voltage. This leakage is undesirable, obviously the lower the better.
Generally the maximum leakage current is specified.
3. Current Rating. Average current is used, not RMS current. A larger
chip and package of high thermal conductivity are both conducive to a
higher current ratting. Generally, the rated forward current is specified.
4. Breakdown Voltage. It is the maximum reverse voltage the diode can
operate.
Figure 2.25 presents a diode and its schematic representation.
67
cathode anode
Band at
cathode end
Figure 2.25
2.6.2 Zener Diode

The Zener diodes are operating reverse biased at breakdown voltage. Figure
2.21 is useful for understanding the principle of operation. It is interesting to
observe that while for the conventional rectifier – or cathode anode
a diode in general – it is imperative to operate
below this voltage, the Zener diode is intended to Figure 2.26
operate at that voltage. that is why its greatest
application is as voltage regulator Their symbol is presented in figure 2.26. The
basic parameters are:
Zener Voltage. It must be specified. The common rage is 3.3V÷75V.
Power handling capability is also stated. Popular power ranges are:
0.25W, 0.5W, 1W, 5W, 10W and 50W.
Tolerance of the Zener voltage. Popular tolerances are 5% and 10%
2.6.3. Varactor Diode
The varactor diodes are diodes whose principle of cathode anode
operation is based on C-V characteristic. In fact
they are operating reverse biased because the Figure 2.27
depletion region (junction) capacitance is greater
than diffusion capacitance. This property, of varying the diode capacitance with
the reverse voltage is useful in tuning circuits, Automatic Frequency Control
(AFC) Circuits, etc. Its symbol is presented in figure 2.27. Major parameters
are:
Capacitance value;
Voltage;
Variation in capacitance with voltage;
Maximum working voltage;
Leakage current.
2.6.4 PIN Diode

PIN diode is a semiconductor device that operates as a variable resistor at RF
and Microwave Frequencies. It can be also used as a switch and limiter. The
variable resistor property makes it usable as attenuator.
68
P-N Diode
Principle of operation. Figure 2.28shows the construction of a PIN diode. One

can observe that between P-type region
and n-type region there is an intrinsic
anode cathode
region. The diode resistance is given by P I N
the intrinsic region resistance. When the
diode is forward biased the holes from p Figure 2.28
region and the electrons from n region
are injected into intrinsic region. So, a quantity of stored charged appears (its
time-life depends on the carriers lifetime). The effect of this stored charge is
lowering the resistivity of I region. So as forward current increases the
resistance decreases. This explains the use as a Current Controlled Resistor.
2.6.5 Step Recovery Diode
Step recovery diode is diode that can generate an impulse of current (or a train
of impulses) by applying a step voltage (or a train of step voltages) input to the
diode. The impulse of current is generally named step recovery signal. These
diodes are used in microwave frequencies for frequency multiplication,
harmonic frequency generation or comb generation.
69
Problems
Problem 1. This problem is regarding the p-n junction electrostatic. Find the
potential across the depletion region for a p-n diode at an applied voltage of:
a) v A=0V;
b) v A=0.4V;
c) v A=-10V.
The built-in voltage is 0.6V
Solution:
The potential across the depletion region may be calculated according to:
ΦB = ΦB0 − v A (1)
where:
ΦB 0 built-in voltage;
By consequence:
a) ΦB = 0.6 V (figure2.4d);
b) ΦB = 0.2 V (figure2.5d);
c) ΦB = 10.6 V (figure2.6d);
maximum electric field in the depletion region for a p-n diode. Assume that:
the built-in voltage is ΦB0 = 0.6V
the applied voltage is v A=0V
the depletion region is w=1 micron
Solution:
According to (2.58), (2.59) and (1) one finds:
ΦB Φ − vA kV
Emax = −2 = −2 B0 = −12 (2)
w w cm
Problem 3. This problem is regarding the p-n junction electrostatic. Sketch the
electric field and the potential as a function of position, for a p-n diode. Assume
that:
the built-in voltage is ΦB0 = 0.6V
70
P-N Diode
the net doping density ND − NA is he same in the p-type and n-type

region.
the applied voltage is
v A=0V E
the depletion region is -
-
-
-
-
-
-----
-----
+++++
+++++
l 0=1 micron p - - - ----- +++++
n
- - - -- - - - +++++
- - - -- - - - + + + + ++
Solution: - - - -- - - - + + ++ + +
Figure 1 shows the p-n diode. p-type neutral depletion p-type neutral
Figure 2 shows the electric region region region
charge distribution according Figure 1 p-n diode
to problem statement. Figure
3 presents the electric field ρv
distribution. The maximum -lpo +qND
value is calculated in (2).
-qNA +lno
Figure 4 sketches the
potential.
Figure 2. Electric charge distribution
E
Problem 4. This problem is
-l po=-0.5 µ m +l no= 0.5 µ m
regarding the p-n junction
electrostatic. Find the built-in
voltage of a p-n diode. -12kV/cm
Assume that it is an abrupt
junction consisting of a p-type Figure 3 Electric field distribution
16 -3
region that contains 10 cm v
acceptors and a n-type region
16 -3
that contains 9 × 10 cm Φ BO=0.6V
10 -3
donors (ni=10 cm ).
-lpo +lno
Solution:
According to (2.84) the built-in Figure 4 Potential drop distribution
voltage is
kT NA ND
ΦBO = ln 2 = 0.771V (3)
q ni
total width of the depletion region of a p-n diode at an applied voltage of:
a) v A=0V;
b) v A=0.5V;
c) v A=-2.5V.
71
Assume that it is an abrupt junction consisting of a p-type region that contains

16 -3 16 -3
10 cm acceptors and a n-type region that contains 9 × 10 cm donors
10 -3
(ni=10 cm ).
Solution:
a.) According to (2.66) the total width is:
2ε  1 1 
l0 =  + ΦBO ≅ 0.35µm (4)
q  ND NA 
b.) From (2.71) and (2.72) one finds:
2ε  1 1 
l =  +  (ΦBO − v A ) ≅ 0.20µm (5)
q  ND NA 
c.) l=0.72 µm
Problem 6. This problem is regarding the large-signal quasi-static parameters.

Assume that for i A ∈ [1µA, 1mA ] , a diode follows (2.53) equation, with Is=10 A.
-12
Find “the third order model” of this diode, considering that:

this diode is turned on for iA1= 1µA and
the two characteristics are matching for iA2=10mA (figure 1).
iA
iA2
Third order
approximation
iA1 vA
vA1 vA2
Figure 5
Solution: The third order model is characterized by:

Vγ knee voltage, and
rB bulk resistance
Knee voltage may be calculated from (2.53) equation. One finds:
KT i A1 + Is
Vγ = ln =0.36mV (6)
q Is
Bulk resistance may be calculated according to figure 2.17
72
P-N Diode
v A 2 − v A1
rB = = 21.5 Ω (7)
iA 2 − i A1
Problem 7. This problem presents the differences between a piece-wise linear

model and an exponential model. Calculate the drop voltage across the diode
presented in problem 1 for iA1=0.1mA, i A2=1mA and i A3=5mA, in two situations:
use the third order model
use the exponential model
Evaluate the differences.
Solution: The drop voltage for exponential model is expressed by
KT iA + Is
vA = ln (8)
q Is
The drop voltage for the third order model is stated by:
v A = rB i A + Vγ (9)
Table 1 presents the results obtained by placing i A1, i A2 and iA3 in (8) and (9)
current drop voltage drop voltage piece- differences in drop

values exponential model wise linear model voltage
0.1 mA 0.46 V 0.362 V 0.098 V
1 mA 0.518 V 0.382 V 0.136 V
5 mA 0.558 V 0.468 V 0.09 V
Table 1
Problem 8. This problem is regarding the parallel diodes. Find the currents IA1
and IA2 for the schematic diagram presented in figure 6. Assume that those two
-12
diodes are the same type, but due to the parameters scattering, Is1=10 A; and
-12
Is2=3 × 10 A (exponential model).
Solution:
IA1 IA2
One can write:
I=1mA V
D1 D2
I=IA1+IA2 (10)
 V 
IA1 = Is1 exp 
 (11) Figure 6
 VT 
73
 V 
IA 2 = Is 2 exp 
 (12)
 VT 
and finally, one finds:
IA1=0.25 mA and IA2=0.75 mA
Conclusion: The current is unequal divided between the diodes even if they
are the same type (due to parameters scattering).
Problem 9. This problem is regarding the parallel diodes. Find the currents IA1
and IA2 for the schematic diagram presented in figure 7. Assume that those two
-12
diodes are the same type, but due to parameters scattering, Is1=10 A; and
-12
IA1 IA2
R1 R2
I=1mA V 0.2K 0.2K
D1 D2
Figure 7
Solution:
Kirchhoff laws :
I=IA1+IA2 (13)
0=R1IA1+VA1-V (14)
0=R2IA2+VA2-V (15)
Diode exponential law:
V 
IA1 = Is1 exp A1  (16
 VT 
V 
IA 2 = Is 2 exp A 2  (17)
 VT 
One obtains:
IA1 ≅ 0.46 mA and IA 2 ≅ 0.54 mA
Conclusion: The current is approximately equally divided between the
diodes, thanks to R1 and R2 resistors.
74
P-N Diode
Problem 10. This problem is regarding the series diodes. Find the drop
voltages VA1 and VA2 across the two diodes
presented in schematic diagram from figure 8. VA1 VA2
Assume that they are the same type, but due
-12
to parameters scattering, Is1=10 A; and D1 D2
-12 IA
Solution:
One may write: E (100V)
-E=VA1+VA2 (18) Figure 8
KT IA + Is1
VA1 = ln (19)
q Is1
KT IA + Is 2
VA 2 = ln (20)
q Is 2
At last, the results are: VA1=-99.99 V, and VA2=-0.01V

Conclusion: The reverse drop voltage is unequal divided between the
diodes even if they are the same type (due to parameters
scattering).
Problem 11. This problem is regarding the series diodes. Find the drop
voltages VA1 and VA2 across the two diodes presented in schematic diagram
from figure 9. Assume that they are the same type, but due to parameters
scattering, Is1=10-12A; and Is2=3 × 10-12A (exponential model) and R1=R2=100k
VA1 VA2
R1 R2
IA D1 D2
E (100V)
Figure 9
Solution:
One can write:
IA=IA1+IR1 (21)
75
IA=IA2+IR2 (22)
KT  IA1 + Is1  KT  IA 2 + Is 2 
-E= ln + ln  (23)
q  Is1  q  Is 2 
KT IA1 + Is1
0 = IR1R1 − ln (24)
q Is1
KT IA 2 + Is 2
0 = IR2R 2 − ln (25)
q Is 2
VA1=IR1R1 (26)
VA2=IR2R2 (27)
This time the results are: VA1 ≅ 50.01 V , and VA 2 ≅ 49.99 V
Conclusion: This time the reverse drop voltage is equally divided between
the diodes thanks to R1, R2 resistors.
76
• By Hand Large-Signal Analysis
• By Hand Small-Signal Analysis
• Rectifier Circuits
• Clipping Circuits
• Clamping Circuits
Chapter 3
Circuit Applications of P-N Diodes
The chapter presents fundamental circuits with p-n diodes and, related to
these, basic techniques involved in diode circuits analysis. As fundamental
circuits, one discusses about:
rectification circuits,
clamping circuits
clipping circuits.
As basic analysis techniques one presents:
by hand large-signal analysis techniques
by hand large-signal analysis techniques
SPICE analysis.
By consequence, the outline of the chapter is:
The first section, whose title is “By Hand Large-Signal Analysis
Techniques”, presents the algorithm and also an example of such kind
of analysis;
The second section is dedicated to small-signal analysis techniques.
There is also an example shown;
The third section treats rectification circuits. Half-wave rectifier, full-
wave rectifier, filtering power supply, split power supply and voltage
multiplier are described.
The fourth section presents clipping circuit.
The fifth section introduces clamping circuits.
Finally, must be added that each circuit will be discussed according to next
frame:
77
Device Modelling for Circuit Analysis
a) schematic diagram, one illustrates the electronic circuit with the

components represented by their symbols;
b) parts function, one presents role of each part;
c) circuit operation a brief description of circuit behavior;
d) large-signal analysis, one presents by hand analysis;
e) SPICE analysis
3.1 By Hand Large-Signal Analysis

1. Algorithm presentation;
2. Example
3.1.1 Algorithm Presentation
Generally, there are three steps that must be followed in the electronic circuit
analysis:
1. Modeling of the electronic devices. At this step, the electronic device is
replaced by its model. The electronic circuit becomes a simply
electrical circuit. This new circuit is usually named modeled circuit. One
says that electronic problem is reduced to an electrical problem.
2. The modeled circuit is analyzed according to the operation regime with
the convenient technique (Kirchhoff, Laplace, etc…). One obtains a
system of equations. One says that electrical problem is reduced to
an algebraic problem
3. One solves the algebraic problem
Two observations must be made:
The electronic device model must be chosen according to the
operating conditions.
The complexity of the electronic device model must be chosen
according to the level of approximation allowed by the purpose of the
analysis.
In the case of diode circuits an additional problem appears. A diode may be
forward biased or reverse biased and by consequence the large-signal model
must be chosen according to this constraint. The algorithm of testing the diode
state is:
1. One supposes that diode is forward biased;
2. One models the circuit according to this hypothesis;
3. One determines the current through the diode;
4. One compares the current value with zero:
78
if current is grater than zero the hypothesis was right

if current is smaller than zero the hypothesis was wrong
There is also possible another algorithm:
1. One supposes that diode is reverse bias;
2. One models the circuit according to this hypothesis;
3. One determines the voltage across the diode;
4. One compares the voltage value with zero:
if current is smaller than zero the hypothesis was right
if current is grater than zero the hypothesis was wrong
In conclusion, in diode case, the state of the diode must be found first. After
that, the general algorithm may be applied.
3.1.2 Example
Problem formulation. For the circuit below the operating point (IA, VA) must be
calculated.
R (1k)
IR
IA
I E
(20mA) VA (10V)
Figure 3.1
Solution 1; By hand analysis. The first order approximation model will be

used for the diode.
I. The test of the diode state. The second algorithm will be used.
1. One supposes that the diode is reverse biased. That means that the diode
will be replaced as figure 3.2 shows:
Figure 3.2 The model of a diode reversed biased, first approximation.
2. One models the circuit. The schematic diagram from figure 3.1 is modeled
as figure 3.3 exposes.
3. One determines the voltage across the diode. First of all the network will be
solved. It must be observed that there is only one loop.
E = − VX + IR (3.1)
The only unknown variable is VX. It results:
79
VX R VX VA R
I E I E
VX = −E + IR (3.2)
According to figure 3.4 it may be written:

VA=VX (3.3)
Finally, from (3.2) and (3.3) VA becomes:
VA = −E + IR (3.4)
4. One compares the voltage value with zero. The value of VA is:
VA = −10 + 20 × 1 = 10V > 0 (3.5)
The value of 10V is an impossible value. The only meaning of this value is that
diode is forward biased. Once again, this is not the real value of the voltage
across the diode.
Keeping in mind that the diode is forward biased one can pass at the next step:
II The calculation of the operating point.
1. The modeled circuit .The diode will be replaced as figure 3.5 shows. The
modeled circuit is presented in figure 3.6.
R
(1)
IR
IA
I (I) (II) E
Vx VA
2. The system of equations:

(1) I-IA-IR=0 (3.6)
(I) 0=VX (3.7)
(II) E=IRR (3.9)
This system has three unknown variables: IA, VX and IR.
3. The problem solution. For IA:
80
E 10
IA = I − IR = I − = 20 − = 10mA (3.10)
R 1
For VA must be observed that:
VA=VX=0V (3.11)
Solution 2. SPICE analysis. It is a solution that involves SPICE simulation.
The results are presented in figure 3.7
Figure 3.7
It must be observed that the results are similar in spite of the grosser
approximations involved by first order diode model.
3.2 By Hand Small-Signal Analysis
A common approach to hand analysis of signal processing circuits is to find the

DC operating point using large-signal model of the device, and then linearize
the characteristic around the DC bias operating point in order to examine what
happens with signal that vary around the DC point bias. Mathematically, as it
had been shown in the previous chapter, linearization of device (diode)
characteristics amounts to taking a Taylor expansion of the device non-linear
characteristic at DC bias operating point and retaining only the linear terms in
expansion. This section shows how the small-signal device (diode) model can
be applied efficiently so that the results for more core complex circuits can be
obtained with minimum of algebra. It treats:
1. Algorithm presentation;
2. Example
3.2.1 Algorithm Presentation
This algorithm follows the same steps like large-signal algorithm, but, at least,
two differences exist.
the small-signal model of the diode is used;
81
there is no need to test the diode bias, because in small-signal

conditions they are operating forward bias.
Under these circumstances, the algorithms becomes:
a.) Modeling of electric and electronic devices (components). At
this step, their models replace the electric and electronic devices
(components). The small-signal circuit is obtained. A list of small-
signal models for the electrical component is presented bellow:
Electrical component Small-signal model
R R
C C
great values ( µF )
L L
great values (mH)

E
+ - E
b.) The small-signal circuit is analyzed using appropriate technique

(Kirchhoff, Laplace, etc…). One obtains a system of equations.
c.) One solves the algebraic problem
3.2.2 Example
Problem formulation. For the circuit presented in figure 3.8 the voltage across
the load resistor operating (RL) must be calculated (the frequency of AC source
is 1kHz).
Solution 1; By hand analysis.. As it had been mentioned, any small-signal
analysis starts with a large signal analysis involving DC operating point. The
DC operating point is necessary for calculating the parameter small-signal
model. By consequence:
82
+E (10V)
R (1K)
C
10 µF D
+
Va
(10mV) RL (1K)
-
Figure 3.8
I.) DC bias operating point calculation; The schematic diagram presented in

figure 3.8 may be re-drawn according to DC condition as figure 3.9 exposes.
R (1K) D
+E (10V) RL (1K)
Figure 3.9
II.) The test of the diode state.

1. One supposes that the diode is forward biased. That means that the diode
will be replaced as figure 3.9 shows:
Figure 3.9 The model of a diode forward biased, first approximation.
2. One models the circuit. The schematic diagram from figure 3.9 is modeled
as figure 3.10 exposes.
3. One determines the current through the diode. This is:
E
IA = (3.12)
R + RL
83
R D IA
+E RL
Figure 3.10
4. One compares the current value with zero. The value of IA is:
10
IA = = 5 mA > 0 (3.13)
1+ 1
This means that the diode is forward biased.
III.) The calculation of the DC operating point.
1. The modeled circuits. The modeled circuit is presented in figure 3.10 (the
same).
2. The system of equations is formed by 3.12 equation.
3. The problem solution. For IA the solution is presented in 3.13:
E 10
IA = I − IR = I − = 20 − = 10mA (3.14)
R 1
For VA must be observed (according to first order approximation model) that:
VA=0V (3.15)
IV.) The calculation of the DC voltage across the load resistor.
VL=IARL=5 V (3.16)
V.) The calculation of the small-signal parameters. for diodes the only small-
signal parameter is the small-signal conductance given by (2.146) formula.
ga = 40 IA = 40 × 5 = 200 mS (3.17)
That means that small-signal resistance is:

1 1
ra = = = 0.005kΩ = 5Ω (3.18)
ga 200
VI.) By hand small-signal analysis..

1. The small signal circuits . The modeled circuit is presented in figure 3.11.
84
C Ia Il ra
Ir
+
Va
R RL
-
Figure 3.11
2. The system of equations is:

Ia=Il+Ir (3.19)
Va=IaR (3.20)
0=Ilra+IlRL-IrR (3.21)
The system contains three equations and three unknown variables (Ia, Il, Ir)
3. The small-signal problem solution. Observing that:
Vl=IlRL (3.22)
one obtains finally:
RL 1
Vl = Va = 10 ≈ 10mV (3.23)
ra + RL 0.005 + 1
VII.) General solution. The general solution my be written as a sum of two

terms:
DC term
AC term
as (3.24) formula shows:
v L = VL + Vl sin(ωt ) = 5 + 10 × 10−3 sin(2000πt ) V (3.24)
Solution 2. SPICE simulation

It is a solution that involves SPICE
simulation. The results are
presented in figure 3.12
Figure 3.13 presents AC analysis.
The final solution is:
Figure 3.12
85
v L = 4.6595 + 9.80043 × 10−3 sin(2000πt ) V (3.25)
In closing, comparing the results, it must be observed that they are quite
comparable.
Figure 3.13
3.3 Rectifiers
The term rectifier designates electronic circuits that transform AC energy into
DC energy. Their principle of operation relies on a simple idea: The sinusoidal
AC power wave is twisted so that a DC component appears. In fact the rectified
signal is combination of an AC signal and a DC component. The DC part of the
rectified signal is of interest. The AC constituent of the rectified signal – called
ripple – is un-welcomed. It is desirable to remove it by low-pass filters.
This section treats the principal types of rectifiers:
1. Half–wave rectifier;
2. Full-wave rectifier;
3. Filtering;
4. Split rectifier
5. Voltage multiplier
3.3.1 Half-Wave Rectifier
a.) schematic diagram is presented in figure 3.14
b.) parts function
86
Vs AC power source
D non-linear element; its role is to twist the shape of the wave;
RL load resistor;
c.) circuit operation; vA
when v s is positive, diode D conducts and iL

+ D
allows the current from source to flow
through load resistor; the voltage v L is Vs
RL vL
positive and equals v s. -
when v s is negative, diode D is blocked.
No current is circulating through load
resistor; the voltage v L is zero. Figure 3.14
in consequence, the mean value of vL is positive

d.) large-signal analysis
It treats:
DC component (VL) calculation;
output characteristic;
diode stress;
efficiency.
d1 ) DC component calculation.
As it had been said, the voltage across the load resistor, v L, has two
components:
v L=VL+v l (3.27)
where:
vL the total instantaneous value of the voltage;
VL DC component of the voltage;
vl AC component of the voltage.
The purpose of this section is to calculate UL vA
value. The algorithm presented at 3.1
paragraph will be followed. iL
+ D
I.) The diode state Vs
RL vL
1. One assumes that the diode is forward -
biased. The circuit from figure 3.14 is
modeled according to this assumption.
Figure 3.15 presents this new circuit Figure 3.15
2. One solves the circuit.

Va sin(ωt ) = iLRL (3.28)
87
3. One tests the current value:

Va
iL = sin(ωt ) (3.29)
RL
It may be observed that:

> 0 if ωt ∈ U (2kπ, (2k + 1)π)

iL ⇒  k∈Z
(3.30)
< 0 if ωt ∈ R − U (2kπ, (2k + 1)π )
 k∈Z
Conclusion:
During the part of the wave when the input is positive, the diode is
forward biased.
During the part of the wave when the input is negative the diode is
reversed biased.
II.) The voltage calculation
A. ωt ∈ U (2kπ, (2k + 1)π)
k ∈Z
. Diode is forward biased. One can use the
schematic diagram from figure 3.15. It

vA
results:
v L = VS sin(ωt ) (3.31) iL
+ D
Vs
B. ωt ∈ R − U (2kπ, (2k + 1)π) . Diode is RL vL
k∈Z
-
reversed biased. The schematic diagram
from figure 3.14 must be modeled as figure
3.16 shows. It results: Figure 3.16
vL = 0 (3.32)
Finally, one can write:

Vs sin(ωt ) if ωt ∈ U (2kπ, (2k + 1)π)

vL ⇒  k∈Z
(3.33)
 0 if ωt ∈ R − U (2kπ, (2k + 1)π)
 k∈Z
Figure 3.17 displays the waveforms associated with v L.

The DC component may be calculated according to (3.34).
T
1
T ∫0
VL = v(t )dt (3.35)
88
Replacing (3.34) in (3.35) one finds:

Vs
VL = (3.36)
π
Vs
Similar, for current follows: ωt
VL V 1π 2π 3π 4π 5π
IL = = s (3.37)
RL πRL vL
Vs
d2 ) Output characteristic is represented
by the dependence: VL
ωt
VL=VL(IL) (3.38)
Figure 3.17
The explicit form of (3.38) is given by
(3.36), and is shown on figure 3.18
One can observe that in real situations the output characteristic curve is not a
parallel to X axis due to internal resistance. In fact, this resistance may be
calculated – as the figure 3.18 emphasizes – according to (3.39) formula:
ideal real
VL
characteristic characteristic
∆VL
∆I L IL
Figure 3.18
∆VL
r=− (3.39)
∆IL
d3.) diode stress.

At this point of the analysis two electrical parameters are important:
maximum forward current through the diode (IFM), and
maximum reverse voltage across the diode (VRM)
The maximum forward current may be estimated inspecting figure 3.15. One
finds:
Vs
IFM = (3.40)
RL
The maximum reverse voltage may be estimated inspecting figure 3.16. This
time, one finds:
VRM=Vs (3.41)
These last two values are important for designers engineering.
89
d4) efficiency
Efficiency is evaluated as being the ratio between DC power generated by the
rectifier, and the input AC power. For this type of rectifier the efficiency is
around 40%. It is a small figure.
e.) SPICE simulation
Figure 3.19 shows the circuit utilized for simulation. As AC source a stimulus
was used. It follows:
v s [V ] = 10 sin(100πt ) (3.42)
Figure 3.19
The results are presented in 3.20 figure and they confirm by hand analysis.
Figure 3.20
Observation: In practical situations, instead of an AC stimulus a transformer

is used. The real schematic diagram becomes:
90
vA
Tr
iL
+ D
Vin Vs RL vL
Figure 3.21
3.3.2 Full-Wave Rectifier

a.) schematic diagram is presented in figure 3.22. Figure 3.23 presents just
D4 D1 iL
+
Vs D1 D3 iL
+
RL vL
Vs
- RL vL
D2 D3
-
D4 D2
another arrangements of the parts. It is also called bridge rectifier.

b.) parts function
Vs AC power source
D1, D2,D3,D4 diode bridge; in many cases the diode bridge is
available as a four-terminal component in a number of
different power and voltage ratings.
RL load resistor;
c.) circuit operation;
when vs is positive, diodes D1 and D2 are conducting (D3, D4 are
blocked) and allow the current from source to flow through load
resistor; the voltage v L is positive and equals v s.
when v s is negative, diodes D3 and D4 are conducting (D1, D2 are
blocked) and allow the current from source to flow through load
resistor; the voltage v L is also positive and equals -v s.
in consequence, the mean value of vL is positive
Similar to half-wave rectifier this section treats:
DC component (VL) calculation;
output characteristic;
91
diode stress
efficiency.
The calculation may simplified if one observe that the diodes act to route the
current from both halves of AC wave through the load resistor in the same
direction, and the voltage across the load resistor becomes the rectified output
signal. In fact, for the positive part of AC wave, the diodes D1 and D2 are
forward biased and the diodes D3 and D4 are reversed biased. The circuit from
figure 3.23 is modeled in figure 3.24. For the negative part of AC wave, the
diodes D1 and D2 are reverse biased and the diodes D3 and D4 are forward
iL current iL current
+ D1 D3 - D1 D3
Vs Vs
RL vL RL vL
- +
D4 D2 D4 D2
biased. The circuit from figure 3.23 is modeled in figure 3.25.

Inspecting these two figures, one can write:
v L = VS sin(ωt ) (3.43)
Figure 3.26 displays the waveforms associated with v L.

Vs
ωt
1π 2π 3π 4π 5π
vL
Vs
VL
ωt
Figure 3.26
Replacing (3.43) in (3.35) follows:

2Vs
VL = (3.44)
π
and hence for current:
92
2Vs
IL = (3.45)
πRL
d2 ) Output characteristic is – as (3.44) shows - a constant. The considerations

made for half-wave rectifier are still good.
d3.) diode stress.
The maximum forward current and the maximum reverse voltage may be
estimated inspecting figure 3.24 (or 3.25). One finds:
Vs
IFM = (3.46)
RL
Vs
VRM= (3.47)
2
d4) efficiency
For this type of rectifier the efficiency is around 80%, double, related to half
wave rectifier.
Figure 3.27 shows the circuit utilized for simulation. The same AC source was
used as stimulus.
v s [V ] = 10 sin(100πt ) (3.48)
Figure 3.27
The result are presented in 3.28 figure and they confirm by hand analysis. In
fact a difference exists: The rectified signal is 1.2V smaller than the source
voltage. That is because the PN diode turn-on voltage is 0.6V
93
Figure 3.28
Observation: In practical situations, the real schematic diagram becomes:

D4 D1 iL
Vin Vs RL vL
D2 D3
Figure 3.29
It must be also mentioned that for full wave rectifier there is also possible
another topological solution:
D1
Tr
iL
Vs
Vin RL vL
Vs
D2
Figure 3.30
3.3.3 Filtering
As it had been stated, the rectified waveforms have two components;
a DC component, and;
94
an AC component (ripple)
The AC component is not desirable. It must be removed. This may realized
using smoothing filters. These smoothing filters are, in fact, low-pass filters.
They may be designed using capacitors or bobbins. For small powers,
capacitors are used. That’s the reason why only capacitive filters will be
analyzed from now on. Figure 3.31 shows such a solution.
a.) schematic diagram
D4 D1 iC iL
+
Vs
C RL vL
-
D2 D3
Figure 3.31
b.) parts function

Vs AC power source
D1, D2,D3,D4 diode bridge; in many cases the diode bridge is
RL load resistor;
C capacitor used for filtering; its value is chosen in order
to ensure small ripple, by making the time constant for
discharging much greater than the period of the wave
forms.
c.) circuit operation;
when one of the pairs of diodes is conducting, (D1 D2 or D3, D4) the
current from the source is flowing both through the load resistor and
through the capacitor; the voltage v L is positive and equals v s; in this
short period of time the capacitor is recharging.
when the diodes are blocked, the current through the load resistor is
assured by the capacitor which is discharging; the voltage v L is also
positive
in consequence, the mean value of vL is positive and due to discharging
process of the capacitor the waveforms are very smooth.
Tacking into account the assumption regarding the capacitor, the large signal
analysis will be made related to wave-forms exposed in figure 3.32.
95
Vs VL Vl
IM
IL
t
t0 charging current
Figure 3.32
The notation used in figure 3.32 are:

Vs AC amplitude of the power supply;
VL DC component on the load resistor;
Vl AC amplitude of the ripple;
IM maximum value of the re-charging current;
t0 re-charging time interval
DC component may be easier evaluated using charge conservation law applied
for the capacitor. One notes:
q = 2CVl
c
(3.49)
qd = IL (T − t 0 ) ≅ IL T (3.50)
where:
qc re-charging charge;
qd dis-charging charging;
T signal period,
This last approximation is allowed only if the time constant τ = RLC is much
greater than T – period of the wave forms. This was stated at the beginning of
this analysis. In these conditions T>>t0.
But,
qc=qd (3.51)
and therefore:
IL (T − t0 ) ILT
Vl = ≅ (3.52)
2C 2C
96
Inspecting figure 3.32 one notices:

VL=Vs -Vl (3.53)
and finally:
IL (T − t 0 ) IT
VL = Vs − ≅ Vs − L (3.54)
2C 2C
In closing, must be emphasized that grater the capacitor is, grater the DC
component is and in the same time smaller the ripple are.
d2 ) Output characteristic is exposed by 3.54 equation and is displayed in figure
3.33.
VL
Vs
IL
Figure 3.33
This time – regardless of the other rectifiers analyzed above – the DC output
voltage is decreasing while DC output current increases. The maximum value
of DC voltage is Vs and it occurs when the output current is zero.
d3.) diode stress.
The maximum forward current and the maximum reverse voltage may be
estimated inspecting figure 3.24 (or 3.25). For the current estimation, the law of
charge conservation must be once again applied. This time the re-charging
charge one writes as:
qr=IMt0 (3.55)
Replacing this formula into (3.51), the current becomes:
T
IFM ≅ IL (3.56)
t0
For voltage one finds:

VRM=Vs (3.57)
d4) efficiency
For this type of rectifier the efficiency is around 80%, double, related to half
wave rectifier.
97

Figure 3.34 shows the circuit utilized for
simulation. The same AC source was used
as stimulus.
v s [V ] = 10 sin(100πt ) (3.58)
The result are presented in 3.35 figure and Figure 3.34

they, once again, confirm by hand analysis.
Regarding figure 3.35, it must be stressed that the first 20 mS represent
transient solution.
Figure 3.35
3.3.4 Split Rectifier

In modern circuitry, there are a lot of circuits that requires power supply able to
provide both positive and negative voltages. On their turn, these power
supplies require special rectifiers. This section presents a solution for these
kinds of rectifiers. Because, they are
a.) schematic diagram is shown in figure 3.36
b.) parts function
Vs AC power source
D1, D2, D3, D4 diode bridge; in many cases the diode bridge is
C capacitors used for filtering;
c.) circuit operation the presence of the ground point between those two
capacitors, make possible the existence of both positive and negative output
voltages.
98
+V
C
D4 D1
+
Vs
-
D2 D3 C
-V

The circuit presented in figure 3.31 is in fact a filtering rectifier. Previous
section presented by hand analysis for this kind of rectifiers, analysis that is still
good in this case.
Figure 3.37 shows the circuit utilized for simulation. One may observe that two
load resistors and an AC source were added. The stimulus is described by the
(3.58) equation. The waveform for positive and negative output voltage are
presented in figure in 3.38
Figure 3.38
3.3.5 Voltage Multipliers.

For reasons of simplicity of presentation, for this type of circuit, one assumes
that the load doesn’t draw a significant charge from the capacitors.
99
a.) schematic diagram of a doubler circuit is shown in figure 3.39.
D1
+
+
Vs
C1
-
2Vs
C2
-
D2
Figure 3.39
b.) parts function

Vs AC power source
D1, C1, half-wave rectifier with capacitive load; it is working on
the positive half wave.
D2, C2, half-wave rectifier with capacitive load; it is working on
the negative half wave.
c.) circuit operation
when D1 conducts (D2 is blocked) C1 is charged at +Vs;
when D2 conducts (D1 is blocked) C2 is charged at -Vs;
the output voltage is the total drop voltage across C1 andC2 and it is 2Vs.
In order to simplify the analysis an observation must be made: the two diodes
may operate into three “states”:
D1 forward biased and D2 reverse biased; it happens a short period of
time t01 during the positive half-cycle.
D2 forward biased and D1 reverse biased; it happens a short period of
time t02 during the negative half-cycle.
D1 reverse biased and D2 reverse biased; it happens for the rest of the
time.
So, for t01 period the circuit from figure 3.39 may be modeled as figure 3.40
shows. The current iC1 charges the capacitor C1 at the peak value Vs. For t02
period the circuit from figure 3.39 may be modeled as figure 3.41 shows. The
current i C2 charges the capacitor C2 also at the peak value Vs.
100
D1
+ D1 -
+
Vs Vs
C1 Vs C1
iC1 iC1
-
- +
+
C2 C2 Vs
-
D2 D2
For the rest of the time figure 3.42 exposes the circuit model. One can observe
that the output voltage is the sum of the capacitors voltages and equals 2Vs.
+ D1
+
Vs C1
- -
2Vs
C2
D2

Figure 3.43 shows the circuit utilized for simulation. The stimulus is also
described by (3.58) equation. Figure 3.44 confirms by hand analysis.
Figure 3.43
101
Figure 3.44 shows other topological solution for a doubler, and figure 3.45
exposes a four-time multiplier.
3Vs
Vs Vs 2Vs
+ C1 + C1 C3
Vs Vs
D1 D2 D1 D2 D3 D4
- -
C2 C2 C4
2Vs 2Vs 2Vs
4Vs
3.4 Clipping Circuits
This section is dedicated to those circuits used to limit the voltage swings to
references voltages. It treats:
1. Clipping up circuits
2. Clipping down circuits
3. Bilateral clipping circuits
3.4.1 Clipping-down Circuits
There are two possible topological arrays: series and parallel configurations
a.) schematic diagram
Figure 3.46 shows a series configuration. Figure 3.47 exposes parallel
configuration.
D R
R
D
vIN vO vIN vO
E E
b.) parts function

E, R clipping voltage
D, clipping diode.
102
v IN input voltage
vO output voltage
c.) circuit operation (fig.3.46)
when v IN>E diode D is conducting; v O equals vIN
when v IN<E diode D is blocked; vO equals E
In consequence, the diode cuts any voltage lower than E
Only the series circuit will be analyzed. In order to highlight the circuit
operation, the transfer characteristic will be developed:
v O=v O(v IN) (3.59)
I.) The diode state
1. One assumes that the diode is forward biased. The circuit from figure 3.46 is
iA D iA D
R R
vIN vO vIN vO
E E
modeled according to this assumption. Figure 3.48 presents this new circuit.
-E=-v IN+iAR (3.60)
v IN − E
iA = (3.61)
R
and hence:
> 0 if v IN > E
iA ⇒  (3.62)
< 0 if v IN < E
Conclusion:
The diode is forward biased if v IN>E
The diode is reversed biased if v IN<E.
103
A. v IN>E; Diode is forward biased. Inspecting figure 3.48 one finds:

v O=v IN (3.63)
B. v IN<E. Diode is reversed biased. The schematic diagram from figure 3.46
must be modeled as figure 3.49 shows. It results:
v O=E (3.64)
v if v IN > E
v O ⇒  IN (3.65)
E if v IN < E
Figure 3.50 displays the characteristic.
vO
vIN

The simulation was made using the circuit from figure 3.51. Input voltage, Vin,
Figure 3.52
swept linear between -10V and 10V with an increment of 0.1V. The transfer
characteristic is presented in figure 3.52. One can observe that those two
104
characteristics – the one obtained using by hand large-signal analysis

techniques, and the other using SPICE techniques – are very similar.
3.4.2 Clipping-up Circuits
There are – also - two possible topological arrays: series and parallel
configurations
a.)schematic diagram
Figure 3.53 shows a series configuration. Figure 3.54 exposes parallel
configuration.
D R
R
D
vIN vO vIN vO
E E
b.) parts function

E, R clipping voltage;
D, clipping diode;
v IN input voltage;
vO output voltage.
c.) circuit operation (fig.3.46)
when v IN<E diode D is conducting; v O equals v IN
when v IN>E diode D is blocked; v O equals E
In consequence, the diode cuts any voltage higher than E
Only the series circuit will be analyzed in order to develop the transfer
characteristic (3.59). The parallel configuration is very similar, and leads to the
same results.
I.) The diode state
1. One assumes that the diode is forward biased. The circuit from figure 3.53 is
modeled according to this assumption. Figure 3.55 presents this new circuit.
E=v IN+i AR (3.66)
105
E − v IN
iA = (3.67)
R
and hence:
iA D iA D
R R
vIN vO uIN uO
E E
> 0 if v IN < E
iA ⇒  (3.68)
< 0 if v IN > E
Conclusion:
The diode is forward biased if v IN<E
The diode is reversed biased if v IN>E.
A. v IN<E; Diode is forward biased. Inspecting the figure 3.55 one finds:
v O=v IN (3.69)
B. v IN>E. Diode is reversed biased. The circuit diagram from the figure 3.53
must be modeled as figure 3.56 shows. It results:
v O=E (3.70)
v if v IN < E
v O ⇒  IN (3.71)
E if vIN > E
Figure 3.57 displays the characteristic.
vO
vIN
106

The simulation was made using the circuit from figure 3.58. Input voltage, Vin,
swept linear between -10V and 10V with an increment of 0.1V. The transfer
characteristic is presented in figure 3.52. One can observe, like it was done in
the previous section, that those two characteristics – the one obtained using by
hand large-signal analysis techniques, and the other using SPICE techniques –
are very similar.
Figure 3.59
3.5 Clamping Circuits
These circuits are able to establish a DC reference for an output voltage.

a.) schematic diagram is presented in
figure 3.60
+
b.) parts function C
Vs D uO
D diode clamp; it does not -
allows capacitor
discharging;
C capacitor; it may be Figure 3.60
charged only through the
diode.
107
c.) circuit operation because the anode of the diode is grounded, the output
voltage must be always positive; in this case it will be sinusoidal, and it will vary
between zero and 2Vs.
The output voltage will be calculated. One can write:
Vs sin(ωt ) = u A + uC (3.72)
During the first period (transient period) the capacitor is charged. Its voltage
equals the positive peak voltage of the AC source and after that (because there
is no way of discharging –except eventually the load ) it can not be discharged.
That means that in steady-state conditions:
uC=Vs (3.73)
In the same time, the voltage across the diode is
u A = Vs sin(ωt ) − uC = Vs sin(ωt ) − Vs = − Vs [1 − sin(ωt )] (3.74)
One observes that the voltage across the

diode has two components:
an AC component that equals
“ Vs sin ωt ”
a DC component that equals “-Vs”
In other words the voltage across the diode is
varying between 0 and 2Vs. This is the output
voltage. Figure 3.61
Figure 3.61 shows the circuit utilized for simulation.
Figure 3.62
108
The stimulus is described by (3.58) equation. The waveform across the

capacitor C1 and the diode D1 are presented in figure in 3.62 One can observe
that after almost 20 mS the circuit enters in steady-state conditions. The output
voltage has a DC component that equal 10 volts
109
Problems
Problem 1 This problem is regarding the half-wave rectifier circuit. For the half-
wave rectifier presented in figure 1 find the D
effective value of the AC source if the DC load iIN
voltage (VL) has 12V. The diode may be modeled
using the first order model. vS RL vL
Solution:
In accordance with (3.36), the peak value (Vs) of Figure 1
the AC source is:
Vs = πVL (1)
and by consequence, the effective value is:

Vs π
Veff = = VL ≅ 26.73V (2)
2 2
wave rectifier presented in figure 1 find the maximum value of the reverse
voltage on the diode, if the DC load voltage (VL) has 12V. The diode may be
modeled using the first order model.
Solution:
(3.41) formula shows that the maximum value of the reverse voltage (VRM) is:
VRM=Vs=37.698 V (3)
wave rectifier presented in figure 1 find the DC component and the peak value
of the load current, if the DC load voltage (VL) has 12V and load resistor (RL)
has 12 Ω . The diode may be modeled using the first order model.
Solution:
a.) According to (3.37) the DC component of the load current is:
VL 12
IL = = = 1A (4)
R L 12
b.) The peak value of the load current is:
110
Vs 37.698
IL = = ≅ 3.14 A (5)
MAX
RL 12
Problem 4 This problem is regarding the bridge rectifier circuit. For the bridge
rectifier presented in figure 2 find the effective value of the AC source if the DC
load voltage (VL) has 12V. The diode may be modeled using the first order
model.
D4 D1 iL
+
Vs
RL vL
-
D2 D3
Figure 2
Solution:
From (3.44) results:
π
Vs = VL (6)
2
and hence:
Vs πVL
Veff = = ≅ 13.37 V (7)
2 2 2
rectifier presented in figure 2 find the maximum value of the reverse voltage
upon a diode, if the DC load voltage (VL) has 12V. The diode may be modeled
using the first order model.
Solution:
The maximum reverse voltage in this case may be calculated considering
(3.47) formula:
Vs
VRM= ≅ 9 .42 V (8)
2
It was considered that the two diodes are identically.
111
rectifier presented in figure 2 find the DC component and the peak value of the
load current, if the DC load voltage (VL) has 12V and load resistor (RL) has 12
Ω . The diode may be modeled using the first order model.
Solution:
a.) The DC component of the load current is:
VL 12
IL = = = 1A (9)
R L 12

Vs πVL 3.14 × 12
IL = = ≅ = 1.57 A (10)
MAX
RL 2R L 2 × 12
Problem 7 This problem is regarding the full-wave rectifier circuit. For the full-
wave rectifier presented in figure 3, find the effective value of the AC source if
the DC load voltage (VL) has 12V. The diode may be modeled using the first
order model.
D1
Tr
iL
Vs
Vin RL vL
Vs
D2
Figure 3
Solution:
From (3.44) results:
π
Vs = VL (11)
2
and hence:
Vs πVL
Veff = = ≅ 13.37 V (12)
2 2 2
112
wave rectifier presented in figure 3, find the maximum value of the reverse
voltage upon a diode, if the DC load voltage (VL) has 12V. The diode may be
modeled using the first order model.
Solution:
figure 4. One observes that:
D1
Tr
iL
vs
vin RL vL
vs
vR
D2
Figure 4
v R=2v s (13)
v R reaches its peak value, when v s reaches its own peak value. That means:
π
VRM=2Vs = 2 VL ≅ 37.689 V (14)
2
wave rectifier presented in figure 3, find the DC component and the peak value
of the load current, if the DC load voltage (VL) has 12V and load resistor (RL)
has 12 Ω . The diode may be modeled using the first order model.
Solution:
a.) The DC component of the load current is:
VL 12
IL = = = 1A (15)
R L 12

Vs πVL 3.14 × 12
ILMAX = = ≅ = 1.57 A (16)
RL 2R L 2 × 12
Problem 10 This problem is regarding the filtering rectifier circuit. For the
filtering rectifier circuit presented in figure 5, find the effective value of the AC
113
source if the DC load voltage (VL) has 12V. The diode may be modeled using
the first order model. Assume that RL=1.2k Ω and C=1000 µF and the
frequency of AC source is 50 Hz.
D4 D1 iC iL
+
Vs
C RL vL
-
D2 D3
Figure 5
Solution:
First of all, it must be made the comparison between the time constant:
τ = R L C =1200mS (17)
and the period T of the waveforms. Because the AC frequency source is 50Hz
the period is :
T=10mS (18)
Comparing (17) with (18) results:
τ >> T (19)
That means that the approximate analysis presented in section 3.3.3. is still
good. In these conditions Vs may be estimated using (3.54)
IL T VT
Vs ≅ VL + = VL + L =
2C 2CRL
(20)
12 × 10 × 10 −3
= 12 + = 12.05 V
2 × 1000 × 10 −6 × 1.2 × 103
The effective value is:
Vs
Veff = ≅ 8.55V (21)
2
filtering rectifier circuit presented in figure 5, find the maximum value of the
reverse voltage across a diode, if the DC load voltage (VL) has 12V. The diode
may be modeled using the first order model. Assume that RL=1.2k Ω and
C=1000 µF and the frequency of AC source is 50 Hz.
114
Solution:
(3.57)
VRM=Vs ≅ 12 V (22)
filtering rectifier circuit presented in figure 5, find the ripple value, if the DC
load voltage (VL) has 12V. The diode may be modeled using the first order
model. Assume that RL=1.2k Ω and C=1000 µF and the frequency of AC source
is 50 Hz.
Solution:
According to (3.52)
IL T 12 × 10 × 10 −3
Vl ≅ = = 50mV (23)
2C 2 × 1000 × 10 −6 × 1.2 × 10 3
Problem 13. This problem is regarding the clipping circuits. For the circuit
presented in figure 6, sketch the expected output waveforms when a 100Hz
sine wave with a peak-to-peak voltage of 10 V is applied.
R1(1k) D E (2V)
iIN
R2
vIN vO
2K
Figure 6
Solution: Three steps must be followed:

determination of the diode state;
calculation of the transfer characteristic;
v O=v O(v IN) (24)
sketching the output waveforms according to (24)
The first order approximation model will be used for the diode.
I. The test of the diode state.
1. One supposes that the diode is forward biased.
2. One models the circuit. The circuit from figure 6 will be modeled as figure 7
displays:
115
R1(1k) D E (2V) R1(1k) D E (2V)

iIN iIN
+ +
R2 vA R2
vIN vIN
2K 2K
- -
Figure 7 Figure 8
3. One determines the current through the diode (iIN). First of all the network will
be solved. It must be observed that there is only one loop.
v IN-E=iINR1+i INR2 (25)
v IN − E
iIN = (26)
R1 + R2
4. One compares this expression with zero. It results:

a) v IN>E the diode is forward biased;
b) v IN<E the diode is reversed biased;
II The calculation of the transfer characteristic (24).
a.) uIN>E
1. The modeled circuit is shown in figure 7.
2. The system of equations is represented by the equation (25)
3. The problem solution is:
R2
v O = (v IN − E) (27)
R1 + R2
b.) uIN<E
1. The modeled circuit is shown in figure 8.
2. The system of equations is represented by the equation (28)
iIN=0 (28)
3. The problem solution is:
vO = 0 (29)
116
Figure 9 presents the transfer characteristic:
R2 2 5V vIN
Slope R + R = 3
1 2
vO
vO 2V
t
2V vIN -5V
Figure 9 Figure 10
III.) The output waveforms are presented in figure 10 It must be observed the
maximum value of the output voltage is obtained when input voltage is
maximum.
(
v OMAX = v INMAX − E ) R R+ R = (5 − 2) 1 +2 2 = 2 V
2
(30)
1 2
Problem 14. This problem is regarding the clipping circuits. For the circuit
presented in figure 11, sketch the expected output waveforms when a 100Hz
sine wave with a peak-to-peak voltage of 20 V is applied. The first order
approximation model will be used for the diodes.
R2(2k) D2 E2(2V)
iIN
R3
vIN R1(1k) D1 E1(1V) vO
3K
Figure 11
Solution:
2
Because there are two diodes, there are 4 states (2 ). Table 1 presents these
states noted Σ i i = 1∴ 4 .
117
D1 D2
Σ1 non conducting non conducting
Σ2 conducting non conducting
Σ3 non conducting conducting
Σ4 conducting conducting
Table 1
It is very possible that, when v IN is supposed to vary between −∞ and + ∞ , in

order to settle (24), the circuit will pass through these four states. In this
condition becomes necessary to determine the circuit state related to v IN range
of variation. So, in order to sketch the expected output waveforms, it is
necessary to follow the next procedure:
I. state allocation; at this step one determines the
correspondence between v IN and the state of the circuit;
II. calculation of the transfer characteristic (24);
III. sketching the output waveforms according to (24)
I.) State allocation.
1. The selection of the start state. The analysis may begin from any state. But,
assuming that v IN ∈ (−∞,+∞ ) , for this case, it is recommended to select as start
state, Σ 3 . This selection was made observing that if v IN → −∞ D1 is blocked (a
very high negative voltage on its anode) and D2 is conducting (a very high
negative voltage on its cathode). According to this assumption one models the
circuit. The circuit from figure 11 will be modeled as figure 12 displays:
R2(2k) D2 E2(2V)
iA2
vA1
R3
3K
Figure 12
The mathematical conditions for the existence of Σ 3 are:
v A1<0 (31)
and
118
i A2>0 (32)
and the next problem may be formulated: find the limits of variation for vIN so
that (31) and (32) are simultaneously satisfied. The answer may be found
solving the circuits. Applying Kirchhoff second theorem on the doted mesh
(figure 12), one finds:
E2=v IN+R3iA2+R2iA2 (33)
Solving (33) results:
E 2 − v IN
iA2 = (34)
R2 + R3
Introducing (34) in (32) this last one becomes:

E 2 − v IN
>0 (35)
R2 + R3
and hence:
v IN ∈ (−∞, E 2 ) (36)
or
v IN ∈ (−∞,2) (37)
v A1 may be calculated applying Kirchhoff second theorem on the doted mesh

from the circuit drawn in figure 13
R2(2k) iA2 D2 E2(2V)
vA1
R3
3K
Figure 13
E2-E1=iA2R2+v A1 (38)
Introducing (34) in (38) v A1 becomes:
E 2 R 3 − E 1 (R 2 + R 3 ) + v INR 2
v A1 = (39)
R2 + R3
So, (31) condition may be rewritten:
119
E 2 R 3 − E 1 (R 2 + R 3 ) + v IN R 2
<0 (40)
R 2 + R3
and v IN must respect:

 E (R + R 3 ) − E 2 R 3 
v IN ∈  − ∞, 1 2 
 (41)
 R2 
or:
 1
v IN ∈  − ∞,−  (42)
 2
Because v IN must meet both (37) and (42) restrictions simultaneously one
obtains:
 1  1
v IN ∈ (− ∞,2) I  − ∞,−  =  − ∞,−  (43)
 2  2
 1
Conclusion: If v IN ∈  − ∞,−  D1 is blocked and D2 is conducting
 2 
2. The selection of the second state. There is no restriction in selection of the
second state. But the analysis may be simplified if some observations are
made. In this case, the second state may be picked up observing that when v IN
tends to reach –0.5V, the diode D1 tends to change its state. So it shifts into
conducting state. That is why, Σ 4 (D1 conducting, D2 conducting) is the next
recommended state for analyzing. In the same time, it must be added that the
analysis must be made considering:
 1 
v IN ∈  − ,+∞  (44)
 2 
The circuit from figure 12 is modeled, according to Σ 4 state, in figure 14
R2(2k) D2 E2(2V)
iIN
iA2
iA1
R3
3K
Figure 14
120
The mathematical conditions for the existence of Σ 4 are:
i A1>0 (45)
and
i A2>0 (46)
Kirkhhoff equations for this circuit are:
i IN+i A2=i A1 (47)
E1=-i INR3-i A1R1+v IN (48)
-E1+E2=i A1R1+i A2R2 (49)
The solutions are:
v INR 2 − E 1 (R 2 + R 3 ) + E 2 R 3
i A1 = (50)
R 1R 2 + R 1R 3 + R 2 R 3
− v IN R 1 − E 1R 3 + E 2 (R 1 + R 3 )
iA2 = (51)
R 2 (R 1R 2 + R 1R 3 + R 2R 3 )
v IN (R 1 + R 2 ) − E 1R 2 − E 2R 1
i IN = (52)
R 1R 2 + R 1R 3 + R 2 R 3
Introducing (50) in (45) one finds:

E 1 (R 2 + R 3 ) − E 2R 3
v IN > (53)
R2
or:
 1 
v IN ∈  − ,+∞  (54)
 2 
Applying the same procedure for iA2 results:
− E 1R 3 + E 2 (R 1 + R 3 )
v IN < (55)
R1
or
v IN ∈ (−∞,+5) (56)
Finally (44), (54) and (56) restrictions must be put together:
 1   1   1 
v IN ∈  − ,+∞  I  − ,+∞  I (− ∞,+5 ) =  − ,+5  (57)
 2   2   2 
121
 1 
Conclusion: If v IN ∈  − ,+5  both D1 and D2 are conducting
 2 
2. The selection of the third state. There is, also, no restriction in selection of
the second state. But, in order to simplify the analysis, may be observed that
around +5V, D2 diode changes its state. So it shifts into blocking state. That is
why, Σ 2 (D1 conducting, D2 non-conducting) is the next recommended state for
analyzing. In the same time, it must be added that the analysis must be made
considering:
v IN ∈ (+5,+∞ ) (58)
The circuit from figure 12 is modeled, according to Σ 2 state, in figure 15
R2(2k) D2 E2(2V)
vA2
iA1
R3
3K
Figure 15
The mathematical conditions for the existence of Σ1 are:
iA1>0 (59)
and
v A2<0 (60)
The system of equations is (only one):
E1=-iA1R1+v IN-R3 (61)
The solution is:
v IN − E1
i A1 = (62)
R1 + R 3
uA2 may be evaluated using figure 16.
122
R2(2k) D2 E2(2V)
vA2
iA1
R3
3K
Figure 16
Applying Kirchhoff on the doted mesh, one establishes:

-E1+E2=v A2+R1iA1 (63)
Replacing i A1 the final expression for v A2 becomes:
R1 −E 1R 3 + E 2 (R 1 + R 3 )
v A 2 = − v IN + (64)
R 1 +R 3 R1 + R 3
Now the electrical problem is completely solves. These solutions are useful in
studying the range of variation for v IN. Substituting (62) in (59) one reaches at:
v IN>E1=1 (65)
or:
v IN ∈ (+1. + ∞ ) (66)
Substituting (64) in (60) one reaches at:

−E1R 3 + E 2 (R 1 + R 3 ) −3 + 2(1 + 3)
v IN > = =5 (67)
R1 1
or
v IN ∈ (+5,+∞ ) (68)
Putting together (58), (66) and (68) restrictions one gets:

v IN ∈ (+5,+∞ ) I (+1,+∞ ) I (+5,+∞ ) = (+5,+∞ ) (69)
Conclusion: If v IN ∈ (+ 5,+∞) D1 is conducting and D2 is blocked.
So, at the first step of the analysis one concludes that:
123
 1 
  − ∞,− V  ⇒ D1 is blocked; D2 is conducting
 2 
 1 
vIN ∈  − V,+5V  ⇒ D1 is conducting; D2 is conducting (70)
 2 
(+ 5 V,+∞) ⇒ D1 is conducting; D2 is blocked


II. Calculation of the transfer characteristic;
This calculation must be made according to (70)
 1 
1. v IN ∈  − ∞,− V  . v O may be calculated using figure 13:
 2 
v O=-iA2R3 (71)
iA2 is given by (34). Replacing this expression in (71), one obtains:
R3 E 2R 3
vO = v IN − (72)
R 2 + R3 R 2 + R3
Numerical values are:

3 6
vO = v IN − (73)
5 5
 1 
2. v IN ∈  − V,+5 V  . v O may be calculated using figure 14:
 2 
v O=iINR3 (74)
iIN is given by (52). Replacing this expression in (74) one obtains:
(R 2 − R 1 )R 3 (E1R 2 + E 2R 1 )R 3
vO = v IN − (75)
R 1R 2 + R 1R 3 + R 2R 3 R 1R 2 + R 1R 3 + R 2R 3

3 12
vO = v IN − (76)
11 11
3. v IN ∈ (+5 V,+∞ ) . v O may be calculated using figure 15:
v O=iA1R3 (77)
iA1 is given by (62). Replacing this expression in (77) one obtains:
124
R3 E 1R 3
vO = v IN − (78)
R1 + R 3 R1 + R 3

3 3
vO = v IN − (79)
4 4
In conclusion:
3 6  1
 v IN − if v IN ∈  − ∞,− 
 5 5  2 
3 12  1 
vO =  v IN − if v IN ∈  − ,+5  (80)
 11 11  2 
 3 3
 4 v IN − 4 if v IN ∈ (+ 5,+∞ )

This last expression is exposed in figure 17
vO
vO
VT1
(5, 3/11)
t1 t4 t5 t
vIN t2 t3
(-1/2, -3/2)
VT2
Figure 17 Figure 18
III. The output waveforms

The analytical expression of the output waveforms may be found combining the
output voltage function:
v O=v O(v IN) (81)
with the input voltage function;
v IN=v IN(t) (82)
The analytical expression of (81) is given by (80). The two threshold voltages
are noted:
VT1=5V (83)
1
VT2=- V (84)
2
The analytical expression of (82) is given by (85):
125
v IN = Vin sin(ωt ) = 10 sin (100πt ) V (85)
Tacking into account that (80) is multi-defined (it has two points of
discontinuity: VT1 and VT2), the combination of these two functions must be
studied on certain intervals. Figure 18 shows, which is the correspondence
between discontinuity points on voltage domain (VT1, VT2) and the discontinuity
points on time domain (t1, t2, t3, and t4). In fact, they may be expressed as
follows:
 1
− 
V  arcsin 2 
arcsin T 2   10 
  
 Vin   
t1 = = = −0.16mS (86)
ω 100π
V 
arcsin T1  arcsin 
5
 Vin   10 
t2 = = ≅ 1.67mS (87)
ω 100π
V 
π − arcsin T1  π − arcsin 
5
V
 in   
10
t3 = = ≅ 8.33mS (88)
ω 100π
 1
 
V  π + arcsin 2 
π − arcsin T 2   10 
  
 Vin   
t4 = = ≅ 10.16mS (89)
ω 100π
t5=t1+T ≅ -0.16+20=19.34mS (90)
The final solution is:
 R3
 (Vin sinωt) − E2R3 if t ∈ (t4 + kT,t5 + kT)
 R2 + R3 R2 + R3 k ∈Z
 (R2 − R1)R3 (E1R2 + E2R1)R3
R R + R R + R R (Vin sinωt) − R R + R R + R R
 1 2 1 3 2 3 1 2 1 3 2 3
vO(t) =  (91)
 if t ∈[(t1 + kT,t2 + kT) U (t3 + kT,t4 + kT)]
 k ∈Z

R
 3 (V sinωt) − 1 3 − E R 3
if t ∈ (t2 + kT,t3 + kT)
R1 + R3 in R1 + R3 4 k ∈Z

and numerical form:
126
 6
 6sin100πt − if t ∈ (t4 + kT,t5 + kT)
 5 k ∈Z
 30 12
vO(t) =  sin100πt − if t ∈ [(t1 + kT,t2 + kT) U (t3 + kT,t4 + kT)] (92)
 11 11 k ∈Z
15 3
 sin100πt − if t ∈ (t2 + kT,t3 + kT)
 2 4 k ∈Z
Figure 19 shows the graphical representation of (92).

vO
Input waveform
Output waveform
t4 t5 t
t2 t3
Figure 19
127
• Preliminary
• Quasi-Static Large Signal
Behavior
• Quasi-Static Small Signal
Behavior
• DC Biasing
Chapter 4
Bipolar Junction Transistor
The second chapter of this book presented P-N junction. Two important ideas
were there emphasized:
1. through a forward biased junction an important current may pass;
2. through a reverse biased junction, there is almost no current.
This chapter will present a new situation: in special circumstances, through a
reversed biased junction a considerable current may flow. Schockley, Brattain
and Bardeen discovered this phenomenon on December 16, 1947. Public
announcement of the discovery was delayed for six month until June 1948. This
was the birth certificate of a new device: Bipolar Junction transistor (BJT).
The bipolar junction transistor is a multi-junction semiconductor device. When
used in conjunction with the appropriate circuit elements, BJT is capable of
current gain, voltage gain and signal power gain. This chapter reveals the
behavior of this electronic device in large or small signal conditions at various
frequencies. For any of the situations mentioned above, BJT models are
developed. The outline of the chapter is:
The first section whose title is “Preliminary” presents structure, symbol,
the principle of operation and methods of mathematical description
related to the range of operation;
bipolar transistor. The seven-equation system (1.35) ÷ (1.41) is
integrated in quasi-static conditions and Ebers-Moll models (including
SPICE model) are developed. In addition, non-ideal effects such as:
series resistance, high injection, generation-recombination
phenomenon, base-width modulation, junction breakdown, temperature
dependence and thermal run-away are treated. In the following, “I-V
characteristics” both for common emitter connection and for common
base connection are presented. Finally, piecewise linear models for
active model are derived.
129

dynamic large signal conditions. One discusses about charge control
models. Gummel-Poon SPICE model is also presented.
The fourth section presents quasi-static small-signal model. Three
different models are showed: conductances model, hybrid π model, or
fundamental models (and SPICE model as a consequence) and in
closing, ‘h”-parameter model.
The fifth section introduces dynamic small-signal models. The dynamic
small signal model presented in this section completes the hybrid model
by adding the capacitive effects. It is also presented estimation for cut-
off frequency.
The sixth section is dedicated to DC bias circuits. One defines the
quiescent point and an usual biasing circuit is treated.
4.1 Preliminary

3. Methods of mathematical description related to the range of operation;
From the very beginning, it must be mentioned that there are two types of
bipolar transistors:
npn transistor (figure 4.1) and,
pnp transistor (figure 4.2)
emitter collector emitter collector

junction junction junction junction
n++ p n p++ n p
base base
As one can see, a BJT is formed from two back-to-back p-n junctions, one
between the base and the emitter and the other between the base and the
collector. At this point of the discussion, it seems that a transistor may by
assimilated to circuit containing two series diodes. In fact, there are two
important design conditions that make a clear-cut distinction between a
transistor and a circuit formed by two diodes:
130
emitter doped much more heavily than the base and, by consequence,
(when the junction is forward biased) the current that flows through the E-B
junction is almost entirely formed by mobile carriers injected by the emitter;
base very narrow ; that’s why the current injected by the emitter passes
directly into the collector; so, the collector current is almost equal to the
emitter current and is roughly independent of he voltage applied between
the base and the collector.
Because of these two conditions presented above, the two junctions are
electrically coupled. This electrical coupling, due to a proper design of three-
layer structure, generates the so-called transistor effect: the current generated
in a low impedance circuit, the emitter-base, creates a similar current in a high-
impedance circuit, the collector-base. In normal conditions – when transistor
effect exists – the principal current of the transistor (the current that flows
between emitter and collector) is controlled by the voltage across base-emitter
junction.
Figure 4.3 and figure 4.4 show the symbols associated with BJT.
C C
iC iC
vCB vBC
iB iB
B vCE B vEC
vBE vEB
iE iE
E E
where:
E emitter
B base
C collector
iE emitter current vCE collector-emitter voltage
iC collector current vBE base-emitter voltage
iB base current vCB collector-base voltage
Both in figure 4.3 and in figure 4.4 are presented the natural directions for
current and voltages in normal operation conditions. It must be observed that
the differences between those two types of BJT are associated with current and
voltages directions. That is why, in the following, only npn type will be analyzed.
The aim of this section is to explain the transistor effect. This effect comes into
view only if a junction is forward biased and the other is reverse biased. In fact,
the way that these junctions are biased is crucial for BJT behavior. There are
131
only four possible modes of biasing and they are presented in table 4.1. As one
can see, they are also called “regimes” of operation or “regions” of operation.
Forward Active Region (Normal Active Region). Emitter-base junction is
forward biased and collector-base junction is reverse biased. In this situation
the transistor effect appears. Figures 4.5, 4.6 and 4.7 are very useful for
understanding these circumstances.
junction junction junction junction
++
p n p p++ n p
base base
Figure 4.5 A pnp structure with heavy base Figure 4.6 A pnp structure with average base
The physical explication is: at the level of the emitter-base junction (being
forward biased), the injection
emitter collector
phenomenon emerges. There-fore, junction junction
a current flows between base and p
++
n p
emitter. If the base is large enough, emitter collector
larger than the carrier diffusion
length, - figure 4.5 - the whole
emitter current is ended in the
base. Between emitter and base
collector, there is no current. The Figure 4.7 A pnp structure with thin base
structure behaves like two opposite (structure of a pnp transistor)
series diodes. If the base length is comparable with the diffusion length (figure
4.6), a small part of the mobile carriers injected by the emitter in the base, may
reach the collector junction and they are “collected”.
Base-Collector Junction
Forward Bias Reverse Bias
Saturation Region Forward Active Region

Forward
(Closed Switch) (Normal Active Region)
Bias
Base- (Good Amplifier)
Emitter
Reverse Active Region Cutoff Region
Junction
Reverse
(Inverse Active Region) (Open Switch)
Bias
(Poor Amplifier)
Table 4.1
132
They pass through the junction due to the external electric field generated by
the reverse biasing of the collector base junction. This is a poor transistor effect.
Figure 4.7 presents a real structure of a pnp transistor. Because the base is
very thin, much shorter than the diffusion length of the mobile carriers injected
by the emitter, the greatest part of the current that starts from emitter ends in
collector. This is a real transistor effect. The value of this current is
controlled by voltage applied across the emitter-base junction. From this
point of view, when a transistor operates in this region, it behaves as voltage
controlled current source. That’s why it can be used in amplifier circuits. The
operation of the device is illustrated with figure 4.8
vBE vBC
iB
iEp
ICB0
iEBr
iBr
iE iC
iEn iCn
Figure 4.8
At the level of the emitter-base junction, because this junction is forward biased,
injection phenomenon appears. Electrons diffuse from the emitter (n type) to the
base (p type) and holes diffuse from the base into emitter. This carrier diffusion
is identical to that in a p-n junction forward biased. One can see that
recombination currents are predominant:
i Ep recombination current into emitter;
i Br recombination current into base;
i EBr recombination current into depletion region of the emitter base
junction
At the level of the collector-base junction, because this junction is reverse
biased, generation currents are predominant. ICB0 is such a current.
However, what is different is that the electrons can diffuse as minority carriers
through the quasi-neutral region in the base. Once the electrons arrive at the
collector-base depletion region, they are swept through the depletion layer due
to the electric field. These electrons contribute essential to the collector current
(i Cn). Usually, a transport factor is defined as the ratio of the collector and
emitter current:
iC
αF = (4.1)
iE
133
and 0.95 ≤ α F < 1 . In the same time, it is usual – in the transistor theory – to
define another factor:
iC
βF = (4.2)
iB
βF is called current gain and 20 ≤ βF ≤ 500 . These two factors are very
important for further analysis.
Reverse Active Region Emitter-base junction is reversed biased and collector-
base junction is forward biased. It represents an Inverse Active Region. In fact,
the emitter is replaced by the collector and the collector is replaced by the
emitter. One can define also a transport factor, αR , and a current gain, βR This
situation presents no relevancy for real circuitry, because pnp (or npn) structure
is not a symmetrical one.
Saturation Region Both emitter-base and collector base junctions are forward
biased (figure 4.9). The transistor behaves like a closes switch. It allows great
values for the currents at its pins, but the voltages between the terminals are
emitter collector very small.
junction junction
p ++ n p Cutoff Region Both emitter-base and
emitter collector
collector base junctions are reversed
biased. The transistor behaves like an
open switch. It allows great values for
base the voltages between the terminals,
+ - - + but the currents at its pins are very
Figure 4.9 small.
4.1.3 Methods of Mathematical Description

In this case, because the transistor has three terminals (emitter, base and
collector), the complete mathematical description is given by two -and only two -
characteristic equations. These equations may be represented as follows:
diI dn i di dm i
E1( ∫ iI dt, iI , ,K, nI , ∫ i J dt, i J , J ,K, mJ ,
dt dt dt dt
(4.3)
dv IJ dp v IJ dv IK dq v IK
v IJ , ,K, p , v IK , ,K, , θ1,K θ r ) = 0
dt dt dt dt q
diI dni di dm i
E 2 ( ∫ iI dt, iI , ,K, nI , ∫ iJ dt, iJ , J ,K, mJ ,
dt dt dt dt
p
(4.4)
q
dv d v dv d v IK
v IJ , IJ ,K, pIJ , v IK , IK ,K, , θ1,K θr ) = 0
dt dt dt dt q
134
where:
I ≠ J ≠ K ∈ {E,B, C}
i I, iJ instantaneous values of the currents;
vIJ , vIK instantaneous values of the voltages;
θ1, K , θr are non-electric parameters;
As it was discussed in the previous chapter, according to operation conditions,
these equations may be simplified as follows:
1. large-signal quasi-static conditions equations (4.3) and (4.4) become:
E1 (iI ,i J, v IJ , v IK ) = 0 (4.5)
E 2 (iI , iJ, v IJ , v IK ) = 0 (4.6)
or:
i I=i I(vIJ, vIK) (4.7)
i J=i J(vIJ , vIK) (4.8)
Equations (4.7) and (4.8) are usually called static characteristic
equations. They represent “I-V characteristics”
2. large-signal dynamic conditions; equations (4.3), (4.4) become:
 dv dv 
E1  ∫ iI dt, iI , ∫ i J dt, i J , v IJ , IJ , v IK , IK  = 0 (4.9)
 dt dt 
 dv dv 
E 2  ∫ iI dt, iI , ∫ i J dt, i J , v IJ , IJ , v IK , IK  = 0 (4.10)
 dt dt 
3. small-signal dynamic conditions; equations (4.3) and (4.4) become:

dv ij dv ik
ii = g11v ij + g12 v ik + C11 + C12 (4.11)
dt dt
dv ij dv ik
i j = g21v ij + g22 v ik + C 21 + C 22 (4.12)
dt dt
where:
i i, ij small signal currents (instantaneous value);
vij, vik small signal voltages drop (instantaneous
value);
g11, g12, g21, g22 equivalent conductances;
C11, C12, C21, C22 equivalent capacitors;
4. small-signal quasi-static conditions; equations (4.3), (4.4) become:
135
ii = g11v ij + g12v ik
(4.13)
i j = g21v ij + g22 v ik (4.14)
The above presentation, is a general one. Both i i and ij may be i E, iB or iC. In the
same time, vij and vik may be vBE, vBC or vCE. So, it becomes necessary to
establish some criteria for choosing the appropriate currents and voltages,
related to the application in study. The most convenient solution is to consider
the transistor as being a two-port network. Therefore, the mathematical
approach used in two-port theory may be applied in transistor study. According
to this point of view, one discusses about three basic connection of BJT:
• common emitter connection;
• common base connection;
• common collector connection.
Common emitter connection

There are two topological solutions presented in figures 4.10 and 4.11, but only
the solution presented in figure 4.10 is practiced in real circuitry.
iC iC
C C
iB iB
B vCE Output Input vCE B
Input vBE vBE Output
E E
The input parameters are:

• base-emitter voltage;
• base current.
The output parameters are
• collector-emitter voltage;
• collector current.
For this connection characteristic equations are:
1. large-signal quasi-static conditions; equations (4.5) ÷ (4.8) become:
E1 (iC ,iB , v BE , v CE ) = 0 (4.15)
E 2 (iC , iB, v BE , v CE ) = 0 (4.16)
or:
iC=iC(vBE, vCE) (4.17)
iB=iB(vBE, vCE) (4.18)
136
where:
i C, iB instantaneous values of the currents;
vBE, vCE instantaneous values of the voltages;
 dv dv 
E1  ∫ i C dt, i C , ∫ iB dt, iB , v BE , BE , v CE , CE  = 0 (4.19)
 dt dt 
 dv dv 
E 2  ∫ iC dt, iC , ∫ iB dt, iB , v BE , BE , v CE , CE  = 0 (4.20)
 dt dt 
dv be dv
i c = g11v be + g12 v ce + C11 + C12 ce (4.21)
dt dt
dv be dv
ib = g21v be + g22 v ce + C 21 + C 22 ce (4.22)
dt dt
where:
i c, i b small signal currents (instantaneous value);
vbe, vce small signal voltages (instantaneous value);
ic = g11v be + g12 v ce (4.23)
ib = g21v be + g22 v ce (4.24)
Common base connection

There are also two topological solution presented in figures 4.12 and 4.13, but
only the solution presented in figure 4.12 is practiced in real circuitry.
iE E C iC iC C E iE
Input vEB vCB Output Input vCB vEB Output

B B

• emitter-base voltage;
• emitter current.
• collector-base voltage;
137
• collector current.
For this connection characteristic equations are:
E1(iC,− iE , v EB , v CB ) = 0 (4.25)
E2(iC ,− iE , vEB , v CB ) = 0 (4.26)
or:
iC=iC(vEB, vCB) (4.27)
-iE=-iE(vEB, vCB) (4.28)
where:
iC, -iE instantaneous values of the currents;
vEB, vCB instantaneous values of the voltages;
 dv dv 
E1  ∫ i C dt, i C , ∫ − iE dt, − iE , v EB , EB , v CB , CB  = 0 (4.29)
 dt dt 
 dv dv 
E 2  ∫ iC dt, iC , ∫ − iE dt, − iE , v EB , EB , v CB , CB =0 (4.30)
 dt dt 
dv eb dv
i c = g11v eb + g12 v cb + C11 + C12 cb (4.31)
dt dt
dv eb dv cb
i e = g21v eb + g22 v cb + C 21 + C 22 (4.32)
dt dt
where:
ic, ib small signal currents (instantaneous value);
vbe, vce small signal voltages (instantaneous value);
ic = g11v eb + g12 v cb (4.33)
i e = g21v eb + g 22 v cb (4.34)
In closing, it must be added that common base connections may be also

described using characteristic equations developed for common emitter
connection.
138
Common collector connection

There are also two topological solutions presented in figures 4.14 and 4.15, but
only the solution presented in figure 4.14 is practiced in real circuitry.
iE iE
E E
iB iB
B vEC Output vEC B Output
Input vBC C Input C vBC

• base-collector voltage;
• base current.
• emitter-collector voltage;
• emitter current.
This connection is usually described handling characteristic equations
developed for common emitter connection:
The quasi-static large-signal behavior is a consequence of the transistor effect.

This section treats this effect in its first part, developing the Ebers-Moll model of
the transistor. In the following, some other models are presented. The outline is:
1. Ebers-Moll models;
2. Ebers Moll SPICE model;
3. Non-ideal Effects
4. I-V characteristics for common emitter connection;
5. I-V characteristics for common base connection;
6. Piecewise linear models for active mode
4.2.1 Ebers-Moll Models
Ebers-Moll models represent a set of two equations (ex. (4.25) and (4.26) for
common base connection or (4.15) and (4.16) for common emitter connection,
developed under next five hypotheses:
1. mono-dimensional model;
2. abrupt profile of impurities (impurity concentrations are considered
constant into emitter, base and collector);
139
3. all quasi-neutral regions in the device are smaller than the minority-
carrier diffusion length in these regions;
4. small level of injection (the excess of majority-carriers may be
neglected);
5. recombination-generation phenomenon within the depletion regions
may be neglected.
In the following iC and iE will be estimated. The same approach used for ideal
diode equation may be used in these cases. The start point is the estimation of
the minority holes distribution into the base. This distribution is given by:
dp ′n ( x) p n′ (x )
= 2 (4.35)
dx 2 Lp
with boundary conditions (Shockley conditions):

 v  
p′n (0) = pno exp EB  − 1
 (4.36)
  VT  
 v  
p′n ( W ) = pno exp CB  − 1 (4.37)
  VT  
where:
p′n (x) = pn (x) − pno (4.38)
Lp holes diffusion length in the base;
pno holes concentration into the base at equilibrium;
pn(x) actual holes concentration into the base in the presence of the
diffusion phenomenon.
W base length
The solution is:
W −x  x 
sh   sh  
 L   
p′n ( x ) = p′n (0 ) 
p  + p′ ( W )  L p  (4.39)
W W
n
sh   sh  
L  L 
 p  p
If the base is very thin, this solution may be approximated as:
 x  x
p′n ( x ) ≅ 1 −  p′n (0) + p′n ( W ) (4.40)
 W  W
(4.40) equation emphasizes a linear distribution of the hole into the base. This
result corresponds to a constant diffusion current through the base (without
recombination):
140
dp′n qDp
jp (x ) = − qDp
dx
=
W
[p′n (0) − p′n (W)] (4.41)
The emitter current becomes:
 qD n( E ) qDpp no  W   v  
iE = A J  n,E po + cth  exp  EB  − 1 −
 L n,E Lp  
 L p    VT  
A J q Dpp no 1   v CB   (4.42)
− exp  − 1
Lp  W    VT  
sh 
L 
 p
and the collector current is:
 qD n( C ) qDpp no  W   v  
i C = − A J  n,C po + cth  exp CB  − 1 +
 L n,C Lp  
 L p    VT  
A JqDpp no 1   v EB   (4.43)
+ exp  − 1
Lp  W    VT  
sh 
L 
 p
or simpler:
 v    v  
iE = a11 exp EB  − 1 − a12 exp  CB  − 1 (4.44)
  VT     VT  
 v    v  
iC = a 21 exp EB  − 1 − a 22 exp  CB
 V
 − 1
 (4.45)
  VT     T  
It must be observed that:
a21=a12 (4.46)
Usually, (4.42) and (4.43) equations are written as follows:
 v    v  
iE = IES exp  EB  − 1 − α RICS exp CB  − 1
 (4.47)
 V
 T     VT  
 v    v  
iC = α FIES exp EB  − 1 − ICS exp CB  − 1 (4.48)
  VT     VT  
where:
IES saturation current of the emitter-base diode measured when
vCB=0
141
ICS saturation current of the collector-base diode measured when

vEB=0
(4.47) and (4.48) equations are known as Ebers-Moll model of bipolar
transistor. Again, one may write, according to (4.46):
α FIES = α RI CS = I S (4.49)
The equivalent circuit related to these equations is presented in figure 4.16.

αRiR αFiF
E iE iC
C
iB
 v    v  
iF = IES exp  EB  − 1 iR = ICS exp  CB  − 1
  VT     VT  
B
Figure 4.16
 v  
It must be mentioned that terms like IES exp  EB  − 1 usually noted iF (forward
  VT  
 v  
current) and ICS exp CB  − 1 usually noted i R (reverse current) are modeled as
  VT  
 v    v  
diodes and terms like αFIES exp  EB  − 1 and αRICS exp  CB  − 1 are modeled
  VT     VT  
as current sources. The value of the current generated by these sources is
  v  
controlled by the current through the diodes  IES exp EB  − 1 , respective
   VT  
 
  v  
ICS exp CB  − 1  . That is why this type of model is usually named Ebers-Moll
  VT   
model for a pnp transistor, using current sources controlled by diodes currents.
In the case of npn transistor equations (4.45) and (4.46) may write as follows:
 v    v  
iE = IES exp BE  − 1 − α RICS exp BC  − 1 (4.50)
  VT     VT  
 v    v  
i C = α FIES exp  BE  − 1 − ICS exp BC  − 1 (4.51)
  VT     VT  
142
The equivalent circuit related to these two equations is presented in figure 4.17.
αRiR αFiF
E iE iC
C
iB
 v    v  
iF = IES exp  BE  − 1 iR = ICS exp BC  − 1
  VT     VT  
B
Figure 4.17
There is also another possibility to rewrite the system of equation (4.49) and
(4.50) so that the currents generated by the sources may be controlled by
currents through the terminals. This new representation is usually called Ebers
Moll model using current sources controlled by the currents through the
terminals.
 v  
i C = α F i E − ICBO exp  CB  − 1 (4.52)
  VT  
 v  
i E = α R i C − IEBO exp EB  − 1 (4.53)
  VT  
For npn transistor these equations become:
 v  
i C = α FiE + ICBO exp  BC  − 1 (4.54)
  VT  
 v  
iE = α RiC + IEBO exp  BE  − 1 (4.55)
  VT  
Figure 4.18 shows the equivalent circuit associated with (4.52), (4.53) and
figure 4.19 shows the equivalent circuit associated with (4.54), (4.55).
αRiC αFiE αRiC αFiE
iE iC iE iC
IEB0 ICB0 IEB0 ICB0
iB iB
143
The models described above are general. They may be particularized according
to the operating mode. One finds approximate models very useful for by hand
analysis of the electronic circuits
Active mode.
In the case of pnp transistors it must be observed:
v 
exp EB  >> 1 (4.56)
 VT 
and
v 
exp CB  << 1 (4.57)
 VT 
Taking into account these simplifications, (4.47) and (4.48) may be rewritten:
v  v  IS v 
i E ≅ IES exp EB  + α R ICS ≅ IES exp EB  = exp EB  (4.58)
 VT   VT  αF  VT 
v  v  v 
iC ≅ αFIES exp EB  + ICS ≅ αFIES exp EB  = IS exp EB  (4.59)
 VT   VT   VT 
and more:
1 − αF v  I v 
i B = iE − i C = IS exp EB  = S exp EB  (4.60)
αF V
 T  β F  VT 
The (4.59) and (4.60) equations represent the ideal model of the transistor.
Figures 4.20 and 4.21 illustrate this model.
iB iB
iC iC
B C B
C
IS v 
vEB IS exp EB  vEB
IS βF iB
βF  VT  βF
iE iE
E E
144
It is important to observe that while in figure 4.20 current source from collector
is controlled by the vEB voltage, in figure 4.21 current source from collector is
controlled by the base current i B.
In the case of npn transistors the same approach yields to:
IS v 
iE = exp BE  (4.61)
αF  VT 
v 
i C = IS exp BE  (4.62)
 VT 
IS v 
iB = exp BE  (4.63)
βF  VT 
Figures 4.22 and 4.23 illustrate this model.
iB iB
B iC C iC
B C
IS v 
vBE I S exp  BE  v BE
IS
β F iB
βF  VT  βF
iE iE
E E
Saturation mode
It is characterized by the fact that both diodes from transistor structure are
forward biased. The mathematical conditions are:
α FiE > iC (4.64)
α R i C > iE (4.65)
After a simple algebraic calculus (4.64) relation may be rewritten as:

β F iB > i C (4.66)
The (4.66) expression is very useful for circuit designers. On the other hand,
when both diodes are forward biased the transistor behaves like short-circuit.
One says that the transistor is in “on” state. It’s a state of low resistance. The
typical voltages between the transistor terminals are: vCEsat= 0.2 V ÷ 0.4 V and
VBEsat= 0.8 V ÷ 0.9 V . From Ebers-Moll model one can derive “on” voltage as
follows:
145
 i 
 1 + C (1 − α R ) 
 iB 
v CEsat = Vt ln  (4.67)
 α 1 − i C (1 − α F)  
 R i 
α F  
  B
The approximate models for pnp transistors are:

vEB=VEBsat (4.68)
vEC=VECsat (4.69)
or more simple:
v EB ≈ 0 (4.70)
v EC ≈ 0 (4.71)
Figure 4.24 shows the equivalent diagram circuit based on (4.68) and (4.69),
and figure 4.25 indicates the equivalent circuit diagram of a pnp transistor
modeled with (4.70) and (4.71).
B C
B C
vEBsat vECsat
E
In the case of npn transistors the mathematical model is:

vBE=VBEsat (4.72)
vCE=vCEsat (4.73)
and:
v BE ≈ 0 (4.74)
v CE ≈ 0 (4.75)
Figures 4.26 and 4.27 illustrate these models:

B C
vBEsat vCEsat B C
E
146
Cut-off mode
It is characterized by the fact that both diodes from transistor structure are
reverse biased.
In the case of the pnp transistors that means:
v 
exp EB  << 1 (4.76)
 VT 
and
v 
exp CB  << 1 (4.77)
 VT 
Now (4.47) and (4.48) may be rewritten:
IS I
iE ≅ −IES + α RICS = − + IS = − S (4.78)
αF βF
IS I
i C ≅ −α FIES + ICS = −IS + = S (4.79)
α R βR
For iB one obtains:
 1 1
iB = iE − iC = −IS  +  (4.80)
 βF βR 
Usually
β F >> β R (4.81)
so that the current expressions become:
iE ≅ 0 (4.82)
IS
iC ≅ (4.83)
βR
IS
iB ≅ − (4.84)
βR
These expressions may be also simplified observing that:
10 −18 A ≤ I S ≤ 10 −9 A (4.85)
and
0 < β R ≤ 20 (4.86)
147
Taking into account this figures the currents may be approximated as:
iE ≅ 0 (4.87)
iC ≅ 0 (4.88)
iB ≅ 0 (4.89)
Figure 4.28 illustrates (4.82) ÷ (4.84) system of equations and figure 4.29
illustrates (4.87) ÷ (4.89)
For npn transistors, a similar approach yields to identical system of equations.
IS
βF
iB iC iB iC
B C B
C
iE iE
E E
The equivalent circuits are presented in figures 4.30 and 4.31.

IS
βF
iB iC iB iC
B C B C
iE iE
E E
4.2.2 Ebers-Moll SPICE Models

This section presents Ebers-Moll models rearranged for SPICE. A npn
transistor will be used as example.
Using superposition principle the general current equations may be
obtained considering two cases:
– forward transport
v BE ≠ o and v BC = o (4.90)
– reverse transport
148
v BE = o and v BC ≠ o (4.91)
Forward transport
Figure 4.32 emphasizes only the principal currents that flow into a npn
structure.
The base-emitter voltage establishes the emitter current witch equals the total
current crossing the base-emitter junction. It respects Schockley equation
(2.53). The emitter current – for forward transport conditions - may be written
introducing (4.90) into (4.50). One obtains:
 v  
i EF = IES exp BE  − 1
 (4.92)
  VT  
Keeping in mind (4.49), iEF may be rewritten as follows
IS   v BE    β + 1   v BE  
i EF = exp  − 1 = I S  F

 
 β exp  V
 − 1
 (4.93)
α F   VT    F   T  
iC iC
n Collector n Collector
vBC
iCF iCR
p Base p Base
iB iB
i CF iCR
βF βR
vBE n++ Emitter n++ Emitter
iE iE
A similar approach – introducing (4.90) into (4.51) and using (4.49) - the
collector current for forward transport becomes:
 v  
i CF = IS exp BE  − 1 (4.94)
  VT  
For base current in similar conditions one finds
IS   v BE  
i BF = exp   − 1
 (4.95)
βF   VT  
149
Reverse transport
This time figure 4.33 may be useful. This time the collector current is controlled
base collector voltage. One obtains:
 v  
i ER = IS exp BC  − 1 (4.96)
  VT  
IS   v BC  
i CR = exp   − 1
 (4.97)
αR   VT  
IS   v BC  
i BR = exp  − 1
 (4.98)
βF   VT  
Total terminal currents
The total terminal current – due to superposition procedure – may be gathered
by summing the forward and reverse components. That means:
iC=iCF+i CR (4.99)
iE=iEF+iER (4.100)
iB=iBF+iBR (4.101)
The final expressions of the currents are:
 v  v  IS   v BC  
i C = IS exp BE  − exp BC  − exp  − 1 (4.102)
  VT   VT  β R   VT  
 v  v  I S   v BE  
i E = I S exp  BE  − exp  BC
 V
 +
 exp  − 1
 (4.103)
  VT   T  β F 
  VT  
IS   v BE   IS   v BC  
iB = exp   − 1 + exp  − 1 (4.104)
βF   VT   βR   VT  
The equivalent circuit related to (4102) ÷ (4.104) mathematical model of npn
transistor is presented in figure 4.34. In the case of pnp transistors the
mathematical model is:
 v  v  I S   v CB  
i C = IS exp EB  − exp CB
 V
 −
 exp  − 1
 (4.105)
  VT   T  β R   VT  
 v   v  I   v EB  
iE = IS exp EB  − exp CB  + S exp   − 1 (4.106)
  VT   VT  βF   VT  
150
C
iC
IS
βR
B iB   v BE  v 
iCC =I S exp  − exp BC
 V


  VT   T 
IS
βF
iE
E
Figure 4.34
IS   v EB   IS   v CB  
iB = exp  − 1 + exp  − 1 (4.107)
βF   VT   βR   VT  
The equivalent circuit diagram is presented in figure 4.35.
C
iC
IS
βR
B iB   v EB  v 
iCC = I S  exp   − exp  CB  
  VT   VT  
IS
βF
iE
E
Figure 4.35
4.2.3 Non-Ideal Effects

The approach presented above - due to those five hypotheses stated in the
beginning of 4.2 section - ignored some phenomena such as:
series resistance;
high injection;
generation-recombination phenomenon;
base-width modulation;
junction breakdown;
temperature dependence
thermal run-away.
The impact if these phenomena are presented below.
151
Series resistance.
There are three series resistors – usually called terminal resistors - that worth to
be mentioned: collector resistor, emitter resistors and base resistor. They
behave as (2.85) formula explains.
High injection
As it had been mentioned, "high injection" occurs at high forward bias, when the
excess minority carrier density exceeds the doping density in the material. The
neutrality condition demands a similar increase of majority carrier density. In
fact, the excess electron density must equal the excess hole density, because
no net charge may exist. If there is a net charge, the electric field causes the
carriers to move and the neutrality condition is re-established.
The aim of this section is to find the influence of the excess carrier density on
collector current expression. In fact, such an analysis was presented in section
2.2.3 for diode current. A similar approach, applied in this case, yields to
conclusion that in high condition; the collector current is proportional with
v 
exp BE 
 2V T 
Generation-recombination phenomenon
The additional mechanism of generation-recombination phenomenon involves
two new currents that must be considered:
a generation-recombination current due to emitter-base junction;
  v  
iRE = ISE exp  BE  − 1 (4.108)
  nE VT  
a generation-recombination current due to collector-base junction
  v  
iRC = ISC exp BC  − 1 (4.109)
  n C VT  
where:
ISE base-emitter leakage current
nE base-emitter leakage emission coefficient
ISC base-collector leakage current
nE base-collector leakage emission coefficient
Both (4.108) and (4.109) follow (2.101).
Base-Width Modulation
It is also called Early effect, because this phenomenon was first identified in
1952 by James Early. As (2.70) and (2.71) have proved, the edges of the
space-charge region – in the case of pn junction - are moving due to the voltage
152
applied across the junction. this phenomenon is predominant for reverse bias.
In the case of the bipolar transistor when reverse bias across the collector-base
junction increases, the width of the collector-base depletion layer increases, and
the width of the base decreases. It must be added that higher the reverse
voltage across collector base junction is, smaller is the width of the base.
Figure4.36 illustrates this fact.
B
Depletion
region
n p n
E w1
C
w2
Figure 4.36
In the mean time, the saturation current IS is inversely proportional to the base
width wB, so a decrease in wB results in an increase in the collector current
(figure 4.37).
Figure 4.37 represents iC related to vCE with iB parameter. It has been observed
experimentally that when the output characteristic curves are extrapolated back
to the point of zero collector current, the curves all intersect at a common point
vCE=VA. VA is called Early voltage. It is typically between 25V and 150 V
The dependence of the transistor currents on the collector-emitter voltage is
easily included in the simplified mathematical model (4.59) and (4.60), for the
forward-active region of the BJT
 v  v 
iC = IS 1 + CE  exp  BE  (4.110)
 VA   VT 
IS v 
iB = exp BE  (4.111)
βF 0  VT 
In the same time:
 v 
β F = β F0 1 + CE 
 (4.112)
 VT 
where: β FO represents the value of β F extrapolated to vCE=0
153
iC
iB4
iB3
iB2
iB1
VA vCE
Figure 4.37
Junction Breakdown Voltages

The BJT is formed from two pn junctions electrically coupled. Each of these
junctions has a Zener breakdown voltage associated with it. Generally, these
voltages are noted:
VEB0 breakdown voltage for emitter-base junction with collector
unconnected;
VCB0 breakdown voltage for emitter-base junction with collector
unconnected;
and they may be estimated following the procedure presented in section 2.2.5
The purpose of this section is to present a procedure for evaluating breakdown
voltages taking into account the electrical coupling.
Collector-base junction; breakdown voltages
There are two situations to discuss:
Common base connection; for this connection
iE=const (4.113)
and the collector current is:
i C = Mα F i E (4.114)
where M according to (2.103) is: iC
1 iE4
M= n
(4.115)
 v CB  iE3
1−  
V 
 CB 0  iE2
Introducing (4.115) in (4.114) one finds: iE1
αFiE vCB
ic = n
(4.116) VCB0
 v CB 
1−  
V  Figure 4.38
 CB 0 
154
So, i C → ∞ if M → ∞ , and that means v CB → VCB0 In conclusion, for common

base connection the breakdown voltage of the collector-base junction is VCB0.
This value does not depend of emitter current. Figure 4.38 illustrates this
observation.
Common emitter connection. For this connection
i B=const (4.117)
and this time i C must be expressed function of iB But:
i E=iC+iB (4.118)
and related to (4.115) i C becomes:
MαFiB
ic = (4.119)
1 − MαF
1
One observes that now i C → ∞ if M → . This new value for M must be
αF
introduced in (4.115). One obtains for vCB the estimation;
VCB 0
v CB = VCB0 n 1 − α F = (4.120)
n
1 + βF
Because
v CB ≅ v CE (4.121)
one finds finally

VCB0
VCEs = VCB 0 n 1 − α F = (4.122)
n
1 + βF
Where VCEs is called sustaining voltage. It represents the value of vCE that make
possible an unlimited increase of i C. Usually:
1 1
VCEs = VCB0 ÷ VCB 0 (4.123)
10 3
Figure 4.39 emphasizes sustaining voltage. It must be observed that the
transistor may – theoretically - function over sustaining voltage.
An usual situation is represented by the so called phenomenon “secondary
breakdown”. Figure 4.40 presents this phenomenon. One observes that the
collector current is increasing while the voltage across the collector junction is
decreasing. For the moment, there is no satisfactory explanation for this fact.
155
iC iC
Secondary
breakdown
iB3>iB2
iB2>iB1
iB5<0 iB=0
iB1>0
iB4=0 vCE
vCE
VCEs
Emitter-base junction; breakdown voltage

Because generally this junction is forward biased, the multiplication
phenomenon is not so present. Typical values of this voltage are 5-10V
Temperature Dependence
One can discuses about the temperature dependency of any of the parameters
mentioned above, but only two important parameter are generally mentioned:
1. base-emitter voltage, whose variation related to temperature may
0
considered as being somewhere around 2-2.5 mV/ C
2. and β F whose law of variation may be estimated as:
 T − T0 
βF (T ) = βF (T0 )1 +  (4.125)
 K 
where:
T0=250C
0 0
K=100 C for Ge and K=50 C for Si
Thermal run-away;
It is a phenomenon that consists in uncontrolled increasing of the collector
current due to temperature increasing. The explanation resides on positive
feedback that may occur in the structure. Two factors make possible this
regenerative process:
1. when temperature is increasing, iC is increasing, because:
β F is increasing with temperature and
i B is increasing with temperature
2. when iC is increasing, temperature is increasing due to thermal
effect of the current.
156
In this conditions an increasing of the temperature generates an increasing of

the collector current. This one generates an increasing of temperature and so
on. Finally, the collector current increases unlimited.
4.2.4 “I-V” Characteristics for Common Emitter Connection
Section 4.1.3 explained that, usually, common emitter connection is described
using (4.17) and (4.18) equations. In fact, in real situation, one makes use of a
different form:
i C=iC(i B, vCE) (4.126)
i B=iB(vBE, vCE) (4.127)
where:
i C, iB instantaneous values of the currents;
vBE, vCE instantaneous values of the voltages;
Both (4.126) and (4.127) are functions of two variables. They must be
represented in R3 (tri-dimensional space). A R2 representation is possible only if
(4.126) and (4.127) are rewritten as follows:
ic = iC ( v CE ) (4.128)
iB = const.
iB = iB (v BE ) (4.129)
uCE = const.
Under this form, they are known static characteristics. (4.128) relation is an
output characteristic and (4.129) relation is an input characteristic.
iB = iB (v BE ) is presented in figure 4.39. Because the breakdown

uCE = const.
region is not interesting for real applications, in catalogues or other specific
papers, this region is not represented. Figure 4.41 illustrates an output
characteristic as it is presented usually.
iC iB
iB4 vCE1
vCB=0 active region
saturation iB3 vCE2>vCE1
region
iB2
cut-off
region iB1
vCE vBE
157
One can observe that

• it has the shape of a diode characteristic (in fact is emitter base
diode);
• it has the shape of a diode characteristic (in fact is emitter base
diode);
4.2.5 “I-V” Characteristics for Common Base Connection
Section 4.1.3 stated that common base connection is described by using (4.27)
and (4.28) equations, but, in real situation, one uses different forms:
iC=iC(iE, vCB) (4.130)
iE=iE(vEB, vCB) (4.131)
2
Their R representations are:
ic = iC ( v CB ) (4.132)
iE = const.
for output characteristic and:
iE = iE (v BE ) (4.133)
uCB = const.
for input characteristic and:

Output characteristic is presented in figure 4.43.
One can observe the three important operation regions: saturation, active and
iC
iE
iE4>iE3 vCB1
active region
saturation iE3>iE2
region vCB2<uCB1
iE2>iE1
iE1=0
vCB vBE
cut-off
region
cut-off
Input characteristic is presented in figure 4.44. Because emitter-base junction
represents the input, the shape of the characteristic preserves the shape of a
diode characteristic
158
4.2.6 Piecewise Linear Models for Active Mode

This section treats only active mode because, for saturation or cut-off modes of
operation, the models presented in section 4.2.1 cover this topic. The modes
presented there are piecewise linear.
Regarding the active mode, it must be mentioned that there are two types of
models in respect with the level of approximation:
First order approximation
One consider:
• vBE=constant; It equals the knee voltage 0.6-0.7V
• collector current equals emitter current (good assumption because
generally α F . > 0.98
vBE=const. (4.134)
i C=iE (4.135)
The electrical model will be not presented here, because it requires advanced
knowledge concerning circuit theory.
Pnp transistor is modeled as follows:
vEB=const. (4.136)
i C=iE (4.137)
Second order approximation
The "I-V" characteristics are linearized as figures 4.45 and 4.46 expose:
iC iB second order
second order
approximation
approximation
(vBE=const.)
(iC=β F iB)
iB4
iB3
iB2
iB1
knee voltage
vCE vBE
The mathematical model is:

vBE=const. (4.138)
159
i C = β F iB (4.139)
The electrical model is showed in figure 4.47
iB iB
iC iC
B C B
C
vBE βF iB vEB β F iB
iE iE
E E
For pnp transistors the mathematical model is represented by (4.140) and

(4.141) equations and electrical model is presented in figure 4.48
vEB=const. (4.140)
i C = β F iB (4.141)
The mathematical models presented above have taken into account only the
low frequency behavior of the transistor. When the speed of operation is
increased, capacitive comportment becomes weightier. The usual approach, for
these conditions, resides in developing of charge-control models. That’s why
this section treats:
1. charge-control model;
2. Gummel-Poon SPICE model.
4.3.1 Charge-Control Model
In order to develop a charge control model for a transistor, it is necessary to
write the three currents of the transistor in respect with the distribution of the
charged stored in the structure. In this section, such a model will be developed
in two steps. First step will consider only the excess charge stored in base. The
second step will add the excess charge stored both in collector and emitter
junctions. Then, as section 4.2.2 just did, the principle of superposition will be
applied. The analysis will be made for a npn transistor.
The effect of the excess charge stored into the base.
160
One may write:

QB=QF+QR (4.142)
where:
QB total excess charge in the base;
QF forward excess charge in the base;
QR reverse excess charge in the base.
Obviously, forward excess charge in the base may be determined through the
analysis of forward transport.
Forward transport
Taking into account (4.35), equation written for electrons one obtains:
dn ′n ( x ) n ′n ( x )
= 2 (4.143)
dx 2 Ln
Shockley conditions are:
 v  
n ′p (0) = n p 0 exp BE  − 1 (4.144)
  VT  
 v  
n′p ( W ) = np 0 exp  BC  − 1 (4.145)
  VT  
where:
n′p ( x ) = np ( x ) − n p0 (4.146)
Lp electrons diffusion length in the base;
np0 electrons concentration into the base at equilibrium;
np(x) actual electrons concentration into the base in the presence of
the diffusion phenomenon.
The solution is:
W −x  x
sh   sh  
Ln  L
n′p ( x ) = n′p (0 )  + n′p ( W )  n  (4.147)
W W
sh   sh  
L
 n  Ln 
If the base is very thin, this solution may be approximated as:
 x  x
n′p ( x ) ≅ 1 −  n′p (0) + n′p ( W ) (4.148)
 W W
161
Figure 4.48 illustrates this result. One observes the triangle form of the electron
distribution. The excess charge is represented by the triangle aria:
emitter base collector emitter base collector
n++ p n n++ p n
pC0 pC0
pE0 pE0
np0 np0
W × n′p (0 )
QF = eA j (4.149)
2
Introducing (4.144) in (4.149) one finds:
eA j Wn p 0   v BE  
QF = exp  − 1 (4.150)
2   VT  
On the other hand, collector current one may write:
dn′p qA jDn
i C = −qA jDn
dx
=
W
[n′ (0) − n′ ( W )] ≅ qAWD
p p
j n
n′p (0 ) (4.151)
With Shockley boundary conditions, collector current becomes:
qA jDn  v  
iC = np0 exp BE  − 1 (4.152)
W   VT  
Comparing (4.150) with (4.152) one may write:
QF
iC = (4.153)
τF
where:
W2
τF = (4.154)
2Dn
The same approach for base current yields to:

QF
iB = (4.155)
τBF
with
162
1
τ BF = (4.156)
1 2 D p p n0
+
τ b W We np0
where:
τb life time of the excess carriers in the base;
pn0 holes concentration in the emitter for equilibrium conditions
np0 electrons concentration in the emitter for equilibrium conditions
We emitter weight.
Finally the emitter current is:
QF Q F
iE = iB + iC = + (4.157)
τBF τF
The analysis presented above considered only quasi-static conditions. If the

speed of variation is increased, of course the charge distribution in the base
must vary. In the following, one considers that the instantaneous shape
distribution is also a triangle (of course this assumption is valid only if the speed
is not very high). Because the collector current depends only of the shape of the
excess charge distributions in the base, (4.153) is still good for dynamic
conditions.
In the case of the base current, it must be observed that only this current
supports the variations of the charge stored in the base. That means that only
the base sets base charge current. In fact, this current has two components:
• First component is due both to recombination process and to injection
phenomenon in the emitter. This component is a quasi-static
Q
component and it may be written as F ;
τF
• The second component represents the carriers due to the variation of

the charge. This component is dynamic component and it may be
dQF
written as .
dt
Therefore, the base current may be expressed as:
dQF QF
iB = + (4.158)
dt τBF
and hence the emitter current is:

dQ F Q F Q F
iE = + + (4.159)
dt τBF τF
163
Reverse transport
The charge distribution in the whole structure is presented in figure (4.49).
Taking into account that for reverse transport the emitter becomes collector and
the collector behaves like emitter, the terminal current may be written as:
dQ R QR QR
iC = − − − (4.160)
dt τBR τR
dQR QR
iB = + (4.161)
dt τBR
QR
iE = − (4.162)
τR
where:
eA j Wn p0   v BC  
QR = exp  − 1 (4.163)
2   VT  
and τBR or τR have the same significance as τBF or τF .
Transport equations
Figure 4.50 and figure 4.51 indicate the distribution of the charge carriers both
for saturation and cut-off regions.
emitter base collector emitter base collector

n++ n n++ p n
p
pC0 pC0
pE0 pE0
np0 np0
One may observe that these distributions may be obtained as an appropriate

combination between the charge carrier distribution corresponding to active
mode and reverse mode. According to (4.142) the terminal currents are:
Q F dQR  1 1 
iC = − − QR  +  (4.164)
τF dt  τR τBR 
dQF QF dQR QR
iB = + + + (4.165)
dt τBF dt τBR
164
dQF  1 1  QR
iE = − − QF  +  + (4.166)
dt τ
 F τ BF 
τR
For pnp transistors they are:

QF dQR  1 1 
iC = − + + QR  + 
(4.167)
τF dt  τR τBR 
dQ F Q F dQ R Q R
iB = − − − − (4.168)
dt τ BF dt τ BR
dQ F  1 1  QR
iE = + Q F  +  − (4.169)
dt τ
 F τ BF  τR
The effect of the excess charge stored into the depletion regions.
The two depletion regions may be analyzed according to the formalism
developed in section 2.3.coniderring only QJE the charge due to the space
charge layer. So, QJE may be expressed as:
Φ B0E
Q JE = ∫C
0
JE
dv BE (4.170)
where
− m JE
 v 
C JE = C J 0E 1 − BE 
 (4.171)
 Φ B0E 
if v BE ≤ f C Φ B 0E and
 v BE 
C JE = C J 0E (1 − f C ) 1 − f C (1 + m JE ) + m JE
− (1+ m JE )
 (4.172)
 Φ B0E 
if v BE > f C Φ B0E .
Φ B 0E built-in voltage
mJE the exponent of the voltage factor for vBE
CJ0E depletion capacitance at zero bias.
dQ JE
The component of the current due to this charge may be written as being
dt
A similar analysis may be made for collector junction. One finds that the
165
component of the current due to collector base junction may be written as being
dQ JC
.
dt
Finally, the terminal currents may be stated as:
Q F dQ R  1 1  dQ JC
iC = + − − Q R  +  − (4.173)
τF dt τ
 R τ BR  dt
dQ F Q F dQ R Q R dQ JE dQ JC
iB = + + + + + + (4.174)
dt τ BF dt τ BR dt dt
dQ F  1 1  Q R dQ JE
iE = − − Q F  +  + − (4.175)
dt  τ F τ BF  τR dt
For pnp transistors the equations are:

Q F dQ R  1 1  dQ JC
iC = − + + Q R  + +

τF dt τ τ dt (4.176)
 R BR 
dQ F Q F dQ R Q R dQ JE dQ JC
iB = − − − − − − (4.177)
dt τ BF dt τ BR dt dt
dQ F  1 1  Q R dQ VE
iE = + Q F  + −
 τ + dt (4.178)
dt  τ F τ BF  R
There is one more question to answer: the range of frequencies that the model
presented above is accurate. Regarding this problem, it must be reminded that
equations (4.173) ÷ (4.178) were deduced considering that the shape of the
charge carrier distribution in the base is triangular. More exactly, the
mathematical model just presented, assumed that the speed of variation is
small enough, so that, each moment, the distribution remains triangular. That
means that the dynamic regime was treated like a succession of static regimes.
4.3.2 Gummel-Poon SPICE Model
The SPICE model is a charge control model similar with Gummel Poon (G-P)
model. That’s why one discusses about a Gummel Poon SPICE model. In the
same time it must be added that for quasi-static conditions SPICE model is
reduced to Ebers-Moll (E-M) model.
G-P model has some major improvements over the E-M model. In facts G-P
model includes the non-ideal effects such as:
• high injection effects;
• Early effects;
166
• terminal series resistances;

• generation –recombination phenomenon;
• temperature dependencies.
Being a charge model, these corrections over the E-M are acquainted
describing more accurate the majority charge carrier population in the base.
According to this approach,
QB=QB0+QJE+QJC+QDE+QDC (4.179)
where:
QB0 fix charge in the base;
QJE+QJC added holes charge (depletion regions)
QDE+QDC neutralizing holes charge (compensating injected
electrons)
and
v v 
Q JE + Q JC = Q B0  B′C′ + B′E′ 
 (4.180)
V
 AF VAR 
Q B0
Q DE + Q DC = −IS ×
SQ B
(4.181)
  v    v   
× τF exp B′E′  − 1 + τ R exp B′C′  − 1 
   VT     VT   
with
VAF Forward Early Voltage
VAR Reverse Early Voltage
QB 1 1 2
= Q1 + Q1 + Q 2 (4.182)
QB 0 2 4
v B′C′ v B′E′
Q1 = 1 + + (4.183)
VAF VAR
IS   v B′E′   IS   v B′C′  
Q2 = exp  − 1 + exp  − 1 (4.184)
IKF   VT   IKR   VT  
IKF corner for β F high-current roll-off;

IKR corner for β R high-current roll-off;
It worth to be mentioned that at small level of injection
167
QB
≈ Q1 (4.185)
Q B0
and that includes Early effect, while at high level of injection

QB
≈ Q2 (4.186)
Q B0
With this new expression for QB (4.179) the terminal currents become:
dQB
iB = iBE + iBC + iRE + iRC + S (4.187)
dt
dQDC dv
i C = i CC − iBC − iRC − S − CDC BC (4.188)
dt dt
dQ DE dv
iE = iCC + iBE + iRE + S + CDE BE (4.189)
dt dt
where:
iBE forward current
IS   v B′E′  
i BE = exp  − 1 (4.190)
βF   nF VT  
iBC reverse current
IS   v B′C′  
i BC = exp  − 1 (4.191)
βR   nR VT  
iRE base emitter generation-recombination current
  v  
i RE = ISE exp B′E′  − 1 (4.192)
  nE VT  
iRE base collector generation-recombination current
  v  
i RC = ISC exp B′C′  − 1
 (4.193)
  n C VT  
Q B0   v   v 
i CC = IS exp B′E′  − exp B′C′  (4.194)
Q B   nF VT   nR VT 
168
Figure 4.52 shows the equivalent circuit. The diffusion charges QDE and QDC –
described in terms of minority carrier lifetime – give rise to diffusion
capacitances CDE and CDC.
C
dv B′C′ iC
dQ DC CJC
S dt RC
dt
iRC iBC
C’
IS
CDC CJC ISC
RB βR
iB C’
B
iCC
CDE CJE ISE IS

βF
E’
iRE iBE
dQ DE
S dv B′E′ RE
dt C JE
dt iE
Figure 4.52
4.4 Quasi-Static Small Signal Behavior
There are two possible approaches to developing the incremental models:

• linearizing the large-signal models;
• linearizing the equations that describe physical behavior of the
transistor
This section follows the first approach.
Section one of these chapter shows that an appropriate description of the small
signal behavior of BJT, is given by (4.24) and (4.25) equations. These
equations will be rewritten here:
ic = g11v be + g12 v ce (4.195)
ib = g21v be + g22 v ce (4.196)

where g11, g12, g21 and g22 are quasi-static small-signal parameters. This section
defines these parameters and related to them, develops the electrical model.
This model is the so-called conductances model. There are also many other
possibilities to describe a BJT. In fact, a bipolar transistor may be represented
169
as a two-port network and by consequence, the whole mathematical apparatus

of this theory, may be applied successfully. This section treats only:
1. Conductances Model;
2. Hybrid π Model. SPICE Model
3. H-Parameter Model.
4.4.1 Conductances Model
Quasi-Static Small-Signal Parameters
As a rule, small signal parameters are introduced over the linerization of the
large signal modes around a quiescent point of operation. The procedure goes
through the next steps:
1. One determines the mathematical large signal model. For example, in case
of bipolar transistor this may be given by (4.17) and (4.18) equations
rewritten here:
iC=iC(vBE, vCE) (4.197)
iB=iB(vBE, vCE) (4.198)
2. One finds the total differential form for iC and i B:
∂i C ∂i C
di C = dv BE + dv CE (4.199)
∂v BE QP ∂v CE QP
∂iB ∂iB
diB = dv BE + dv CE (4.200)
3. One defines the differential conductances:

gm mutual conductance (forward transfer conductance, or trans-
conductance)
∂i C
gm = (4.201)
∂v BE QP
go output conductance
∂i C
go = (4.202)
∂v CE QP
gπ input conductance (base emitter conductance)
∂iB
gπ = (4.203)
∂v BE QP
170
gmr reverse transfer conductance
∂iB
gmr = (4.204)
∂v CE QP
4. One approximates the infinitesimal variations with small finite variations:
∆i C ∆i C
∆i C ≅ ∆v BE + ∆v CE (4.205)
∆v BE ∆v CE
∆v CE = 0 ∆v BE = 0
∆iB ∆iB
∆iB ≅ ∆v BE + ∆v CE (4.206)
∆v BE ∆v CE
∆v CE = 0 ∆v BE = 0
5. One considers finite variation as being small signal
ic ic
ic = v be + v ce (4.207)
v be v ce
Vce = 0 Vbe = 0
ib ib
ib = v be + v ce (4.208)
v be v ce
Vce = 0 Vbe = 0
6. One defines the small signal conductances:

g(ms ) mutual conductance
ic
g(ms ) = (4.209)
v be
Vce = 0
g(os ) output conductance
ic
g(os ) = (4.210)
v ce
Vbe = 0
g(πs ) input conductance
171
ib
g(πs ) = (4.211)
v be
Vce = 0
g(mrs ) reverse transfer conductance
ib
g(mrs ) = (4.212)
v ce
Vbe = 0
7. One observes that small signal conductances are very well approximate by
differential conductances.
g(ms ) ≅ g m (4.213)
g(os) ≅ go (4.214)
g(πs) ≅ gπ (4.215)
g(mrs ) ≅ gmr (4.216)
The (4.213) ÷ (4.216) relations offer an easy way to calculate the incremental
conductances. In fact there is no need to use a double list for conductances,
and that’s why, from now on only the symbols of differential conductances will
be used. Relating these parameters to those introduced by (4.195) and (4.196)
one observes:
g11 = gm (4.217)
g12 = g 0 (4.218)
g 21 = g π (4.219)
and finally:
g 22 = gmr (4.220)
Quasi-Static Small-Signal Model
8. Introducing (4.217) ÷ (4.220) into (4.207) and (4.208) one obtains:
ic = gm v be + go v ce (4.221)
ib = gπ v be + gmr v ce (4.222)
These equations represent a mathematical model for bipolar transistor in small

signal conditions. In respect with this model, one may develop the equivalent
circuit
172
9. The equivalent circuit based on (4.217) and (4.218) equations is

presented in figure 4.53:
B ib ic C
vbe gπ vce
ge
gmrvce gmvbe
Figure 4.53
In the following, as an issue of this approach, the incremental parameters of a

BJT that follows the (4.110) and (4.111) mathematical model will be computed.
These equations, rewritten here, are:
 v  v 
iC = IS 1 + CE  exp BE  (4.223)
 VA   VT 
IS v 
iB = exp BE  (4.224)
βF0  VT 
The small signal parameters become:
  v  v 
∂ I S 1 + CE  exp BE 
∂i C   V A   VT  IC
gm = = = (4.225)
∂v BE QP ∂v Be QP VT
  v  v 
∂ IS 1 + CE  exp BE 
∂i C   VA   VT  IC
go = = ≅ (4.226)
∂v CE QP ∂v CE QP VA
I  v 
∂  S exp  BE 
∂iB  βF 0  VT 
= 
IB
gπ = = (4.227)
∂v BE QP ∂v BE QP VT
I  v 
∂  S exp BE 
∂iB β
 F0  VT 
gmr = =  =0 (4.228)
∂v CE QP ∂v BE
Usually, instead of g π and go one uses rπ and ro:
1
rπ = (4.229)
gπ
173
1
ro = (4.230)
go
The equivalent circuit is (figure 4.53):
B ib ic C B ib ic C
vbe rπ gmvbe ro vce vbe rπ βi b ro vce
Under this form, this model is similar to “hybrid- π model”.

In the same time, it is important to observe that, if in quasi-static large signal
condition, the ratio between collector current and base current is β F this time
the new ratio is:
ic 1 1 1
β0 = = = = (4.231)
ib ib ∂ ∂  iC 
iB  
iC ∂i C ∂i C β 
QP  F  QP
If β F is constant then:
β 0 = βF (4.232)
Because, for real situations, the values of β F and β 0 are matching, from now on,
no distinction will be made between these two current gain factors, and a single
notation will be used. The current gain for common emitter connection will be
simply noted as β. According to this new notation it easy to observe that:
gm rπ = β (4.233)
This last relation allows a re-modeling of equivalent circuit presented in figure
4.53. Figure 4.54 presents this new model. One can observe that in this case
the transistor is controlled by the base current.
4.4.2 Hybrid- π Model. SPICE Model

Hybrid π model is often used in CE configuration. It relates very well to
physical parameters of BJT. Is also used in SPICE.
Hybrid π model is associated with Ebers-Moll model rearranged for SPICE.
This model is represented by (4.102) ÷ (4.104) equations, rewritten here as
follows.
174
i C = i CC − i BC (4.234)
iB = iBE + iBC (4.235)
where:
 v  v 
i CC = I S exp  BE  − exp  BC  (4.236)
  VT   VT 
IS   v BE  
iBE = exp  − 1 (4.237)
βF   VT  
IS   v BC  
iBC = exp  − 1 (4.238)
βR   VT  
One can observe that there are three currents:
• i BE the current between base and emitter. The linearization of this current
yields to a conductance:
∂iBE
ibe = v be = gbe v be (4.239)
∂v BE QP
• i BC the current between base and collector. The linearization of this current
yields to a conductance:
∂iBC
ibc = v be = gbc v bc (4.240)
∂v BC QP
• i CC the current between collector and emitter The linearization of this

current yields to two transconductances (each transconductance is
represented by a controlled current source):
∂i CC ∂i CC
i cc = v be + v bc = g m v be + g r v bc (4.241)
∂v BE QP ∂v BC QP
But because:
v BC ≅ −v CE (4.242)
for active mode of operation, usually instead of grvbc term one uses the
term gcevce, as (4.243) shows:
∂i CC ∂iCC
v bc ≅ v ce = gce v ce (4.243)
∂v BC QP ∂v CE QP
175
In this conditions, the linearization of iCC current yields to a

conductances and a transconductances:
∂i CC ∂i CC
i cc = v be + v bc ≅
∂v BE QP ∂v BC QP
(4.244)
∂i ∂i
≅ CC v be + CC v ce = g m v be + g ce v ce
Calculating these conductances one finds:
IS   v BE  
∂ exp   − 1
∂iBE βF   VT   IB
gbe = = = = gπ (4.245)
∂v BE QP ∂v BE QP VT
∂i CC ∂iC
gce = ≅− = go (4.246)
∂v CE QP ∂v CE QP
iC
∂
∂iBC ∂iB β go
gbc = ≅ = = = gµ (4.247)
∂v BC QP ∂v CE QP ∂v CE QP β
The equivalent circuit is presented in figure 4.55. Figure 4.56 shows the model
rµ rµ
B ib ic C B ib ic C
vbe rπ gmvbe ro vce vbe rπ βi b ro vce
controlled by the base current

The models presented above are also known as fundamental models.
4.4.3 H-Parameter Model
It is a model borrowed from the two-port mathematical theory. In fact,
“conductances model” has the same roots. This time, the set of equations that
describes the transistor in common emitter connection is:
v be = hieib + hre v ce (4.248)
i c = h feib + h o v ce (4.249)
where:
176
hie short-circuit input impedance (resistance);
v be
h ie = = rπ (4.250)
ib
Vce = 0
hre open circuit reverse voltage ratio;
v be
h ie = (4.251)
v ce
Ib = 0
hfe short circuit forward current ratio;
ic
h ie = =β (4.252)
ib
Vce = 0
hoe open circuit output admittance (conductance);
ic 1
h oe = = (4.253)
v ce ro
Ib = 0
The equivalent circuit corresponding to (4.248) ÷ (4.253) set of equations is

presented in figure 4.57. Because
h re ≈ 0 (4.254)
Ib Ib
B C B C
hie
1 1
Vbe + Vce Vbe Vce
hfeIb hoe hie hfeIb hoe
hreVce
E E
the usual circuit is showed in figure 4.58
177
4.5 Dynamic Small Signal Behavior
The dynamic small signal model presented in this section completes the hybrid
model by adding the capacitive effects. It is also presented estimation for cut-off
frequency.
1. Hybrid π Model.
2. Cut-off Frequency
4.5.1 Hybrid π Model. SPICE Model

The dynamic behavior in small signal is characterized by a set of parameters
that may be defined as follows:
Emitter base capacitance:
d(Q JE + QDE )
Cπ = (4.255)
dv BE QP
For QDE one may write:

iCC
QDE = τFF (4.256)
QB
Q B0
and
2
 i   
τFF = τF 1 + x τF CC  exp  − 0.694 v BE  (4.257)
 i CC +IτF
  VτF 
   
where:
x τF the dividing factor in τFF (iCC , v BC ) relation
QJE follows (4.170) relation.

Φ B 0E
Q JE = ∫C
0
JE
dv BE (4.170)
where:
178
− m JE
 v 
C JE = C J0E 1 − BE 
 (4.171)
 Φ B0E 
if v BE ≤ f C Φ B 0E and
 v BE 
C JE = C J0E (1 − f C ) 1 − f C (1 + m JE ) + m JE
− (1+ m JE )
 (4.172)
 Φ B0E 
if v BE > f C Φ B0E , with:
Φ B 0E built-in voltage
mJE the exponent of the voltage factor for vBE
CJ0E depletion capacitance at zero bias.
Collector base capacitance:
d(Q JC + Q DC )
Cµ = (4.257)
dv BC QP
and:
  v  
QDC = τRIS exp BC  − 1 (4.258)
  nR VT  
QJC – similar to QJE – may be expressed as:
ΦB 0 C
Q JC = ∫C
0
JC
dv BC (4.259)
where:
− mJC
 v 
C JC = CJ 0C 1 − BC  (4.260)
 Φ B 0C 
if v BC ≤ fC Φ B0 C and
 v BC 
C JC = CJ 0C (1 − fC ) 1 − fC (1 + m JC ) + m JC
−(1+m JC )
 (4.261)
 Φ B0 C 
if v BC > fCΦ B 0C .
Hence:
Φ B0 C built-in voltage
179

mJC the exponent of the voltage factor for vBC
CJ0C depletion capacitance at zero bias.
In these circumstances, the equivalent circuit is presented in figure 4.59:
rµ rµ
rx
B C B B’ C
Cµ Cµ
Vbe rπ Cπ gmVbe rO Vb’e rπ Cπ gmVb’e rO
E E
Figure 4.60 completes the equivalent circuit adding a series resistance in base.
Under this form, the circuit is known as Giacoletto circuit.
4.5.2 Cut-off Frequency
The circuits presented above emphasize a new aspect. C µ creates a new way
for the current between base and collector. It is easy to observe that once the
frequency is increased, the component of the collector current due to C µ
becomes predominant, and by consequence, the transistor effect becomes
insignificant. In this situation, the current gain may be considered unessential.
At limit, one may consider that there is a frequency that equals the collector
current and the base current. Generally, this frequency is named cut-off
frequency (fT). The formal definition is:
iC (f )
For f = f T ⇒ β(f ) = =1 (4.262)
iB ( f )
Vce = 0
According to the definition the circuit diagram represented in figure 4.59 must
be redrawn as figure 4.61 shows:
180
rµ
Cµ
B ib ic C B ib iµ ic C
Cµ
Vbe rπ Cπ gmVbe rO Ib
vbe rπ Cπ gmvbe
E E
The circuit diagram presented in figure 4.62 may be simplified observing that:
• at high frequencies, the current that flows through rµ is much smaller
than the current that flows through C µ ;
• due to the output short-circuit between collector and emitter ro may be
neglected.
Figure 4.63 exposes the new circuit diagram used for f T calculation. One
considers that the circuit is driven by i b current source and the response is
collector current ic. Using symbolic transformation one finds:
ic ( jω) = gmv be ( jω) − Iµ ≅ gm v be ( jω) (4.263)
where:
  1  rπ
v be ( jω) = ib ( jω)rπ    = i ( j ω) (4.264)
  jω(C + C )  b 1 + j ω r (C π + Cµ )
 π µ 
 π
One considers that I µ contribution may be neglected. Under these

circumstances, (4.262), (4.263) and (4.264) relations yield to:
gmrπ
β ( j ω) = (4.265)
1 + jωrπ (C π + C µ )
Remembering that:
β F = gm rπ (4.266)
the final expression for β( jω) is:
βF
β ( j ω) = (4.267)
Cπ + Cµ
1 + jωβ F
gm
181
At high frequencies:
Cπ + Cµ
jωβ F >> 1 (4.268)
gm
and by consequence:
gm
β ( j ω) ≅ j ω (4.269)
Cπ + Cµ
Rewriting (4.262) condition using symbolic formalism one reaches at:

β ( jω T ) = 1 (4.270)
Introducing (4.269) into (4.270) ω T becomes:
gm
ωT = (4.271)
C π + Cµ
and finally the cut-off frequency is:

ωT 1 gm
fT = = (4.272)
2π 2π C π + C µ
The behavior of the bipolar transistor may be illustrated drawing β( jω) in

respect with ω . Figure 4.64 exposes this representation using logarithmic
scales both for β( jω) and ω
β( jω)
1000
-3dB
βF
100 dB
− 20
dec
10
ωβ ωT ω
Figure 4.64
182
where ωβ is defined as being the angular frequency corresponding to –3dB (in

βF
fact ) decrease of β( j ω) . Observing that:
2
βF
β( jω) = (4.273)
2
 C + Cµ 
1 +  ωβ F π 
 gm 
ωβ may be estimated from:
βF βF
= (4.274)
2
 C + Cµ  2
1 +  ωββF π 
 gm 
One finds:
1 gm gπ
ωβ = = (4.275)
βF C π + Cµ C π + Cµ
and in the same time:

ωT = βF ωβ
The frequency corresponding to ωβ is:
ωβ 1 gπ
fβ = = (4.276)
2π 2π C π + C µ
4.6 D.C. Biasing
The locution “DC biasing” generally refers to the procedure of applying

continuos voltages across the transistor junctions, in order to establish the so-
called quiescent point. The quiescent point represents all the continuous
currents and voltages lay on the transistor according to the desired regime of
operation. For this purpose, it is necessary to design a special circuitry known
as biasing circuits. That is why this section treats:
1. Quiescent Point
2. Usual Biasing Circuit
183
4.6.1 Quiescent point

In respect with the above definition, the quiescent point, - or operation point or
static point – is defined by {VCE, VBE, VCB, IC, IB, IE} array. The biasing circuit
must fix all this parameters. Observing that between these six parameters are
linked by four equations:
• two of them being Kirchhoff equations:
IE=IC+IB (4.277)
VCE=VBE+VCB (4.278)
• and other two the device
equations: safe area
iC
PDmax
IC=IC(VBE, VCE) (4.279)
ICmax
IB=IB(VBE, VCE) (4.280) cut-off
region
one concludes, that only two of these
parameters are independent. In saturation
region
general, one chooses as
vCE
independent parameters VCE and IC. VCES
That is the reason why the static
point of a transistor is fixed on the Figure 4.65
output characteristic. Figure 4.65
presents the safe area, in fact the region that allows BJT to operate in active
mode.
One can see that the borders of the safe area are:
• saturation region;
• cut-off region;
• maximum limit of the collector current;
• maximum dissipated power;
• maximum limit of the collector-emitter voltage.
The actual position of the quiescent point inside this region depends of the
application. However, there are some rules that must be followed when a static
point is positioned. These are:
• The guarantee of the linear operation of the transistor. This problem
appears in large-signal regimes. If quiescent point is un-adequate
positioned, the distortion of the signal will occur.
• The control of small-signal parameters. This problem appears in small-
signal regimes. It must be reminded that the small-signal parameters
are related to static values of the both collector current and collector-
emitter voltage.
184
• The control of the power dissipated. This problem appears also in

large-signal regimes. If quiescent point is un-adequate positioned, the
thermal runaway will happen.
4.6.2. Usual Biasing Circuit
Any biasing circuit has an important task: to place the quiescent point so that
the transistor may be able to operate in the best conditions. In addition to this
requirement, two other exigencies must be fulfilled:
• quiescent point stabilization related to temperature
• quiescent point stabilization related to dispersion of the parameters
At this point of discussion, an observation must be made: IC stabilization yields
to quiescent point stabilization. This observation stands because in any
situation IC and UCE are related through a supplementary circuit equation.
A quantitative criterion for the evaluation of the influence of the factors,
mentioned above, to IC may be introduced as follows:
Because vBE is affected - in principal - by the temperature, and β is the most
affected parameter by the dispersion phenomenon, one differentiates the
relation:
i C=iC(vBE, β) (4.281)
Obtaining:
 ∂i   ∂i 
di C =  C  dv BE +  C  dβ (4.282)
 ∂v BE  QP  ∂β  QP
One notes:
 ∂i 
S v =  C  (4.283)
 ∂v BE  QP
 ∂i 
S β =  C  (4.284)
 ∂β  QP
Replacing (4.282 and (4.284) in (4.282) one finds:

di C = S v dv BE + S β dβ (4.285)
For small variations (4.285) becomes:
∆I C ≅ S v ∆VBE + S β ∆β (4.286)
QP QP
185
Under this form, both Sv and S β become two parameters that allow an
estimation of the stabilization quality of the quiescent point.
The most common biasing circuit is presented below.
EC I1 I
IC
RB1 RC
RB1 RC
B C
EC
IB VBE β IB
VCE
I2
RB2 RE
E
RB2 RE
IE
b.) parts function

RB1, RB2 voltage divider; it fixes the appropriate voltage in the
base;
RC load resistor;
RE it represents a negative feedback that assures thermal
stability; IC can not increase while temperature is
increasing. (figure 4.67):
T↑ ⇒ IC↑ ⇒ VRE ↑ ⇒ VE ↑ ⇒ VBE ↓ ⇒ IC ↓
Figure 4.67
where:
VRE drop voltage across RE resistor;
VE emitter potential.
c.) D.C analysis.
Two problems must be treated:
• Direct problem: one considers that the values of the parts are known
and QP must be calculated (analysis problem);
• Reverse problem: one considers that QP is known and the values of the
parts must be calculated (design problem);
c1.) direct problem
Problem formulation: For the circuit diagram presented in figure 4.66, IC must be
calculated. One considers EC, RB1, RB2, and RC, RE, VBE, β known.
Solution:
186
The circuit presented in figure 4.66 is modeled in figure 4.68. Writing Kirchhoff
laws on this new diagram circuit one obtains:
I=I1+βIB (4.287)
I1=I2+IB (4.288)
IB+βIB=IE (4.289)
EC=βIBRC+VCE+IERE (4.290)
-VBE=-VCE-βIBRC+I1RB1 (4.291)
VBE=I2RB2-IERE (4.292)
The equations written above must be completed with:
IC = β IB (4.293)
These seven equations represent a system of seven equations with seven

EC
I
RC RC
B C
EC
IB VBE βIB
EB VCE
EB
RB RE
E
RB RE
IE
unknown variables {I, I1, I2, IB, IE, IC, VCE} and by consequence the problem is
solved. The system written above may be simplified if Thevenin transformation
is applied to base divider. According with this approach, the circuit presented in
figure 4.66 is transformed as figure 4.69 shows. Figure 4.70 represents the
modeled circuit.
Kirchhoff equations are:
IE=IB+βIB (4.294)
EB-VBE=REIE+RBIB (4.296)
where:
RB 2
EB = EC (4.297)
RB1 + RB 2
RB1 RB2
RB = (4.298)
RB1 + RB 2
187
it must be observed that the initial system is reduced to three equations

(4.294)÷(4.296). The solution of this system (regarding IC) is:
β(E B − VBE )
IC = (4.299)
R B + (β + 1)R E
Now the stabilization factors become:
∂I C β
Sv = =− (4.300)
∂VBE R B + (β + 1)R E
∂IC (EB − VBE )(RB + RE )

Sβ = = (4.301)
∂β [RB + (β + 1)RE ]2
The presence of (β+1)RE factor in the denominator shows that the values of Sv
and Sβ may be small even if the values of the resistors are moderate. That
means small variations for IC.
c2.) reverse problem
Problem formulation: For the circuit diagram presented in figure 4.66, RB1, RB2,
and RE must be calculated. One considers that the limits of allowed variation for
IC (ICmin, ICmax) are given. In the same time, EC, RC, UBE, and β are considered
known
•
The worst case solution:

Input parameters:
ICmax maximum value of the collector current;
ICmin minimum value of the collector current;
VBEmax maximum value of the emitter-base voltage;
VBEmin minimum value of the emitter-base voltage;
βmax maximum value of β;
βmin minimum value of β;
The scattering of the parameters mentioned above may have two causes: one
technological and other due to the temperature.
Restrictions:
Upper limit:
IC<ICmax even if β=βmax and VBE=VBEmax (4.302)
Lower limit
IC>ICmin even if β=βmin and VBE=VBEmin (4.303)
Approach:
Observing that
188
β>>1 (4.304)
The (4.299) relation may be approximated as follows:
β(E B − VBE )
IC = (4.305)
R B + βRE
and more:
R 
IC  B + RE  = E B − VBE (4.306)
 β 
Writing this last relation both for upper limit and lower limit conditions one
obtains:
R 
IC min  B + R E  = E B − VBE min (4.307)
 β min 
R 
IC max  B + RE  = E B − VBE max (4.308)
β
 max 
Eliminating EB between those two equations RB becomes:
VBE min − VBE max + [IC max − IC min ]R E
RB = (4.309)
IC max IC min
−
β max β min
This is a linear relation between RB and RE. In the same time, it must be
observed that (4.309) is true only if both RB and RE are positive. That means
that there is a minimum value for RE that assure the physical realization of the
circuit:
VBE max − VBE min
R E min = (4.310)
IC max − IC min
It is obvious that RE must respect:
RE>REmin (4.311)
In the following, RB is chosen according to (4.309). The next step is EB
calculation using (4.307) or (4.308). The effective values for RB1 and RB2 may
be found using (4.297) and (4.298)
The practical solution:
If the scattering of the parameters is reduces, (for example the ambient
temperature is almost constant) a new approach may be applied. The central
189
point of this approach is the minimization of Sv and Sβ. Taking into account that
in normal situations
(β+1)RE>> RB (4.312)
The (4.300) may be rewritten:
1 (4.313)
Sv ≅ −
RE
For Sβ, - if RB is considered small – one finds:

(EB − VBE )
Sβ ≅ (4.314)
β 2R E
Comparing (4.313) with (4.314) one observes that a low value for stability
factors leads to high value for RE, and small value for RB. Generally, it is difficult
to meet this request. In these conditions, according to this approach RE is
chosen as follows:
VRE
RE = (4.315)
IC
where VRE – the drop voltage across RE – is chosen 3-4V.
The next step is RB designing:
RB≅10 RE (4.316)
Observing that
IC
EB =
β
[RB + (β + 1)RE ] (4.317)
RB1 and RB2 become:

EC
RB1 = RB (4.318)
EB
RB1RB
RB 2 = (4.319)
RB1 − RB
190
Problems
Problem 1. This problem is regarding the minority carriers into the base of a
npn transistor. Find the electrons distribution into the base of a npn transistor in
quasi-static regime. The recombination phenomenon may be neglected.
Assume that:
a.) base-emitter voltage is; v BE = 25 VT ;
b.) collector-base is; vCB >>VT
-3
c.) acceptor doing density; NA= 2 × 1016 cm ;
d.) intrinsic carrier density; ni = 1.5 × 1010 cm-3;
e.) base length w = 2µm
Solution:
The current and the continuity equations written for electrons must be
integrated. The boundary conditions are Shockley conditions:
Current equations:
∂n p
j n= qµnnE + qD n (1.35)
∂x
Continuity equations:
∂np np − npo 1 ∂jn
=− + (1.38)
∂t τn q ∂x
Boundary conditions:
v 
n p (0) = n p 0 exp BE  (1)
 VT 
v 
n p ( w ) = n p 0 exp BC  (2)
 VT 
where:
ni2
np 0 = (3)
NA
Observing that:
E≅0 (4)
because the electric field into the base may be neglected,
191
∂n p
≅0 (5)
∂t
because there are quasi-static conditions, and
n p − n po
=0 (6)
τn
because generation recombination phenomenon may be ignored, the two
equations become:
∂n p
jn= qD n (7)
∂x
∂j n
=0 (8)
∂x
Introducing (7) in (8) one finds:
∂ 2 np
=0 (9)
∂x 2
The boundary conditions for this equation may be found replacing vBE and vCB
values into (1) and (2). It follows:
np (0) =
(1.5 × 10 ) 10 2
 25VT
exp

 ≅ 8 × 1014 cm−3 (10)
2 × 10
16
 VT 
np ( w ) ≅ 0 (11)
The general solution of (9) is:

np(x)=K1x+K2 (12)
where K1 and K2 are constants that may be found from boundary conditions:
np(0)=K2 (13)
np(w)=K1 w+K2 (14)
The (13) and (14) equations form a system of two equations with two unknown
quantities K1 and K2. Solving this system one obtains:
K 2 = 8 × 1014 cm−3 (15)
K2
K1 = − = −4 × 1018 cm−4 (16)
2 × 10 −4
Introducing (15) and (16) into (12) one finds the final solution:
n p ( x ) = 8 × 1014 − 4 × 1018 x (17)
x must be expressed in cm.
192
Problem 2 This problem is regarding Ebers-Moll model rearranged for Spice.

There are five topological possibilities to transform a bipolar transistor in a
diode. Set the diode equation for each one.
IC
vBC vBC
iB iB iB iB iB
vBE vBE iE vBE
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5
Solution:
The Ebers-Moll model rearranged for SPICE is
 v   IS 
v  v BC  
i C = IS exp BE  − exp BC
 − exp  − 1 (4.102)
  VT   β R 
 VT  VT  
 v   v  I  v  
i E = I S exp BE  − exp BC  + S exp BE  − 1 (4.103)
  VT   VT  β F   VT  
IS   v BE   IS   v BC  
iB = exp  − 1 + exp  − 1 (4.104)
βF   VT   βR   VT  
Circuit 1; the diode equation is represented by
i A=iA(vBE) (18)
where:
i A=iB (19)
Due to the connection
i C=0 (20)
and this means:
 v   v  I   v BC  
IS exp BE  − exp BC  − S exp  − 1 = 0 (21)
  VT   VT  βR   VT  
Hence:
v   β  v  
exp BC  − 1 =  R exp BE  − 1 (22)
 VT  β
 R + 1   VT  
Introducing this in (4.104) one finds:
193
 1 1  v  
i B = IS  +  exp BE  − 1 (4.104)
 β F β R + 1   VT  
Circuit 2; this time the diode equation is represented by:
iA=iA(vBE) (23)
where:
iA=iE (24)
Now
vBC=0 (25)
Introducing this in (4.103) one finds:
 1  v  
iE = IS 1 +  exp BE  − 1 (26)
 β F    VT  
Circuit 3; it is similar to circuit 1. The only difference is that instead base-emitter
junction is used base collector junction. One observes that the diode equation is
represented by:
iB=iB(vBC) (27)
and
iE=0 (28)
Consequently;
 v   v  I  v  
IS exp BE  − exp BC  + S exp BE  − 1 = 0 (29)
  VT   VT  βF   VT  
v 
and exp BE  becomes:
 VT 
v  1
exp BC  +
v
exp BE

 =  VT  βF
(30)
 VT  1
1+
βF
Introducing this expression into (4.104) one reaches at:
 1 1  v  
i B = I S  + exp BC  − 1 (31)
β
 F + 1 β R   VT  
194
Circuit 4; this circuit is similar to circuit 2. The diode equation is:

i A=iA(vBC) (32)
where:
i A=-i C (33)
The condition is:
vBE=0 (34)
This condition must be introduced in (4.102). One finds:
 1  v  
i A = IS 1 − exp BC  − 1 (35)
 β R   VT  
Circuit 5; the diode equation is represented by:
i B=iB(vBE) (36)
Due to the short circuit connection:
vCE =0 (37)
and that means:
vBC=vBE (38)
In this conditions iB becomes:
 1 1  v  
i B = IS  + exp BE
 V
 − 1
 (39)
β
 F β R   T  
Problem 3 This problem treats the problem of operating modes. For the circuits
presented in figure 1 determine the operating mode for the transistors.
Solution
a.) The base is positive biased from EC through R. The emitter is grounded. By
consequence, the BE junction is forward biased. That means that the
transistor is either in active mode or in saturation. Assume that the
transistor is in saturation. Then the collector potential is VCesat (0.2-0.4V), but
this is impossible because
VCE=EC (40)
Therefore, T is in active mode.
b.) As in a) T is in active mode or in saturation. If:
VCE > VCEsat (41)
195
than T is active region, else T is saturation

EC1 EC2
RL
EC EC
EC EC
R T1 T2 T1 T2
R
R R
T T T R RL RE1 RE2
Figure 1a Figure1b Figure 1c Figure 1d Figure 1e
c.) The base is positive biased from EC through R. The collector is grounded.
By consequence, the BC junction is reverse biased (np junction). On the
other hand, the voltage across the emitter base junction equals the voltage
across the R resistor. The current through R resistor, IB, flows BC junction
and, because this junction is blocked, equals zero. It means that the voltage
across the emitter base junction equals zero and this junction is also
blocked. Therefore, T is cut-off.
d.) The transistor T1 is diode connected. See “circuit 2”, problem 2. His BE
junction is forward biased from EC through R. The drop voltage of BC
junction equals zero because of the short-circuit placed between base and
collector. In conclusion, T1 is operating at the edge between active mode
and saturation mode. Regarding T2, it must be observed that the drop
voltage across its emitter-base junction equals the drop voltage across the
emitter-base junction of the T1. In the same time, its collector is grounded
through RL and, by consequence, its base-collector junction is not forward
biased. In conclusion, T2, may be either in active mode or in saturation. Its
real state depends of RL value. If RL is small enough, its drop voltage is
small enough and VCE 2 > VCEsat . In this situation, T2 is in active mode, else
T2 is in saturation. Something more must be added: this configuration is
known as current mirror and it is frequently used in integrated circuits as
current source. In fact, the current through RL is controlled (equals) by the
current through R. This must be proved relatively simply:
v 
IR = I S1 exp BE1  (42)
 VT 
and
v 
IRL = IS 2 exp BE2  (43)
 VT 
But,
196
vBE1=vBE2 (44)
due to connection, and
IS1=IS2 (45)
due to technology. Therefore:
IRL=IR (46)
Observing that:
v 
EC = v BE1 + IS1R exp BE1  (47)
 VT 
may be concluded that the value of vBE1 may be adjusted through the
value of the R resistor. Because vBE1 controls IRL [see ( 43 ) ÷ ( 46 ) ], one
can say that the current through RL is controlled by the value of the R
resistor. This is good since:
E C − VCEsat
RL < RL max = (48)
IR
e.) This is a current source with npn transistors. This time the resistors, that are
responsible for the value of the IRL current, are moved in the emitters.
Regarding the operation mode, it must be observed that T1 is operating at
the edge between active mode and saturation (see d.) and T2 is operating in
active mode because its BE junction is forward biased through EC2 and RE2.
At limit, if RL exceeds a specified value or EC2 is low enough, T2 may be
saturated. The circuit analysis may be made using second order model
(figure 4.47). Figure 2 presents the circuit model.
vBE=const. (4.138)
i C = β F iB (4.139)
EC1 EC2
RL
C1 B1 B2
C2
iB1 iB2
βF1iB1 βF 2 i B 2
vBE1 vBE2
E1 E2
RE1 RE2
Figure 2
197
Applying the second Kirchhoff’s theorem on the dotted mesh one finds:
v BE1 − v BE2 = −(β1 + 1)iB1R E1 + (β 2 + 1)iB 2 (49)
Considering the two transistors identically may be written:
vBE1=vBE2 (50)
β1 = β 2 (51)
In the same time, it is true that for low power transistors:

β >> 1 (52)
Introducing (50) and (51) in (49) and taking into account (4.139)
and (52) one reach at:
R E1
i C2 ≅ i C1 (53)
R E2
Problem 4 This problem treats the problem of quiescent point. For the circuits
presented in figure 3 determine the quiescent point and the stabilization factors
Assume that β = 200 and VBE=0.7V for all the transistors. One considers that
the current is measured in mA, the voltage in V and the resistance in K Ω ).
EC EC
EC
(25V) (25V)
(25V)
RB RL
EC RB RL (470K) (1K) RB1 RL
(25V) (470K) (1K) (15K) (1K)
RB RL T T T
(470K) (1K)
RE RE RB2 RE
T
(9.3K) (9.3K) (10K) (9.3K)
(
Figure 3a Figure3b Figure 3c Figure 3d
a.) Solution I
The transistor is modeled using second order approximation. The circuit
presented in figure 3a becomes (figure 4):
The system of equations is:
I = I B + β IB (54)
E C − V BE = I B R B (55)
EC = βIBR C + VCE (56)
198
EC
EC (+15V)
(25V) RC1 RL
RB1 RL (11.3)K (1K)
(470K) (1K) )
T1 T2
T
RE1 RE2
(3K) (1.5K)
RB2 RE
(100K) (9.3K)
EE
(-15V)
Figure 3e Figure3f
It has three unknown variable I, IB and VCE., but only IB and VCE are interesting.
One finds:
E C − VBE
IB = = 51 .7 µA
RB RB RL I
(57)
B C EC
R − βR C βRC IB
VCE = B EC + VBE = 14.66 V β IB
RB RB VBE VCE
(58)
E
Finally, the quiescent point co-
ordinates are: Figure 4
IB = 51 .7µA
IC = β IB = 10.24 mA (59)
IE=IC+IB=10.29 mA (60)
VBE=0.7 V
VCE=14.66 V
VCB=VCE-VBE=12.96 V (61)
(4.283) and (4.284) equations give the stabilization factors as follows:
 ∂i 
S v =  C  (4.283)
 ∂v BE  QP
 ∂i 
S β =  C  (4.284)
 ∂β  QP
199
For Sv one finds:

 E − VBE 
∂ β C 

 RB  β
Sv = =− =0.43 (62)
∂v BE RB
 E − VBE 
∂ β C 
Sβ = 
RB  = E C − VBE = 0.052
(63)
∂β RB
b.) Solution II (SPICE solution)

The transistor is 2N2222. One finds:
VCE=14.3810 V
VBE=.7038 V
Figure 5
b. ) Solution I ;is based on first order
approximation model for the transistor. According to this approximation, the
circuit diagram from figure 3b is modeled in figure
6
RB RL
The kirchhoff theorems yield to: B C
EC
IE = IB + β IB (64) IB VBE βIB
VCE
EC=βIBRL+VCE+IERE (65) E
RE
-VBE=-VCE-βIBRL+RBIB (66) IE
The solutions are: Figure 6
IB =
(EC − VBE ) = 10.39µA (67)
RB + (β + 1)R E
VCE=EC-βIBRL-(β+1)IBRE=21.04 V (68)
Therefore the co-ordinates of the quiescent point are
IB = 10.39µA
IC=βIB=2.078 mA (69)
IE=IB+IC=2.089 mA (70)
VBE=0.7 V
VCE=4.4 V
200
Now the stabilization factors become:
∂I C β
Sv = =− =0.085 (72)
∂VBE R B + (β + 1)R E
∂IC (EC − VBE )(RB + RE )

Sβ = = ≅ 0.002 (73)
∂β [RB + (β + 1)RE ]2
Comparing these values with those obtained for the circuit described in figure
3a one can conclude that this one is more stable in respect with the parameters
scattering.
b. ) Solution II (SPICE solution)
This time the results are:
VC=23.0080 V (collector voltage)
VB=19.3040 V (base voltage)
VE=18.6410 V (emitter voltage)
VCE=4.367 V
VBE=0.663 V
VCB=3.704 V Figure 7
c. ) Solution I ;
The circuit diagram presented in figure 3c is modeled in figure 8 and the system
of equations is presented below:
IE=IB+βIB (74)
EC=IERL+VCE +IERE (75)
RL
-VBE=-VCE+IBRB (76) B
RB
C
EC
IB βIB
The solutions are: VBE VCE
E C − VBE E
IB = ≅ 9.6 µA (77)
R B + (β + 1)(RL + RE )
RE
IE
IE =
(β + 1)(E − V ) =1.92 mA
C BE
(78) Figure 8
R + (β + 1)(R + R )
B L E
E C − VBE
VCE = VBE + R B =5.2 V (79)
R B + (β + 1)(R L + RE )
They must be completed with:
201
β(E C − VBE )
IC = =1.91 mA (80)
R B + (β + 1)(RL + R E )
The stabilization factors are:
∂IC β
Sv = =− ≅ 0.079 (82)
∂VBE R B + (β + 1)(RE + RL )
∂IC (EB − VBE )(RB + RE + RL )

Sβ = = ≅ 0.002 (83)
∂β [RB + (β + 1)(R E + R L )]2
Solution II (SPICE solution)
The SPICE diagram circuit is presented in
figure 9. The results are:
VC=23.1440V
VB=17.9250V
VE=17.2650V
VCE=5.8815V
VBE=0.66V
VCB=5.2251 V
Figure 9
d. ) Solution I ;
The circuit diagram presented in figure 3d was treated in section 4.6 (see figure
4.66). The modeled circuit is presented in figure 4.68 and the system of
I I
equations associated is formed by
(4.287) ÷ (4.292). Both the modeled circuit
1
R B1 R L
B C and the system of equations are transferred

E
IB V BEβI B here. The notations introduced in figure 3d
C
V
I
2
were preserved.
CE
E
RB2 RE
IE
I=I1+βIB (84)
Figure 10
I1=I2+IB (85)
IB+βIB=IE (86)
EC=βIBRC+VCE+IERE (87)
-VBE=-VCE-βIBRL+I1RB1 (88)
202
VBE=I2RB2-IERE (89)
The solutions – without I, I1 and I2, which are unimportant - are:
(β + 1) E C
R B2 
− VBE 
 RB1 + R B 2 
IE = =0.981 mA (90)
RB1RB 2
+ (β + 1)R E
RB1 + RB 2
RB 2
EC − VBE
RB1 + R B2
IB = = 4.88 µA (91)
RB1R B 2
+ (β + 1)RE
RB1 + R B2
VCE= EC-βIBRC-IERE=14.9 V (93)

For IC, and VCE one obtains:
I C = βIB = 0.976 mA (94)
The stabilization factors become:
∂IC β
Sv = =− =0.105 (96)
∂VBE R B1R B2
+ (β + 1)RE
RB1 + RB 2
R B2 R R
(EC − VBE )( B1 B 2 + RE )
∂I RB1 + R B2 RB1 + R B2
Sβ = C = =0.00004 (97)
∂β
2
 RB1RB 2 
 + (β + 1)R E 
 R B1 + RB 2 
Solution II
This solution uses Thevenin transformation. Figure 11 presents the
EC
I
RC RL
B C
EC
IB VBE βIB
EB VCE
EB
RB RE
E
RB RE
IE
Figure 11 Figure 12
203
transformation of the circuit exposed in figure 3d. This circuit is modeled in

figure 12.
where:
RB 2
EB = EC (98)
RB1 + RB 2
R B1 R B2
RB = (99)
RB1 + RB 2
Kirchhoff equations are:

IE=IB+βIB (100)
EC=βIBRC+VCE+IERE (101)
EB-VBE=REIE+RBIB (102)
The solutions of this system are identically with those shown in ( 90) ÷ ( 95) .
Solution III
This solution uses “first order approximation”; (4.134) and (4.135) equations.
• vBE=0.7 V (constant) (103)
• IC=IE (104)
Step I (one establishes collector current)
Because collector current equals emitter current, base current is considered
zero:
IB(1) = 0 (105)
In these circumstances, the potential into the base may be written as:
RB 2 10
VB(1) = EC = 25 = 10 V (106)
RB1 + R B 2 15 + 10
The emitter potential is:
VE(1) = VB(1) − VBE = 10 − 0.7 = 9.3 mA (107)

The collector current may be obtained observing that:
VRE=VE (108)
VRE=ICRE (109)
From (108) and (109) it results:
204
VE(1) 9.3
IC(1) = = = 1 mA (110)
RE 9 .3
Step II
This step validates the IC value. The validation procedure requires a new
estimation for IC (noted I(C2 ) ). If
IC( 2) − IC(1) < ε (111)
where ε is an acceptable error, then one considers:
IC = IC(1) (112)
else a new IB and IC are computed. The procedure stops when (111) is satisfied.
Assuming that ε = 10% , for this problem one finds:
I(C1) 1
IB( 2) = = = 0.005 mA (113)
β 200
(
VB( 2 ) = EC − IB( 2)RB1 ) R R+ R
B2
= 14.949 V (114)
B1 B2
VE( 2 ) = VB( 2) − VBE = 9.249 V (115)
VE( 2) 9.249
IC( 2) = = = 0.995 mA (116)
RE 9 .3
Comparing the currents one finds:
IC( 2) − IC(1) = 0.995 − 1 = 0.005 (117)
The (111) criterion is satisfied. In conclusion, the co-ordinate of the quiescent

point are:
IC=1 mA
IE=1 mA
IB=0 mA
VBE=0.7 V
VCE=EC-IC(RL+RE)=25-1*(1+9.3)=14.7 V
VCB=VCE-VBE=14.7-0.7=14V
205
Solution IV (SPICE solution)

Figure 13 presents the results. The voltages required by the quiescent point
are:
VC=24.0030 V
VB=9.9654 V
VE=9.3241 V
VCE=14.0376 V
VBE=0.6413 V
VCB=13.3963 V
e. ) Solution I ;
The circuit diagram presented in figure 3e is
modeled in figure 14. The second order
approximation was used for the transistor. The
Figure 13
system of equations is:
I=I1+ β IB (118)
I1=IB+I2 (119)
RB1 RL
B I1 C
IE = IB + β IB (120) IB
VBE βIB VCE I
EC=RLI+VCE+REIE (121) I2 EC
E
-VBE=-VCE+RB1I1 (122) RB2
RE
IE
VBE=RB2I2-REIE (123)
Figure 14
The solutions are:
ECRB2 − VBE (RL + RB1 + RB2 )
IB = = 4.6µA (124)
(β + 1)[RE (RL + RB1) + RB2 (RL + RE )] + RB1RB2
IE = (β + 1)IB =0.92 mA (125)
IC= β IB=0.91 mA (126)

VCE=VBE+RB1I1=14.2 V (127)
The stabilization factors are:
−R E (R L + R B1 ) − R B2 (R L + R E )
Sβ = (129)
{R B1R B2 + (β + 1)[R E (R L + R B1 ) + R B2 (R L + R E )]}
2
206
S β = −97.7 × 10 −9
−(R L + R B1 + R B 2 )
Sv = (130)
R B1R B2 + (β + 1)[R E (R L + R B1 ) + R B2 (R L + R E )]
S v = 5.121× 10 −3
The circuit diagram used for
simulation is presented in figure 15.
The results are:
VC=23.1530 V
VB=9.2292 V
VE=8.5900 V
VCE=14.5630 V
VBE=0.6392 V Figure 15
VBC=13.9238 V
f. ) Solution I ;
The circuit diagram presented in figure 3f is modeled in figure 16.
EC
RC1
RL
C1 B1 B2
C2
iB1 iB2
βF1iB1 β F2iB2
vBE1 vBE2
E1 E2
R E1 RE2
-EE
Figure 16
Applying the same approach used for the circuit diagram represented in figure
2, one finds:
VBE1 − VBE2 = −(β1 + 1)IB1RE1 + (β 2 + 1)IB2RE2 (131)
Considering the two transistors identically one reaches at:
RE1
IC 2 ≅ IC1 (132)
RE 2
where IC1 may be approximated as follows:
207
EE − VBE1
IC1 = (133)
R C + RE1
The solutions are:
IC1=1mA
IC2=1mA
IC1
IB1 = = 5µA
β
I
I B 2 = C2 = 5µA
β
IE1=IC1+IB1=1.05 mA
IE2=IC2+IB2=1.05 mA
VCE1=0.7V
VBE1=0.7V
VCB1=0V
VCE2 ≅ EC+EE-IC2(RL+RE2)=26V (134)
VBE2=0.7V
VCB2=25.3 V
The circuit diagram is presented in
figure 17. The solutions are (only
dots potentials):
VC1=-11.3550 V
VB1=VB2=-11.3550 V
VE1=-11.9930 V
VC2=14.0030 V
Figure 17
VE2=-12.0010 V
208
• Common Emitter
• Common Collector
• Common Base
• By Hand Large-Signal Analysis
• By Hand Small-Signal Analysis
Chapter 5
The Fundamental Bipolar Transistor Circuits
Under this title, the theory of the electronic circuits treats the behavior of the
circuits based on principal connection of the bipolar transistor:
• common emitter connection;
• common collector connection;
• common base connection.
This chapter presents a comprehensive analysis of these circuits and in
addition – as a result – by hand analysis techniques for bipolar transistors are
developed. The outline of the chapter is:
• The first section is dedicated to common emitter connection.
Transfer characteristic is developed and based on this,
amplification and commutation applications are presented. For
amplification circuit, voltage gain, input and output resistances are
computed. The frequency response is also treated.
• The second section presents the common collector connection.
• The third section analyses the common base connection. Both
second and third sections treat the same topics as section one did.
• The fourth section presents an analysis technique dedicated to DC
regime. This technique uses first order approximation model for the
transistor.
• The fifth section exposes a procedure for evaluation of the
incremental resistaces of the transistor.
209
Device Modeling for Circuit Simulation
5.1 The Common Emitter Connection
The input signal is applied between base and emitter terminals and the output
signal is generated between collector and emitter terminals.
EC EC EC
iC iC EC
iC βiIN
RC RC RC vCEsat RC
iIN C iIN B C
B B C
E vIN
vIN vO vIN vO vO vIN vBEsat vO
E
E
Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4
b.) parts function

RC load resistor;
v IN total instantaneous value of the input voltage;
iIN total instantaneous value of the input current;
vO total instantaneous value of the output voltage
c.) large signal analysis
This analysis is dedicated to transfer characteristic;
v O=v O(v IN) (5.1)
Theoretically, v IN may vary between - ∞ and + ∞ . This large range of variation
implies the usage of different types of models for the transistors, according to
their state:
I. For
v IN ∈ (− ∞, Vγ ) (5.2)
the transistor is blocked. The circuit presented in figure (5.1) must be modeled
as figure 5.2 shows. It is obvious that:
v O=EC (5.3)
II. For:
[
v IN ∈ Vγ , v BEsat ) (5.4)
the transistor is in active region. The circuit diagram from figure 5.1 is modeled
in figure 5.3. Observing that:
210
v O=EC-i CRC (5.5)

and
v BE
i C = I S exp (5.6)
VT
v BE=v IN (5.7)
for output voltage one finds:
v IN
v O = E C − IS R C exp (5.8)
VT
III. For:
v IN ≈ v BEsat (5.9)
the transistor is in saturation. The circuit diagram presented in figure 5.1 is

modeled in figure 5.4. One may observe that the output voltage is:
v O=v CEsat. (5.10)
Tacking into account (5.3.), (5.8) and (5.10), (5.1) becomes:
 EC if v IN ∈ (− ∞, Vγ )

vO
v
= E C − I S R C exp IN
VT
[
if v IN ∈ Vγ , v BEsat . ) (5.11)
 if v IN ≈ v BEsat .
 v CEsat .
and it is represented in figure 5.5. Related to this figure some observations
must be made:
vO Cut-off Region 1. The stage may operate as an amplifier
EC vBEsat.
if the transistor is working in active region.
Active Region
In this case, the input voltage varies
Vγ
Saturation Region between knee voltage Vγ and v BEsat.
vCEsat
(approx. 150-200 mV). If linear operation is
vIN
0.5V 1V needed, then the range of variation for v IN
Figure 5.5 is only 10mV (the so called “small signal
condition”). It is the duty of the bias circuit
to settle the operating point in this region.
2. This stage may operate as a switching circuit. In this case it runs between
cut-off and saturation regions.
d.) SPICE simulation.
For SPICE simulation the circuit drawn in figure 5.6 was used. The results are
presented in figure 5.7.
211
One may observe that they are very similar to those presented in figure 5.5.
Figure5.6 figure 5.7
In this case eIN was varied between –15V to +15V with a step of 0.1V. The
transition region begun at 573mV and ended at 715mV
5.1.1 Common Emitter Amplifier
The previous section treated the large signal behavior of this connection. This
section treats the small signal behavior.
a.) circuit diagram is presented in figure 5.8. EC
b.) parts function RB1 RC
RB1, RB2 bias divider; they set-up the Iin

C1
C2
base potential of the
transistor. Vin
Vo
RE thermal stability; RB2 RE CE
C1,C2 coupling capacitors; they
isolate the DC operating point;
for large enough frequencies Figure 5.8
the signal passes through the
coupling capacitors.
CE de-coupling capacitors; for large enough frequencies the
emitter may be considered grounded.
RC load.
c.) small signal analysis
This section treats;
• voltage gain;
• input resistance;
• output resistance;
• frequency response.
c1.) voltage gain
It is defined as:
212
Vot
AV = (5.12)
Vt
where (see figure 5.9)

Vt test voltage source (amplitude);
Vot circuit response to voltage test (amplitude).
EC
Ir
RB1 RC
It Ib B C Ic
It
C1
C2
Vt RB rπ Vbe gmVbe RC Vot
Vot E
Vt
RB2 RE CE
The circuit from figure 5.9 is modeled in figure 5.10. RB is:
R B1R B 2
R B = R B1 R B 2 = (5.13)
R B1 + R B 2
One finds:
Vot=-gmVbeRC (5.14)
Vt=Vbe (5.15)
Introducing (5.14) and (5.15) in (5.12) one reaches at:
A v = −g m R C (5.16)
The (5.16) expression proves that:

• the voltage gain is high;
• the phase difference between the output voltage and input voltage is
1800 (minus sign).
c2.) input resistance
It is defined as:
Vt
R in = (5.16)
It
Rin may be determined using 5.10 figure.

It=Ir+Ib (5.17)
213
Vt
It = (5.18)
RB
Vt
Ib = (5.19)
rπ
(5.16) ÷ (5.19) expressions yield to:

R in = R B rπ (5.20)
Because in many cases:

RB>> rπ (5.21)
(5.20) may be rewritten:

R in ≅ rπ (5.22)
In conclusion, the input resistance has a moderate value that equals rπ
c3.) output resistance;

It is defined as:
Vt
Ro = (5.23)
It
Vin = 0
Figure 5.11 shows the placement of the testing source. In the same time it
must be observed that the short circuit condition from (5.23) relation is realized
by CS.
+EC
RB1
RC It
B C It It
+
C2 +
+
RB rπ Vbe gmVbe RC Vt RC Vt
C1
Vt
CS - -
RB2 RE CE E
-
Figure 5.11 Figure5.12 Figure 5.13
The circuit presented in figure 5.11 is modeled in 5.12. Because:

Vbe=0 (5.24)
The circuit diagram from figure 5.12 is reduced as figure 5.13 exposes. By
consequence:
214
Ro=RC (5.25)
In conclusion, the output resistance has a moderate value that equals RC.
c4.) frequency response;
The analysis presented above did not take into account the capacitive effects.
From this point of view it was an incomplete analysis. A global examination is
very difficult to be done. The usual way to include these effects is to consider
three situations:
1. high frequency response of the circuit;
• the parasitic capacitors ( C π and C µ ) must be introduced in the
modeled circuits;
• the coupling and de-coupling capacitors are considered short
circuit;
the new circuit is named high frequency circuit model.
2. medium frequency response of the circuit;
• the parasitic capacitors ( C π and C µ ) are considered open circuit;
• the coupling and de-coupling capacitors are consider short circuit;
the new circuit is named medium frequency circuit model; it is the
situation treated until now.
3. low frequency response of the circuit;
• the parasitic capacitors ( C π and C µ ) are considered open circuit;
• the coupling and de-coupling capacitors must be introduced in the
modeled circuits;
the new circuit is named low frequency circuit model.
This approach allows a simple method to inspect all kind of functions of the
circuit. This section treats only the voltage gain defined as:
Vo (ω)
A v (ω) = (5.26)
E in (ω)
where and Vo and Ein are defined in figure 5.14.
EC
Iin
RB1 RC
RG C1
C2
+
RL Vo
Ein Vin
RB2 RE CE
-
Figure 5.14
215
In order to enlarge the analysis, the circuit diagram presented in figure 5.9 is
completed with an external load (RL) and the driving circuit Thevenin modeled
(Ein ,RG). Figure 5.14 exposes the new circuit diagram.
• high frequency response;
The high frequency circuit diagram is showed in figure 5.15.
Iin = Ir + Irπ + ICπ + ICµ (5.27)
ICµ + Ic = gm Vbe (5.28)
Ein = RRIin + RBIr (5.29)
0 = rπIrπ − RBIr (5.30)
RG Cµ
Iin B ICµ C Ic
+ Ir Irπ ICπ
Ein Vin RB rπ Cπ Vbe gmVbe RCL Vo
- E
Figure 5.15
ICπ
0= − rπIrπ (5.31)
sC π
ICµ ICπ
0= + Vo − (5.32)
sC µ sC π
0 = Vo − R CLIc 0 (5.33)
and
ICπ
Vbe = (5.34)
sC π
From the reasons of simplicity, the Laplace transformation was used. Solving
this system, Av becomes:
sCµ
1−
Vo gR R gm
= − m LC (5.35)
Ein RG 1+ s(CµRLC + CµR + CπR + gmRLCRCµ ) + s2RLCRCπCµ
216
where:
R = RG RB rπ (5.36)
It is interesting to be observed that at middle frequency the voltage gain is:
g m R LC r π
A v = A v ( ω) =− (5.37)
R G + rπ
ω=0
which is similar to (5.16). One may observes that (5.36) has a zero and two
poles as follows:
gm
z1 = − ≅ −ω T (5.38)
Cµ
Cµ (RLC + R + gmRLCR ) + CπR

p1 = − +
2RRLCCπCµ
(5.39)
[C (R ]
2
µ LC + R + gmRLCR ) + CπR − 4RRLCCπCµ
+
2RRLCCπCµ
p2 = − −
2RRLCCπCµ
(5.39’)
[C (R ]
2
µ LC + R + gmRLCR ) + CπR − 4RRLCCπ Cµ
−
2RRLCCπ Cµ
Under this form poles expression are non-usual. Usual approach considers:
RG>>rπ (5.40)
RB>>rπ (5.41)
RLC→0 (5.42)
and poles expressions may be simplified:
1 ω
p1 ≅ − ≅ − T ≅ −ω β (5.43)
rπ (C π + C µ ) β
 1 1 1 g   1 g 
p 2 ≅ − + + + m  ≅ − + m  < −ωT (5.44)
 RLCCµ RCπ RLCCπ Cπ  r C C
   π π π 
A more detailed look on the simplifications made in the (5.43) and (5.44)
expressions may by found in the problem 4 from the end of the chapter.
217
In conclusion the first pole – the dominant pole – is situated near ωβ . The other
pole corresponds to a frequency superior to ω T (very high). The frequency
corresponding to the “zero” is also ω T . In these conditions, the first pole
dictates the high frequency behavior of the stage. Figures 5.16 and 5.17
Au
dB
jω
s plan
p2 z1 p1 σ
p1 z1 p2 ω
indicate the poles position in s plan and the shape of the gain characteristic.
• low frequency response;
The low frequency circuit diagram corresponding to circuit diagram presented
in figure 4.14 is showed in figure 5.18. One can observe that C1, C2 capacitors
and RB1, RB2 resistors were omitted for simplicity reasons. In fact for certain
situations CE contribution at low frequency response is essential.
RG
Ib B C Ic
rπ βIb RLC
+ E
Ein Vo
- RE CE
Figure 5.18
Noting:
RE
ZE = RE CE = (5.45)
1+ sRECE
it may be written:
Vo=-βRLCIb (5.46)
Ein=Ib(RG+rπ)+ZE(β+1)Ib (5.47)
Dividing (5.46) through (5.47) one reaches at:
218
β RE (1 + sRECE )
Av = − (5.48)
[RG + rπ + (β + 1)RE ] + sRECE (RG + rπ )
This expression has a zero:
1
z1 = − (5.49)
RECE
and a pole:
RG + rπ + (β + 1)RE β
p1 = ≅− (5.50)
RECE (RG + rπ ) CE (RG + rπ )
For normal situations, the pole is much higher then the zero. The shape of the
gain voltage characteristic for low frequency is displayed in figure 5.19.
Au
dB
z1 p1 ω
Figure 5.19
d.) SPICE analysis

Figure 5.20 shows the circuit diagram used for simulation. Figure 5.21 exposes
the results of simulation.
Due to relatively low input impedance, the stage must be suitable driven by a
current source. RG transforms the input voltage source into a current source.
One can observe that:
• at high frequency there is a dominant pole situated at 592 MHz
• at low frequency there is a dominant pole situated 30 Hz
219
5.1.2 Common Emitter Inverter

The digital electronics processes discrete signals. These signals have only two
possible values. Generally the lower value is considered “0” logic or false and
higher value is considered “1” logic or true. This association allows the use of
the Boole algebra formalism in digital electronics. From this point of view the
inverter, based on a common emitter circuit, is the simplest digital circuit. It
realizes “not” function. In the following, this circuit is analyzed.
a.) schematic diagram is presented in figure 5.22.
EC EC
EC
RC RC
vCEsat RC
RB C RB
B B C
v IN ≈ 0
E vIN ≈ EC
vIN vO vO vBEsat vO
E
Figure 5.22 Figure 5.23 Figure 5.24
b.) parts function

RB limiting resistor.
RC load resistor.
c.) circuit analysis
Two problems are treated:
• direct problem or:
v O=v O(v IN) (5.51)
characteristic, and
• reverse problem or the design problem; assuming (5.51) known, RB
and RC must be dimensioned.
c1.) direct problem
The (5.51) characteristic must be developed considering that EC, RC and RB are
known. The difficulty of the problem resides in the fact that v IN has only two
values. Figure 5.25 exposes this situation.
One may observe that in real situations the voltage levels are replaced by
zones, due to parameters scattering. This does not change the essence of the
problem: the (5.51) characteristic is a boolean function and it must be described
using boolean formalism. Figure 5.25 defines also the association between the
voltage levels and the logic states. In these conditions the problem may be
reformulated as follows:
220
find the output logic state of the voltage assuming known the input logic
state of the voltage.
voltage voltage
high level high level logic

EC approx. EC “1”
low level low level logic

0V approx. 0V “0”
ideal real
situation situation
Figure 5.25
The solution is:

• if
v IN ≈ 0 V (5.52)
then
v O ≈ EC (5.53)
(see figure 5.23)
• if
v IN ≈ E C (5.54)
then
v O ≈ 0V (5.55)
(see figure 5.24)
According to (5.52)÷(5.55) the truth table of the v O vIN vO
function is presented in table 5.1. Using canonical
forms v O may be written as: 0 1
v O = v IN (5.56) 1 0
Table 5.1
The RB and RC resistors may be dimensioned forcing the saturation condition:
βiB > i C (5.57)
where:
EC
iB ≅ (5.58)
RB
and
221
EC
iC ≅ (5.59)
RC
The (5.57)÷(5.59) expressions yield to:
βR C > R B (5.60)
In the same time it must be noted that cut-off conditions are implicit realized
because low level voltage is smaller then Vγ , the knee voltage.
5.2 The Common Collector Connection
The input signal is applied between base and collector terminals and the output
signal is generated between emitter and collector terminals.
EC
iIN B C EC
EC EC B C
C
iIN iIN B vBE βiIN vBEsat vCEsat
E E
vIN E
vIN vIN vIN
RE vO RE vO RE vO vO
RE
b.) parts function

RE load resistor;
This analysis is dedicated – as previous chapter did - to transfer characteristic:
v O=v O(v IN) (5.1)
The transistor model will be picked up in respect with the v IN value:
I. For
v IN ∈ (− ∞, Vγ ) (5.61)
222
the transistor is blocked. The circuit presented in figure (5.26) is modeled in

figure 5.27. It is obvious that:
v O=0 (5.62)
II. For:
v IN ∈ [ Vγ , EC) (5.63)
the transistor is in active region. The condition:

v CB=0 (5.64)
was considered the limit of incipient saturation. The circuit diagram from figure
5.26 is modeled in figure 5.28. It must be noticed that this time the transistor
was modeled using second order approximation, because v IN does not equal
v BE. Applying K2 theorem on the dotted mesh one finds:
v O=v IN-v BE (5.65)
III. For:
v IN=EC (5.66)
the transistor is in saturation. The circuit diagram presented in figure 5.26 is
v O=EC-v CEsat. (5.67)
From (5.62.), (5.65) and (5.67) expressions, the (5.1) transfer characteristic
may be rewritten:
 0 for v IN ∈ (− ∞, Vγ ]
v IN ∈ (Vγ , E C )

v O =  v IN − v BE for (5.68)
E − v for v IN = E C
 C CEsat.

must be made:
vO 1. The stage may operate as an
EC-vCEsat. amplifier if the transistor will work in the
active region. In this case, the input
Saturation Region
voltage varies between knee voltage Vγ
Active Region
and EC. The operation is nearly linear,
Vγ EC vIN but the amplification ratio is almost one.
Cut-off Region It is the duty of the bias circuit to settle
the operating point in this region.
Figure 5.30
2. This stage may operate as a
switching circuit. In this case it runs between cut-off and saturation regions.
223
Figure 5.31 presents the circuit used for simulation. Figure 5.32 presents the
results of the simulation. EIN – the input voltage – was varied between –15V
and 15 V. the output characteristic is very similar to that exposed in figure 5.30.
e.) application - common collector amplifier The previous section treated

the large signal behavior of this connection. This section treats only the small
signal behavior.
e.1) schematic diagram is presented in figure 5.33.
e.2) parts function
RB1, RB2 bias divider; they set-up the base potential of the transistor.
RE load and thermal stability;
C1,C2 coupling capacitors; they isolate the DC operating point; for
large enough frequencies the signal passes through the
e.3) small signal analysis EC
This section treats; RB1

voltage gain; Iin
• C1
• input resistance; C2
• output resistance; Vin
• frequency response. RB2 RE Vo
• voltage gain
The 5.12 definition is maintained: Figure 5.33
Vot
AV = (5.12)
Vt

224
The circuit from figure 5.34 is modeled in figure 5.35.
EC
It Ib B C Ic
RB1
It rπ βIb
C1
E
C2
Vt Ir RB
Vot
Vt RE Vot
RB2 RE
where RB is also given by 5.13:
R B1R B 2
R B = R B1 R B 2 = (5.13)
R B1 + R B 2
For Vot one finds:

Vot= (β + 1)Ib R E (5.69)
If Vt is expressed from the dotted mesh:

Vt = Ib rπ + (β + 1)R E (5.70)
Introducing (5.68) and (5.69) in (5.12) one reaches at:
Av =
(β + 1)RE (5.71)
rπ + (β + 1)R E
This expression may be simplified because usually:

(β + 1)R E >> rπ (5.72)
Therefore, the voltage gain may be approximated as follows:

Av ≅ 1 (5.73)
Conclusions;
• the voltage gain equals unity (there is no gain);
• there is no the phase difference between the output voltage and input
voltage.
• input resistance
It is defined according to (5.16):
Vt
R in = (5.16)
It
225
and may find using 5.35 figure.

It=Ir+Ib (5.74)
Vt
It = (5.75)
RB
Ib is derived from (5.70)

Vt
Ib = (5.76)
rπ + (β + 1)R E
(5.16) together with (5.74) ÷ (5.76) expressions yield to:

R in = R B [ rπ + (β + 1)R E ] (5.77)
Considering:
R in = R B >> [ rπ + (β + 1)R E ] (5.78)
Rin may be rewritten:

R in ≅ rπ + (β + 1)R E (5.79)
Once again, tacking into account (5.72), Rin expression may be simplified:
R in ≅ (β + 1)R E ≅ β R E (5.80)
Conclusions:
• the input resistance is very high;
• the resistance that is seen into the base of transistor equals the emitter
resistances multiplied by beta (in special cases rπ must be added).
It is defined using (5.23):
Vt
Ro = (5.23)
It
Vin = 0
and figure 5.36 shows the placement of the testing source. In the same time it
by CS.
226
+EC
RB1
Ib B C
rπ βI b
C2 It It
RB
C1 E Ie +
+
CS
RB2 RE Vt RE Vt
-
-
Figure 5.36 Figure5.37
The circuit presented in figure 5.36 is modeled in 5.37. The test current is:
I t = Ie − (β + 1)Ib (5.81)
where:
Vt
Ie = (5.82)
RE
and
Vt
Ib = − (5.83)
rπ
Introducing (5.82) and (5.83) into (5.81), for Ro one finds:

rπ
R o = RE (5.84)
β+1
Usually
rπ
R E >> (5.85)
β +1
so that output resistance may be approximated:
rπ r
Ro ≅ ≅ π (5.86)
β +1 β
Conclusions:
• the output resistance has a low value;
• the resistance that is seen into the emitter of a transistor equals the
base resistances divided by beta.
Observation: Due to its qualities:
• high input resistace;
• low output resistance;
227
• unitary gain,
this stage is used as buffer stage. It is also called emitter follower.
• frequency response
This section treats the frequency behavior of the voltage gain, the input
impedance and the output impedance because all these three parameters are
important when the stage is used as a buffer. In order to simplify the analysis,
the effects of Cµ and RB will be neglected.
• frequency response – gain voltage
The modeled circuit is presented in figure 5.38
It IC B
rπ Cπ Vbe
Ir E Io
Vt
gmVbe RE Vot
Figure 5.38
On this circuit it may be written:

Vt=Vbe+Vo (5.87)
Vbe
It = (5.88)
Zπ
rπ
Zπ = (5.89)
1 + srπ C π
Vot
I t + g m Vbe = (5.90)
RE
Din (5.88) ÷(5.90) results:

Vot 1
Vbe = (5.91)
RE 1
gm + (1 + sC π rπ )
rπ
Replacing (5.91) and (5.88) into (5.87) one reaches at:

Vot 1
Vt = + Vot (5.92)
RE 1
gm + (1 + sC πrπ )
rπ
228
From here one obtains:

 1
 gm + RE + sC πRE
Vot rπ 
=  (5.93)
Vt  1
1 +  gm + RE + sC πRE
 rπ 
The final expression (5.93) has a zero and a pole:

gm + gπ g
z1 = − ≅ − m ≅ −ωT (5.94)
Cπ Cπ
1 + (gm + gπ )RE
p1 = − (5.95)
C πR E
The (5.95) expression may be also simplified as follows:

1 + (gm + gπ )RE 1+ gmRE g R g
p1 = − ≅− ≅ − m E ≅ − m ≅ −ωT (5.96)
CπRE CπRE CπRE Cπ
Both the zero and the pole are situated around ω T but the zero is generally a
little bit higher. In fact at high frequency the effect of Cµ must be taken into
account.
• frequency response – input impedance
The simplest to find the Laplace transformation of the input impedance is to
replace rπ with Zπ into the (5.79) expression. Zπ represents the equivalent
impedance of the rπ and Cπ parallel group. So:
Zin=Zπ.+(gm Zπ.+1)RE (5.97)
Where:
rπ
Zπ = (5.98)
1 + sr π C π
Bringing (5.98 into (5.97) Zin becomes:

rπ + R E + g m R E rπ + sC π rπ R E
Z in = ≅
1 + sC π r π
Cπ (5.99)
1+ s
g R r + sC π rπ R E gm
≅ m E π = gm rπ R E
1 + sC π rπ 1 + sC π rπ
The (5.99) expression emphasizes a “zero”:
229
gm
z1 = − ≅ −ω T (5.100)
Cπ
and a pole:
1 ω
p1 = ≅ − T = ωβ (5.101)
C π rπ β
The pole is much lower then the “zero” so the pole acts the first in frequency
response. It means that the frequency corresponding at a decrease of 3 dB for
the input impedance magnitude is:
ωHZi ≅ ωβ (5.102)
The (5.102) formula shows that the input impedance has high value only for a
low range of frequency. It is also interesting to note that for high frequency Zin
becomes:
ω→∞ ⇒ Z in → R E (5.103)
In the same time, noting:

R=(1+gmRE)rπ (5.104)
Cπ
C= (5.105)
1 + gmRE
the input impedance may be rewritten:
R  1 
Z in = + R E =  R  + R E (5.106)
1 + sCR  sC 
That means that the input impedance may be B
represented as figure 5.39 exposes.
Conclusions:
C R
1. The input impedance is decreasing while Zin
the frequency is increasing. It has a
capacitive behavior.
RE
2. The high value (approx. βRE) is maintained
only for low frequencies
3. The “zero” is too high (approx. ωT) to
induce any influence in the frequency Figure 5.39
behavior.
230
• frequency response – output impedance

The output impedance may be found using the same approach. The only
difference is the presence of RS figured in circuit diagram from figure 5.40. RS
is the output impedance of the driving stage.
rπ Cπ Vbe
E It
RS
+
gmVbe RE Vt
-
C
Figure 5.40
Zo becomes:
rπ
1 + sC π rπ
Z o = RE (5.107)
rπ
1 + gm
1 + sC π r π
More exactly Zo is:
Zo =
(
RE R s + rπ + sC πrπ R S ) (5.108)
R S + rπ + (1 + gmrπ )R E + sC πrπ (R E + R S )
So there is a “zero” and a pole:

RS + rπ
z1 = − (5.109)
C π rπR S
R S + r π + (1 + gmrπ )RE
p1 = − (5.110)
C πrπ (RE + R S )
For a easier estimation of their position, RS will be considered of low value and
gmrπ of high value. In these circumstances both the “zero” and the pole may
approximated as follows:
1
z1 = − (5.111)
C πRS
gm
p1 = − ≅ −ω T (5.112)
Cπ
231
The pole is much higher then the “zero” so the “zero” acts the first in frequency
response. It means that the frequency corresponding at a decrease of 3 dB for
the output impedance magnitude is determined by the “zero” and it is a low
frequency.
Conclusions:
1. The output impedance is increasing while the frequency is increasing. It
has an inductive behavior.
R + rπ
2. The low value (approx. S ) is maintained only for low frequencies
β
3. At high frequencies Z o ≅ R S
4. The pole is too high (approx. ωT) to induce any influence in the
frequency behavior.
e4.) SPICE analysis
Figure 5.41 presents the circuit used for
simulation of the gain voltage and the
input impedance. It must be observed
that the circuit is driven with voltage
source because it has high input
impedance.
Figure 5.42 exposes the gain voltage
behaviour in respect with frequency. In
this case, the low frequency is situated Figure 5.41
around 17 kHz and the high frequency
is situated at 5.51 GHz.
Figure 5.43 shows the input impedance variation in respect with frequency. In
this case the high frequency (the frequency where the input impedance
decreases with 3 dB) is 6.41 MHz.
Figure 5.44 presents the schematic circuit used for output impedance
simulation. Two observations must be made:
232
• the circuit is driven by a current source (V2 together with RG behave

like a current source due to high value of RG resistor)
• the RE resistor is only 0.93k in order to increase gm. (the effect of
increasing of the output impedance with frequency is more evident for
high currents.
This time the high frequency is 82 MHz.
In conclusion, it must be said that the simulation results are similar to the
theoretical results.
5.3 The Common Base Connection
The input signal is applied between emitter and base terminals and the output
signal is generated between collector and base terminals.
EC EC EC
EC iC iC
iC
RC RC RC
RC
iIN vCEsat
E C
iIN E C E
C
B
vIN vO vIN vBEsat vO vIN βiIN vO vIN vO
B
B
b.) parts function

RC load resistor;
i IN total instantaneous value of the input current;
233

This analysis is dedicated – as previous chapter did - to transfer characteristic:
v O=v O(v IN) (5.1)
The transistor model will be picked up in respect with the v IN value. It must also
be added that:
v IN=-v BE (5.113)
I. For
v IN ≅ v BEsat (5.114)
the transistor is saturated. The circuit presented in figure (5.46) is modeled in

figure 5.47. Applying K2 theorem on the dotted mesh, one finds:
v O=-v BEsat+v CEsat ≅ 0 (5.115)
II. For:
v IN ∈ (-v BEsat, - Vγ ) (5.116)
the transistor is in active region. The circuit diagram from figure 5.46 is
modeled in figure 5.48. It must be noticed that this time the transistor was
modeled using first order approximation, due to (5.113) relation. The output
voltage may be found as follows:
v O=EC-iCRC (5.117)
But
v BE  v 
i C = IS exp = IS exp − IN  (5.118)
VT  VT 
In these conditions v O is:
 v 
v O = E C − R CI S exp − IN 
 (5.119)
 VT 
III. For:
[
v IN ∈ − Vγ ,+∞ ) (5.120)
the transistor is blocked. The circuit diagram presented in figure 5.46 is

v O=ECt. (5.121)
From (5.115.), (5.119) and (5.121) expressions, the (5.1) transfer characteristic
may be rewritten:
234
 0 for v IN ∈ (− ∞, Vγ ]
v IN ∈ (Vγ , E C )

v O =  v IN − v BE for (5.122)
E − v for v IN = E C
 C CEsat.

must be made:
vO 1. The stage may operate as an amplifier if the
EC transistor will work into the active region. In this
case, the input voltage varies between –v BEsat and
Cut-off Region - Vγ (knee voltage). This means that the range of
Active Region variation is 150-200 mV. The linear operation is
Saturation Region assures only for small signal condition (10mV). It is
-vBEsat - V γ vIN the duty of the bias circuit to settle the operating
point in this region.
Figure 5.50
2. This stage may operate as a switching circuit.
In this case it runs between cut-off and saturation regions.
The simulated circuit is presented in figure 5.51. The RE resistor is a limiter
resistor.
The results are presented in figure 5.52 and look like the theoretical results
presented in figure 5.50.
e.) application - common base amplifier As the previous two sections did,
this section treats only the small signal behavior.
Figure5.51 Figure 5.52

e.2) parts function
RB1, RB2 bias divider; they set-up the base potential of the transistor.
RE thermal stability;
235
C1,C2 coupling capacitors; they isolate the DC operating point; for

large enough frequencies the signal passes through the
CB de-coupling capacitors; for large enough frequencies the base
may be considered grounded.
RC load.
+EC
e.3) small signal analysis
RB2 RC
This section treats; Iin
• voltage gain; C1 C2
• input resistance; Vin
output resistance; Vo
• RE CB RB1
• voltage gain Figure 5.53
The 5.12 definition is maintained:
Vot
AV = (5.12)
Vt

+EC
RB2 RC
It βIb
It
C1 C2 Ib
Ie
Vx
Vt
Vot Vt RE rπ RC Vot
RE CB RB1
For Vot one finds:

Vot= −β Ib R E (5.123)
where:
Vt
Ib = − (5.124)
rπ
Introducing (5.124) in (5.123) and keeping in mind (5.12) the gain voltage
becomes:
236
A v = g mR C (5.125)
Conclusions;
• the voltage gain has high values;
• there is no the phase difference between the output voltage and input
voltage.
Vt
R in = (5.16)
It
and may be found using 5.55 figure. From this figure the test current is:
I t = Ie − (β + 1)Ib (5.126)
Ib is expressed by and (5.124). for Ie one finds:

Vt
Ie = (5.127)
RE
Introducing (5.124) and (5.126) into (5.127) It may be rewritten:

Vt Vt
It = + (5.128)
R e  rπ 
 
 β + 1
(5.128) and (5.16) yield together to
rπ
R in = R E (5.129)
β +1
Because, in great majority of real situations:

rπ
R E >> (5.130)
β +1
Rin may be rewritten:
rπ r
R in ≅ ≅ π (5.131)
β +1 β
Conclusion: the input resistance is very low;
237
Vt
Ro = (5.23)
It
Vin = 0
by CS.
+EC
RB2 RC
gmVbe
It It
C1 C2 Ib
Ie
Vx
Vt Vbe RE rπ RC Vt
RE CB RB1

Vbe=0 (5.132)
the 5.57 figure is redrawn in figure 5.58. Through simple inspection Ro
becomes:
Ro=RC (5.133)
Conclusion: the output resistance has a moderate value;
Instead of the voltage gain usually for this circuit the current gain is analyzed.
The high frequency circuit corresponding to circuit diagram presented in figure
5.56 is exposed in figure 5.59. It must be said that Cµ effect is neglected. The
gmVbe
It It E C
IR Ir IC Io
Vx
RC Vt Vt RE rπ Cπ Vbe RC Vot
first Kirchhoff theorem applied in the emitter yields to:

Vt
It + + sC πUt + gmUt = 0 (5.134)
rπ
Io=gmVt (5.135)
238

Io α
= (5.136)
Iin 1+ s Cπ
gm
where:
β
α= (5.137)
β+1
This results emphasizes that there is a pole:

gm
p=− ≅ − ωT (5.138)
Cπ
This result proves that this stage has a good response in frequency. Its
bandwidth equals ωT , being very useful in high frequency applications.
e4.)SPICE analysis
Figure 5.60 presents the circuit diagram used for simulation. It must be
observed that V2 together with RG behave as a current source due to small
value of the input impedance.
Figure 5.61 shows the frequency response of the current gain. One can see
that the high frequency is situated around 70MHz
5.4 By Hand Large-Signal Analysis
Section 3.1 presented the principal steps of the large-signal analysis techniques
in the case of the electrical circuits.
239
This section applies the mentioned procedure for the calculation of the
quiescent points for bipolar transistor circuits. The first order approximation
model is used for the transistor. The approach is presented in figure 5.62 and
follows the next steps:
Start the counter; m=0
(0)
Set all the base currentsIBk =0 k∈{1,2,...n}
(0)
Calculate all the collector currentsICk k∈{1,2,...n}
Increase the counter: m=m+1
I(Cmk−1)
(m)
=
Calculate all the base currents I Bk
βk k∈{1,2,...n}
(m)
Calculate all the collector currentsICk k∈{1,2,...n}
yes I(Cmk) − IC(mk−1) < ε

no
STOP
Figure 5.62
1. The current (voltage) sources whose voltages (currents) are easy to

determine are identified. If some supplying points of these sources
have unknown voltage levels, a trial voltage is assumed and the
calculation is repeated till the convergence is obtained.
2. The currents through the circuits are computed. An iterative method
must be used. The procedure is presented in figure 5.62
3. The potentials of all the nodes are computed.
Example
For the circuit presented in figure 5.63
+E C
R1 R2 R5 R6
T7
-
Ui
T1 T2 T5 T6
R7
Ui+
T8
R12 R13
T3 T9
UO
T4 T10
R3 R4 R11 R 10 R9 R8
-EE
Figure 5.63
the quiescent points must be calculated. Assume that:
240
R1=12 kΩ R2=12 kΩ R3=3 kΩ R4=1,5 kΩ R5=4 kΩ

R6=6 kΩ R7=6.7 kΩ R8=6 kΩ R9=1,5 kΩ R10=1,5 kΩ
R11=8,67 kΩ R12=4,17 kΩ R13=9,85 kΩ EC=+12V EE=-12V
VBE= 0,65V; β=50 (for all the transistors). Consider also:
+ --
Vi =Vi =0 (5.139)
Solution
There are two current sources formed by T3 together with T4 and T9 together
with cu T10. They are the start points. The currents through them are:
E − VBE
IT4 = E = 2mA (5.140)
R 4 + R 12
R
IT 3 = 4 IT 4 = 1 mA (5.141)
R3
E E − VBE
I T10 = = 1mA (5.142)
R 10 + R 13
R
IT 9 = 10 IT 10 = 1 mA (5.143)
R9
The currents through the transistors biased by these sources are:
1
IT1=IT2= IT3=0,5 mA (5.144)
2
IT7=IT9=1 mA (5.145)
The current through the R11 resistor is:
EC + EE − R1IT1 − VBE
IR11= = 2mA (5.146)
R!!
and therefore the currents through T5 and T6 are:

1
IT5=IT6= IR11=1 mA (5.147)
2
The current through the final transistor T8 is:
E C + E E − R 6 IT 6 − 2 VBE − R 7 IT 7
IT8= = 2mA (5.148)
R8
The potentials of the nodes are presented in table 5.2. The 5.2 table has also
the results of the simulation. It must be observed that the differences are
irrelevant and by consequence there is no need of a new iteration.
241
Node By hand Simulated Node By hand Simulated

voltage (V) voltage (V) voltage (V) voltage (V)
-
VI 0 0 VET5 5,35 5,336
VI+ 0 0 VCT10 -9,85 -9,856
VCT1 6 5,994 VET10 -10,50 -10,51
VCT2 6 5,994 VET9 -10,50 -10,51
VET1 -0,65 -0,64 VCT9 0,65 0,638
VET1 -9 -8.997 VCT7 7,35 7,343
VCT4 -5,35 -5,339 Uo 0 -0,038
VET4 -9 -9,015 EC 12 12
VCT5 8 8,041 EE -12 -12
VCT6 8 8,001
Table 5.2
5.5 By Hand Small-Signal Analysis
As discussed in section 3.2 the small signal analysis techniques, can be applied
in order to examine what happens with signal that varies around the DC point
bias. From this point of view, the small signal analysis can be applied to obtain
results such as:
• input to output transfer functions (voltage gain, current gain, noise
margins, etc.); these transfer function show how the signal propagates
through the circuit.
• input or output impedance; the impedance allows us to predict
interactions among various parts of a larger circuit, input sensors and
output loads.
An efficient small signal analysis must rely on the following techniques:
1. Prior knowledge of the incremental resistances “seen looking into the
device terminals. For bipolar transistor (figure 5.64) they are:
• resistance seen looking into the base
R b = rπ + (β + 1)R E (5.149)
242
if
RC
RE=0 (5.150)
RB Rc
then
Re
R b = rπ (5.151) Rb
RE
else
R b ≅ βR E `
Figure 5.64
(5.152)
because in many cases
rπ << β R E (5.153)
• resistance seen looking into the emitter

rπ + R B
Re = (5.154)
β+1
if
RB=0 (5.155)
(ex. common base connection) then
rπ 1 V
Re ≅ = = T (5.156)
β gm IC
• resistance seen looking into the collector

 βR E 
R c = ro 1 + 
 (5.157)
 R E + rπ + R B 
In any case Rc is relatively high. For common applications
Rc → ∞ (5.158)
2. Prior knowledge of the voltage gain for simple frequently repeated circuits.
In the case of the BJT these are:
• signal voltage measured in emitter related to base signal voltage
Ve=Vb (5.159)
• signal voltage measured in collector related to base signal voltage
RC
Vc ≅ − Vb (5.160)
RE
if
243
RE=0 (5.161)
then
VC=-gmRCVb (5.162)
3. Prior knowledge of the current gain for simple frequently repeated circuits.
In the case of the BJT these are:
• collector current
Ic = β Ib (5.163)
or
β
Ic = αIe = Ie ≅ Ie (5.164)
β +1
• emitter current
I e = (β + 1)Ib ≅ β Ib (5.165)
or
Ic β+1
Ie = = Ic ≅ Ic (5.166)
α β
• base current
Ic Ie
Ib = = (5.167)
β β
Example
For the circuit presented in figure 5.65 find the voltage gain.
EC
Iin1 Iin2
RB1 RC RB3
RG C1 C2
Ib1 Ib2
T1 T2
+
Vin
Ein
RB2 RE1 CE RB4 RL Vo
-
Figure 5.65
Solution:
The voltage gain is:
244
Vo
Au = (5.168)
Vin
The solution presented herein after applies the procedure just discussed. The
circuit diagram from the 5.65 figure is modeled in figure 5.66. It must be added
that:
Ic1
RG
Iin Ib1 Ib2
T1 T2
+
Ie2
Vin
Ein
R’B RC R’’B RL Vo
-
Figure 5.66
R = R B1 R B 2
'
B (5.169)
R'B' = RB 3 RB 4 (5.170)
The calculation begins with output voltage estimation:

Vo = I e2 R L (5.171)
but,
I e2 = (β 2 + 1)Ib 2 (5.172)
and
R C R B''
Ib2 = −Ic1 =
R b2 + (R C R B'' )
(5.173)
R C R B''
= −Ic1
[r π + (β 2 + 1)R L ] + (R C R B'' )
A similar procedure for Ic1 leads to:

Ic1 = β1Ib1 (5.174)
R 'B
Ib1 = Iin (5.175)
rπ' + R B'
Vin
Iin = (5.176)
r R B'
'
π
Multiplying (5.171) ÷ (5.176) one by one, the output voltage becomes:
245
R C R B''
Vo = −R L (β 2 + 1) ×
[rπ + (β 2 + 1)R L ] + (R C R B' ' )
(5.177)
R 'B Vin
× β1
rπ' + R B' rπ' R B'
Tacking into account (5.168) the gain voltage may be written as:
R C R B''
A u = −R L (β 2 + 1) ×
[rπ + (β 2 + 1)R E ] + (R C R B'' )
(5.178)
R B' 1
× β1
rπ' + R 'B r π' R 'B
This final form may be easy simplified because:

(β 2 + 1) ≅ β 2 (5.179)
RC RB' ' RC R
≅ ≅ C (5.180)
[rπ + (β2 + 1)RL ] + (RC R ) ''
B
β2RL + RC β2RL
R B'
≅1 (5.181)
rπ' + R B'
1 1
≅ (5.182)
'
r R
π
'
B
rπ'
RC 1 R
A u = −R L β 2 β 1 ' = −β 1 'C = −gm1R C (5.183)
β 2R L rπ rπ
This result confirms the expectations, because the first stage is a common
emitter with “–gmRC” voltage amplification and the second stage is emitter
follower whose amplification equals unity.
246
Problems
Problem 1. This problem is treating the calculation of the voltage gain, input
resistance and output resistance for the common emitter amplifier. For the
circuit presented in figure 1, find the voltage gain, input resistance, and output
resistance.
EC
RB1 RC
Iin C1
C2
Vo
Vin
RB2 RE CE
Figure 1
Assume that:
RB1=470 k Ω RB2=100 k Ω C2=10µF β = 200
RC=1 k Ω C1=10µF EC=25V VBE=0.7V

RE=4.7 k Ω CE=100µF
Table 1
Solution
Three steps must be followed in order to find the voltage gain, input resistance
and output resistance:
• DC analysis whose aim is the quiescent points calculation;
• the calculation of the small signal parameters;
• AC analysis whose aim is the calculation of the voltage gain, input
resistance and output resistance:
DC analysis
For DC analysis, the circuit presented in figure 1 may be simplified as figure 2
shows, because the current can not flow through the capacitors. This figure is
identical with that numbered 4.66. That is why the procedure applied in the
fourth section (DC Biasing) may be applied in the following. Figure 4.67
presents the large signal model of this circuit. The system of equations
associated with the modeled circuit is the system described by (4.287) ÷ (4.293)
equations:
247
I=I1+βIB (4.287)
I1=I2+IB (4.288)
IB+βIB=IE (4.289)
-VBE=-VCE-βIBRC+I1RB1 (4.291)
VBE=I2RB2-IERE (4.292)
IC = β IB (4.293)
EC
IC I1 I
RB1 RC
RB1 RC
B C
EC
IB VBE βIB
VCE
I2
RB2 RE
E
RB2 RE
IE
Figure 2 Figure 4.68
For IC, one finds:

 R B2 
β E C − VBE 
 R B1 + R B 2 
IC = =
R B1R B 2
+ (β + 1)R E
R B1 + R B 2
(1)
 100 
200 25 − 0 .7 
 100 + 470 
= ≅ 0.7mA
100 × 470
+ (200 + 1)4 .7
100 + 470
Of course, the system may be simplified if the Thevenin transformation is
applied. The figure 4.69 presents the circuit after transformation and the figure
4.70 the modeled circuit. In this case the system of equations is:
IE=IB+β IB (4.294)
EC=β IBRC+VCE+IERE (4.295)
EB-VBE=REIE+RBIB (4.296)
where:
RB 2
EB = EC (4.297)
RB1 + RB 2
248
RB1 RB2
RB = (4.298)
RB1 + RB 2
and IC is:
β(E B − VBE )
IC = (4.299)
R B + (β + 1)R E
EC
I
RC RC
B C
EC
IB VBE βIB
EB VCE
EB
RB RE
E
RB RE
IE
The (1) and (4.299) expressions are identical. Introducing (4.297) and (4.298)
into (4.299), (1) is obtained.
Small signal parameters.
The (4.225) ÷ (4.228) relations define the small signal parameters. For a large
class of application only the transconductance “gm“ and the input resistance
“ rπ ”are needed. Usually they are rewritten as follows:
gm[mS]=40IC[mA] = 40 × 0.7 = 28 mS (2)
β 200
rπ = = ≅ 7.14 kΩ (3)
gm 28
AC analysis was presented in the 5.1.1 section. The most important results will
be presented below. Ir
• The voltage gain is defined as: It Ib B C Ic
Vot Vt RB Vbe gmVbe RC Vot

AV = = −gmR C = rπ
Vt (3) E
= −28 × 1 = −28
Figure 5.10
The AC circuit diagram is shown in the
5.10 figure.
• The input resistance is (according to (5.20)):
249
R B1R B 2
rπ
R B1R B 2 R B1 + R B 2
R in = R B rπ = rπ =
R B1 + R B 2 R B1R B 2
+ rπ
R B1 + R B 2 (4)
470 × 100
× 7.14
= 470 + 100 ≅ 6.57 kΩ
470 × 100
+ 7.14
470 + 100
• The output resistance is given by (5.25)
Ro=RC=1k Ω (5)
SPICE analysis was made using the circuit diagram presented in figure 3. The
results are:
NAME Q_Q1
MODEL Q2N2222
IB 4.07E-06
IC 7.23E-04
VBE 6.31E-01
VBC -2.02E+01
VCE 2.09E+01
BETA DC 1.78E+02
BETA AC 1.99E+02
Figure 3 GM 2.79E-02
RPI 7.16E+03
RX 1.00E+01
RO 1.31E+05
BETAAC 2.00E+02
resistance and output resistance for the common collector amplifier. For the
circuit presented in figure 4, find the voltage gain, input resistance, and output
resistance.
EC
RB1
Iin C1
C2
Vin
RB2 RE Vo
Figure 4
Assume that:
250
RB1=470 k Ω C1=10µF β = 200
RB2=100 k Ω C2=10µF VBE=0.7V

RE=4.7 k Ω EC=25V
Table 2
Solution
DC analysis
The DC circuit diagram is presented in the figure 4 and its modeled circuit in
the figure 5.
I1 I
RB1 RB1
B C
EC
EC IB VBE β IB
VCE
I2
RB2 RE E
RB2 RE
IE
Figure 4 Figure 5
The Kirchhoff system of equations is:

I=I1+βIB (6)
I1=I2+IB (7)
IB+βIB=IE (8)
EC=VCE+IERE (9)
-VBE=-VCE+I1RB1 (10)
VBE=I2RB2-IERE (11)
and of course, IC is:
IC = β IB (12)
It is interesting to observe that:
251
 R B2 
β E C − VBE 
 R + R 
IC = =
B1 B2
R B1R B 2
+ (β + 1)R E
R B1 + R B 2
(13)
 100 
200 25 − 0 .7 
 100 + 470 
= ≅ 0.7mA
100 × 470
+ (200 + 1)4 .7
100 + 470
and is identical with (1). If Thevenin transformation is used (the figure 5
presents the circuit after the transformation and the figure 6 the modeled
circuit), then the system just presented is simplified as follows:
IE=IB+β IB (14)
EC=VCE+IERE (15)
EB-VBE=REIE+RBIB (16)
where EB and RB have the significance given by (4.297) and (4.298). IC is:
β(E B − VBE )
IC = (17)
R B + (β + 1)R E
EC
I
B C
EC
IB VBE βIB
EB VCE
EB
RB RE
E
RB RE
IE
Figure 5 Figure 6
It may be observed that (17) is identical with (13).

Because the biasing circuit is the same, the small signal parameters are
identical:
gm[mS]=40IC[mA] = 40 × 0.7 = 28 mS (2)
β 200
rπ = = ≅ 7.14 kΩ (3)
gm 28
252
AC analysis was presented in the 5.2 section. The most important results will
be presented below.
• The voltage gain may be estimated using figure 5.35 (redrawn here) and it
approximates unity(formula (5.71)):
(β + 1)R E (200 + 1) × 4.7
Av = = ≅ 0.987 (5.71)
rπ + (β + 1)R E 7.14 + (200 + 1) × 4.7
It Ib B C Ic
rπ βIb
E
Vt Ir RB
RE Vot
Figure 5.35
• The input resistance is (according to (5.77)):

R in = R B [ rπ + (β + 1)R E ] (5.77)
R in = R B [ rπ + (β + 1)R E ] = [ rπ + (β + 1)R E ] =
R B1R B 2
R B1 + R B 2
R B1R B 2
[ rπ + (β + 1)R E ]
R B1 + R B 2
= = (18)
+ [ rπ + (β + 1)R E ]
R B1R B 2
R B1 + R B 2
470 × 100
× [7.14 + (200 + 1) × 4 .7]
= 470 + 100 ≅ 75.92 kΩ
470 × 100
+ 7.14 + (200 + 1) × 4.7
470 + 100
• The output resistance may be computed using the figures numbered 5.35
and 5.36 and has the expression (5.84):
rπ 7.14
RE 4 .7
rπ β +1 200 + 1 ≅ 0.034kΩ
R o = RE = = (19)
β +1 rπ 7.14
RE + 4 .7 +
β +1 200 + 1
SPICE Analysis. The 7 figure was utilized for simulation. The results are:
253
NAME Q_Q1
MODEL Q2N2222
IB 4.04E-06
IC 7.24E-04
VBE 6.31E-01
VBC -2.09E+01
VCE 2.16E+01
BETADC 1.79E+02
GM 2.79E-02
Figure 7
RPI 7.16E+03
RX 1.00E+01
RO 1.31E+05
BETAAC 2.00E+02
resistance and output resistance for the common base amplifier. For the circuit
presented in figure 8, find the voltage gain, input resistance, and output
resistance.
+EC
R B2 RC
Iin
C1 C2
Vin
Vo
RE CB RB1
Figure 7
Assume that:
RB1=470 k Ω RB2=100 k Ω C2=10µF β = 200
RC=1 k Ω C1=10µF EC=25V VBE=0.7V

RE=4.7 k Ω CB=100µF
Table 3
Solution
DC analysis.
The DC circuit corresponding to the circuit presented in figure 7 is identical to
that presented in the 2 figure. In fact the same bias circuit was used both for
common emitter configuration and common base configuration. Under these
254
circumstances, the results are identical. Collector current is also 0.7mA and the
small signal parameters are:
gm = 28 mS (20)
rπ ≅ 7.14 kΩ (21)
AC analysis was treated in section 5.3. In the following only the results are
presented.
• The voltage gain is given by the (5.125 formula).
A v = gmR C = 28 × 1 = 28 (22)
• The input resistance may be estimated using the (5.128) expression:

rπ 7.14
R in = R E = 4 .7 ≅ 0.035 kΩ (23)
β+1 200 + 1
• The output resistance is (according to (5.133))

Ro=RC=1k Ω (24)
Problem 4. This problem is dealing with cut-off frequencies for a common

emitter amplifier. For the circuit presented in figure 8, find the bandwidth
(measured at –3dB). For low frequency, consider only the effect of the CE
capacitor.
EC
Iin
RB1 RC
RG C1
C2
+
RL Vo
Ein Vin
RB2 RE CE
-
Figure 8
Assume that:
RB1=470 k Ω RB2=100 k Ω C2=10µF β = 200
RC=1 k Ω C1=10µF EC=25V C µ = 2.34 pF
RE=4.7 k Ω CE=100µF VBE=0.7V C π = 47 pF
Table 4
255
For RL and RG, consider the next four combinations:
RL RG
100 k Ω 100 k Ω
0.01 k Ω 100 k Ω
100 k Ω 0.01 k Ω
0.01 k Ω 0.01 k Ω
Table 5
Solution
The DC analysis is identical with that presented at “problem 1”. In this
conditions:
• IC=0.7 mA;
• gm=28mS;
• r π = 7.14 k Ω .
The fT cut-off frequency may be estimated as follows:

1 gm 1 28 × 10 −3
fT = = = 89 MHz
2π C π + C µ 2 × 3.14 47 × 10 −12 + 2.34 × 10 −12
According to the 5.38 expression, the pole corresponding to the high frequency
is:
p1 = − +
2RRLCCπCµ
(5.38)
[C (R ]
2
µ LC + R + gmRLCR ) + CπR − 4RRLCCπCµ
+
2RRLCCπCµ
where R and RLC are defined as:
R = RG RB rπ (5.35)
R LC = R L R C (25)
The high frequency (measured at –3dB) is

ωH
fH = (26)
2π
256
with
ωH = −p 1 (27)
The approach presented above is not usual for by hand calculation because
[C µ (R LC + R + g m R LC R) + C π R] 2
>> 4RR LC C π C µ (28)
In fact [C µ (R LC + R + g m R LC R) + C R]
π
2
exceeds with three or four orders of
magnitude 4RR LC C π C µ and by consequence the calculation must be made
keeping in mind at least six significance figures. That is the reason why – for by
hand calculation - the poled calculation implies a different approach. The
central problem is to find a comfortable solution at the
1+ s(CµRLC + CµR + CπR + gmRLCRCµ ) + s2RLCRCπCµ = 0 (29)
equation. This equation is the denominator of the (5.34) expression. The

solution, implied by the (5.38) relation, is the classical solution given by the
well-known formula:
4ac
− b ± b 1−
b2
x 1,2 = (30)
2a
for the equation:
ax 2 + bx + c = 0 (31)
Observing that, if
4ac
<< 1 (32)
b2
then
4ac 1 4ac 2ac

1− ≅ 1− = 1− 2 (33)
b2 2 b2 b
the (30 )solution may be rewritten as follows:
 2ac 
− b ± b1 − 2 
 b 
x 1,2 ≅ (34)
2a
or:
c
x1 ≅ − (35)
b
257
and
b
x2 ≅ − (36)
a
For the (29) equation this judgement leads to:
1
p1 ≅ − (37)
CµRLC + CµR + CπR + gmRLCRCµ
CµRLC + CµR + CπR + gmRLCRCµ

p2 ≅ − (38)
RLCRCπCµ
Of course if the (5.40), (5.41) and (5.42) are accepted, the (37) and the (38)
expressions for the poles may be simplified as (5.38) and (5.39) shows. In the
case of this of this problem, the (37) expression is considered the best
estimation for the dominant pole. In these circumstances the high cut-off
frequency becomes:
1 1
fH−3dB ≅ (39)
2π CµRLC + CµR + CπR + gmRLCRCµ
(39) gives the upper edge of the bandwidth. The lower edge may be estimated
finding the pole corresponding to the low frequency. That is
R G + rπ + (β + 1)R E
p1 = − (5.50)
R E C E (R G + rπ )
and by consequence, the cut-off low frequency (defined at –3dB) is:

1 R G + rπ + (β + 1)R E
fL −3 dB = (40)
2π R E C E (R G + rπ )
The results are presented in table 6
RL RG fH fH (SPICE) fL
100 k Ω 100 k Ω 223kHz 223kHz 22Hz
0.01 k Ω 100 k Ω 518kHz 538kHz 22Hz
100 k Ω 0.01 k Ω 45.5MHz 50.4MHz 282Hz
0.01 k Ω 0.01 k Ω 204MHz 295MHz 282Hz
Table 6
Two observations must be made (related to the table 6):
258
• If a large bandwidth is desired, the stage will have to driven by a voltage

source and the load will have to be very low (short circuit if possible);
• The fourth columns present SPICE results. Comparing these results with
those from the third columns one can say that by hand calculation is
sufficiently accurate.
Problem 5. This problem is dealing with cut-off frequencies for a common

collector amplifier. For the circuit presented in figure 9, find the cut-off
frequencies (measured at –3dB) for the voltage gain, the input impedance and
the output impedance.
EC
Iin
RB1
RG C1
C2
+
Ein Vin
RB2 RE RL Vo
-
Figure 9
Assume that:
RB1=470 k Ω RB2=100 k Ω C2=10µF β = 200
RC=1 k Ω C1=10µF EC=25V C µ = 2.34 pF
RE=4.7 k Ω VBE=0.7V C π = 47 pF
Table 4
RL RG
100 k Ω 100 k Ω
0.01 k Ω 100 k Ω
100 k Ω 0.01 k Ω
0.01 k Ω 0.01 k Ω
Table 5
259
Solution
conditions:
• IC=0.7 mA
• gm=28 mS
• rπ = 7.14 kΩ
• fT=89MHz
The dominant pole for the voltage gain is given by (5.95):
1 + ( gm + g π )R EL
p1 = − (5.95)
C πR EL
For the input impedance, (5.101) gives the dominant pole:

1
p1 = (5.101)
C π rπ
In the case of the output impedance, the “zero” is important:

RG + rπ
z1 = − (5.109)
C π rπ R G
The final results are presented as tables. These tables contain both by hand
calculation and computer calculation. In each case a comparison is made.
1. voltage gain:
RL RG fH fH SPICE
100 k Ω 100 k Ω 954MHz 1.33MHz
0.01 k Ω 100 k Ω 8.49GHz 5.33KHz
100 k Ω 0.01 k Ω 954MHz 3.18GHz
0.01 k Ω 0.01 k Ω 8.49GHz 9.7GHz
Table 6
1 1 + (g m + g π )R EL
fH−3dB = (41)
2π C πR EL
Conclusion: The (41) formula offers a good estimation only if the stage is
driven by a voltage source (RG=0.001K).
260
2. input impedance
1 1
fHZin = (42)
2π C π r π
RL RG fHZin f HZin SPICE

100 k Ω 100 k Ω 475kHz 797kHz
0.01 k Ω 100 k Ω 475kHz 443kHz
100 k Ω 0.01 k Ω 475kHz 797kHz
0.01 k Ω 0.01 k Ω 475kHz 443kHz
Table 7
Conclusion: The (42) formula offers a good estimation for the cut-off
frequency of the input impedance.
3. output impedance
1 RG + r π
fHZout = (43)
2π C π r π R G
RL RG f HZout fHZour SPICE

100 k Ω 100 k Ω 507kHz 596kHz
0.01 k Ω 100 k Ω 507kHz 596kHz
100 k Ω 0.01 k Ω 339MHz ------
0.01 k Ω 0.01 k Ω 339MHz ------
Table 8
Conclusion: The (5.109) formula offers a good estimation for “zero” position
only if the condition presented when the formula was
developed is satisfied. That is why the (43) expression offers a
good estimation only in relatively few situations.
Problem 6. This problem is dealing with cut-off frequency for the voltage gain
in the case of a common base amplifier. For the circuit presented in figure 10,
find the cut-off frequency (measured at –3dB) for the voltage gain.
261
+EC
RB2 RC
RG Iin
C1 C2
Ein Vin RL Vo
RE CB RB1
Figure10
Assume that:
RB1=470 k Ω RB2=100 k Ω C2=10µF β = 200
RC=1 k Ω C1=10µF EC=25V C µ = 2.34 pF
RE=4.7 k Ω CB=100µF VBE=0.7V C π = 47 pF
Table 9
RL RG
100 k Ω 100 k Ω
0.01 k Ω 100 k Ω
100 k Ω 0.01 k Ω
0.01 k Ω 0.01 k Ω
Table 10
Solution
conditions:
• IC=0.7 mA
• gm=28 mS
• rπ = 7.14 kΩ
• fT=89MHz
This time the dominant pole has the expression given by (5.138)
262
gm
p=− (5.138)
Cπ
and by consequence the cut off frequency is:

1 gm
fH−3dB = (44)
2π C π
The results are

RL RG fH fH SPICE
100 k Ω 100 k Ω 95MHz 48MHz
0.01 k Ω 100 k Ω 95MHz 89MHz
100 k Ω 0.01 k Ω 95MHz 52MHz
0.01 k Ω 0.01 k Ω 95MHz 242MHz
Table 11
Conclusion: The estimation given by the (44) formula offers a reasonable

estimation for the cut-off frequency.
263
• Preliminary
• Quasi-Static Large Signal
Behavior
• Quasi-Static Small Signal
Behavior
• DC Biasing
Chapter 6
The Field Effect Transistors
The first idea concerning the field effect transistor appeared in 1930 when Lillian
in United States and Heil in England proposed the utilization of the surface field
effect for generating power amplification in a solid state structure. Bell labs
developed this idea (1940), but the discovery of the bipolar transistor stopped
the research in this area for almost one decade. In 1952 Schockley invented the
junction field effect transistor (JFET) and Dacey and Ross built it in 1953. The
appearance of the silicon-dioxide system yielded to the so-called field effect
transistor metal oxide semiconductor (TECMOS). The inventors are Kahng and
Atalia. It was 1960. From that moment, the researches intensified their works
and a lot of new types of field effect transistors appeared. Nowadays, the field
effect transistor (under different forms) is the most important transistor.
Its principle of operation is completely different related to that of the bipolar
transistor. If the bipolar transistor operates with two types of mobile carriers and
– much more - the behavior of the minority carriers is the key of the its action,
the junction field effect transistor operates with only one type of carriers and
they are the majority ones. The bipolar transistor has low input impedance,
small high frequency gain and is non-linear when VCE<2V due to the saturation
region. FET overcomes some of these problems. This chapter presents the
solutions involved by the realization of this new device.
The outline of the chapter is very similar to that exposed by the chapter 4:
The first section whose title is “Preliminary” presents structure, symbol,
the principle of operation and methods of mathematical description
related to the range of operation;
the junction field effect transistor. The expression for drain current is
265
derived for all types of field effect transistor. In addition, non-ideal

effects such as: effective channel length, channel length modulation,
parasitic resistances, body effect and junction breakdown are treated.
In the following, “I-V characteristics” are presented. From these
characteristics, some approximate models are derived. Finally SPICE
models are exposed.
dynamic large signal conditions. One considers the effects of the
parasitic capacitors. SPICE model is presented.
The fourth section presents quasi-static small-signal model. Both
SPICE models and simplified models are presented.
The fifth section introduces dynamic small-signal models. This section
treats also SPICE models and simplified models useful for by hand
analysis.
The sixth section is dedicated to DC bias circuits. One defines
quiescent point and a usual biasing circuit is treated.
6.1 Preliminary

3. Methods of mathematical description related to the range of operation;
Figure 6.1 presents a general structure for a field effect transistor.
S G D
insulator
strongly channel strongly
doped doped
semiconductor substrate (semi-insulator)
B
S
Figure 6.1
One may observe that the structure comprises:

• a source terminal (noted S); source serves as the origin of the carriers;
266
• a drain terminal (noted D); drain serves as the sink;

• a grill terminal (noted G); grill controls the current that flows between source
and drain;
• an insulator situated between the grill and the channel; it does not allow any
current to flow through the grill.
The central element of this structure is the channel situated under the grill. The
operation of this transistor is based on the mobile carriers flowing, from the
source to the drain, through the channel. The channel resistance may be
modified by the electric field generated by the potential applied on the grill and
thus, the grill controls the current running from source to drain. That is the
reason why this transistor is called field effect transistor.
This short explanation emphasizes the fact that the grill (sometimes called gate)
terminal must be electrically isolated by the structure. The current technological
realizations offer two general solutions of this problem:
1. the usage of a reversed junction, and
2. the usage of a insulator layer.
According to the type of the junction used the field effect transistor family may
be divided as follows:
• Junction field effect transistor (JFET); a reversed biased pn junction
which represents the insulator;
• Metal semiconductor field effect transistor (MESFET); a metal-
semiconductor junction (Schottkly barrier) is used as insulator;
• Heterojunction field effect transistor (HFET); the junction is in fact a
heterojunction. A heterojunction is a junction formed between two
dissimilar semiconductors, such as the binary compound GaAs and the
ternary compound AlxGa1 - xAs.
According to the type of insulator there are also:
• Metal oxide semiconductor field effect transistor (MOSFET);
the insulator is realized by a thin layer of SiO2
• Metal insulator semiconductor field effect transistor (MISFET);
the insulator is realized using any other substance except the
Silicon oxide.
There is also another constructive criterion that is usually used for the FET’s
categorizing – the type of the mobile carriers that flow through the channel.
From this point of view there are:
• n-channel FETs (the mobile carriers are electrons) and
• p-channel FETs (the mobile carriers are holes).
It must be added that n-channel MOSFETs are called NMOS and p-channel
MOSFETs are called PMOS This chapter treats n-channel JFET and MOSFET.
267
The behavior of the p-channel FETs is similar, except the fact that the courses
of the currents and voltages are reversed.
Figure 6.2 presents a typical structure of JFET.
p-n G p-n
junction junction
n p n
S D
channel
G
S
Figure 6.2
It is interesting to observe that:

• both source and drain are ohmic contacts;
• the channel is situated into the volume of the semiconductor.
The symbol used for JFETs are shown in figure 6.3 (n type channel) and (6.4)
(p type channel)
D D
iD iD
vDG vGD
iG iG
G vDS G vSD
vSGS iS S
v iS
S
S S
where:
iG grill current vGS grill-sources voltage
iS source current vDG drain-grill voltage
iD drain current vDS drain-sources voltage
In the case of the MOSFET there are two possible structures:
• enhancement type (figure 6.5);
• depletion type (figure 6.6
268
S G D S G D
SiO2 SiO2
++ channel ++ ++ n ++
n n n n
channel
p p
B B
S S
where B (body) is the substrate.

In these cases it is interesting to observe that:
• both drain and source are rectifying p-n junctions instead of ohmic
contacts;
• the channel is situated at the surface of the semiconductor just
underneath the insulator;
• there is a new terminal the body (noted B); usually is connected to the
sources; in special cases may be used as a secondary grill.
In enhancement type MOSFETs (E-FET), the application of a gate voltage
activates the channel (by inducing a layer of carriers between sources and drain
under the gate). Figure 6.7 presents the symbol of a n-type channel E-FET and
figure 6.8 presents the symbol of a p-type channel E-FET.
D D
iD
iD
vDG vGD
B B
vDS
G vSD
G
iG
vS iS iG
G
vS
S iS
S S
In depletion type MOSFET (D-FET), there is a small strip of semiconductor of

the same type as that of the source and drain, and the gate voltage can either
reduce (by depleting carriers) or increase (by increasing carriers the channel
current. Figure 6.9 presents the symbol of a n-type channel D-FET and figure
6.10 presents the symbol of a p-type channel D-FET.
269
D D
iD iD
vDG
vGD B
B
vDS vDS
G G
iG iG
vS
S iS vS
G iS
S S

As it had been said the field effect transistor is characterized by the grill control
about the current between source and drain. This section describes the physical
phenomenon that enables this feature.
A. Junction Field Effect Transistor.
In normal condition of operation both grill-source and grill-drain junction must be
reverse biased. The figures 6.11, 6.12 and 6.13 expose such a possibility. In
fact these figures are very useful for the explanation of the principle of
operation. One can observe that the source terminal is grounded, the grill
terminal is connected at a negative potential and the drain terminal is connected
at positive potential. The grill terminal is kept (in all three cases) at –vG, while
the potential applied on the drain is increased from vD1 to vD2. The usual
explanation of the operation takes into account two situations:
A1. The drain source voltage has low values (vD<-vDsat). Figure 6.11
represents such a situation.
G space-charge
region (non-
conducting)
n p n
S D
channel
+vD1
p
G
S
-vG
Figure 6.11
An increase or decrease of the gate (grill) voltage with respect to the source
causes the space charge region to expand or shrink; this in turn changes the
270
channel geometry and thus its resistance. The JFET thus can be considered a
voltage-controlled resistor. If vDS is small enough (around one volt usually) the
drain current increases linearly with drain voltage, indicating that the conductive
channel acts as a constant resistor. This regime is generally referred as linear
regime. As the drain voltage increases, however, the cross-sectional area of
the conductive channel is reduced, causing an increase in the channel
resistance. As a result, the current increases at a slower rate. This new non-
linear regime is generally referred as triode regime. A further increase of the
drain source voltage yields to the current saturation. Figure 6.12 presents this
situation. One can observe that the channel is cut-off. This phenomenon is
called pinch-off phenomenon. It must be added that the drain voltage equals the
value, frequently noted, vDsat.
G
X point
n p
S D
channel
+vDsat>vD1
p n
G
S
-vG
Figure 6.12
A2. The drain source voltage has low values (vD>-vDsat). Figure 6.13 presents
this situation.
G
X point
n p n
S D
channel
+vD2>vDs at
p
G
S
-vG
Figure 6.13
This regime is called saturation regime. Its principal characteristic resides in

the fact that the drain current remains constant when the drain-source voltage is
modified. The common explanation starts with the observation that through a
space charge region may pass a considerable current in two situations:
271
1. if the carriers are created inside the region (ex. thermal generation,
multiplication);
2. if the carriers are injected (ex. collector junction at BJT).
For JFET, the second situation is quite suitable. An injection of carriers occurs
at the level of X point. (see figure 6.13). It is important to be observed that the
voltage across the channel always equals vDsat and thus the channel current
does not depend of vD. The difference vD-vDsat may be found across the space
charge region. The value of the drain current may be modified only varying the
gate voltage.
In conclusion:
• for small drain sources voltages the JFET behaves like a controlled
resistor;
• for high drain sources voltages the JFET behaves like a voltage
controlled current source.
The analysis presented above considers that gate voltage is constant and the
drain voltage is varied. Of course it is possible to imagine the complementary
analysis: the drain voltage is kept fixed and the gate voltage is varied. This type
of examination is useful for defining another concept: the threshold voltage
(vT). The threshold voltage represents that grill voltage that cuts off the channel
current. This regime is called the cut-off regime. From the physical point of
view, the threshold voltage is defined by the total depletion of the channel.
B. Metal Oxide Semiconductor Field Effect Transistor.
In this case the same three problems must be examined:
• the channel generation;
• the saturation
• threshold voltage
B1. The channel generation
The channel generation may be easier understood if the so-called MOS
structure is primarily analyzed. The 6.14, 6.15 and 6.16 figures present this
structure in three situations:
-vG +vG ++vG
G G G
SiO2 SiO2 SiO2
++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++++++++++++++++++
holes Space charge electrons

p region p p
B B B
S S S
272
1. Accumulation regime (figure 6.14); It appears when vG<0. Due to the

electric field created by the grill potential into the semiconductor, holes are
accumulated at the level of the Si-SiO2 interface.
2. Depletion regime (figure 6.15); It appears when vG>0 (moderate values).
Due to the electric field created by the grill potential into the semiconductor,
holes are rejected from the Si-SiO2 interface.
3. Inversion regime (figure 6.16); It appears when vG>>0 (high values). Due
to the electric field created by the grill potential into the semiconductor, the
electrons from the semiconductor volume are attracted at the level of the Si-
SiO2 interface.
In the D-MOSFET case, the drain and the source are connected through a
supplementary diffusion that represents the channel. This channel operates in
depletion regime.
In the E-MOSFET case, the grill voltage induces the channel. The channel
exists while the grill voltage exists. This channel operates in inversion regime.
B2. The Saturation
For D-MOSFETs the current saturates because of saturation of the electron
velocity near drain.
For E-MOSFETs, there are two mechanisms responsible for the saturation:
pinch-off and velocity saturation. The 6.17, 6.18 and 6.19 figures illustrates the
saturation phenomenon. The 6.17 figure shows the E-MOSFET behavior for
small values vDS voltages.
+vG +vD1
S GG D
SiO 2
++ Channel ++
n n
Space
charge p
region
B
S
Figure 6.17
In these conditions the MOSFET is a controlled resistor. There is also a linear

regime for very small vDS values and a non-linear regime. Figure 6.18 exposes
the moment when the saturation is installed.
273
+vG +vDsat
S GG D
SiO2
Channel
n++ n++
Space X point
charge
region p
B
S
Figure 6.18
Figure 6.19 presents the saturation regime. The channel current can not be
+vG +vD2
S GG D
SiO 2
Channel
n++ n++
Space X point
charge
region p
B
S
Figure 6.19
varied operating the drain voltage.

The MOSFET behaves like a controlled current source.
B3. The threshold voltage
For D-MOSFETs, the threshold voltage is defined by the total depletion of the
channel.
For E-MOSFETs, the threshold voltage defines the onset of strong inversion in
the channel.
6.1.3 Methods of Mathematical Description
All types of field effect transistor may be described as three terminal devices
(the body terminal is usually connected to the source). That is why the
description presented in the 4.1.3 section is still good. This section assumes
that approach. Conform to that procedure for FETs, there are three possible
connections:
• common source;
• common drain and
• common grill.
274
Common Source Connection

There are two topological solutions. They are presented in figures 6.20 and
6.21. It must be added that the solution presented in figure 6.21 is not used in
any application.
D D
iD iD
iG Input iG
G vDS Output vDS G
InputS vGS S
vGS Output
S S

• grill current;
• grill-source voltage;
The output parameters are:
• drain current;
• drain source voltage.
According to the regime of operation, the mathematical model becomes:
E1 (iD , iG , v GS , v DS ) = 0 (6.1)
E2 (iD , iG, v GS , v DS ) = 0 (6.2)
or:
i D=iD(vGS, vDS) (6.3)
i G=iG(vGS, vDS) (6.4)
where:
i D, iG instantaneous values of the currents;
vGS, vDS instantaneous values of the voltages;
In quasi-static conditions the equation numbered (6.4) may be rewritten:
i G=0 (6.5)
because the grill is a high input resistance terminal.
275
 dv dv 
E1 ∫ iD dt, iD , ∫ iG dt, iG , v GS , GS , v DS , DS  = 0 (6.6)
 dt dt 
 dv dv 
E2  ∫ iD dt, iD , ∫ iG dt, iG , v GS , GS , v DS , DS  = 0 (6.7)
 dt dt 
dv gs dv ds
i d = g11v gs + g12 v ds + C11 + C12 (6.8)
dt dt
dv gs dv ds
i g = g21v gs + g22 v ds + C 21 + C 22 (6.9)
dt dt
where:
id, ig small signal currents (instantaneous value);
vgs, vds small signal voltages (instantaneous value);
Once again the grill current may be written in a simple manner:
dv gs dv ds
i g = C 21 + C 22 (6.10)
dt dt
because, only the capacitive components are significant.
i d = g11v gs + g12 v ds (6.11)
i g = g21v gs + g22 v ds (6.12)
(6.12) is in fact:
ig = 0 (6.13)
Common Drain Connection

The two topological solutions are presented in figures 6.22 and 6.23. It must be
added that the solution presented in figure 6.23 is not used in any application.
S S
iS iS
G G
S iG vSD Output Input vSD
iG S
Input vGD vGD Output
D D
276

• grill current;
• grill-drain voltage;
• source current;
• source-drain voltage.
The mathematical models are identically with those presented for common
source connection.
Common Grill Connection
The figures numbered 6.24 and 6.25 expose the two possible topological
solutions, but only the solution presented in figure 6.24 is valid.
iS iD iD iS
S D D S
Input vSG vDG Output Input vDG vSG Output
G G

• source current;
• source-grill voltage;
• drain current;
• drain-grill voltage.
The mathematical models are also identically with those presented for common
source connection.

1. Currents derivation;
2. Non-ideal effects;
3. I-V characteristics;
4. Approximate quasi-static large-signal models.
5. Spice Models
277
6.2.1 Currents Derivation

The aim of this section is to develop the (6.3) and (6.4) equations both for JFET
and MOSFET.
A. Junction Field Effect Transistor
Analytical Expressions of the Currents. In a first approximation, the grill current
may be neglected. In these circumstances the source current equals the drain
current. In the following, only the drain current is evaluated.
One considers a JFET structure as 6.26 figure shows. Because the gate
channel junction is an abrupt junction, it is considered that the space charge
region extends only into the channel.
-vG space-charge
region (non-
G conducting)
n p n
S D
d L
+vS +vD
p
l dl
G
S
-vG
Figure 6.26
The drop voltage across an infinitesimal element (dl) of the channel is:
dvDS=i DdR (6.14)
The notations are known:
vDS - drain-source voltage (all this voltage drops across the channel)
iD - drain current (it flows through the channel)
dR - the resistance of the infinitesimal element of the channel.
But
dl
dR = (6.15)
qµ nND Z[d − 2W (l)]
where:
µn electrons mobility;
ND donor concentration into the channel;
Z the depth of the channel (it is not exposed in the figure being
the third dimension of the channel).
278
W(l) the length of the space charge region al the distance “l“ from
the source. According to (2.70), if ND>>NA, it may be written as
follows:
2k S ε 0 [v DS (l) + Φ B − v GS ]
W (l) = (6.16)
qND
and Φ B is the built in voltage of the grill-channel junction. Introducing (6.16) into
(6.15) and the result into (6.14), one finds:
dl
dv DS = i D (6.17)
 2k S ε 0 [v DS (l) + Φ B − v GS ] 
qµ nND Z d − 2 
 qND 
This expression may be integrated along the channel considering the boundary
conditions:
vDS(0)=0 (6.18)
vDS(L)=vDS (6.19)
Finally one finds:
 2 8k S ε 0  
v DS + Φ B − v GS ) 2 − (Φ B − v GS ) 2   (6.20)
3 3
i D = G 0 v DS − 2 
(  
 3 qND d  
where:
Zqµ nND d
G0 = (6.21)
L
G0 the conductance of the metallurgical channel.
The Saturation Voltage (VDSsat). The (6.20) relation is correct only if:
vDS<VDSsat. (6.22)
When
vDS=VDSsat., (6.23)
the channel is cut-off. Figure 6.12 presents this phenomenon. One observes
that the length of the space charge region is:
d
W(l)= (6.24)
2
Introducing (6.23) and (6.24) into (6.16), the saturation voltage becomes:
qNDd2
VDSsat. = − ΦB (6.25)
8k sε0
279
If the effect of vGS is included then (6.25) gets:
qND d 2
VDSsat . = − Φ B + v GS (6.26)
8k s ε 0
This results is also important because it enables the drain current derivation
when vDS>VDssat., the new expression for iD is:
 2 8k ε (Φ − v )  1 qN D d 
2
i D = G 0  S 0 B GS
− 1 ( Φ B − v GS ) +  (6.27)
 3 qND d 2  3 8k S ε 0 

It is interesting to observe that if:
vDS<<ΦB-vGS (6.28)
the (6.27) expression yields to:
 8k S ε 0 (Φ B − v GS ) 
i D ≅ G 0 1 −  v DS (6.29)
 qND d 2 
The importance of (6.29) resides in the fact that it shows a linear dependency
between iD and vDS. In these circumstances it may be stated that if (6.28)
condition is accomplished, the JFET will operate in a linear regime. The value of
the conductance associated is:
 8k S ε 0 (Φ B − v GS ) 
G = G 0 1 −  (6.30)
 qND d 2 
The Threshold Voltage. The (6.30 ) formula emphasizes the possibility to annul
the channel conductance for a certain grill source voltage. This voltage is the
threshold voltage and it corresponds to the situation in which the depletion
region covers the whole channel. Its value is:
qNDd2
vT = − + ΦB (6.31)
8k S ε0
Taking into account (6.26), (6.31) may be rewritten as follows:
vT =vGS- VDSsat. (6.32)
In the beginning of the section the grill current was ignored. In order to improve
this approximation it may be said that the real value of the grill current is
represented by the leakage current of the two junctions: grill-source and grill-
drain. Both of them are reverse biased. In these circumstances the grill current
becomes:
iG≅2IS (6.33)
where
280
IS the leakage current of a reverse biased junction.

B. Metal Oxide Semiconductor Field Effect Transistor
The approach presented for JFET is very suitable for D-MOS because it
operates at depletion. That is why this section treats only E-MOS.
Analytical Expressions of the Currents. One considers an E-MOS operating with
channel on (figure 6.27).
+vS +vG +vD

S GG D
SiO 2
n
++ x n
++
dx d
y dy
L
Space charge region
p (depletion)
B
S 6.27
Figure
The determination of the currents through the structure is, in principle, a 2D

problem. According to the approaches used for solving this problem, three
important mathematical models were developed:
• Simple Charge Control Model (SSCM); separates the 2D problem
into two coupled 1D equations; solves Poisson equation (along “d”)
for vertical potential and charge distribution; this approximation is
valid only if the variation of the electric field component along the
channel is much smaller; as a result it overestimates the saturation
current neglecting the variation in depletion charge and velocity
saturation.
• Meyer Model (MM); includes variation in depletion charge;
• Velocity Saturation Model (VSM); includes the effects of velocity
saturation.
In the following, the solution involved by Simple Charge Control Model is
presented. The general expression for the drain current may be obtained
integrating the fundamental equations of semiconductor theory. Considering the
electric field along the channel Ey much smaller than the electric field that
generate the inversion Ex, the equations are:
1. Poisson equation into semiconductor:
∂ 2 Φ qN A
= (6.34)
∂x 2 εs
2. Laplace equation into oxide:
281
∂ 2Φ
=0 (6.35)
∂x 2
3. current equation:
iD= Zqµnn( Φ )Ey(y) (6.36)
where:
Φ the electric potential;
n( Φ ) electron concentration into the inversion layer;
µn electron mobility.
The first two equations allow the electric potential calculation. This potential
enables the estimation of the mobile carrier density. The drain current may be
obtained using the third equation. In spite of these simplifications, the system
remains difficult to integrate. Its non-linear form gives the main difficulty. The
literature presents some possible manners in order to solve this problem. In the
following the quadratic model is presented.
According to this model, the electric field responsible for conduction may be
written:
dv( y )
Ey(y)= − (6.37)
dy
where:
v(y)= vGS-vT-vD(y) (6.38)
and
vD(y) the voltage induce by the drain voltage al point “y”
vT threshold voltage considered constant (neglect variation in
depletion charge along the channel).
The electron concentration “n” may be found observing that the inversion layer
charge per unit area (Qinv) may be written in two ways:
Qinv=qn (6.39)
Qinv=Cox[vGS-vT-v(y)] (6.40)
where Cox represents the oxide capacitor. Taking into account (6.39) and (6.40)
the drain current becomes:
dv( y )
i D = Zµ n C ox [v GS − v T − v( y )] (6.41)
dl
Integrating (6.41):
L v DS
∫ iD dy =
0
∫
0
Zµ n C ox [v GS − v T − v( y )]dv( y ) (6.42)
282
one finds:
EC ΦM ΦS EC
ΦM ΦS
Ei Ei
EF EF
VFB
SiO2 EV Al SiO2 EV
Al p-type Si p-type Si
Z v  2
DS
iD = µnCox ( v GS − v T )v DS −  (6.43)
L 2 
This relation is accurate if:

vDS<vGS-vT (6.44),
because this is the limit of the MOSFET operation with channel on.
The Saturation Voltage (VDSsat). When the drains source voltage equals the
value indicated by (6.44), the saturation phenomenon occurs (figure 6.17). That
is why the saturation voltage is defined as:
VDSsat.=vGS-vT (6.45)
According to (6.40), the drain current reaches its maximum value:
2
Z ( v GS − v T )
i Dsat. = µ n C ox (6.46)
L 2
From (6.43) and (6.46), a general drain current expression may be written:
 Z 2
v DS 
µnCox ( v GS − v T )v DS −  for v DS ≤ VDSsat.
 L 2 
iD =  (6.47)
 Z (v GS − v T )2
 µ nCox for v DS > VDSsat
L 2
The Threshold Voltage was defined (for E-MOS only) as the onset of strong
inversion in the channel. In terms of carriers concentration this means the
electron concentration at the insulator-semiconductor interface becomes equals
to the hole concentration in the body. In terms of band energy approach the
threshold voltage defines the gate voltage at which the total band bending at the
surface is equal to double the difference Φ B (Fermi potential), between the
intrinsic Fermi level Ei and the Fermi level in the substrate EFS. Figure 6.28
283
illustrates the energy band situation when no external voltage is applied on the
structure, while the figure 6.29 exposes the “flat band” situation. In this case the
external voltage equals the so-called Flat Band Voltage (VFB)
Keeping in mind this new concept, the threshold voltage definition may be
reformulated. Thus the threshold voltage must equal the sum of the flat band
voltage and twice the Fermi potential (body potential). At this sum the voltage
across the oxide due to the depletion layer charge must be added. Finally one
finds:
 1 1

v T = v T0 + γ (Φ − v BS' )2 − Φ 2  (6.48)
 
where:
QSS
v T0 = ΦMS − +Φ+γ Φ (6.49)
Cox
 1 1

The term γ (Φ − v BS' )2 − Φ 2  is a correction due to the so-called “body effect”.
 
(See section 6.22).
2qε Siε 0NB
γ= (6.50)
C ox
γ body effect parameter;
kT NB
Φ=2 ln (6.51)
q ni
and
Φ surface potential;
Qss surface charge;
 E − Ei 
ΦMS = Φ M − Φ S = Φ M −  χ + C + Φ  is the workfunction difference.
 2q 
6.2.2 Non-Ideal Effects
The mathematical approach presented above may be improved if such
phenomena are taking into account:
effective channel length;
channel length modulation;
parasitic resistances;
body effect;
junction breakdown.
284
Effective Channel Length

Usually, an effective length (Leff) is substituted to the drawn length (L). This
modification quantifies the edge effects of the electric fields in the performance
of the device. The formulas numbered (6.21) for JFET and (6.47) for EMOS
become:
Zqµ nN D d
G0 = (6.52)
L eff
 Z  2
v DS 
µnCox ( v GS − v T )v DS −  for v DS ≤ VDSsat.
 L eff  2 
iD =  2
(6.53)
 µ C Z ( v GS − v T ) for vDS > VDSsat
 n ox L eff 2
Channel Length Modulation

Due to the drain-source voltage a channel length modulation effect appears.
This effect is generally described a new parameter – noted “ λ ”. The drain
current for E-MOS turns into:
 Z  2
vDS 
µnCox ( v GS − v T )v DS −  (1 + λv DS ) for vDS ≤ VDSsat.
 L eff  2 
iD =  (6.54)
µ C Z ( v GS − v T )2
 n ox L eff
(1 + λvDS ) for vDS > VDSsat
2
The drain current for JFET is also modified with (1 + λv DS ) term.

Parasitic Resistances
A parasitic source resistance term is added which subtracts from the gate
voltage. The final equation (for MOSFET in saturation) is:
Z [( v GS − iDRS ) − v T ]
2
iD = µnCox (6.55)
L eff 2
In many cases, a drain parasitic resistance term is also included.
Body (Bulk) Effect
It is called also “substrate bias effect”. The voltage applied to the back contact
affects the threshold voltage of a MOSFET. The voltage difference between the
source and the bulk, vBS changes the width of the depletion layer and therefore
also the voltage across the oxide due to the change in the depletion region. This
results in a difference in threshold voltage which equals the difference in charge
in the depletion region divided by the oxide capacitance, yielding:
285
2ε S qNB
∆v T =
C ox
( 2Φ + v SB − 2Φ F ) (6.56)
Junction Breakdown
The phenomenon appears at the edge from the drain of the channel, when the
drain voltage reaches great values. It is caused by the avalanche multiplication
mechanism and it is similar to that described for bipolar transistor.
6.2.3 “I-V” Characteristics
The “I-V” characteristics are generally presented for common source
connection. The equations numbered (6.3) and (6.4) show the general form of
these characteristics. Taking into account that grill current is practically zero –
see (6.5) equation – only the drain current must be fixed. Because a bi-
dimensional representation is needed, the (6.3) expression is rewritten as
follows:
i D = i D ( v DS ) (6.57)
v GS = const.
i D = i D ( v GS ) (6.58)
v DS = const.
Under this form, they are known as static characteristics. The (6.57) relation
is the output characteristic and the (6.58) relation is the transfer
characteristic.
In the following, these characteristics (for JFET, D-MOS and E-MOS) are
presented.
Junction field effect transistor;
The output characteristic is presented in figure 6.30
iD
knee vGS-vT
region
saturation region
linear vGS=0.1V
region
vGS=0V
cut-off
vGS=2V
region
vGS=-4V
vGS=VT
vDS
Figure 6.30
286
One can see that this characteristic is very similar to that presented for bipolar
transistor. This time four regions may be defined:
• linear region; the transistor behaves like a controlled resistor; the
characteristics may be approximated with straight lines.
• knee region; the characteristics may be parabolic approximated;
• saturation region; the transistor behaves like a voltage controlled
current source resistor.
• cut-off region; no current is flowing through the transistor.
The 6.31 figure exposes the transfer
characteristic. IDSS represents the drain iD
current for vGS=0. It may be approximated
as a parabolic curve. According to that
approximation the drain current may be
written as follows:
IDSS
2 vT
 v 
iD = IDSS 1 − GS  (6.59)
 vT 
vGS
This equation is very useful for by hand Figure 6.31

analysis. It may replace the (6.27)
equation.
The (6.59) equation is usually rewritten using:
IDSS
β= (6.59’)
v 2T
as (6.59’’) shows:
i D = β(v T − v GS )
2
(6.59’’)
Metal oxide semiconductor field effect transistor;

The output characteristics both for D-MOS and E-MOS are similar with that
iD
D-MOS IDSS
JFET
E-MOS
IDSS
vGS
vT vT vT
Figure 6.32
287
presented in figure 6.30 for JFET. The grill-source voltages give the only
difference. This difference may be easier observed on the transfer
characteristics. Figure 6.32 shows a comparison among these transistors.
6.2.4 Approximate Quasi-Static Large-Signal Models
The input port, the port between grill and source is modeled using an open
circuit because the grill current may be neglected for all types of field effect
transistor. The output port is modeled approximating the output characteristic.
Finally one finds:
Junction Field Effect Transistor.
a.) Linear region
The mathematical model;
iG=0 (6.60)
iD=0 (6.61)
The electric model;
The figure numbered 6.32 presents n-channel JFET and the figure 6.33
presents p-channel model.
G D G D
v GS vDS v SG v SD
S S
The saturation region;

The mathematical model;
iG=0 (6.61)
2
 v 
i D = IDSS 1 − GS  = β(v T − v GS )2
 (6.62)
 VT 
The electrical model is presented in figure 6.34 for n channel JFET and in figure
6.35 for p channel JFET.
G D G D
VGS 2
VSG 2
IDSS 1 − v GS  IDSS 1 − v SG 
 vT   vT 
   
S S
288
The linear region

The mathematical model ;
i G=0 (6.63)
1
iD = v DS (6.64)
G
where G is given by (6.30) equation. For practical situation the value of the
output resistance is estimated using:
Ro
R= (6.65)
1 − kv GS
and Ro the resistance for vGS=0;
k a constant depending of the transistor.
The electrical model (for n-channel) is presented in figure 6.36. The p channel
model is exposed in figure 6.37
G D G D
vGS vSG
R R
S S
Metal Oxide Semiconductor Field Effect Transistor.

Because the characteristics are very similar to those presented for JFET, the
electrical models are also very similar. The D-MOS description is, in fact,
identically with that presented for JFET. Some differences appear in the
mathematical models of the E-MOS operating into the saturation region and into
the linear region.
For the saturation region, one of the suitable descriptions is given by Sah
model. According to this approach, the drain current may be written as:
i D = K (v GS − v T )
2
(6.66)
K is the conductance parameter. It may be expressed (starting from the relation
numbered (6.46)):
Z Z
K = µ n C ox = Kp (6.67)
2L 2L
In these circumstances the mathematical model is:
i G=0 (6.68)
289
i D = K (v GS − v T )
2
(6.69)
For the linear region using the notation introduced by (6.67), the drain current
may be derived from (6.43) equation. One reaches at:
[
i D = K 2(v GS − v T )v DS − v DS
2
]
≅ 2K (v GS − v T )v DS (6.70)
for vDS very small. The other equation is (of course):
iG=0 (6.71)
6.2.5 SPICE Models
The quasi-static behavior of the field effect transistors is affected by the biasing
procedure. In fact, for certain applications, the source may replace the drain and
of course the drain becomes source. This kind of operation is a reversed one.
This section presents this regime too.
The 6.38 figure presents the electrical model for the n-channel JFET. The p-
channel JFET is exposed in figure 6.39.
D D
RD RD
D’ D’
DGD DGD
G iD G iD
DGS DGS
S’ S’
RS RS
S S
The corresponding equations, for n-channel JFET, are:

Linear/quasi-linear regime forward operation;
This regime is characterized by the following conditions;
vGS’>vT (6.72)
vD’S’ <vGS’-vT (6.73)
The drain current is:
iD = βv D' S' [2(v GS' − v T ) − vD' S' ](1 + λvD' S' ) (6.74)
290
Linear/quasi-linear regime reverse operation;

vGD’>vT (6.75)
-vD’S’<vGD’-vT (6.76)
iD = β vD' S' [2(v GD' − v T ) + v D' S' ](1 − λvD' S' ) (6.77)
Saturation regime forward operation;
vGS’>vT (6.78)
vD’S’ >vGS’-vT (6.79)
2
 v 
iD = β(v T − v GS' ) (1 + λvD'S' ) = IDSS 1 − GS'  (1 + λvD' S' )
2
(6.80)
 vT 
Saturation regime; reverse operation;

vGD’>vT (6.81)
-vD’S’>vGD’-vT (6.82)
2
 v 
iD = IDSS 1 − GD'  (1 − λvD'S' ) (6.83)
 vT 
Cut-off regime forward operation;

vGS’<vT (6.84)
vD’S’ >0 (6.85)
iD = 0 (6.86)
Cut-off regime reverse operation;
vGD<vT (6.87)
291
vDS<0 (6.88)
iD = 0 (6.89)
Finally, the currents through the diodes must be added:
 v  
iGS′ = IS exp GS'  − 1 (6.90)
  VT  
 v  
iGD′ = IS exp GD'  − 1 (6.91)
  VT  
Both D-MOS and E-MOS have the same electrical model. The 6.40 presents n-
channel MOS. The p-channel MOS is presented in figure 6.41.
D D
RD RD
D’ D’
D BD D BD
G G
iD B iD B
DBS DBS
vGS S’ vSG S’
RS RS
S S
The corresponding equations, for n-channel MOSFET, are:

Linear/quasi-linear regime forward operation;
vGS’>vT (6.92)
vD’S’ <vGS’-vT (6.93)
i D = Kv D'S ' [2(v GS' − v T ) − v D'S ' ](1 + λv D'S ' ) (6.94)
Saturation regime forward operation;
292
vGS’>vT (6.95)
vD’S’ >vGS’-vT (6.96)
i D = K (v GS' − v T ) (1 + λv D'S ' )

2
(6.97)
Cut-off regime forward operation;
vGS’<vT (6.98)
vD’S’ >0 (6.99)
iD = 0 (6.100)
This time, the current through the diodes is:
 v  
i BS ′ = I' S exp BS '  − 1
 (6.101)
  VT  
 v  
i BD′ = I' ' S exp BD'  − 1 (6.102)
  VT  
The dynamic large signal behavior may be described introducing the capacitive
D D
RD RD
QGD’/CGD’ QGD’/CGD’
D’ D’
DGD DGD
G iD G iD
DGS DGS
S’ S’
QGS’/CGS’ QGS’/CGS’
RS RS
S S
293
elements as follows:
The figure numbered 6.42 illustrates the presence of parasitic capacitors for n-
channel JFET, while the figure numbered 6.43 illustrates the same effect for p-
channel JFET. The capacitors are:

 −
1
  v GS'  2
 C GS' 0 1 − Φ  v GS' ≤ fC Φ B
  B  QP
C GS' = (6.102)
 V − fC Φ B
 1 + 0.5 GS'
C Φ B − fC Φ B
v GS' > f C Φ B
 GS'0 1
 (1 − fC ) 2

 −
1
  v GD'  2
 C GD'0 1 − Φ  v GD' ≤ f C Φ B
  B  QP
C GD' = (6.103)
 V − fC Φ B
 1 + 0.5 GD'
C Φ B − fC Φ B
v GD' > f C Φ B
 GD' 0 1
 (1 − f C ) 2
The approach follows the procedure presented in section 2 [expressions
(2.119)÷(2.122)]. It must be reminded that:
m the exponent of the voltage factor for vGS’ or vGD’
CGS’0 CGD’0 depletion capacitance at zero bias.
In this case the parasitic capacitances are presented in figure 6.44 for n-
channel transistor and in figure 6.45 for p-channel transistor.
The CBS’ and CBD’ capacitances are junction capacitances, so they follow the
description presented in section 2. In these conditions CBS’ may be written:
If:
v GS' ≤ f C Φ B (6.104)
then
294
− mJ
 v 
C BS ' = C BS '0 1 − BS' 
 (6.105)
 ΦB  QP
else
v GS' > f C Φ B (6.106)
and
 V − fC Φ B   V − fC Φ B 
C ′J A D 1 + m J BS' 
 C ′JSW PS 1 + m JSW BS' 

 Φ B − fC Φ B   Φ B − fC Φ B  (6.107)
C BS ' = +
(1 − f C )(1+m j ) (1 − f C ) (1+m SWj )
D D
RD RD
QGD’/CGD QBD’/CBD QGD’/CGD QBD’/CBD
D’ D’
G DBD B G DBD B
iD iD
DBS DBS
QGS’/CGS’ S’ QGS’/CGS’ S’
QBS’/C BS QBS’/C BS
RS RS
QGB/CGB S QGB/CGB S
A similar approach for CGD’ yields to:

If:
v GD' ≤ f C Φ B (6.108)
then
−mJ
 v 
CBD' = CBD'0 1 − BD'  (6.109)
 ΦB  QP
else
v GD' > f C Φ B (6.110)
and
295
 V −f Φ   V −f Φ 
C′JA D 1 + mJ BD' C B  C′JSW PS 1 + mJSW BD' C B 
 Φ B − f Φ
C B   ΦB − fCΦB 
CBD' = (1+ m j )
+ (1+ mSWj )
(6.111)
(1 − fC ) (1 − fC )
The first terms of the sums (6.107) and (6.111) refers to the substrate capacitor
in its central zone, while the second terms refer to the substrate capacitor in its
peripheral zone. The other capacitors must be modeled considering the oxide
layer. According to the regime of operation, for CGS’ one obtains:
Cut-off regime
dQ GS'
C GS' = = C' GS'0 W (6.112)
dv GS' OFF
Linear regime
dQGS' 2   V − VD'S'  
2
CGS' = = C'ox WLef 1−  D'S'sat   + C'GS'0 W (6.113)

dvGS' 3   2VD'S' sat − VD' S'  
L
 
Saturation regime
dQ GS ' 2
C GS ' = = C' ox WL ef (6.114)
dv GS ' S 3
In the same manner, CGD’ becomes:

Cut-off regime
dQ GD'
C GD' = = C' GD'0 W (6.115)
dv GD' OFF
Linear regime
dQGD' 2   VD'S' sat  

2
CGD' = = C'ox WLef 1 −    + C'GD'0 W (6.116)

dvGD' 3   2VD' S'sat − VD' S'  
L
 
Saturation regime
dQ GD '
C GD' = = C' GD '0 W (6.117)
dv GD ' S
The grill-bulk capacitors are:
296
Cut-off regime
dQ GB
C GB = = C' ox WL ef + C' GB 0 L ef (6.118)
dv GB OFF
Linear regime
dQ GB
C GB = = C' GB 0 L ef (6.119)
dv GB L
Saturation regime
dQ GB
C GB = = C' GB0 L ef (6.120)
dv GB S
6.4 Quasi-Static Small Signal Behavior
The small signal models are derived from large signal model through a
linearization procedure.
6.4.1 SPICE Models
The electrical models exposed in the 6.38 and 6.39 figures are used as start
point for the developing of JFET SPICE small signal model.
The 6.46 figure presents the small signal electrical model for a JFET.
D D
RD RD
D’ D’
ggd’ gbd
gmvgs gmbv bs
G B
G
go
ggs’ gmvgs’ gbs
v gs
vgs’ S’ S’
RS RS
S S
297
The small signal parameters are:
diGS ' diGS IGS + IS

ggs ' = ≅ = ggs = (6.121)
dv GS ' QP dv GS QP VT
diGD' diGD IGD + IS

ggd' = ≅ = ggd = (6.122)
dv GD' QP dv GD QP VT
diD diD λID

go = ≅ = (6.123)
dv D'S ' QP dv DS QP 1 + λVDS
diD diD 2IDSS  V  2ID

gm = ≅ =− 1 − GS  = (6.124)
dv D' S' QP dv DS QP vT  v T  VGS − v T
In respect with these parameters the mathematical model becomes:

ig=ggdvgd+ggsvgs (6.125)
id=gmvgs+govds-ggdvgd (6.126)
Because:
vgd=vgs-vds (6.127)
the (6.125) and (6.126) relations may be rewritten:
ig=(ggs+ggd)vgs-ggdvds (6.128)
id=(gm-ggs)vgs+(go+ggs)vds (6.129)
In this case the electrical model is presented in figure 6.47. In this case the new
parameters are:
diBS' diBS IBS + IS

gbs' = ≅ = gbs = (6.130)
dv BS' QP dv BS QP VT
diBD' diBD IBD + IS

gbd ' = ≅ = gbd = (6.131)
dv BD ' QP dv BD QP VT
KVDS (1 + λ VDS ) linear regime

di D  2I
gm ≅ = D (6.132)
dv DS saturation regime
QP  VGS − v T

diD gm γ
gmb ≅ = (6.133)
dv BS QP 2(Φ B − VBS )
298
β( VGS − v T − VDS linear regime

diD  λID
go ≅ = (6.134)
dv DS saturation regime
QP  1 + λVDS
The mathematical model becomes:

i g=0 (6.135)
i d=gmvgs+govds+gmbvbs-gbdvbd (6.136)
but:
vbd=vbs-vds (6.137)
and the drain current is:
i d=gmvgs+(go+gbd)vds+(gmb-gbd)vbs (6.138)
6.4.2 Simplified Models
By hand analysis does not request sophisticated models. This section is
dedicated to the so-called simplified models, very useful for rapid examination.
Figures 6.48 and 6.49 present two possible simplified electrical models for both
JFET and MOSFET.
G gmvgs’ D G gmvgs’ D
vgs’ go vgs’
S S
The mathematical model associated to the electrical model presented in figure

6.48 is:
i g=0 (6.139)
i d=gmvgs+govds (6.140)
Because:
go ≅ 0 (6.141)
the above model may be simplified as follows:
i g=0 (6.142)
i d=gmvgs (6.143)
Figure 6.49 models this system of equation.
299
6.5 Dynamic Small Signal Behavior
The dynamic small signal models are obtained linearizing the dynamic large
signal models presented in section 6.3. This section treats both SPICE models
and simplified models.
6.5.1 SPICE Models

The SPICE models for dynamic small signal regime are obtained linearizing the
SPICE models for dynamic large signal regime.
The Junction Field Effect transistor
Figure 6.50 exposes the small signal model for a JFET.
The Metal Oxide Semiconductor Field Effect transistor
The dynamic small signal model is presented in figure 6.51. The parameters
used both in figure 6.50 and 6.51 are those defined in previous sections.
D D
RD RD
Cgd’ Cbd’
D’ D’
gmvgs gmbv bs
ggd’ gbd B
G
go C gd
ggs’ gmvgs’ G ’ gbs
S’ C gb S’
Cgs’ Cbs’
RS RS
S S
6.5.2 Simplified Models

The figures numbered 6.52 and 6.53 present two useful models. The only
difference between them is the presence of the output conductance.
300
G C gd gmvgs’ D G Cgd gmvgs’ D
C gs Cgs
go
S S
6.6 D.C. Biasing
As section 4.6 showed, the biasing circuits must:

• guarantee of the linear operation of the transistor;
• control of the small-signal parameters;
• control of the power dissipated.
In order to satisfy these requirements, two problems must be solved:
• quiescent point positioning;
• quiescent point stabilisation.
That is why this section treats:
1. Quiescent Point Positioning;
2. Quiescent Point Stabilisation;
3. Usual Biasing Circuits.
6.6.1 Quiescent Point Positioning

In respect with the above definition in section given in section 6.6, the quiescent
point is defined by {VDS, VGS, VDG, ID, IG, IS} array for a p-channel FET. In the
case of the p-channel FET, this array becomes {VSD, VSG, VGD, ID, IG, IS}. The
biasing circuit must fix all this parameters. Observing that between these six
parameters are linked by four equations (two of them being Kirchhoff equations
and other two the device equations), one concludes, that only two of these
parameters are independent. In general, one chooses as independent
parameters VDS and ID. That is the reason why the static point of a transistor is
fixed on the output characteristic. Figure 6.54 presents the safe area, the region
that allows FETs operate in the saturation mode.
One can see that the borders of the safe area are:
• linear/non-linear region;
• cut-off region;
• maximum limit of the drain current;
301
• maximum dissipated power;

• maximum limit of the drain-source voltage.
iD safe area
iD
PDmax
T1
IDmax T2>T1 IDSS1
cut-off IDSS2 T2
region
Z
linear
region IZ
vEDS
VDSmax VT2 VT1 UG uGS
The actual position of the quiescent point inside this region depends of the
application.
6.6.2 Quiescent Point Stabilization
The above section showed that the fixing of the quiescent point requires the
fixing of the doublet {VDS, ID}. In real circuits these two electrical parameters are
linked together by a supplementary Kirchhoff equation. Because of this, the
stabilization of the quiescent point requires the stabilization (only) of the drain
current.
Two important factors may cause the moving of the quiescent point:
• the scattering of the parameters;
• the temperature.
The scattering of the parameters is a result of the technologic process. Both vT
and IDSS vary from simple to double. The design of the bias circuit must solve
this problem
The variation of the ambient temperature causes the variation of the “I-V”
characteristics as figure 6.55 proves. One can see that:
• IDSS is decreasing while the temperature is increasing;
• vT is decreasing while the temperature is increasing.
The effect of these variations is the existence of the “Z point”. The co-ordinates
of this point (VGSZ, IDZ) do not depend of the temperature variation. It is
interesting to be observed that for large currents (ID>IDZ), the drain current is
decreasing when the temperature is increasing. That means that in this range of
variation for ID,
IDZ ≤ ID ≤ IDSS (6.144)
the thermal run away problem does not exist.
302
6.6.3. Usual Biasing Circuits

The analysis presented below refers only to n-channel FETs. For p-channel
FETs the same procedure must be followed except the sign of the voltages that
must be changed.
Theoretically, there are three types of biasing circuits in respect with the grill–
source voltage:
1. The grill-source voltage is always negative. These circuits are used for
JFETs and sometimes for D-MOSs when they operates with negative
grill related to source.
2. The grill-source voltage is both negative and positive. These circuits are
used for D-MOSs.
3. The grill-source voltage is always positive. These circuits are used for
E-MOSs and sometimes for D-MOSs when they operates with positive
grill related to source.
Junction Field Effect Transistor Bias
Two kinds of circuits are presented:
1. Self-Bias Circuit
2. Voltage Divider Bias.
Self-bias Circuit
ED
b.) parts function
RG, RS self-bias for the grill.
Explication: The gate is tied to ground (0V) via a resistor
RG (usually large ≈ MΩ ), so VG=0V (recall that due to
the high impedance it is assumed IG=0). A current ID RG RS
flows through RD and RS so VS is positive. Thus VGS is
negative. Indeed
VGS=VG-VS (6.145)
Figure 6.56
but:
VG=IGRG (6.146)
Because
IG≅0 (6.147)
(6.146) becomes:
VG≅0 (6.148)
In the same time:
303
VS=RSID>0 (6.149)
Replacing (6.149) and (6.148) into (6.145), one finds:
VGS=-RSID<0 (6.150)
c.) D.C analysis.
Two problems must be treated:
• Direct problem: one considers that the values of the parts are known
and QP must be calculated (analysis problem);
• Reverse problem: one considers that QP is known and the values of the
parts must be calculated (design problem);
c1.) direct problem
Problem formulation: For the circuit diagram presented in figure 6.56, ID must be
calculated. One considers ED, RG, RS, IDSS, and vT known.
Solution:
The circuit presented in figure 6.56 is modeled in figure 6.57.
G D
iD
vGS=-RSiD
VGS ID VDS
IDSS
S
ED ID
RG RS
vT VGS vGS
Writing Kirchhoff second law on the single mesh of the circuit one obtains:
ED= IDRS+VDS (6.151)
But:
2
 V 
ID = IDSS 1 − GS  (6.152)
 vT 
where:
VGS=-IDRS (6.153)
These three equations (6.151)÷(6.153) represent a system of three equations
with three unknown variables {ID, VDS, VGS} and by consequence the problem is
solved. Another possible approach is presented in figure 6.58. The quiescent
point is settled in the intersection point of those two curves. That is the so-called
grafo-analytical solution.
304

Problem formulation: For the circuit diagram presented in figure 6.56, RG and RS
must be calculated. One considers that the limits of the allowed variation for ID,
(
ID ∈ IDmin , IDmax ) (6.154)
are imposed by the designer. In the same time it is assumed that ED is

considered known and of course the type of the transistor. That means that the
dispersion of the parameters is also given. That is for vT:
(
v T ∈ v Tmin , v Tmax ) (6.155)
and for IDSS

(
IDSS ∈ IDSSmin ,IDSSmax ) (6.156)
The 6.59 figure is very useful for the design algorithm that will be presented.
iD
vGS=-RSiD
IA
A IB
y
B
vGS
VA
VB
Figure 6.59
it must be observed that only the extreme characteristics (VTmax., IDSSmin) and
(VTmin., IDSSmax) are drawn.
RS. Designing
I.) One solves the system (6.151)÷(6.153) looking for RS expression. This is:
vT  ID 
RS =  − 1 (6.157)
ID  IDSS 
 
II.) One determines the allowed limits of variation for RS, taking into account the
“worst case conditions”. These are:
Lower limit
ID=IDmax (6.158)
if:
305
IDSS=IDSSmax. (6.159)
vT=vTmin. (6.160)
RS=RSmin. (6.161)
Introducing these values into (6.157) RSmin becomes:
v T min  ID max 
R S min =  − 1 (6.162)
ID max  IDSS max 
 
Upper limit
ID=IDmin (6.163)
if:
IDSS=IDSSmin. (6.164)
vT=vTmax. (6.166)
RS=RSmax. (6.167)
The RSmax is:
v T max  ID min 
R S max =  − 1 (6.168)
ID min  IDSS min 
 
III One chooses RS:
[
RS∈ RS min,RS max ] (6.169)
Observation: It may happen to obtain

RSmin>RSmax (6.170)
That means that there no possible solution for RS. In these conditions another
topological bias circuit must be considered. A desirable solution is the next one.
RG Designing
The higher value has RG, the better is. This high value is desirable in order to
assure high input impedance for the transistor. Usually it has few MΩ . The
upper limit is given by the condition to maintain a small drop voltage across RG,
due to the leakage current of the grill junction.
Voltage Divider Bias
b.) parts function
R1, R2 grill divider; it set up the grill potential
306
RS it set up the source potential
c.) DC analysis.
c1.) direct problem
Problem formulation: For the circuit diagram presented in figure 6.60, ID must be
calculated. One considers ED, R1, R2, RS, IDSS, and vT known.
Solution:
The circuit presented in figure 6.60 is modeled in figure 6.61.
ED R1 G D
G D
R1
IR V GS ID V DS EG VG S ID VDS
I
S S
ED R ED
R2 RS R 2 RS G RS
If the R1, R2 divider is transformed according to Thevenin theorem, the circuit

from figure 6.62 will be obtained. For this circuit one may write:
ED= IDRS+VDS (6.171)
EG=VGS+I DRS (6.172)
where:
R2
EG = ED (6.173)
R1 + R 2
R1R2
RG = (6.174)
R1 + R2
These four equation form a system of four equation with four unknown variables
{ID, VDS, VGS, EG}. The problem is solved. The grafo-analytical solution is
presented in figure 6.63
c2 ) reverse problem
Problem formulation: For the circuit diagram presented in figure 6.70, R1, R2 and
RS must be calculated. The limits of variation for the electrical parameters are
those given by (6.154), (6.155) and (6.156). The figure noted 6.62 emphasizes
the algorithm used for designing. This algorithm is identical with that followed for
the self-bias circuit.
307
iD iD
vGS=EG+RSiD vGS=EG+RSiD IA
IDSS IB
ID A
y
B
vT VDS EG vGS vGS

VA
VB
RS Designing .
I. ) One finds RS from the above system, considering that EG, vT, ID and IDSS are
given.
EG v T  ID 
RS = + − 1 (6.175)
ID 
ID  IDSS 

II.) One chooses EG respecting:
EG∈ [ 0, ED ] (6.176)
III. ) Applying the same conditions for Rsmax and RSmin one reaches at:
EG v T max  ID min 
R S max = +  − 1 (6.177)
ID min ID min  IDSS min 
 
EG v T min  ID max 
R S min = +  − 1 (6.178)
ID max I D max  IDSS max 
 
If RSmin is larger than RSmax, a new value for EG must be chosen. Finally RS must
be chosen from:
[
RS∈ RS min,RS max ] (6.179)
R1 and R2 Designing
They may be dimensioned solving (6.173) and (6.174) equations. Because RG
value is needed, this may be found using the procedure used for self-bias
circuit.
D-MOSFET Bias
The simplest way to bias a D-MOSFET is to use the zero bias network. This is
reasonable since vGS can be positive negative.
308
Zero Bias Circuit

a.) schematic diagram is presented in figure 6.63 ED
b.) parts function
RG sets up the grill potential RD
Rd load resistor (it has no role for
DC bias)
c.) DC analysis.
c1.) direct problem
It may be observed that: RG
VGS=0 (6.180)
ID=IDSS (6.181) Figure 6.63
VDS=ED-IDRD (6.182)
The only resistor that must be dimensioned is RG. It must be dimensioned
respecting the procedure described for the other bias circuit.
E-MOSFET Bias
The voltage divider bias network is also useful for E-MOSFET. In the case of
an n-type E-MOSFET, a positive VGS is needed.
Divider Bias Circuit
a.) schematic diagram is presented in figure 6.64 ED
b.) parts function
R1
R1, R2 sets up the grill potential RD
Rd load resistor (it has no role
for DC bias)
c.) DC analysis.
c1.) direct problem
It may be observed that: R2
R2
VGS= E D (6.183)
R1 + R 2
Figure 6.63
R1 and R2 designing follows the procedure described for JFET.
309
Problems
Problem 1 This problem analyses DC biasing circuits treats for JFETs. For the
circuits presented in figure 1, test the region of operation and than determine
mA
the quiescent point. Assume that β = 1.3 2 and vT=-3V for all the transistors.
V
ED(20V)
ED (+20V) RD(1K)
ED(20V) iD D
RG1(50k) RD (10K)
RD(1K) iG
iD D D G
S iS
S
iG
G G RG(10M) R2 RS (1K)
S iS S S (9K)
S
RG(1M) RS (1K) RG2 (40k)
R1(1K)
-EG(-5V) EG(-5V)
Figure 1a Figure 1b Figure 1c
a.) Solution I
Through the simple inspection of the circuit it may be observed that
1. grill is grounded (there is no current through RG)
2. source potential is positive or zero (equals the drop voltage across RS)
In conclusion the grill-source voltage is negative or zero. On the other hand, the
drain-source voltage is positive due to ED. In these conditions, it is a good
guess to assume that the transistor operates in saturation region. Supposing
that the transistor operates in the saturation region, the circuit presented in
figure 1a is modeled in figure 2.
Writing Kirchhoff second law on the single mesh of the circuit, one obtains:
ED=IDRD+VDS+IDRS (1)
But from (6.80), ignoring the parasitic resistances and considering
λ=0 (2)
one obtains:
310
ID = β(v T − VGS )
2
(3)
G D
VGS ID VDS
RD
S
RG RS ED
Figure 2 Figure 3
From the inspection of the circuit it may be observed that:

VGS=-IDRS (4)
The equations numbered (1), (2) and (4) represent a system of three equations
with three unknown variables {ID, VDS, VGS}. The solutions are:
− (2βv T R S − 1) ± (2βv T R S − 1)2 − 4β 2 R 2S v 2T

I D1,2 = (5)
2β R S2
and therefore:
ID1=4.95 mA (6)
ID2=1.82 mA (7)
From (4) for VGS one finds:
VGS1=-4.95 V (8)
VGS2=-1.82 V (9)
From (1) VDS becomes:
VDS=ED-ID(RS+RD) (10)
and:
VDS1=10.1V (11)
VDS2=16.36V (12)
311
As one can see there are two possible solutions: {VGS1, ID1, VDS1} and {VGS2, ID2,
VDS2}. The problem is how to choose the
proper one. The solution is presented by iD
the figure 4. It can be seen that in the A(VGS1,ID1)
plain (vGS, iD) only the point B, whose ID1
co-ordinates are (VGS2, ID2), represents vGS=-RSiD IDSS
the valid solution, because the JFET
can operate only if the grill-source
ID2
voltage is greater than threshold
voltage. V GS1 v T V GS2 vGS
B(VGS2,ID2)
Finally observing that
ID>0 (13) Figure 4
VGS>vT (14)
VDS> few volts (15)
one can conclude that the transistor operates in the saturation region.
SPICE solution
The circuit simulated is presented in figure 3. The transistor used is 2N3819, a
n-channel JFET. Its parameters are:
VTO -3
BETA 1.304000E-03
LAMBDA 2.250000E-03
IS 33.570000E-15
ISR 322.400000E-15
ALPHA 311.700000E-06
VK 243.6
RD 1
RS 1
CGD 1.600000E-12
CGS 2.414000E-12
M .3622
VTOTC -2.500000E-03
BETATCE -.5
KF 9.882000E-18
Table 1
The simulation results are:

ID 1.83E-03
VGS -1.83E+00
VDS 1.63E+01
312
b.) Solution I
Once again, through the simple inspection of the circuit it may be observed that
1. grill potential is fixed by the RG1, RG2 divider; it is reasonable to assume
that this potential is negative due to EG.
In conclusion the grill-source voltage is negative. On the other hand, the drain-
source voltage seems to be positive (ED is greater than EG, and RG1 plus RG2
are greater than RD). In these conditions, it is a good guess is to assume that
the transistor operates in saturation region. Supposing that the transistor
operates in the saturation region, the circuit presented in figure 1b is modeled in
figure 5.
R G1
G D
I1 I
R G2 VGS ID VDS
RD
S
ED
EG
Figure 5 Figure 6
The Kirchhoff system of equation associated to this circuit is:

I=I1+ID (16)
ED=IRD+VDS (17)
ED+EG=IRD+I1(RG1+R G2) (18)
It must be completed with:
2
(3)
VGS=-EG+I1RG2 (19)
These five equations form a system of five unknown variables {I, I1, ID, VDS,
VGS}. Noting:
R D − R G2 ( )
R G1 2 R G1 + R G2 − R D
a = v T + EG + ED (20)
R G1 + R G 2 − R D RD R G1 + R G2 − R D
313
R G1 + R G2
b = R D + R G1 (21)
R G1 + R G2 − R D
the solutions for the drain current are:
(2abβ + 1) ± (2abβ + 1) 2 − (2abβ) 2

ID1,2 =
2b 2 β
That means:
ID1=1.48 mA
ID2=2.72 mA
For VGS from (3) one finds:
ID
VGS = v T ± (22)
β
The numerical values are:
ID1 − 4.07 V
VGS1 = v T ± = (23)
β − 2.93 V
Because V GS must be higher than vT , the accepted value is:
VGS1 = −2.93 V
For ID2 one reaches at:
ID 2 − 4.45 V
VGS 2 = v T ± = (24)
β − 2.55 V
The good value is:
VGS1 = −2.55 V
For VGS the expression is:

 RD 
VGS = (E G + E D )1 − −
 R G + R G + RD 
 1 2 
(25)
 RD 
− IDR D 1 + 
 R + R G2 + R D

 G1 
and the values are:
VDS1= 6.22V
314
and
VDS2= -7.42V
Because VDS must be greater then zero, the accepted value is 6.22 V.
Conclusion: The complete solution is:
ID1=1.48 mA
VGS1 = −2.93 V
VDS1= 6.22V
and transistor operates into saturation region.
SPICE solution
The circuit simulated is presented in figure 6. The results are:
ID 1.71E-03
VGS -1.85E+00
VDS 2.08E+00
c.) Solution I
This time it may be observed that
1. grill potential is negative (it is fixed by the R1, R2 divider)
In conclusion the grill-source voltage is negative. On the other hand, the drain-
source voltage is positive due to ED. In these conditions, it is a good guess is to
assume that the transistor operates in saturation region. Supposing that the
transistor operates in the saturation region, the circuit presented in figure 1c is
modeled in figure 7.
G D
ID
RG VGS ID VDS
RD
S
ED
RS
R2
I1
R1 EG
Figure 7 Figure 8
The Kirchhoff system of equations is:

ED=ID(RD+RS)+VDS (26)
315
EG=(R1+R2)I1 (27)
At these equations must be added:
2
(3)
and:
R2
VGS = −E G − ID R S (28)
R1 + R 2
These four equations form a system of four equations with four unknown
variables {ID, VDS, VGS, I1}. The solutions are:
 R2 
1 − 2β R S  v T + E G 
 R 1 + R2 
ID1,2 = 2
±
2βR S
2 2
(29)
  R2   R2 
1 − 2β R S  v T + E G  − 4β 2 R S2  v T + E G
 


  R 1 + R2   R 1 + R2 
±
2βR S2
The numerical values are:

ID1=4.32mA
ID2=1.45 mA
Consequently VGS is (from (28)):
VGS1=-4.84 V
VGS2=-1.95V
The first value can not be accepted because VGS results smaller than vT. Finally
for VDS (from (26)) one finds:
VDS2=19.1V
Conclusion: The complete solution is:
ID2=1.45 mA
VGS2 = −1.95 V
VDS1= 19.1V
and the transistor operates into saturation region.
SPICE solution
The modeled circuit is presented in figure 8. The simulation results are:
ID 1.46E-03
316
VGS -1.96E+00
VDS 1.71E+01
Problem 2 This problem analyses DC biasing circuits for DMOS. For the
circuits presented in figure 9, test the region of operation and then determine
mA
the quiescent point. Assume that K=10 × 10-3 2 and vT=-4V for all the
V
transistors.
ED (20V) ED (20V)
RD RG1 RD
(1K) (1M) (1K)
RG RG2
(1M) (1M)
Figure 9a Figure 9b
ED (20V) ED (20V)
RG1 RD RD
(1M) (1K) (100K)
RG2 RS RG1 RS
(1M) (1K) (1M) (1K)
Figure 9c Figure 9d
a.) Solution I
Through the simple inspection of the circuit it may be observed that
3. grill is grounded (there is no current through RG)
317
4. source potential is zero.

In conclusion the grill-source voltage is zero. On the other hand, the drain-
source voltage is positive due to ED. In these conditions, it is a good guess is to
transistor operates in the saturation region, the circuit presented in figure 9a is
G D
VGS ID VDS
RD
S
RG ED
Figure 10 Figure 11
ED=IDRD+VDS (30)
ID is given by (6.69) expression:
ID = K (VGS − v T )
2
(31)
where:
VGS=0 (32)
Replacing (32) into (31), ID becomes:
I D = Kv 2T = 0.16 mA (33)
From (30) VDS is:

VDS=ED-RDID=19.34 V (34)
For VGS one finds:
ID  0V
VGS = v T ± = (35)
K 2v T = −8 V
Of course only the first value “0V” must be chosen. Because ID is positive, VDS
is greater than VDSsat (few volts) and VGS is zero, the transistor operates in
saturation region.
318
SPICE solution
The circuit simulated is presented in figure 11. The simulation results are:
Transistor parameters:
LEVEL 1
L 100.000000E-06
W 100.000000E-06
VTO -4
KP 20.000000E-06
Quiescent point is:

ID 1.60E-04
VGS 0.00E+00
VDS 1.98E+01
One can observe the simulation results are similar to those obtained using by
hand analysis.
b.) Solution I
Observing the circuit it may be found:
1. grill potential is positive (is given by RG1, RG2 divider)
2. source potential is zero.
In conclusion the grill-source voltage is positive. On the other hand, the drain-
source voltage is positive due to ED. In these conditions, it is a good guess to
transistor operates in the saturation region, the circuit presented in figure 9b is
RG1
RD
G D
VGS ID VDS
RG2 ED
Figure 12 Figure 13
It is easy to observe that:
319
R G2
VGS = E D = 10 V (36)
R G1 + R G2
Replacing this value into (31) ID becomes:

ID=1.96 mA (37)
and of course from (35) VDS is:
VDS=18.04 V (38)
According to these values the transistor operates in saturation.
SPICE solution
The circuit simulated is presented in figure 13. The results are:
The quiescent point is:
ID 1.96E-03
VGS 1.00E+01
VDS 1.80E+01
They are corresponding to those presented in (36), (37) and (38) expressions.
c.) solution I
It seems natural to make the supposition that the transistor operates in the
saturation region because both the grill-source voltage (fixed by the grill divider
RG1, RG2, together with RS resistor) and drain-source voltage (fixed by ED) are
positive. The circuit presented in figure 9c is modeled in figure 14.
RG1 IR
RD ID
G D
VGS ID VDS I
RG2 RS ED
Figure 14 Figure 15
The Kirchhoff equations are:

I=ID+IR (39)
ED=RSID+V DS+RS (40)
320
ED=IRRG1+IRRG2 (41)
They must be completed with the device equation (31)
2
(31)
and the VGS expression:
R G2
VGS = E D − IDR S (42)
R G1 + R G2
These five equations form a system of five equations with five unknown
variables {I, IR, ID, VDS, VGS}. The solutions are:
 R G2 
2KR S  E D − v T  + 1
 R G1 + R G2 
ID = ±
2KR 2S
2
(43)
  R G2    R G2 
2KR S  E D − v T  + 1 − 4KR S  E D − v T 
  R G1 + R G2    R G1 + R G2 
±
2KR 2S

ID1=1.97 mA (44)
ID2=130 mA (45)
From (42) VGS is:
VGS1=8.03V (46)
VGS2=-120V (47)
For VDS, the (40) expression yields to:
VDS1=16.06V (48)
VDS2=-300V (49)
It is obvious that the solutions are {ID1, VDS1, VGS1} and the transistor operates
into the saturation region.
SPICE solution
The circuit simulated is presented in figure 15 and the results are
ID 1.55E-03
VGS 8.45E+00
VDS 1.69E+01
321
d.) Solution I
Because the grill-source voltage is negative (due to RG and RS resistors) and
the drain-source voltage is positive (due to ED) it is reasonable to assume that
the transistor operates into saturation region. The circuit presented in figure 9d
is modeled in figure 16
R D ID
G D
VGS ID VDS
I
S
RG RS ED
Figure 16 Figure 17
At this equation, the device equation must be added, completed with the VGS
expression:
I D = K (V GS − v T )
2
(31)
VGS=-IDRS (51)
The equations numbered (50), (31) and (51) represent a system of three
equations with three unknown variables {ID, VDS, VGS}. The solutions are:
− (2Kv T R S − 1) ± (2Kv T R S − 1)2 − 4K 2R 2S v 2T

ID1,2 = (52)
2KR S2
and consequently:
ID1= 92.72 µA (53)
ID2=6.75 mA (54)
For VGS one finds:
VGS1= −92.72 µV (55)
VGS2=-6.75 V (56)
322
The value indicated by the (56) expression can not be accepted because this
value is lower than the threshold voltage and thus the transistor is blocked. But
according to (54) the transistor can not be blocked. This is the formal
contradiction that makes invalid the (56) expression. In these conditions VDS is:
VDS=9.7V (57)
The final solution indicates that the transistor operates into the saturation
region.
SPICE solution
The circuit simulation is presented in figure 17. The results are:
ID 1.48E-04
VGS -1.48E-01
VDS 5.02E+00
Problem 3 This problem analyses DC biasing circuits for EMOS. For the
circuits presented in figure 18, test the region of operation and then determine
3 mA
the quiescent point. Assume that K=1.53975 × 10 and vT=2.831V for all the
V2
ED (20V) ED (20V)
RG1 RD RG1 RD
(1M) (1K) (1M) (1K)
RG2 RG2 RS
(170K) (1M) (1K)
Figure 18a Figure 18b
transistors.
a.) Solution I
Supposing that the transistor operates into saturation region (both VGS and VDS
are positive; VGS due to RG1, RG2 divider and VDS due to ED), the circuit diagram
presented in figure 18a is modeled in figure 19
323
RG1
G D
VGS ID VDS
RD
S
ED
RG2
Figure 19 Figure 20
Kirchhoff second law on the single mesh of the circuit is:

ED=IDRD+VDS (58)
ID is given by (31) expression:
2
(31)
and VGS by (59):

R G2
VGS = E D (59)
R G1 + R G2
The solutions are:

ID=8.657 mA (60)
VGS=2.9V (61)
VDS=11.343V (62)
In conclusion transistor operates into saturation region.
SPICE Solution
The circuit simulate is presented in figure 19. The simulation results are:
Transistor parameters
L 2.000000E-06
W .3
VTO 2.831
KP 20.530000E-06
Electrical values:
ID 8.68E-03
VGS 2.91E+00
VDS 1.13E+01
324
b.) Solution I
A similar topology was presented in figure 9c. According to the analysis
presented in that situation, it seems natural to make the supposition that the
transistor operates in the saturation region. The circuit presented in figure 18b is
R G1 IR
R D ID
G D
VGS ID VDS
I
R G2 RS ED
Figure 21 Figure 22
The Kirchhoff equations are:

I=ID+IR (63)
ED=RSID+VDS+RSID (64)
ED=IRRG1+IRRG2 (65)
They must be completed with the device equation (31)
2
(31)
and the VGS expression:

R G2
R G1 + R G2
variables {I, IR, ID, VDS, VGS}. The solutions are:
 RG2 
2KRS  ED − v T  + 1
ID =  RG1 + RG2  ±
2KR 2S
2
(67)
  RG2    RG2 
2KRS  ED − v T  + 1 − 4KRS  ED − v T 
  RG1 + RG 2    RG1 + RG 2 
± 2
2KRS
325

ID1=7.27 mA (68)
ID2=7.07 µA (69)
From (66) VGS is:
VGS1 ≅ 2.73 V (70)
which is greater than the threshold voltage, and
VGS2 ≅ 2.9 V (71)
The first one, is lower than the threshold voltage, and can not be accepted. For
VDS, the (64) expression yields to:
VDS2=5.86V (72)
It is obvious that the solutions are {ID2, VDS2, VGS2} and the transistor operates
into the saturation region.
SPICE solution
The circuit simulated is presented in figure 22 and the results are
MODEL IRF150
ID 7.10E-03
VGS 2.90E+00
VDS 5.80E+00
VBS 0.00E+00
VTH 2.83E+00
GM 2.09E-01
Problem 4 This problem treats the behavior of the quiescent point in respect
with grill voltage for JFET, DMOS and EMOS. For the circuits presented in
figure 23 sketch:
• the drain current,
• the grill-source voltage,
• the drain-source voltage and
• the geometric locus for the quiescent point,
in respect with the grill potential.
326
E D(20V) ED (20V) E D (20V)
RD(1K) RD RD
iD D (1K) (1K)
iD iD
G
S G G
iS
S
VG RS RS
VG VG
R S (1K) (1K) (1K)
Assume that:
mA
• for JFET β = 1.3 vT=-3V,
V2
-3 mA
• for DMOS K=10 × 10 vT=-4V
V2
3 mA
• for EMOS K=1.53975 × 10 vT=2.831V
V2
and the transistor operates into saturation region
ED>VDS>VDssat (73)
and
ID>0 (74)
a.) Solution I
The circuit presented in figure 23a is modeled in figure 24.
G D
V GS ID V DS
RD
VG
S
RS ED
Figure 24 Figure 25
327
Writing Kirchhoff second law, the drain current law and the drain-source
expression one reaches at:
2
(76)
VGS=V G-IDRS (77)
These three equations form a system of three equations with three unknown
variables {ID, VDS, VGS}. For ID one reaches at:
β R 2S ID2 − [2β(VG − v T )R S + 1]ID + β( VG − v T ) 2 = 0 (78)
The solutions are:
[2β(VG − v T )R S + 1] ± 1 + 4β R S (VG − v T )
ID1,2 = 2
(79)
2βR S
and finally ID related to VG is:
[2β(VG − v T )R S + 1] − 1 + 4β R S (VG − v T )
ID = 2
(80)
2β R S
From (75) VDS is:
[2β(VG − v T )R S + 1] − 1 + 4βR S (VG − v T )

VDS = E D − (R S + R D ) 2
(81)
2βR S
and from (77) VGS is:
[2β(VG − v T )R S + 1] − 1 + 4β R S (VG − v T )
VGS = VG − R S 2
(82)
2β R S
The range of variation for VG may be found using the (73) restriction. The lower
limit of VG (when the quiescent point is at the limit between saturation and cut-
off region) is reached when:
VDS=ED (83)
and it may be found substituting VDS from (81) into (83). This means:
[2β(VG − v T )R S + 1] − 1 + 4β R S (VG + v T )
E D − (R S + R D ) 2
= ED (84)
2β R S
and more:
328
[2β(VG − v T )R S + 1] − 1 + 4βR S (VG − v T )

(R S + R D ) 2
= 0 (85)
2βR S
The (85) relation is satisfied if:
[2β(VG − v T )R S + 1] − 1 + 4βR S (VG − v T ) = 0 (86)
This yields to:

VG=vT (87)
The upper limit (when the quiescent point is at the limit between saturation and
non-linear region) of variation for VG is reached when:
VDS=VDSsat (88)
The VDSsat voltage may be expressed using (6.32) relation as follows:
VDSsat=VGS-vT (89)
and this means that:
VDS=VGS-vT (90)
when VG reaches its lower limit. Introducing (81) and (82) into (90), one finds:
[2β(VG − v T )R S + 1] − 1 + 4β R S (VG − v T )
E D − (R S + R D ) 2
=
2β R S
(91)
[2β(VG − v T )R S + 1] − 1 + 4βR S (VG − v T )
= ( VG − v T ) −
2βR S
Noting:
x 2 = 1 + 4βR S (VG − v T ) (92)
the (91) equation may be rewritten:
(
(R D + R S )x 2 − 2R D x + R D − R S − 4β R S2 E D = 0 ) (93)
The solutions are:
2R D ± 4R D2 − 4(R D + R S )(R D − R S − 4β R 2S E D )
x 1,2 = (94)
2(R D + R S )
By consequence, from (92) the VG expression is:
329
2
 2R ± 4R 2 − 4(R + R )(R − R − 4βR 2 E ) 
 D D D S D S S D
 −1
 2(R D + R S ) 
 
VG1,2 = vT + (95)
4βR S
Because the positive value must be chosen, the upper limit of the VG potential
is:
2
 2R + 4R 2 − 4(R + R )(R − R − 4βR 2 E ) 
 D D D S D S S D
 −1
 2(R D + R S ) 
 
VG = v T + (96)
4βR S
Finally, the geometrical locus of the quiescent point is represented by the

function:
ID=ID(VDS) (97)
and it may be obtained eliminating VG between (77) and (78) expression. This
procedure yields to
1 1
ID = − VDS + ED (98)
R S + RD R S + RD
Numerical solutions are obtained using SPICE simulation.

SPICE simulation
The circuit simulated is presented in figure 25.
Figure 26 Figure 27
330
The VG voltage was varied between (-4V, 20V) with a step of 0.1 V. The result
obtained for the drain current, the grill-source voltage, the drain-source voltage
variation are presented in figure 26, and the geometric locus for the quiescent
point is presented in figure 27. It is interesting to observe that the range of
variation for the grill voltage is from –3V (that is vT) to around 8 V the value
prescribed by (96).
b.) Solution I
The theoretical approach presented for JFET may be used in this case too.
Because the equivalent circuit diagrams are identical, the system of equations
is also the same:
2
(100)
VGS=VG-IDRS (101)
The only difference appears in the device equation (100). The solution for ID is:
KR 2S ID2 − [2K (VG − v T )R S + 1]ID + K( VG − v T ) 2 = 0 (102)
The solutions are:
[2K (VG − v T )R S + 1] ± 1 + 4KR S (VG − v T )

ID1,2 = 2
(103)
2KR S
and finally ID related to VG is:
[2K (VG − v T )R S + 1] − 1 + 4KR S (VG − v T )

ID = 2
(104)
2KR S
For VDS one finds:
[2K (VG − v T )R S + 1] − 1 + 4KR S (VG − v T )

VDS = E D − (R S + R D ) 2
(105)
2KR S
The VGS voltage is:
[2K (VG − v T )R S + 1] − 1 + 4KR S (VG − v T )

VGS = VG − (106)
2KR S
The locus equation of the quiescent point is obvious identical with (98) equation.
SPICE simulation
331
In this case the VG voltage was varied between (-10V, 20V) with a step of 0.1 V.
Figure28 Figure 29
The result obtained for the drain current, the grill-source voltage, the drain-
source voltage variation are presented in figure 28, and the geometric locus for
the quiescent point is presented in figure 29. It is interesting to observe that the
range of variation for the grill voltage is from –43V (that is vT) to around 20 V the
value prescribed by (96).
c.) Solution I
The system numbered (99)÷(101) describes the circuit presented in figure 23c
because there is no formal difference between a DMOS and a EMOS. Of
course the exact solution may be derived according to (102). In this case it is
interesting to study the situation (it is a common situation):
1
2(VG − v T )R S >> (103)
K
By consequence (102) becomes:
R S2 ID2 − 2R S ( VG − v T ) ID + ( VG − v T ) 2 = 0 (104)
The (104) equation may be rewritten:
[R I
S D − ( VG − v T ) ]2
=0 (105)
and therefore
1 1
ID ≈ VG − vT (106)
RS RS
This time the link between these two variables is linear. For VDS one finds:
R S + RD R + RD
VDS ≈ − VG + E D + S vT (107)
RS RS
332
and for VGS:

VGS ≈ v T (108)
The locus equation of the quiescent point is obvious identical with (98) equation.
SPICE simulation
The VG voltage was also varied between 10V and +20 V with a step of 0.1V.
The results are presented in figures 30 and 31. One can see the linear variation
predicted in theoretical approach.
Figure 30 Figure 31
The range of variation for VG is between almost 3V and 13V.
333
• Common Source
• Common Drain
• Common Grill
• FET Incremental Resistances
Chapter 7
The Fundamental Field Effect Transistor
Circuits
This chapter treats the behavior of the circuits based on the principal
connections of the field effect transistors:
• common source connection;
• common drain connection;
• common grill connection.
The depletion metal oxide semiconductor field effect transistors (D-MOS) is
used to illustrate the approach, but whenever is necessary the examples using
junction field effect transistors (JFET) or enhancement metal oxide
semiconductor field effect transistors (E-MOS) are given. The analysis is similar
to that presented in “Chapter 5” for bipolar transistors, following the same steps.
The outline of the chapter is:
• The first section is dedicated to the common source connection. Transfer
characteristic is developed and based on it, amplification and commutation
applications are presented. For amplification circuit, voltage gain, input and
output resistances are computed. The frequency response is also treated.
• The second section presents the common drain connection. Using the
same procedure, transfer characteristic is developed. For the amplification
circuit, voltage gain, input and output resistances are computed. The
behavior of the voltage gain and the input impedance in respect with the
frequency is treated.
• The third section analyses the common grill connection. The voltage gain,
input and the output resistances are computed.
• The fourth section is dedicate to FET,s incremental resistances.
335
7.1 The Common Source Connection
The input signal is applied between grill and source terminals and the output
signal is generated between drain and source terminals.
ED ED ED
iD iD ED
iD K(vGS-vT)2
RD RD RD RD
G
D G D G D
vIN v O vIN S vO v IN vGS vO v

IN v GS R vO
S S
b.) parts function

RD load resistor;
vIN total instantaneous value of the input voltage;
This analysis is dedicated to transfer characteristic;
vO=vO(vIN) (7.1)
Theoretically, vIN may vary between - ∞ and + ∞ . This large range of variation
implies the usage of different types of models for the transistors, according to
their states:
I. For
vGS<vT (7.2)
and
vGD<vT (7.3)
the transistor is blocked. The circuit presented in figure (7.1) must be modeled
as figure 7.2 shows. It is obvious that:
vO=ED (7.4)
It must be also observed that the conditions numbered (7.2) and (7.3) are
satisfied if:
v IN ∈ (−∞, v T ) (7.5)
336
The Fundamental Field Effect Transistor Circuits
II. For:
vGS>vT (7.6)
and
vGD<vT (7.7)
the transistor is in the saturation region. The circuit diagram from figure 7.1 is
modeled in figure 7.3. Observing that:
vO=ED-i DRD (7.8)
and
i D = K (v GS − v T )
2
(7.9)
vGS=vIN (7.10)
for the output voltage one finds:
v O = E D − KR D (v IN − v T )
2
(7.11)
On the other hand, the range of variation for vIN may be found solving (7.6) and
(7.7) restrictions in respect with vIN. According to (7.10) relation, (7.6) in-
equation may be rewritten as:
vIN>vT (7.12)
Noting that:
vGD=RDiD+vIN-ED (7.13)
the (7.7) in-equation becomes:
2
KR D (vIN-vT) +vIN-ED<vT (7.14)
This in-equation is satisfied if:
− 1 − 1 + 4KR D E D − 1 + 1 + 4KR D E D
+ v T < v IN < + v T (7.15)
2KR D 2KR D
Taking into account (7.12), the final solution is:
− 1 + 1 + 4KR DE D
v T < v IN < + vT (7.16)
2KR D
III. For:
vGS>vT (7.17)
and
vGD>vT (7.18)
337
the transistor is in the triode (linear and knee or non-linear) region. The
transistor is described by the (6.70) and (6.71) equations:
[
i D = K 2(v GS − v T )v DS − v DS
2
]
≅ 2K (v GS − v T )v DS (6.70)
iG=0 (6.71)
In these conditions the circuit diagram presented in figure 7.1 is modeled as
figure 7.4 shows. One may observe that the output voltage is:
R
v O = ED ≈0 (7.19)
R + RD
where R is:
1
R= (7.20)
2K( v GS − v T )
The input voltage must satisfy the condition:
− 1 + 1 + 4KR DE D
vIN> + vT (7.21)
2KR D
Of course this limit may be greater or smaller than ED. As a general rule:
− 1 + 1 + 4KR DE D
+ v T <ED (7.22)
2KR D
Taking into account (7.4) together with (7.5), (7.11) together with (7.16) and
(7.19) together with (7.121) the transfer characteristic (7.1) may be depicted as
figure 7.5 shows. Related to this figure some observations must be made:
vO
Cut-off
Region
ED Saturation
Region
Triode
Region
vT ED v IN
− 1 + 1 + 4β R D E D
+ vT
2β R D
Figure 7.5
1. The stage may operate as an amplifier if the transistor is working in the

saturation region. In this case, the input voltage varies between threshold
338
− 1 + 1 + 4KR D E D
voltage vT and + v T . (a few volts). If linear operation is
2KR D
needed, then the range of variation for vIN will be around 300-500mV (the so
called “small signal condition”). It is the duty of the bias circuit to settle the
operating point in this region.
2. This stage may operate as a switching circuit. In this case, it runs
between cut-off and linear regions.
Three different circuits were simulated. The first one is represented in figure 7.6.
It contains a D-MOS. The input voltage (noted ED) was varied between –10V
and +20V with a step of 0.1 V. The transistor parameters are:
mA
• K=10 × 10-3
V2
• vT=-4V
The transfer curve is presented in figure 7.7.
Figure 7.8 presents a circuit based on JFET. In this case the input voltage was
varied between –5V and 0 with a step of 0.1V. The transistor parameters are:
mA
• β = 1.3
V2
• vT=-3V
The simulation results are presented in figure 7.9. Figure 7.10 exposes a circuit
based on a E-MOS transistor whose parameters are:
mA
K=1.53975 × 10
3
•
V2
• vT=2.831V
339
The simulation results are shown in the 7.11 figure. Comparing the three
characteristics, one can observe that the curves emphasize the same three
regions of operation for the transistors. The only differences are the edges of
the saturation region.

7.1.1 Common Source Amplifier
The previous section treated the large signal behavior of this connection. This
section treats the small signal behavior.
a.) circuit diagram is presented in figure 7.12.
b.) parts function
ED
RG1 RG2 RS bias circuit.
C1, C2 coupling capacitors; they isolate the RG1 RD
DC operating point; for large enough Iin C1
frequencies, the signal passes through C2
the coupling capacitors. Vo
CS de-coupling capacitors; for high Vin
RG2 RS CS
frequencies the emitter may be
considered grounded.
RD load.
Figure 7.12
c.) small signal analysis
• voltage gain;
c1.) voltage gain
It is defined as:
340
Vot
AV = (7.23)
Vt

Vt input test voltage (amplitude);
R G1R G2
R G = R G1 R G2 = (7.24)
R G1 + R G2
R DR L
R D,L = R D R L = (7.25)
R D + RL
One finds:
Vot=-gmVgsRD,L (7.26)
Vt=Vds (7.27)
A v = −gm R D,L (7.28)
The (7.28) expression proves that:

• the voltage gain is high;
0
• the phase difference between the output voltage and input voltage is 180
(minus sign).
c2.) input resistance
It is defined as:
Vt
R in = (7.29)
It
Rin may be determined using 7.14 figure.
Rin=RG (7.30)
In conclusion, the input resistance value is high and equals RG
c3.) output resistance;
It is defined as:
341
Et
Ro = (7.31)
It
Vin = 0
Figure 7.15 shows the placement of the testing source. In the same time it must
be observed that Cs realizes the short circuit condition from (7.31) relation.
ED
G D It It
RG1 RD +
It +
C1 C2 RB Vbg gmVgs RD Et RD Et
Et - -
S
Cs RG2 RS CS

Vgs=0 (7.32)
the circuit diagram from figure 7.16 is reduced as figure 7.17 exposes. By
consequence:
Ro=RD (7.33)
In conclusion, the output resistance has a moderate value and equals RD.
c4.) frequency response;
The high frequency equivalent circuit is showed in figure 7.18.
Rg Cgd
Iin G Igd D Id
+ Ir Igs
Et RG Cgs Vgs g mVgs RDL V ot
- S
Figure 7.18

Iin = Ir + Igs + Igd (7.34)
Igd + Id = gm Vgs (7.35)
E t = R gIin + RGIr (7.36)
Igs
0= − R GIr (7.37)
sC gs
342
Igd Igs
0= + Vot − (7.38)
sC gd sC gs
0 = Vot − R DLId 0 (7.39)

and
Igs
Vgs = (7.40)
sC gs
Solving this system, Av becomes:

sCgd
1−
Vot gmRDLR gm
=− (7.41)
Et Rg 1+ s(CgsRLC + CgdR + CgsR + gmRDLRCgd) + s2RDLRCgsCgd
where:
R = Rg RG (7.42)
It is interesting to be observed that at middle frequency, the voltage gain is:
gmRDLR RG
A v = A v (ω) =− = −gmRDL ≅ −gmRDL (7.43)
Rg R g + RG
ω=0
which is similar to (7.28). One may observe that (7.41) has a zero and two poles
as follows:
gm
z1 = − (7.44)
C gd
C gd (R DL + R + g m R DL R) + C gs R
p1 = − +
2RR LC C π C µ
[C ]
(7.45)
(R DL + R + g m R DL R ) + C gs R − 4RR DL C gs C gd
2
gd
+
2RR DL C gs C gd
C gd (R DL + R + gm R DL R) + C gsR
p2 = − −
2RR LC C π C µ
(7.46)
[C gd (R DL + R + gm R DL R) + C gsR ]
2
− 4RR DL C gd C gs
−
2RR DL C gs C gd
The usual approach considers:
343
RDL→0 (7.47)
and, by consequence, the poles expressions may be simplified as follows:
1
p1 ≅ − (7.48)
R(C gs + C gd )
 1 g 
p 2 ≅ − + m  (7.49)
 RC C 
 gs gs 
Comparing (7.48) with (7.49) it may be observed that:

p 1 << p 2 (7.50)
and, in conclusion, the first pole – the dominant pole – is p1. The other pole (p2)
corresponds to a higher frequency. The frequency corresponding to the “zero” is
also very high. In these conditions, the first pole dictates the high frequency
behavior of the stage. Figures 7.19 and 7.20 indicate the position of the poles in
s plan and the shape of the gain characteristic.
Au
dB
jω
s plan
p2 z1 p1 σ
p1 z1 p2 ω
d.) SPICE analysis

Figure 7.21 shows the circuit diagram used for simulation. Figure 7.22 exposes
the results of simulation.
344
Due to relatively high input impedance, the stage must be suitable driven by a
voltage source.
7.1.2 Common Source Inverter
The common source inverter realizes “not” function. Usually, E-MOS transistors
are used in such applications. Related to the type of the load, there are two
important kinds:
• resistor load and;
• active load.
This section presents a qualitative analysis of these circuits. The figure
numbered 7.23 exposes a resistor load inverter, the figure numbered 7.24
shows an active load inverter with saturation transistor, while the figure 7.25
shows an active load inverter with non saturated transistor.
ED EG ED
ED
RD TL TL
T T
vO vO vO
v IN v IN v IN
The 5.1 table describes their behavior.
7.2 The Common Drain Connection
The input signal is applied between grill and drain terminals and the output
signal is generated between sources and drain terminals.
EC
ED ED iIN G D ED
G D
D
vGS K(vGS-vT )2
G v GS
S R
S vIN S
vIN
v IN RS vO v IN RS vO vO
RS vO RE
345
b.) parts function

RS load resistor;
This analysis is dedicated – as previous chapter did - to the transfer
characteristic:
vO=vO(vIN) (7.1)
The transistor model will be picked up in respect with the vIN value:
I According to (7.2) and (7.3) conditions, if:
vGS<vT (7.2)
and
vGD<vT (7.3)
the transistor is blocked. The circuit presented in figure 7.26 is modeled in figure
7.27. It is obvious that:
vO=ED (7.51)
In the same time, in terms of input voltage, the restrictions (7.2) and (7.3)
become:
vIN<vT (7.52)
For
vGS>vT (7.6)
and
vGD<vT (7.7)
the transistor is in saturation region. The circuit diagram from figure 7.26 is
modeled in figure 7.28. The output voltage is:
vO=RSiD (7.53)
where the drain current is given by (7.9):
i D = K (v GS − v T )
2
(7.9)
and so:
v O = R S K (v GS − v T )
2
(7.54)
The relation between vIN and vGS may be found solving the equation:
346
2
vIN=vGS+RSK(vGS-vT) (7.55)
The output voltage becomes:
1 − 1 + 4KR S ( v IN − v T )
v O = v IN − v T + (7.56)
KR S
Of course the (7.56) expression is true only if the transistor is in saturation. The
edged of the range of variation for the input voltage, corresponding to this
situation, may be find solving (7.6) and (7.7) restrictions. The lower limit is given
by (7.6) condition. This limit may be evaluated observing (see the dotted mesh
from 7.28 figure) that:
vIN=vGS+RSiD (7.57)
and hence:
v IN = v GS + R S K (v GS − v T )
2
(7.58)
The (7.58) relation corroborated with (7.6) condition yield to

vIN>vT (7.59)
For the upper limit the (7.7) condition must be solved in respect with the input
voltage. From the inspection of the 7.28 figure one may write:
ED=vDG+vIN (7.60)
The input voltage becomes:
vIN=ED-vDG=ED+vGD (7.61)
The (7.61) expression together with the (7.7) restriction yield to
vIN<ED+vT (7.62)
In conclusion:
vIN ∈ (vT, ED+vT) (7.63)
III. The transistor is in the triode (linear and knee or non-linear) region if:
vGS>vT (7.17)
and
vGD>vT (7.18)
The modeled circuit is presented in figure 7.29. The output voltage is:
RS
v O = ED ≈ ED (7.64)
R + RS
where R is given by (7.20):
347
1
R= (7.20)
2K( v GS − v T )

vIN<E D+vT (7.65)
From (7.51), (7.56) and (7.64) expressions, the (7.1) transfer characteristic may
be drawn as follows:
vO
ED.
Triode Region
Saturation Region
vT E D+v T vIN
Cut-off Region
Figure 7.30
Related to this figure some observations must be made:

1. The stage may operate as an amplifier if the transistor is working in active
region. In this case, the input voltage varies between threshold voltage vT
and ED+vT. The operation is nearly linear, but the amplification ratio is
almost one. It is the duty of the bias circuit to settle the operating point in
this region.
2. This stage may operate as a switching circuit. In this case, it runs
between cut-off and saturation regions.
Figure 7.31 presents the circuit used for simulation. One can see that the E-
MOS IFR 150 was used for simulation.
348
Figure 7.32 presents the results of the simulation. EIN – the input voltage – was
varied between –10V and 40 V. The output characteristic is very similar to that
exposed in figure 7.30.
e.) application - common drain amplifier The previous section treated the
large signal behavior of this connection. This section treats only the small signal
behavior.
e.2) parts function ED
RG1, RG2 bias divider; they set-up

the base potential of the RG1
transistor. C1
RS load; C2
C1,C2 coupling capacitors; Vin
they isolate the DC RG2 RS Vo
operating point; for
large enough
frequencies the signal Figure 7.33
passes through the
• voltage gain;
• voltage gain
Vot
AV = (5.12)
Vt
349
ED
It G D Id
RG1 V gs g mVgs
It C1
C2
Vt Ir RG S
Vt RG2 RS Vot RS Vot
where RG is given by (7.66):
R G1R G2
R G = R G1 R G2 = (7.66)
R G1 + R G2
For Vot one finds:

Vot=gmVgsRS (7.67)
If Vt is expressed from the dotted mesh:
Vt = Vgs + g m Vgs R S (7.68)

gmR S
Av = (7.69)
1 + gmR S
This expression may be simplified because usually:

gmRS>>1 (7.70)
Therefore, the voltage gain may be approximated equaling unity:
Av ≅ 1 (7.71)
Conclusions:
• the voltage gain equals unity (there is no gain);
• there is no phase difference between the output voltage and input
voltage.
Vt
R in = (5.16)
It
and may be found using 7.35 figure.
350
Vt
It = (7.72)
RG
Therefore:
R in = R G (7.73)
Conclusions:
• the input resistance equals the bias divider.
Vt
Ro = (5.23)
It
Vin = 0
by Csc.
ED
G D
RG1
C1 Vgs gmVgs
C2 It It
RG
+ S Is +
Csc RG2 RS Vt RS Vt
- -
The circuit presented in figure 7.36 is modeled in 7.37. The K1 theorem for the
source node gives:
I t + g m Vgs = I s (7.74)
But:
Vgs=-Vt (7.75)
and
Vt
Is = (7.76)
RS
Introducing (7.75) and (7.76) into (7.74), one reaches at:
351
Vt
I t − g m Vt = (7.77)
RS
and finally;
RS
Ro = (7.78)
1 + gm R S
Because usually:
gmRS>>1 (7.79)
the output resistance may be approximated:
1
Ro ≅ (7.80)
gm
Conclusions:
• the output resistance has a low value;
Observation: Due to its qualities:
• high input resistace;
• low output resistance;
• unitary gain,
this stage is used as buffer stage. It is also called source follower.
In order to simplify the analysis, the effects of Cgs, Cgd and RG will be neglected.
The frequency behavior of the voltage gain and the input impedance will be
treated.
Rg G D
• frequency response – gain voltage
It
+ Cgs Vgs V ds gmVgs
The modeled circuit is presented in figure 7.38. Rg Et
S It
is the output resistance of the Et source. The - RS Vot
voltage gain may be defined as:
Vot (s)
A u ( s) = (7.81) Figure 7.38
E t ( s)
On this circuit it may be written:

It+gmVgs=Is (7.82)
It
Et=RgIt+ +RSIs (7.83)
sC gs
0=Vds+RSIs (7.84)
352
where:
It
Vgs = (7.85)
sC gs
and
Vot=RSIs (7.86)
Solving this system, one reaches at:
R S (gm + sC gs )
A u ( s) = (7.87)
1 + gmRS + sC gs (R S + R g )
The final expression (7.87) has a zero and a pole:

gm
z1 = − (7.88)
C gs
1 + gmR S gmR S
p1 = − ≅− ≅
C gs (R g + R S ) C gs (R g + R S )
(7.89)
gmR S g
≅− = − m = z1
C gsR S C gs
Both the zero and the pole are situated around a frequency corresponding to
 gm 
−  . In these circumstances it must be accepted that the cut-off frequency
 Cgs 
 
of the voltage gain is very high. It may be estimated more rigorous considering
the Cds and Cgd capacitors.
• frequency response – input impedance
The input impedance may be computed as:
E t (s )
Zin (s) = (7.90)
It ( s )
and from the above system may be written:

1 + gmRS + sC gs (R S + R g )
Zin (s) = (7.91)
sC gs
This time the zero is:

1 + gmR S g
z1 = − ≅− m (7.92)
C gs (R g + R S ) C gs
353
and the pole

p1=0 (7.93)
It is obvious that the absolute value of the pole is smaller than the absolute
value of the zero and by consequence, the input impedance decreases when
the frequency increases. In conclusion the input impedance has a capacitive
behavior. In these circumstances the stage can not be used as a buffer stage
excepting the low frequencies.
e4.) SPICE analysis
Figure 7.39 presents the circuit used
for simulation of the gain voltage and
the input impedance. It must be
observed that the transistor is an E-
MOS n-channel. The values of the
capacitors are:
CBD =3.229 nF
CGS =9.027nF
CGD =1.679nF
Figure 7.39
The input source Vin was varied
between 10kHz and 1Ghz. Figure 7.40 exposes the gain voltage behavior in
respect with frequency. In this case, the high frequency is situated at 11MHz.
Figure 7.41 shows the input impedance variation in respect with frequency. It
may be observed that the input impedance decreases dramatically in respect
with frequency.
7.3 The Common Grill Connection
The input signal is applied between source and grill terminals and the output
signal is generated between drain and grill terminals.
354

b.) parts function
RS load resistor;
i IN total instantaneous value of the input current;
ED ED
ED
K(vGS-vT)2 RD RD
ED R
RD iIN S D iIN S D
RD
S D
vIN vGS vO vIN vGS vO
v IN v GS vO
v IN vO G G G

Following the procedure presented in the previous sections, the calculation of
the transfer characteristics will be made.
If:
vGS<vT (7.2)
and
vGD<vT (7.3)
the transistor is blocked. The circuit presented in figure 7.42 is modeled in figure
7.43. It may be observed that:
vO=ED (7.94)
In the same time, the input voltage may be written as:
vIN=-vGS (7.95)
and by consequence:
vIN>-vT (7.96)
For
vGS>vT (7.6)
and
vGD<vT (7.7)
355
the transistor is in saturation region. The circuit diagram from figure 7.42 is
modeled in figure 7.44. The output voltage is:
vO=ED-RDi D (7.97)
and from (7.9) corroborated with (7.95):
v O = E D − R S K (v GS − v T ) = E D − R S K (v IN + v T )
2 2
(7.98)
The limits of variation for the input voltage may be found applying the procedure
from 7.1 section (see (7.16) expression). This yields to:
1 − 1 + 4KR D E D
- v T > v IN > − vT (7.99)
2KR D
For operation into the linear region the transistor must be biased so that:
vGS>vT (7.17)
and
vGD>vT (7.18)
In these conditions the circuit diagram presented in figure 7.42 is modeled in
figure 7.45. One may observe that the output voltage is:
R RD
v O = ED + v IN (7.100)
R + RD R + RD
where R is:
1
R= (7.20)
2K( v GS − v T )
1 − 1 + 4KR D E D
vIN< − vT (7.21)
2KR D
Taking into account (7.94), (7.98) and (7.100) the transfer characteristic is
represented in the figure numbered 7.46: Related to this figure some
observations must be made:
1. The stage may operate as an amplifier if the transistor is working in the
saturation region. In this case, the input voltage varies between
1 − 1 + 4KR D E D
threshold voltage -vT and − v T . (a few volts). It is the
2KR D
duty of the bias circuit to settle the operating point in this region.
356
2. This stage may operate as a switching circuit. In this case it runs

between cut-off and linear regions.
vO
Cut-off
Region
Saturation ED
Region
Linear
Region
ED -vT vIN
1 − 1 + 4βRDED
− vT
2β RD
Figure 7.46

The figure 7.47 presents the circuit used for simulation. The transistor
parameters are:
mA
K=10 × 10
-3

V2
vT=-4V
The input voltage (noted Vin) varied between –20V and +20V with a step of 0.1
V. The transfer characteristics is presented in figure 7.48.
e.) application - common grill amplifier The previous section treated the large
signal behavior of this connection. This section treats the small signal behavior
of the stage.
e.2) parts function
RG1, RG2, RS bias circuit.
357
RD load;
CD de-coupling capacitor;
C1,C2 coupling capacitors;
voltage gain; ED
input resistance;
output resistance; RG1 R G1
C1 C2
voltage gain
Vin Vo
V
AV = ot (5.12) RS R G2 CG
Vt
Figure 7.49
Vt test voltage source
(amplitude);
gmVgs
ED
It S D
RG1 R G1
C1 C2
It
Vt Vgs Vot
Vt Vot RS RD
RS RG2 CG
For Vot one finds:

Vot=-gmVgsRD (7.101)
and the input voltage is:
Vt = − Vgs (7.102)

A v = gmR S (7.103)
Conclusion: The stage has a high voltage amplification.
358
input resistance;
Vt
R in = (5.16)
It
and may be found using 7.51 figure. The test current (It) is:
Vt V
It = − gm Vgs R D = t + gm Vt R D (7.104)
RS RS
Therefore:
RS 1
R in = ≅ (7.105)
1 + gmR S gm
Conclusions: The stage has a small input resistance.
output resistance;
Vt
Ro = (5.23)
It
Vin = 0
and figure 7.52 shows the placement of the testing source and of the short
circuit capacitor. The 7.53 figure shows the modeled circuit. Because
g mVgs
ED
S D It It
RG1 R G1
C1 C2 It
Vgs Vt Vt
C sc
Vt
RS RD RD
RS RG2 CG
Vgs=0 (7.106)
The circuit presented in 7.53 figure is modeled in figure numbered 7.54. it is
obvious that:
Ro=RD (7.107)
Conclusions: the output resistance has a moderate value.
359
7.4 FET Incremental Resistances
This section presents the calculation of the incremental resistances of a field

effect transistor. The 7.55 figure is used for this calculation where:
RD the equivalent resistance in the drain;
RG the equivalent resistance in the grill;
RS the equivalent resistance in the source.
The calculation will be made using the mathematical model described by the
(7.107) and (7.108) equations. The equivalent circuit is presented in 7.56 figure.
ig=0 (7.107)
1
id=gmvgs+ vds (7.108)
ro
RD G gmV gs D
Rd
RG
V gs go
Rs
Rg RS S
and
1
ro = (7.109)
go
7.4.1 Resistance Seen Looking into the Grill.

Figure 7.57 presents the circuit used for the calculation. This circuit is modeled
in the figure noted 7.58.
By the inspection of the circuit it may be observed that:
It=0 (7.110)
In these circumstances:
Rg → ∞ (7.111)
360
It G gmVgs D
V
Rg = t
It RD
V gs ro
It Vt
S RD
RS
Vt RS
Conclusion: the resistance seen into the grill is very high.

7.4.2 Resistance Seen Looking into the Source.
G gmV gs D
RD Io
Vgs V ds ro
RG
It RG S It RD
Vt Vt
V
Rs = t
It
For this circuit one may write:

It=Io+gmVgs (7.112)
Vds=roIo (7.113)
0=roIo+Vt-RDIt (7.114)
and of course:
Vgs = − Vt (7.115)
The resistance seen into the source becomes:

Vt r + RD
Rs = = o (7.116)
It 1 + g m ro
Generally:
361
gmro>>1 (7.117)
and
ro>>RD (7.118)
In these conditions Rs may be approximated:
1
Rs ≅ (7.119)
gm
Conclusion: the resistance seen into the source is relatively low.
7.4.3 Resistance Seen Looking into the Drain.
Vt
Rs = G gmV gs D It
It
Io
It Vgs V ds ro
Vt
RG RG S Vt
RS
RS
For this circuit one may write:

It=Io+gmVgs (7.120)
Vds=roIo (7.121)
0=roIo+Vt-RSIt (7.122)
and of course:
Vgs = −R S I t (7.123)
The resistance seen into the drain is:

Vt
Rs = = ro + (1 + g m ro )R S (7.124)
It
Taking into account (7.117) the resistance seen into the drain may be rewritten:
R s ≅ ro + gm ro R S (7.124)
362
If
RS=0 (7.125)
Rs becomes:
R s ≅ ro (7.126)
else
R s ≅ ro (1 + gm R S ) (7.127)
Because generally:
gmRS>>1 (7.128)
Rs becomes:
R s ≅ ro gm R S (7.129)
Conclusion: in any case Rd is relatively large.
363
Problems
resistance and output resistance for the common source amplifier. For the
circuits presented in figure 1, find the voltage gain, the input resistance, and the
output resistance.
ED ED ED
RD RG1 RD RG1 RD
Iin C1 Iin Iin

C2 C2 C2
C1 C1
Vo Vo Vo
Vin Vin Vin
RG1 RS CS RG2 RS CS RG2 RS CS
Assume that:
• For the circuit presented in Figure 1a:
RG=1 MΩ ; RD=1 k Ω ; RS=1 k Ω ; ED=20V; C1=10µF; C2=10µF;
mA
CS=100µF; β = 1.3 2 ; vT=-3V
V
• For the circuit presented in Figure 1b:
RG1=1 MΩ ; RG2=1 MΩ ; RD=1 k Ω ; RS=1 k Ω ; C1=10µF; C2=10µF;
-3 mA
CS=100µF; ED=20V; K=10 × 10 ; vT=-4V
V2
• For circuit presented in Figure 1c
RG1=1 MΩ ; RG2=1000 k Ω ; RD=1 k Ω ; RS=1 k Ω ; C1=10µF; C2=10µF;
3 mA
CS=100µF; ED=20V; K=1.54 × 10 ; vT=2.831V
V2
Solution
Following the procedure presented in section five, three steps must be followed
in order to find the voltage gain, input resistance and output resistance:
• DC analysis whose aim is the quiescent points calculation;
• the calculation of the small signal parameters;
• AC analysis whose aim is the calculation of the voltage gain, input
resistance and output resistance:
Solution 1a
DC analysis
See the problem 1a from “Chapter 6”. The bias point details are:
364
ID=1.83 mA (1)
VGS=-1.83 V (2)
Simplified models will be used. Mutual conductance is:
2ID 2 × 1.83
gm = = ≅ 3.13mS (3)
VGS − v T − 1.83 − ( −3)
AC analysis
It was presented in the 7.1 section. The most important results will be presented
below.
• The voltage gain is:
Au=-gmRD=-3 ×1 = −3 .13 (4)
• The input resistance is:
Rin=RG=1 MΩ (5)
• The output resistance is:
Ro=RD=1k Ω (6)
Solution 1b
DC analysis
See the problem 2c from “Chapter 6” The bias point details are:
ID=1.55 mA (7)
VGS=8.45V (8)
The mutual conductance is:
2ID 2 × 1.55
gm = = ≅ 0.29mS (9)
VGS − v T 8.45 − (−4)
AC analysis
It was presented in the 7.2 section.
Au=-gmRD=-0.29 ×1 = − 0.29 (10)
365
R G1R G2 1000 × 1000

Rin=RG= = = 500 kΩ (11)
R G1 + R G2 1000 + 1000

Ro=RD=1k Ω (12)
Solution 1c
DC analysis
See the problem 3b from “Chapter 6” The quiescent point co-ordinates are:
ID=7.07 mA (13)
VGS=2.93V (14)
2ID 2 × 7.07
gm = = ≅ 205 mS (15)
VGS − v T 2.9 − 2.831
AC analysis
below.
Au=-gmRD=-205.1 ×1 = −205 (16)
R G1R G2 1000 × 1000
Rin=RG= = = 500 kΩ (17)
R G1 + R G2 1000 + 1000
Ro=RD=1k Ω (18)
Conclusion: E-MOS transistor has the largest voltage amplification.
SPICE Simulation
The circuit presented in figure 1a is simulated using the circuit diagram
presented in figure 2. The simulation included both DC and AC analysis. The
DC analysis included the quiescent point co-ordinates and the gm calculation.
These are:
ID=1.83E-03 A; VGS=-1.83E+00 V; VDS=1.63E+01V; gm=3.15E-03 S
366
R G1R G2 1000 × 1000

Rin=RG= = = 500 kΩ (19)
R G1 + R G2 1000 + 1000

Ro=RD=1k Ω (20)
Solution 1c
DC analysis
See the problem 3b from “Chapter 6” The quiescent point co-ordinates are:
ID=7.07 mA (21)
VGS=2.93V (22)
2ID 2 × 7.07
gm = = ≅ 205 mS (23)
VGS − v T 2.9 − 2.831
AC analysis
below.
Au=-gmRD=-205.1 ×1 = −205 (24)
R G1R G2 1000 × 1000
Rin=RG= = = 500 kΩ (25)
R G1 + R G2 1000 + 1000
Ro=RD=1k Ω (26)
Conclusion: E-MOS transistor has the largest voltage amplification.
SPICE Simulation
The circuit presented in figure 1a is simulated using the circuit diagram
presented in figure 2. The simulation included both DC and AC analysis. The
DC analysis included the quiescent point co-ordinates and the gm calculation.
These are:
ID=1.83E-03 A; VGS=-1.83E+00 V; VDS=1.63E+01V; gm=3.15E-03 S
resistance and output resistance for the common drain amplifier. For the circuits
367
presented in figure 8, find the voltage gain, the input resistance, and the output
resistance.
ED ED ED
RG1 RG1
Iin C1 Iin Iin

C2 C1 C2 C1 C2
Vin Vin
RG RS Vo RG2 RS Vo Vin RG2 RS Vo
Assume that:
For the circuit presented in Figure 8a:
RG=1 MΩ ; RS=1 k Ω ; ED=20V; C1=10µF; C2=10µF; vT=-3V;
mA
β = 1.3 2 .
V
For the circuit presented in Figure 8b:
RG1=1 MΩ ; RG2=1 MΩ ; RS=1 k Ω ; C1=10µF; C2=10µF; ED=20V; vT=-4V;
-3 mA
K=10 × 10 .
V2
For circuit presented in Figure 8c
RG1=1 MΩ ; RG2=1 M k Ω ; RS=1 k Ω ; C1=10µF; C2=10µF; ED=20V;
3 mA
vT=2.831V; K=1.54 × 10 .
V2
Solution 2a
DC analysis
The circuit presented in figure 8a is modeled in D ID
figure 9. This circuit is described by:
β(VGS − v T )
2
E D = VDS + ID R S (27) VDS
G S ED
But VGS
2 RG RS
(28)
and
Figure 9
VGS=-IDRS (29)
From (27), (28) and (29), one reaches at:
368
− (2βv T R S − 1) ± (2βv T R S − 1)2 − 4β 2 R 2S v 2T

ID1,2 = (30)
2β R S2
and therefore:
ID1=4.95 mA (31)
ID2=1.83 mA (32)
For VGS one finds:
VGS1=-4.95 V (33)
VGS2=-1.83 V (34)
Because
VGS1<vT (35)
the right solution is ID2 and VGS2. Accordingly, VDS becomes:
VDS=ED-IDRS=20 –1.83•1=18.17 V (36)
Mutual conductance is:
2ID 2 × 1.83
gm = = ≅ 3.13mS (37)
VGS − v T − 1.83 − ( −3 )
AC analysis
The voltage gain is (in respect with (7.69)):
gm R S 3.13 × 1
Av = = ≅ 0.76 (38)
1 + gm R S 1 + 3.13 × 1
The input resistance is (from (7.73)):
R in = R G =1M Ω (39)
The output resistance is (according to (7.78)):
RS 1
Ro = = (40)
1 + g mR S 1 + 3.13 × 1
Solution 2b
DC analysis
The circuit presented in figure 8b is modeled in figure 10. The Kirchhoff
equations are:
369
I=ID+IR (41)
IR D
ED=VDS+IDRS (42) ID
K(VGS − v T )
2
ED=IRRG1+IRRG2 (43) RG1 VDS
They must be completed with the device G S ED

equation (38) VGS
2
RG2 RS
(44)
and the VGS expression: Figure 10
R G2
R G1 + R G2
variables {I, IR, ID, VDS, VGS}. For the drain current, the solutions are:
ID1=1.58 mA (46)
VGS1=8.03V (47)
VDS1=18.42V (48)
2ID 2 × 1.58
gm = = ≅ 0.26 mS (49)
VGS − v T 8.03 − ( −4 )
AC analysis
The voltage gain is (in respect with (7.69)):
gm R S 0.26 × 1
Av = = ≅ 0.21 (50)
1 + g m R S 1 + 0.26 × 1
The input resistance is:

R G1 × R G2
R in = = 500 kΩ (51)
R G1 + R G2
RS 1
Ro = = ≅ 0.79 kΩ (52)
1 + g m R S 1 + 0.26 × 1
370
SPICE solution
The circuit simulated is presented in figure 11. The DC analysis results are:
ID=1.55E-03 A; VGS=8.45E+00 V; VDS=1.85E+01 V; gm=2.49E-04 S.
The AC analysis results are presented in figure 12. This time, the frequency
range of variation for the input voltage was 10 kHz÷10 MHz
Figure 11 Figure 12
Solution 2c.
The circuit presented in figure 8c is – from the topological point of view –
identical with that presented in figure 8b. In these circumstances, the analysis
presented in section 2b may be applied in the following. The only difference is
the transistor type, and by consequence, only the values of “K” factor and “vT”
threshold voltage must be modified. The final results are:
DC analysis
The quiescent point co-ordinates are:
ID=7mA (53)
VDS=13V (54)
2ID 2×7
gm = = ≅ 200 mS (55)
VGS − v T 2.9 − 2.831
AC analysis
gm R S 200 × 1
Av = = ≅1 (56)
1 + gm R S 1 + 200 × 1
371
R G1 × R G2
R in = = 500 kΩ (57)
R G1 + R G2
The output resistance is:

RS 1
Ro = = ≅5Ω (58)
1 + g m R S 1 + 200 × 1
SPICE solution
The computed results, for the
quiescent point, are:
ID=7.10E-03 A;
VGS=2.90E+00 V;
VDS=1.29E+01 V
gm=2.09E-01 S
The voltage gain is presented in
figure 13. Figure 13
One observes the concordance between the computed results and by hand
analysis results.
resistance and output resistance for the common grill amplifier. For the circuits
presented in figure 14, find the voltage gain, the input resistance, and the output
resistance.
ED ED
C1 RD C2 C1 RG1 RD C2
Vin Vin
Vo Vo
RS RG CG RS RG2 CG
Figure 14a Figure 14b
Assume that:
For the circuit presented in Figure 14a:
RG=1 MΩ ; RS=1 k Ω ;
RD=1 k Ω ; ED=20V; C1=10µF; C2=10µF;
mA
CG=100µF; vT=-3V; β = 1.3 2 .
V
372
For the circuit presented in Figure 14b:

RG1=1 MΩ ; RG2=1 MΩ ; ED
RS=1 k Ω ; RD=1 k Ω ; C1=10µF; C1 RG1 RD C2

C2=10µF; CG=100µF; ED=20V;
-3 mA
vT=-4V; K=10 × 10 .
V2 Vin
Vo
For circuit presented in Figure 14c RS RG2 CG
RG1=1 MΩ ; RG2=1 M k Ω ; RS=1 k Ω ;

RD=1 k Ω ; C1=10µF; C2=10µF;
CG=100µF; ED=20V; vT=2.831V; Figure 14c
3 mA
K=1.54 × 10 .
V2
Note: Because the biasing circuits are identical with that presented in problem
1 only the AC analysis will be presented in the following.
Solution 3a
AC analysis
The voltage gain according to (7.103) is:
A v = g mR D =3.13 ×1 =3.13 (59)
The input resistance is (from (7.105)):

RS 1
R in = = = 242 Ω (60)
1 + g m R S 1 + 3.13 × 1

Ro=RD= 1 kΩ (61)
SPICE solution
The circuit simulated is presented in figure 15. The AC analysis results are
presented in figure 16. The frequency range of variation for the input voltage
was 10 kHz÷10 MHz
Figure 15 Figure 16
373
analysis results.
Solution 3b.
AC analysis
A v = g m R D =0.29 ×1 =0.29 (62)

RS 1
R in = = = 775 Ω (63)
1 + g m R S 1 + 0.29 × 1

Ro=RD= 1 k Ω (64)
SPICE Solution
was 10 kHz÷10 MHz
Figure 17 Figure 18
analysis results.
Solution 3c
AC analysis
A v = g m R D =205 ×1 =205 (65)
374
RS 1
R in = = = 4 .9 Ω (66)
1 + g m R S 1 + 205 × 1

Ro=RD= 1 kΩ (67)
SPICE Solution
was 0.1 kHz÷10 MHz
Figure 19 Figure 20
analysis results.
375
References
Aaron, et. al Circuits and Fields: A First Course London. Prentice Hall 1995
Bãjen Gh. Generatoare de semnal sinusoidal _ Ed. Tehnicã Buc. 1979
Bãlut L. Componente si dispozitive electronice (Electronic Components and Devices) Ed.
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Bialko, Basic Methods for Micomputer-Aided Analysis London. Prentice Hall 1995
Cogdell Foundations of Electric Circuits London. Prentice Hall 1999
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Gray P. R. Circuite integrate analogice. Analiza ºi proiectare _ Ed. Tehnicã Buc. 1983
Gray P.E Bazele electronicii moderne, vol 1 _ Ed. Tehnicã Buc 1973
Gray P.E Bazele electronicii moderne, vol 2 _ Ed. Tehnicã Buc 1973
Grove A.S Fizica si tehnologia dispozitivelor semiconductoare _ Ed. Tehnicã Buc. 1973
Huelsman Basic Circuit Theory London. Prentice Hall 1991
Irwin, et. al Basic Engineering Circuit Analysis London. Prentice Hall 1999
Johnson, et. al Basic Electric Circuit Analysis, London. Prentice Hall 1995
Johnson, et. al Electric Circuit Analysis London. Prentice Hall 1997
Thomas, et. al Analysis and Design of Linear Circuits, London. Prentice Hall 1998
Tomlinson Electrical Networks and Filters London. Prentice Hall 1991
Additional References
Diodes
Brichant, F Électronique de puissance: thyristors et diodes, cycloconvertisseurs, redresseurs,
gradateurs, onduleurs, hacheurs, etc. et leurs applications, Paris : Éditions
techniques et scientifiques
Hess, Karl Advanced theory of semiconductor devices Englewood Cliffs, N.J. : Prentice-Hall,
c1988. ISBN0130115118
Hunter, L,P, Handbook of semiconductor electronics New York : McGraw-Hill, [1970]
Linvill, J., G. Models of transistors and diodes New York : McGraw-Hill, [c1963]
Marston, R. M. Diode, transistor & FET circuits manual Oxford ; Boston : Newnes, 1991 ISBN
0750602287
Neudeck, G., The PN junction diode Reading, Mass. : Addison-Wesley, c1983
Roulston, D. J. Bipolar semiconductor devices New York : McGraw-Hill, c1990.
Traister, R., J The experimenter's guide to solid-state diodes Englewood Cliffs, N.J. : Prentice-
Hall, c1984 ISBN 0132954443
Bipolar Transistors
*** Designing with field-effect transistors New York : McGraw-Hill, c1990.

*** Discrete semiconductors. Transistors. San Diego, Calif. : D.A.T.A. Business
Pub.,c1988-
Arx, C., F. Realization and optimization of pnp transistors in a modular CBiCMOS process for
analog and smart-power applications Konstanz : Hartung-Gorre, 1996
365
Ashburn, P. Design and realization of bipolar transistors Chichester [England] ; New York :
Wiley, c1988
Chang M. F. Current trends in heterojunction bipolar transistors,. Singapore ; River Edge, NJ :
World Scientific c1996.
Çilingiroæglu Systematic analysis of bipolar and MOS transistors Boston : Artech House, c1993.
Dye, N. Radio frequency transistors : principles and practical applications Boston
Butterworth-Heinemann, c1993.
Graaff, H Compact transistor modelling for circuit design New York: Springer-Verlag, c1990.
ISBN 0387821368
Graaff, H. Compact transistor modelling for circuit design Wien : Springer-Verlag, c1990.
Gray, P. Analysis and design of analog integrated circuits New York : Wiley, c1984
Gray, P. Analysis and design of analog integrated circuits New York ; Toronto : Wiley,
c1993
Grebene, A. Bipolar and MOS analog integrated circuit design New York : J. Wiley, c1984
Greenfield, J. Practical transistors and linear integrated circuits New York : Wiley, c1988.
Hess, K. Advanced theory of semiconductor devices Englewood Cliffs, N.J. : Prentice-Hall,
c1988
Liu, William Handbook of III-V heterojunction bipolar transistors New York : Wiley, c1998
Marston, R. M Diode, transistor & FET circuits manual Oxford ; Boston : Newnes, 1991 ISBN
0750602287
Mounic, M. Transistors, problemes avec solutions, du debutant au technicien superieur Paris,
Foucher, 1967-
Neudeck, G. The bipolar junction transistor, Reading, Mass. : Addison-Wesley, c1983
Ryter, Roland Analysis and development of high voltage bipolar transistors for BiCMOS smart
power applications Konstanz : Hartung-Gorre,, 1996
Sanborn, P. Fundamentals of transistors Garden City, N.Y., Doubleday [1970]
Schroder, D. Advanced MOS devices, Reading, Mass. : Addison-Wesley Pub. Co., c1987
Towers, T. D Towers' International transistor selector Blue Ridge Summit, Pa. : TAB Books,
1982 ISBN 0830614168
Warner, R. M. Transistors : fundamentals for the integrated-circuit engineer Malabar, Fla. : R.E.
Krieger Pub. Co., 1990
Field Effect Transistors
Baker, R. J. CMOS circuit design, layout, and simulation 1998 New York : IEEE Press, c1998
Foty, D. MOSFET modeling with SPICE1997 Upper Saddle River, NJ : Prentice Hall PTR,
c1997
Kano, Kanaan Semiconductor devices 1998 Upper Saddle River, N.J. : Prentice Hall, c1998
Liou, J., Analysis and design of MOSFETs, 1998 Boston, MA : Kluwer Academic
Publishers, c1998
Pierret, R. F Field effect devices1983 Reading, MA : Addison-Wesley, c1983
Tsividis, Y. Operation and modeling of the MOS transistor, 1998 Boston : WCB/McGraw-Hill,
c1999
Warner, R. M. MOSFET theory and design 1998 New York : Oxford University Press, 1998
Warner, R. M. Transistors, 1983 New York : Wiley, c1983.
Frequency Response
Carmona, R Practical time-frequency analysis1998 San Diego : Academic Press, 1998

Cohen, Leon. Time-frequency analysis1995 Englewood Cliffs, N.J : Prentice Hall PTR, c1995
Qian, Shie, Joint time-frequency analysis1996 Upper Saddle River, N.J. : PTR Prentice Hall,
c1996.
Tolimieri, R. Time-frequency representations1997 Boston : Birkhauser Boston, 1998
366
References
Useful Sites
http://www.americammicrosemi.com/tutorials/fet.h
http://www.americammicrosemi.com/tutorials/ECG_NTE_SK.HT
http://jamaica.ee.pitt.edu/steve/
http://ece-www.colorado.edu/~ecen4228/n1/node11.html
http://ece-www.colorado.edu/~ecen5355
http://ece-www.colorado.edu/~bart/book/
http://www.macs.ece.mcgill.ca/~roberts/C...ourse/IC_Components_Ccts_HTML
http://nina.ecse.rpi.edu/shur/advanced/Notes/Noteshtm/cmos10
http://nina.ecse.rpi.edu/shur/Ch5
http://www.seas.upenn.edu/~jan/spice/spice.MOSparamlist.html
http://www.seas.upenn.edu/~jan/spice/spice.overview.html
http://bach.ece.jhu.edu/~gert/courses/348/lab4.html
http://pneuma.phys.alberta.ca/~gingrich/phys395/notes/
http://spingot.anu.edu.au/people/mat/engn2211/notes/fetnode1.html
http://froggy.eng.umd.edu/man/
http://froggy.eng.umd.edu/~bassel/man/
http://www-classes.usc.edu/engr/bme/3021/classmat/bastran/
http://www.st-and.ac.uk/~www-pa/Scots_Gu...o/comp/active/jfet/jfetchar/jfetchat.htm
http://www.tcad.ee.ufl.edu/~law/3396
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1. The Fundamental Equations of The Semiconductor Theory 1

3. Circuit Applications of P-N Diodes 63

3.1. By Hand Large-Signal Analysis 64

4. Bipolar Junction Transistor 115

4.1. Preliminary 116

5. The Fundamental Bipolar Transistor Circuits 197

5.1. The Common Emitter Connection 198

6. The Field Effect Transistors 253

6.1. Preliminary 254

7. The Fundamental Field Effect Transistor Circuits 323

7.1. The Common Source Connection 324

Generally, three steps must be followed in the electronic circuit analysis:

Three Terminals Device; only two "characteristics equations" are needed in

and for linear resistors:

The semiconductors are usually defined as materials whose conductibility is

electrons. So, each atom of silicon is bounded by four neighboring electrons

Extra Positiv Ion Positiv Ion

One can observe that:

1.1.3. Energy Bands Representation. Carriers Concentration

One can observe:

F(E) conduction band

The concentration of the mobile carriers in an extrinsic semiconductor.

At room temperature, all atoms of impurities are ionized. By consequence, the

P-type semiconductor In this case the impurities concentrations must respect

1.2 The Fundamental Equations of The

The central problem of the semiconductor theory is to determine the current

hole generation – an electron jumps from valence band to

where V (electric potential) is defined by:

h Plank constant “h”, divided by π

= 102 cm−3 (4)

Problem 6 This problem is regarding the current equations. The hole

Replacing (9) in (8) one obtains:

Figure 2 shows this solution.

Replacing (9) in (11):

Replacing (12) in (13) one finds:

This section treats:

3. Methods of mathematical description related to the regime of

Figure 2.2 shows the electrical symbol of a diode,

In fact, this built-in voltage is the key of

 the equilibrium condition is also disturbed;

where: θ1, K , θp are non-electric parameters.

Related to the regime of operation this equation will be simplified as follows:

1. large-signal quasi-static regime; equation (2.1) becomes:

2.2 Quasi-Static Large-Signal Behavior

“I-V” characteristic related to (2.4) equation will be developed in this section. It

5. "I-V" characteristic. SPICE model.

Fermi level is constant at

Poisson equation Boundary conditions

Long diode approximation Limits of space charge region

Diffusion equations Boundary conditions

Distribution of minority carriers Current equations

Minority diffusion current at

According to “full depletion approximation”, the generation-recombination

diffusion hole current

generation-recombination diffusion electron current

The total current will be the sum of these two components.

Usually one chooses

These equations are usually named diffusion equations.

Introducing (2.41) and (2.42) in(2.43) the expression of holes distribution in n-

n(x ≤ -lp) p(x ≥ ln)

4. The Minority Carrier Current

2. The calculation of mobile charge carrier densities at these points, pn(l n)

The boundary conditions are:

the equilibrium condition is also disturbed;

step recovery diodes

the net doping density ND − NA is he same in the p-type and n-type

if current is grater than zero the hypothesis was right