Cpi Indico IQ Drawings

GENERATOR INDICO IQ
Service Manual - Drawings
GE P/N: 5792129-1EN
NOTES:
HAZARDOUS AND LETHAL NOT INSTALLED ON 50 kW UNITS, AC MAINS GOES DIRECTLY TO THE IDB BOARD
FANS VOLTAGES EXIST INSIDE ** EITHER DSS OR LSS BUT NOT BOTH CAN BE INSTALLED DEPENDING ON CUSTOMER REQUIREMENT
903916-00 THE GENERATOR UNIT INV 3 AND FANS 3 & 4 ARE NOT INSTALLED FOR 50 / 65 kW UNITS OPERATOR CONTROL CONSOLE
***
{
THE LSS/DSS BOARD NO. AND LSS/DSS ASSEMBLY NO. ARE NOT THE SAME. SHIFT CAPACITORS
TO LSS & LSS
TRANSFORMER ** WARNING EVEN IF POWER IS OFF! **** *
DETERMINE THE LSS/DSS ASSEMBLY NUMBERS. SEE CHAP. 2 & 8 OF THE SERVICE MANUAL.
+24VDC
1 3*** 5
c
{
19” Touchscreen
I
15.6” I II III
FOR INV 1&2 FOR INV 3 FOR RES TOUCHSCREEN console mAs mA/ms
-
-
+
+
-
-
+
- +
ASSY AUX
2 4*** J9 J24 J21 J23

INTERNAL CANBUS: LVLE INTERNAL CANBUS: LVLE WARNING
THIS X-RAY UNIT MAY BE DANGEROUS TO
SCHEDULES ARE OBSERVED.

PATIENT AND
SAFE EXPOSURE FACTORS, OPERATING INSTRUCTIONS OPERATOR UNLESS
AND MAINTENANCE
c intel
Atom INSIDE
J12 R/F console

J3 POWER: +5VDC, +12VDC, +/-35VDC, +/-24VDC, /ON/OFF, SYNC 904555-00
903915-00 J8
FANS: 7-12VDC Console Connector Brd REMOTE FLUORO
J2 USB
2.0
CAN 2
ETHERNET
COMM 2 DAP 2 MINI CONSOLE
RIOB TRANSFORMER PRIMARY: 400/480VAC
CAN 1 COMM 1 DAP 1 R&F CONSOLE
AC MAINS
400-480VAC { MEZZANINE
BOARD* J22
TUBE SELECT (2 TUBE OPTION): +130VDC/+35 VDC J23
+/-12VDC
J4 J1
26VAC, 18VAC
ROOM I/O
904731-00
ACB
904133-00 J2 XFRMR
TO CONTACTOR COIL: APPROX. 8-24 VDC
+/-35VDC RIOB ROOM
110VAC, 220VAC
INTERNAL CANBUS: 3.3VDC 738234-00
J6 J11 J5 738213-00 POWER
E4 TO ADR TANK +/-24VDC
THERMAL SWITCH: LVLE
J7 RIOB CONTROL: +24V, +15V, +5V
J3 J6 CUSTOMER
E5 J11 A1 EQUIPMENT
ABS INPUT
J1/J6
!
CONSULT THE SERVICE
J1 AMBIENT
MANUAL FOR DEVICES OR
GCB/CPU
400-480VAC
EQUIPMENT THAT CAN

E7 IDB
AC MAINS
J7 TEMP E1 BE ATTACHED HERE.

SENSOR
904728-00 (50 kW) 904498-00 / 904495-00
{
901531-01 TO CONTACTOR COIL: APPROX. 8-24 VDC 739389-xx
TEMPERATURE SENSORS: +12VDC

904728-02 (65/80/100 kW)
J13 737998-xx
J24 AEC CONTROL: +/-12VDC, +/-24VDC AEC 737992-xx
J5 J25 J10
STATOR
(OPTIONAL) 734654-xx
INV 1
}
+/-12VDC
480VAC
24VDC
TERMINAL SIGNAL INVERTER GATE DRIVE: 734614-xx

BLOCK INV 2 J8
INV3***
120-400 VAC
{
733947-xx
CONT. 733752-xx
CONTACTOR
J1 J2
COIL TO TUBE1 735921-xx
& TUBE 2
J25
DIGITAL I/O CONTROL: +24V, +15V, +5V DIGITAL I/O 903121-xx
RECTIFIER STATOR
(OPTIONAL) 736894-xx
BOARD 738249-01 INV 1 738947-xx
E17
DC BUSS
E16 INVERTER FEEDBACK: LVLE
INV 2
INV3***
J10 } FILAMENT POWER: +/-12VDC, +/-35VDC
738114-xx
902724-xx
E9 E6 E4 E5 E15 J30
TB2 TB3 J4 J5
DC BUSS +
FILAMENT CONTROL: +/-12VDC

560/680VDC
DC BUSS -
E12 DSS** J8
LSS 2/ DSS 2 PWR
J5 J28
903132-03 CAN
PW10-24K-5
E11 INTFC **** J1 DSS CONTROL & PWR: +12VDC
J2 J29
FILAMENT POWER: +/-12VDC, +/-35VDC
DC BUSS -
- - - --- -
E10
- - - --- -
NTION DANGEROUS
VOLTAGE
560/680VDC FILAMENT CONTROL: +/-12VDC

E9
RESONANCE FEEDBACK: LVLE J26
J20
DC BUSS + LSS**
(OPTIONAL) E6,E7,E8
E14,15 HV UNIT FEEDBACK: LVLE
J22 J2 J1 J2 J1
DSS 2 ASSY:
DC BUSS
LSS 2 ASSY:
904925-xx
905135-XX
CAPS ASSY 901531-01 FILAMENT FILAMENT

(80/100 kW only) TEMP J1
903955-00 (100 kW)
E1 E2
SENSOR E1 SHIFT
BOARD BOARD
903955-01 (80 kW) 905111-xx (INV 1 only) CAPACITORS**** (Large or (Small)
FILAMENT DRIVE: LVLE
INVERTER J5
J3
J4
Universal)
731405-02
ASSEMBLY*** J1 731405-01, -00
50 kW (2 INV) -01 HV MODULE T1
80 kW (3 INV) -01 (A-K) J5 J5
1 TUBE: 900786
65 kW (2 INV) -00 J2
100 kW (-37) FROM STATOR
100kW (3 INV) -00 T2
80 kW (-38) (A-K) 2 TUBE: 902607 TERMINAL
BLOCK
E4 E3 65 kW (-35) 100 kW (-03)
50 kW (-36) 80 kW (-02)
E10
65 kW (-01)
+
E9 50 kW (-00) HV Cables -TUBE 1 +
CONT. COIL Lid Ground

CHASSIS Studs (x3)
GROUND CONT. COIL TUBE HOUSING GROUND (should be connected) X-RAY TUBES
INV 3 see compatibility table
903254-xx WHT
-00 (50 kW)
HV Cables - TUBE 2 +
-01 (65 kW) FDBK RESONANCE FEEDBACK: LVLE (OPTIONAL)
+
TO PROTECTIVE -02 (80/100 kW) 1 PER

INVERTER
EARTH GROUND RESONANT BLK
ASSEMBLY DRAWN DATE
WHEN REPLACING PARTS, USE EXACTLY SYSTEM
!
B. ZUEST/J. LAPE 21 FEB 2013
THE SAME TAB NUMBER. TAB -xx VARIES
CHECKED
INTERCONNECT
DEPENDING ON DEVICES AND EQUIPMENT DIAGRAM (Indico IQ TM )
INSTALLED. CHECK YOUR GENERATOR
CONFIGURATION AND SERVICE MANUAL. DES.\MFG.\AUTH.
Use and disclosure is subject to the restrictions on the title page of this CPI document.
L. FOSKIN
MD-0974 REV B
SHEET 1 OF 2
CONTROL CONSOLE
CONNECTIONS;
ONLY ONE CONSOLE
{ J9 R&F CONSOLE
J9 (RAD CONSOLE)
c
R/F
CONSOLE HAND SWITCH (J13)
TO X-RAY EXPOSURE SWITCH
TO BE USED AT A TIME
J3 MINI CONSOLE
I
MINI CONSOLE
R&F CONSOLE
I II III
- + - +
CONSOLE (J5) TO GENERATOR
CONSOLE CONNECTION
mAs mA/ms - + - +
- +
J4 REM FLUORO CONTROLLER - + - +
TABLE SIDE FLUORO CONTROLLER AUX
REMOTE FLUORO
RS232 (J2)
TO DAP CHAMBER 1
J2 DAP CH1 CCB SERIAL COMM PORT
CPI touchscreen
J1 DAP CH2
DAP 1
TO DAP CHAMBER 2
DAP 2
MEMBRANE CONSOLE CONNECTIONS
J5 RS232 1
SERIAL COMM PORT 1 CPU/GCB
COMM 1
COMM 2
ASSEMBLY
SERIAL COMM PORT 2 J8 RS232 2
USB
2.0
ETHERNET
SOFTWARE UPGRADE ONLY, NOT J2 USB
CONNECTED WHEN GENERATOR IS IN USE
TOUCHSCREEN
CAN 2
CAN 1
ETHERNET CONNECTION / J1 ETHERNET CONSOLE
GENERATOR CONFIGURATION
J7 CANBUS 2
CANBUS PORT 2
USB DEVICE PORT (USB B)
J6 CANBUS 1
19” Touchscreen USB PORT
CANBUS PORT 1
Console ETHERNET (ETH)
TO CONFIGURATION PC
c intel
Atom
USB HOST (USB A)

INDICO IQ GENERATOR CONNECTIONS
INSIDE
THIS X-RAY UNIT MAY BE DANGEROUS TO PATIENT

AND
WARNING SAFE EXPOSURE FACTORS, OPERATING INSTRUCTIONSOPERATOR UNLESS
SCHEDULES ARE OBSERVED. AND MAINTENANCE
USB PORT
USB HOST (USB A)

USB PORT
15.6”
Touchscreen RS232 (COMM 1)
SERIAL PORT COMM 1
Console
!
REFER TO THE SERVICE MANUAL FOR
EQUIPMENT OR DEVICES THAT CAN BE
CONNECTED TO THESE PORTS.
TOUCH SCREEN CONSOLE CONNECTIONS
DRAWN DATE
SYSTEM
B. ZUEST/J. LAPE 21 FEB 2013
CHECKED
INTERCONNECT
DIAGRAM (Indico IQ TM )
DES.\MFG.\AUTH.
L. FOSKIN
MD-0974 REV B
SHEET 2 OF 2
E7
PHASES
A
F10
E5
K1
A D7
~ + C10 C12 C14

E6
R21
R20
E18 560 / 680 VDC 560 / 680 VDC
3 PHASE F15 E7 B TO DUAL-SPEED DC BUS TO INVERTER
B DS1
E19 OUT
AC MAINS C11 C13 C15 STARTER BOARD(S)
MD-0983 MD-0980 PG 2
~
INPUT F16 DS2
C E4 C E9
L4 L1
- L2
R23
R24
R30
R25
~
R10 E8
DISCRETE
+ 1 4
LS1
~
R9 DIODE U1
R31
R26
BRIDGE
K3 2 3 DC BUS
~
F11 R11 D1 TO D6 DISCHARGE
- CIRCUIT
F1
F12 DS3 (Q1, D8, D9, BUZZER R27

E11 / E15 F1, ETC) DRIVER CIRCUIT
(Q2, Q3, R33,
COIL OF K3 +12V R35, R36, ETC) R32
R38
R39
R1
R2
SHOWN ON R14
E10 / E14
PAGE 7
1 3
J25-6 J1-6 DS4
R29
E12 / E16 U2
2 4 1 3
J25-1 J1-1
U4
AC MAINS TO
MISC EQUIPMENT. +12V
2 4
REFER TO SEPARATE 400/480 VAC
SUPPLEMENT IN TO PG 3 RECTIFIER BOARD
THIS MANUAL (IF INTERLOCK
APPLICABLE)
RECTIFIER BOARD J2-3 J2-2 J2-1 J2-4 J2-7 J2-5
ROOM POWER TRANSFORMER

K2 J10-3 J10-2 J10-1 J10-4 J10-6 J10-5
F7 J21-7 240V 220V
K1 +12V
J21-5 200V 110V 110/220 VAC
WINDINGS
OPTIONAL
COILS OF K1, K2 SHOWN ON PG 4
J21-1 0V 0V
J18-33
26V TO MD-0977
K2 PG 2
J23-7 J18-31
240V
TO J5 AUXILIARY
K1 19V J18-29
J23-5 CPU BOARD (PG 6)
200V
0V J18-32
J16-2
F6 J23-1 0V 19V FROM J4 AUXILIARY
+5V
HOLD
F13 J24-1
R107 +24V +12V
J24-5
DS1 MAINS
NOT USED AT CONTACTOR PULL
F14 J24-4 THIS TIME
J24-8
J5-1
DRIVER CIRCUIT K1
FOR K1 D5
(U10, Q15, Q17,R10, R11, R18,
J5-2
C52, C49, etc.)
(ON RECTIFIER
BOARD)
INPUT DISTRIBUTION BOARD, 400-480 VAC 3 PHASE (50 KW)
400-480 VAC 3-PHASE 50 KW GENERATOR

DRAWN DATE
G. SANWALD/J. LAPE 22 MAR 2013 DC BUS & POWER
CHECKED DISTRIBUTION
DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 1 OF 8
INPUT FUSE MEZZANINE BOARD E7
PHASES
A
F1
E5
K1
A D7
~ + C10 C12 C14

E10
E6
R21
R20
E18 560 / 680 VDC 560 / 680 VDC
3 PHASE AC F2 E7 B TO DUAL-SPEED DC BUS TO INVERTER
DS1 100 kW UNITS
B E19 STARTER
MAINS INPUT C11 C13 C15 ONLY OUT BOARD(S)
MD-0983 MD-0980 PG 2
~
C F3 E11
E4 C DS2 E9
L4 L1
- L2
R23
R24
R30
R25
~
R10 E8
DISCRETE
+ 1 4
E17 / E11 LS1
~
R9 DIODE U1
R31
R26
E19 / E12 BRIDGE
2 3 DC BUS
~
E18 / E10 R11 D1 TO D6 DISCHARGE
- CIRCUIT
F1
DS3 (Q1, D8, D9, BUZZER R27
AC MAINS TO F1, ETC) DRIVER CIRCUIT
E5 E7 E4 COIL OF K3
MISC EQUIPMENT. (Q2, Q3, R33,
SHOWN ON +12V R35, R36, ETC) R32
R38
R39
R1
R2
REFER TO SEPARATE PAGE 7 R14
SUPPLEMENT IN
THIS MANUAL (IF K3 1 3
F11 J25-6 J1-6 DS4
APPLICABLE)
R29
U2
2 4 1 3
F12 J25-1 J1-1
U4
+12V
2 4
RECTIFIER BOARD
INTERLOCK
400/480 VAC
TO PG 3
RECTIFIER BOARD J2-3 J2-2 J2-1 J2-4 J2-7 J2-5
ROOM POWER TRANSFORMER

K2 J10-3 J10-2 J10-1 J10-4 J10-6 J10-5
F7 J21-7 240V 220V
K1 +12V
J21-5 200V 110V 110/220 VAC
WINDINGS
OPTIONAL
COILS OF K1, K2 SHOWN ON PG 4
J21-1 0V 0V
J18-33
26V TO MD-0977
K2 PG 2
J23-7 J18-31
240V
TO J5 AUXILIARY
K1 19V J18-29
200V
0V J18-32
J16-2
F6 J23-1 0V 19V FROM J4 AUXILIARY
+5V
HOLD
F13 J24-1
R107 +24V +12V
J24-5
DS1 MAINS
NOT USED AT CONTACTOR PULL
F14 J24-4 THIS TIME
J24-8
J5-1
DRIVER CIRCUIT K1
FOR K1 D5
(U10, Q15, Q17,R10, R11, R18,
J5-2
C52, C49, etc.)
(ON RECTIFIER
BOARD)
INPUT DISTRIBUTION BOARD, 400-480 VAC 3 PHASE (65, 80 & 100 KW)
400-480 VAC 3-PHASE 65, 80 & 100 KW GENERATORS

DRAWN DATE
DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 2 OF 8
TP4 +12V
+12V
L2A J8-10
D11
L2B J8-20
J8-2
D12
C7
J8-4
J8-5
R47
~
F9 R53
SWITCHING CIRCUIT
+ C27 T1C T1D TP3
J8-6
DISCRETE +24V +24V
Q10
400/480 VAC F8
~ DIODE DS3
R37
FROM PG 1, 2 BRIDGE DC BUS L2C J8-11
INCLUDES Vgate T2
D45-D50 L3 J8-12
~
F5 R50
D13
- T1A
R22
J8-13
C10 TO J23 GENERATOR
T1E CONTROL BOARD
Q5 (PG 7)
F3 TP2
R33
T3 Q6 Q9 +35V
+35V
C14
F1
D26 L2D J8-3
U3 T1F
R30
F2 D27 C6
F4 TP6
-35V
D23
R65 R66 T1G C8
D24 J8-9
TP9 L2E
+24V STANDBY -35V
PS L2F J8-14
R67
D38
D53
~ DISCRETE DIODE
BRIDGE
+
TP1 T1H D25 C11
R70 R71 ~ D33, 36, 40, 41 - 0V RTN TP5

-24V
-24V
J15-2
TP7 T1B J15-1
LINE FREQ
R72
COUNT
D55 J15-7
J15-8
J15-4
R76 R77 U5
J15-5
ZERO-CROSS J15-3
DETECTOR
TO J7 AUXILIARY
R79
J15-9
D58
J15-10
D1 J15-11
J15-15
U1
J15-14
-12V
REGULATOR J15-16
-24V
J8-1
TO J23 GENERATOR
D2 J8-17
CONTROL BOARD
(PG 7)
D4 J16-33
+24V
J16-35
18 VDC @ 400VAC -12V +24VSB TO J4 AUXILIARY
22 VDC @ 480VAC J16-36 CPU BOARD (PG 5)
(With respect to ground) J16-37
TP15 TP16 TP17
PH-V1 PH-V2 PH-V3
J18-5
DRAWN DATE
J18-24 22 MAR 2013
TO J5 AUXILIARY
G. SANWALD/J. LAPE DC BUS & POWER
J18-4 CHECKED
CPU BOARD (PG 6) DISTRIBUTION
J18-2
INPUT DISTRIBUTION BOARD (400-480 VAC) DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
400-480 VAC GENERATORS Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 3 OF 8
J14 PINS 1 AND 2 SHOULD BE CONNECTED TO A
NORMALLY CLOSED (EPO) SWITCH DURING NORMAL
+24VSB +12V
OPERATION. J14 PINS 3 AND 4 CAN PROVIDE POWER
TO THE POWER DISTRIBUTION RELAY OR TO AN J16-30
J14-1
ILLUMINATED SWITCH THAT REQUIRES 24V. +24V
J14-2 J16-32
EMERGENCY POWER- +35V
OFF SWITCH AND POWER J14-3 +24V J16-24
DISTRIBUTION RELAY * IN THE POSITION “ON W/GENERATOR”, 24 VDC, 26 VAC AND J16-7
J14-4 110 / 220 VAC IS ONLY AVAILABLE ON THE ROOM INTERFACE
BOARD WHEN THE GENERATOR IS SWITCHED ON. IN THE J16-11
POSITION “ON ALWAYS”, 24 VDC, 26 VAC AND 110 / 220 VAC +12V +12VSB +12V
+5V IS AVAILABLE AT ALL TIMES THAT THE GENERATOR IS J16-5
JW2 *1 JW1 ** 1
CONNECTED TO LIVE AC MAINS.
FROM J23-15 GENERATOR J8-15 HIGH CAP 2 -35V
ON W/GENERATOR 2 J16-12
CONTROL BOARD (PG 7) TP14 -24V J16-13
+130V ON ALWAYS 3 LOW CAP 3
+130V
J4-1 BOOST J16-14 TO J4 AUXILIARY
CPU BOARD (PG 5)
FROM J8 AUXILIARY J4-2
CPU BOARD (PG 5) ** JW1 SETS THE DC BUS CHARGING TIME.
J4-3
400-480 V 100 KW UNITS AND 1 PHASE
J4-4 208-230 V UNITS MUST USE THE POSITION J16-34
+12V
“HIGH CAP”, ALL OTHER UNITS MUST USE
THE POSITION “LOW CAP”.
+12VSB J16-29
J18-6 400-480 V GENERATORS CONNECTED

TO + 12V, 208-230 V GENERATORS
CONNECTED TO GROUND
+3.3V
J16-38
J18-28
J18-9
J18-10
FROM J5 AUXILIARY J18-3
CPU BOARD (PG 5) J18-19 TO J5 AUXILIARY
J18-20 J18-8 CPU BOARD (PG 5)
J18-22
J18-37
J18-38
J18-40
FROM J23-16 GENERATOR J8-16

CONTROL BOARD
(MD-0976)
J16-9
K2
D44
J16-10
FROM J4 AUXILIARY
CPU BOARD (PG 5) J16-8
K1 CONTACTS OF K1-K3
D43 SHOWN ON PAGES 1-4
J16-6
+12V
R68
K3
D59 DS5
SOFT
FROM J5 AUXILIARY J18-1 START
CPU BOARD (PG 5)
INPUT DISTRIBUTION BOARD
DRAWN DATE
DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 4 OF 8
+130V J8-1
+12V
J8-2 TO J4 INPUT
* TP19 WILL NORMALLY READ 0V. THIS WILL SWITCH TO +10 V SHOULD ONE J8-3 DISTRIBUTION
OR MORE OF THE FOLLOWING OUTPUTS FROM THE SWITCHING REGULATOR ON BOARD (PG 4)
R89
U25 PAGES 5 & 6 BE LOST: +12 V, +24 V, +35 V, -24 V, OR -35 V DC. J8-4
D59 Q18 CROWBAR
J7-2 PWM Q8, Q9 +12VSB
REGULATOR
DS17 J5-6
U21 DS16
CURRENT LIMIT CIRCUIT D28 +24VSB +12V +24V +35V -24V -35V
INCLUDES Q17, Q18, U26 +3.3V
D58 U6
J5-28
+12V
J7-1 TP19
UNDER J5-9
J7-14
+12 V OVER- VOLTAGE +10V
DETECT J5-10
J7-15 U12 VOLTAGE
DETECT TO J18 INPUT
UNDER-VOLTAGE DETECTION J5-19
J7-3 +24VSB Q3 DISTRIBUTION
FROM J15 INPUT CIRCUIT FOR +12V, +24V, +35V, BOARD (PG 4)
C17 J5-20
DISTRIBUTION J7-6 U3 D26 -24V, AND -35V SUPPLIES
BOARD (PG 3 ) J5-22
J7-9 DS15
J5-37
J7-10
+12V +24V J5-38
J7-11
U4
J5-40
J7-7
J7-8 DC BUS READY +24VSB
J7-4 LOGIC
U7
Q1
J7-5
R17
R14
COMPARATOR / LOGIC
J7-16 “OR” / RELAY Q16
DRIVER CIRCUITS
(U14, 16, 17, 19, 22, J4-8
Q13-Q16, ETC) J4-6
D7 Q14
J4-34
J4-38 Q15 TO J16 INPUT
DISTRIBUTION
R194
BOARD (PG 4)
J4-29
Q13 J4-9
AUXILIARY CPU
J4-32 BOARD INTERLOCK R165 J4-10
R149
R164
TP21
+12V +12V
+24V
FROM J16 INPUT J4-30 +12V TP27
DISTRIBUTION U5 +3.3V
+35V U27 MAINS CON
BOARD (PG 4) J4-24 R23 TP16 +3.3V PULL IN
+5V +5VSB
J4-7 +3V3 (SEE NOTE) J4-3
U1 REGULATOR 1 Hz
R16
R15 +3.3V pulses
J4-11 +12V +12V
R171
REGULATOR TP18
J4-5 HEARTBEAT +12V
R12
R13
J4-12 DS1
-35V HEART
+3.3V Q7 TO J16 INPUT
J4-13 +35V
-24V +24VSB +12VSB BEAT DS13 DS14 DISTRIBUTION
J4-14 TP17 TP20 TP22 TP30 BOARD (PG 1-2)
R86
R46
GND GND GND MAIN SS
R55
+12V SWITCHING MICRO
REGULATOR U10 CON REL
CONTROLLER HLD
(U13, L1, D31, ETC) R47
R56
R169 J4-2
+24VSB TP23
R44, 45, 193

BOOST DR +12V
DRIVER
J4-33 +35 +130V
TO J18 INPUT
R57
FROM J16 INPUT J4-35 J5-1
+130V SWITCHING DISTRIBUTION
DISTRIBUTION J4-36 REGULATOR BOARD (PG 4)
BOARD (PG 3) (U9, Q5, L2, D18, 30,
J4-37 D36, ETC) -35V NOTE: TP27 WILL NORMALLY BE HIGH +12V. IT WILL PULSE LOW FOR
APPROXIMATELY 100 MS IN ORDER TO BRIEFLY TURN ON Q7 (AUXILIARY
J5-8 CPU BOARD) & Q3 ON THE I/P DISTRIBUTION BOARD WHEN THE MAIN
FROM J18 INPUT CONTACTOR IS TO CLOSE.
DISTRIBUTION J5-3 R26
BOARD (PG 4)
AUXILIARY CPU BOARD
DRAWN DATE
DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 5 OF 8
+3.3V
+3.3V
R4
DS5
RECT U5
R30
ITLK
U2
J5-33
DRIVER
R58
R59
J5-32
FROM J18 INPUT TP29 2V @ 680 VDC BUS (480 VAC MAINS)
DISTRIBUTION DC BUS SENSE 1.6V @ 560 VDC BUS (400 VAC MAINS)
BOARD (PG 1-2) R117 0.95V @ 320 VDC BUS (230 VAC MAINS)
J5-31 R140
R126
R127
R147
+
R141 U20B
J5-29
R137
R108
- R79
J5-24 R182 R87
+
U11A MICRO CAN DATA LINK

CONTROLLER REFER TO
R94 MD-0990
- R83
J5-4 R166 R88
+
U11B
FROM J18 INPUT R95
DISTRIBUTION
BOARD (PG 3) - R138
J5-2 R150 R142
+
U20A
TP31 R148
-12V
J5-5
-12V
AUXILIARY CPU BOARD
DRAWN DATE
DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 6 OF 8
TP48
+12V +12V
+5V TP49 +3.3V TP28 +5V
+5V +3.3V
J23-10 J23-15 TO J8-15 INPUT
DISTRIBUTION
J23-20 BOARD (PG 4)
TP45
-15VA +24VSB
+35V -15V SWITCHING
J32-80 J32-75 J32-76 J32-77 J32-78 J32-71 J32-72 J32-29 J32-19 J31-19
REGULATOR
J23-3 TP46 +24V
+24V (U142, D17, L10, ETC)
+35V
TP6 +35V
-15V_A J14-80 J14-75 J14-76 J14-77 J14-78 J14-71 J14-72 J14-29 J14-19 J11-19
J23-11 +12V J29-1 J1-1 F2 +12V
J23-12
DS5 TP11
J23-13 -12V J29-3 J1-4
+24V TO
-12V SWITCHING INTERNAL +5V +2.5V
R273
REGULATOR CIRCUITS +5V J29-6 J1-3
J23-14 U12
+5V SWITCHING
J23-9 (U13, D18, L1, ETC) REGULATOR +2.5V J29-4 J1-2 F1
J32-69 J14-69 REGULATOR
R274
-12V
-24V (U14, Q1,Q4, L3, ETC) -12V
FROM J8 INPUT -12V J29-2 J1-5
TP7 -35V
DISTRIBUTION -35V +3.0V -35V TP2
BOARD (PG 3) -12V +5V J29-5 J1-6
TP44 +15V_A U2
+3.3V
TP6 TP9 TP15 TP26 TP41 +15VA +3.0V
GND GND GND GND GND +15V SWITCHING +3.3V SWITCHING REGULATOR FILAMENT BOARD
J23-2 REGULATOR REGULATOR
+12V
J23-4 (U93, Q21, Q23, L9, ETC) +5V +1.2V
(U13, Q2, Q3, L4, ETC)
J23-5 U40
J23-6 +1.2V +35V
+15V_DAP REGULATOR TP6 +35V
TP12 +1.0V +1.2V_PHY
+5V +3.3V
+15V DAP U11 +12V J30-1 J1-1 F2
U34 +12V
+15V SWITCHING
+1.0V +1.2V
REGULATOR J30-3 J1-4
TP47 REGULATOR REGULATOR
+24VSB
+24VSB (U21, Q6, Q7, L5, ETC)
J30-6 J1-3
J23-17 U95
5V - 3.3V +5V +1.8V J30-4 J1-2 F1
J23-1 R261 R549 J32-20 J14-20 -12V
U39
TO FPGA U53 -12V
+1.8V +5V J30-2 J1-5
REGULATOR TP7 -35V
-35V TP2
+24V +15V_A +15V_DAP +12V J30-5 J1-6
Q9
R151
R135
R137
FILAMENT BOARD
R122
+12V_ISOL +5V_ISOL +12V_ISOL

+12V INDICO 200 X-RAY GENERATORS
R123
DS19 USE ONE OR TWO FILAMENT

12V TO +/-12V
R152
R136
R138
PNG
CONVERTER +5V_ISOL, SUPPLY BOARDS
U50 U26 +12V_ISOL &
-12V_ISOL DS14
DETECTOR
R124
-12V_ISOL CIRCUIT ISOL PG
A/D J31-46 J11-46

TO FPGA U53 TP9 +3.3V
CONVERTER -12V_ISOL
TP GND
Vref
+5V_ISOL
+12V +5V +5V
DS16
12V TO +5V HEARTBEAT +15V_A +15V_A
R156
R154
CONVERTER
R139
J31-2 J11-2
- +24V J3-11 J6-11 +24V_INT
U68 FROM
+ B1 Q5 J3-13 J6-13
CPU
U57 J3-17 J6-17
J3-15 J6-15
R153
R155
R140
CPU BOARD J3-9 J6-9

J3-21 J6-21
-15V_A -15V_A
R141
-15V_A -12V J3-23 J6-23
ROOM I/O BOARD

-24V
DRAWN DATE
GENERATOR CONTROL BOARD
Use and disclosure is subject to the restrictions on the title page of this CPI document. DES.\MFG.\AUTH.
L. FOSKIN
MD-0975 REV C
SHEET 7 OF 8
+5V
+3.3V
TP8
+24V TP7 +1.2V
J4-2 J13-2 J9-13 J5-13 + 5V, + 3.3V, +1.2V TP12
AND - 15V
J4-20 J13-20 J9-15 J5-15 F1 POWER SUPPLY TP2
F1
CIRCUITS
(U9, U10, U11,
D1-D6, L1, ETC.)
J4-10 J13-10 J9-14 J5-14
TP11 TP10
J4-11 J13-11
-15V R&F MEMBRANE CONSOLE
+5V
300 VAC J10-1

BACKLIGHT FLUORESCENT LAMP
POWER SUPPLY J10-4
GENERATOR CONTROL BOARD CONSOLE CONNECTOR BOARD (Q2, Q3, T1,
C61, ETC.)
CONSOLE BOARD (R&F MEMBRANE CONSOLE) LCD DISPLAY ASSEMBLY

R&F MEMBRANE CONSOLE
STARQ TM
TOUCHSCREEN CONSOLE
19 VDC
STARQTM
USE WITH SUPPLIED
IEC 60601
APPROVED
TOUCHSCREEN CONSOLE
AC ADAPTOR ONLY
POWER
SUPPLY
100-240VAC
TOUCHSCREEN CONSOLE
DRAWN DATE
L. FOSKIN
MD-0975 REV C
SHEET 8 OF 8
X-RAY MINI-CONSOLE
+12V
+24VSB
J1-1 J3-1 J13-3 J4-3 F2 JW26
DS4 1
J1-2 J3-2
R4
2 NORMAL
J1-10 J3-10 3 LOCKOUT
J1-9 J3-9
OFF Q38
ON J1-5 J3-5 J13-10 J4-10
J1-13 J3-13 J13-11 J4-11
R536
Q37
MINI-CONSOLE BOARD
S1 +12V +12V D14
D13
OFF
J13-4 J4-4
S2
ON Q40
J23-16 TO J8-16 INPUT DISTRIBUTION
BOARD (MD-0975, SHT 4)
D74
Q36
Q39
J13-5 J4-5
D118
J32-79 J14-79
R&F MEMBRANE CONSOLE

FAULT LATCH
J3-3 J5-10 J9-10 DS17
D7, Q6, Q7, Q8 ETC
POWER
OFF
ON J3-2 J5-11 J9-11
OFF
J3-1 J5-12 J9-12 FROM
CPU
CONSOLE
KEYBOARD ASSEMBLY BOARD
CONSOLE CONNECTOR BOARD GENERATOR CONTROL BOARD CPU BOARD
USE DRAWING DC BUS & POWER DISTRIBUTION, MD-0975, IN

CONJUNCTION WITH THIS DOCUMENT
R&F CONSOLE AND MINI CONSOLE

DRAWN DATE
G. SANWALD/J. LAPE 22 MAR 2013
CHECKED SYSTEM ON
DES.\MFG.\AUTH.
MD-0976 REV C
Use and disclosure is subject to the restrictions on the title page of this CPI document. L. FOSKIN
SHEET 1 OF 2
X-RAY MINI-CONSOLE
+12V
+24VSB
J1-1 J3-1 J13-3 J4-3 F2 JW26
DS4 1
J1-2 J3-2
R4
2 NORMAL
J1-10 J3-10 3 LOCKOUT
J1-9 J3-9
OFF Q38
ON J1-5 J3-5 J13-10 J4-10
J1-13 J3-13 J13-11 J4-11
R536
Q37
MINI-CONSOLE BOARD
S1 +12V +12V D14
D13
OFF
J13-4 J4-4
S2
ON Q40
J23-16 TO J8-16 INPUT DISTRIBUTION
BOARD (MD-0975, SHT 4)
D74
Q36
Q39
J13-5 J4-5
D118
STARQTM TOUCHSCREEN CONSOLE

J32-79 J14-79
*USE MINI-CONSOLE TO TURN ON
GENERATOR
(SEE CHAPTER 3-OPERATOR’S MANUAL FAULT LATCH

DS17
AND CHAPTER 2-SERVICE MANUAL D7, Q6, Q7, Q8 ETC
FOR MORE INFORMATION) POWER
OFF
100-240 VAC
FROM
ON * CPU
(CONSOLE ONLY) *USE ONLY
APPROVED
AC ADAPTOR
INCLUDED WITH
THE CONSOLE
CONSOLE CONNECTOR BOARD GENERATOR CONTROL BOARD CPU BOARD
USE DRAWING DC BUS & POWER DISTRIBUTION, MD-0975, IN

CONJUNCTION WITH THIS DOCUMENT
TOUCHSCREEN CONSOLE DRAWN DATE

CHECKED SYSTEM ON
DES.\MFG.\AUTH.
MD-0976 REV C
SHEET 2 OF 2
+24V +3.3 V max. (proportional
TB10-1 to S.I.D. input)
S.I.D. TP5 TP14

INPUT TB10-2 ISOLATION & J6-20 J3-20 RM I/O BRD ABS
CONVERSION CIRCUIT: S.I.D.
(0 TO 1000 +
INPUT RESISTANCE TO JW16 TO MD-0986
R46
OHMS) TB10-3 +24V VOLTAGE OUTPUT GAIN +3.3V
- NOTE * JW17 R47 SELECT
+3.3V
R39
INCLUDES Q1, Q2, U6, U7, (jumpered
R24
+3.3V by default)
R183
4 3 2 1 JW15 U8A, U13A, ETC.
D9 U65
R33
1 4
TB10-4
R23 U11 DS30
INPUT 10 R22 U31 R38
HEARTBEAT
2 3 +24V
II SAFETY* TB10-5
R118 NOTE * DATA
BUFFER
4 3 2 1 JW44
TB10-6 R145
INPUT 9 +3.3V
ROOM DOOR TB10-7 R21 R30 U29
INTERLOCK* MICRO CAN DATA LINK
1 4 REFER TO
CONTROLLER
+24V U10 DATA MD-0990
NOTE * BUFFER
2 3
4 3 2 1 JW14 +3.3V R103

J31-30 J11-30
TO FPGA U53
TB10-8
1 4
INPUT 8 R20 U9
COLLIMATOR
TB10-9 R19 U30
INTERLOCK* 2 3 +24V
R117 NOTE * DATA
BUFFER
4 3 2 1 JW29 +3.3V
CPU BOARD
TB13-1
1 4
INPUT 13 R68 U28
REMOTE TOMO +5V +3.3V
TB13-2 R67
SELECT* 2 3 TP6 TP7
U33 +3.3V
R97 +3.3V
+24V
+3.3V REGULATOR
R584
NOTE *
+5V
4 3 2 1 JW28 1 4
DS12
U27 TP1 TP4 TP8 TP9
R13
TB13-3 ROOM I/O
2 3 +24V
INPUT 7 R66 NOTE *
BOARD
MULT. SPOT SYNC
ROOM INPUTS
EXPOSURE* TB13-4 R65
4 3 2 1 JW27 +3.3V FROM PAGE 2
R96 U74
5V - 3.3V
TB13-5
1 4
R64
ROOM INPUTS R551
U26 FROM PAGE 3
INPUT 11
TB13-6 R63 2 3 +5V
+24V
R95
+24V NOTE *
R194
+3.3V U4
NOTE *
4 3 2 1 JW25
J6-22 J3-22
4 3 2 1 JW26 1 4
U25
TB13-7 1 5
2 3
R62
INPUT 12 U24
TB13-8 R61 R60
R94
3 4
R59
TB13-9
SYNC
INPUT TB13-10
ROOM I/O BOARD GENERATOR CONTROL BOARD
*DEFAULT
SETTINGS
REFER TO “ROOM DOOR INTERLOCKS” ON SHEET 3
FOR DOOR INTERLOCK CONFIGURATION OPTIONS.
* * FOR THE JUMPERS ASSOCIATED WITH INPUTS ON THE ROOM I/O BOARD
(JW14, 15, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 38, 39, 40, 41, 42, 43, 44: DRAWN DATE
INDICATED;THESE 1 1 G. SANWALD/J. LAPE 18 MAR 2013 ROOM
INPUTS &/OR
OUTPUTS ARE
NOTE: SHORTING JUMPERS SHORTING JUMPERS LIVE POSITION: CHECKED INTERFACE
INSTALLER IN “LIVE” POSITION IN “DRY” POSITION JUMPERS CONNECT THE INPUT TO AN INTERNAL VOLTAGE SOURCE. AN EXTERNAL
PROGRAMMABLE IF THE OPTICALLY-COUPLED INPUTS ON SHEETS 1-3 ARE USED IN THE “DRY” CONTACT CONTACT CLOSURE WILL ENERGIZE THE OPTO-COUPLERS ON THE ROOM I/O BOARD.
POSITION, ENSURE THAT THE VOLTAGE ON EITHER SIDE OF THE JUMPER BLOCK DES.\MFG.\AUTH. MD-0977 REV A
PINS (2 or 3) TO THE GENERATOR GROUND DOES NOT EXCEED 48 VOLTS. DRY POSITION: L. FOSKIN
A JUMPER CONNECTS THE OPTO-COUPLER BACK TO THE INPUT. AN EXTERNAL VOLTAGE SOURCE ENERGIZES
THE OPTO-COUPLER (24 VDC @ 20 mA). SEE NOTE AT LEFT RE GROUNDING THE EXTERNAL SUPPLY. SHEET 1 OF 8
*DEFAULT
SETTINGS +24V
INDICATED;THESE +3.3V
NOTE *
INPUTS &/OR
OUTPUTS ARE
INSTALLER 4 3 2 1 JW34 1 4
PROGRAMMABLE
U22
TB14-3
2 3
FLUORO R78 U31
TIMER RESET TB14-4 R77 DATA
R116 BUFFER
+24V
TB14-5 +3.3V
NOTE *
X-RAY 1 4
4 3 2 1 JW33
DISABLE TB14-6
U21
2 3
+24V
+3.3V R76
NOTE *
R75
1 4 R115
4 3 2 1 JW32
U16
TB14-7
2 3
INPUT 14 R74 U30
MAG MODE
TB14-8 R73
INPUT 1* R112 DATA
BUFFER
+24V
TB14-9 +3.3V
NOTE *
INPUT 15
MAG MODE 4 3 2 1 JW31 1 4
TB14-10 U32
INPUT 2* U15
2 3
+24V
+3.3V R72 DATA
NOTE *
R71 BUFFER
1 4 R111
4 3 2 1 JW30
U20
TB14-11
2 3
INPUT 16 R70
MAG MODE
TB14-12 R69
INPUT 3* R110
+3.3V ROOM INPUTS

DS3
R5 220VAC TO PAGE 1
1 5
U2 DS2 +3.3V
ROOM POWER D2 R4 110VAC
2 4
TRANSFORMER 220 VAC 110 VAC 26 VAC 1 5
FROM MD-0975
PG 1 - PG 4 U1
220V J1-1 F2 R124 D1
2 4
110V J1-3 F1
R123
0V J2-2 F3
26V J2-3 +3.3V

DS6 +3.3V
R12 DS5
26VAC R9 18VAC
19V F4 +24V 1 4 19 VAC (2)
TP3 +3.3V 1 4
DS4
J2-4 U5 R7
0V 18VAC U4
D5 19 VAC (1)
D6 2 3 1 4 D4
2 3
19V J2-6 F5 R13 U3 R8
R3
C1
D3
J2-1 R122 2 3
19 VAC (1) R121
DS1 R6
J2-5 TP2 19 VAC (2) +24VDC R120
ROOM I/O BOARD
DRAWN DATE
G. SANWALD/J. LAPE 18 MAR 2013 ROOM
NOTE:
CHECKED INTERFACE
IF THE OPTICALLY-COUPLED INPUTS ON SHEETS 1-3 ARE USED IN THE “DRY” CONTACT
PINS (2 or 3) TO THE GENERATOR GROUND DOES NOT EXCEED 48 VOLTS. L. FOSKIN
SHEET 2 OF 8
ROOM DOOR INTERLOCKS
Configuration A
Inhibits new exposures if the room
door is open. Does not interrupt
exposures in process when the
door is opened.
+24V
TB15-1 +3.3V
NOTE * DOOR INTERLOCK
INPUT 1 SWITCH
BUCKY 1 4 3 2 1 JW43 1 4
TB15-2 ROOM DOOR INTERLOCK
CONTACTS* U36
INPUT (DEFAULT TB10-6, 7)
2 3 U30
+24V
+3.3V R144
NOTE * DATA
R143 FLUORO FOOT
BUFFER
1 4 R113 SWITCH
4 3 2 1 JW42
U43 (R&F UNITS REMOTE FLUORO EXPOSURE
TB15-3
2 3 ONLY) INPUT (DEFAULT TB16-3, 10)
INPUT 3 R142
BUCKY 2
TB15-4 R141
CONTACTS* R104
+24V ROOM I/O BOARD

TB15-5 +3.3V
NOTE * U29
INPUT 2
BUCKY 3 4 3 2 1 JW41 1 4
TB15-6
CONTACTS* U35
DATA
2 3 BUFFER
+24V
+3.3V R140
NOTE *
R139
R108 Configuration B
4 3 2 1 JW40 1 4
Inhibits new exposures if the room
U42 door is open. Stops fluoro exposures
TB15-7 ROOM INPUTS
2 3 if the room door is opened
INPUT 5 R138 TO PAGE 1
during a fluoro exposure.
BUCKY 4
TB15-8 R137
CONTACTS* R107
+24V DOOR INTERLOCK

TB15-9 +3.3V SWITCH
NOTE *
1 4 ROOM DOOR INTERLOCK

INPUT 4 4 3 2 1 JW39
TB15-10 INPUT (DEFAULT TB10-6, 7)
U34
2 3
+24V
+3.3V R136
NOTE * DOOR INTERLOCK
R135 SWITCH
1 4 R106
4 3 2 1 JW38
U41 REMOTE FLUORO EXPOSURE
TB15-11 INPUT (DEFAULT TB16-3, 10)
2 3
R134 FLUORO FOOT
INPUT 6 SWITCH
TB15-12 R133
R105
ROOM I/O BOARD
NOTE: For this configuration, the room door interlock switch

must be a double-pole type (one pole for the room door
interlock, with the second pole in series with the fluoro
foot switch).
*DEFAULT
SETTINGS
INDICATED;THESE
INPUTS &/OR
OUTPUTS ARE ROOM I/O BOARD
INSTALLER
PROGRAMMABLE
DRAWN DATE
NOTE:
CHECKED INTERFACE
IF THE OPTICALLY-COUPLED INPUTS ON SHEETS 1-3 ARE USED IN THE “DRY” CONTACT
PINS (2 or 3) TO THE GENERATOR GROUND DOES NOT EXCEED 48 VOLTS. L. FOSKIN
SHEET 3 OF 8
REFER TO MD-0975, SHEET 9, FOR
THE +24V INT SOURCE
C9
TB8-2
+24V INT
R17 JW9 OUTPUT 7
TB20 K4 TB8-1 BUCKY 1
K4
1 SELECT*
2
C8
3 TB8-4
K1 K5 JW4 1 2 3 4 5 6 7 8 R16 JW8 OUTPUT 3
R160
4 DRY * LIVE * K3 TB8-3 BUCKY 2
5 SELECT*
DS18
OUT 1 6
U65 U69
JW3 1 2 3 4 5 6 7 8
DRY * LIVE *
TB7
1
K2 K3
C7
R158
2
TB8-7
K3 3
R15 JW7 OUTPUT 4
R156
K2 K2 TB8-6 BUCKY 3
DS28
OUT 4 4 SELECT*
DS24 5
OUT 3 K1 C6
6 TB8-10
JW2 1 2 3 4 5 6 7 8 R14 JW6 OUTPUT 1
DRY * LIVE * K1 TB8-9 BUCKY 4 /
TOMO SELECT*
K4 220 VAC
R153
K5 TB4 JW1 1 2 3 4 5 6 7 8
R154
DRIVER
DS16 DRY * LIVE *
OUT 7
DS23
OUT 2 C4
TB9-10
R11 JW11 OUTPUT 2
CAN DATA LINK
REFER TO MICRO K5 TB9-9 BUCKY /
MD-0990 CONTROLLER TOMO START*
K6 TB9-6
C10
R165
K7 JW5 1 2 3 4 5 6 7 8 OUTPUT 5
R28
110 VAC K6 TB9-5
R157
C5 ROOM LIGHT*
DS25 DRY * LIVE *
JW12
OUT 5 TB3 R10 JW10
DS22 TB9-3
OUT 6 K7
NOTE THE FOLLOWING IF USING JW1, JW2,

JW3, JW4, OR JW5 IN THE LIVE CONTACT TB9-1 OUTPUT 6
POSITION:
TB9-2
K8 A JUMPER WIRE MUST BE CONNECTED TO
R166
TB20 PINS 1, 3 AND TB7 PINS, 1, 3, & 5 FROM TB2,

TB3, OR TB4 IN ORDER TO SUPPLY +24V, TB10-12
R167 K11 C11
DS13 110 VAC, OR 220 VAC AT THE SELECTED OUTPUT OUTPUT 11
OUT 11 R18 JW13 K8 COLLIMATOR
U70 TB10-11
BYPASS*
DS12
OUT 8
DRIVER +24V
C24 R58 JW22
TB2 TB6
TB11-2
ADDRESS / DATA BUS

FROM PAGE 8 TB11-3
K11 OUTPUT 8
+24V
TB11-1
JW23 1 2 3 4
C30
DRY ** R131 JW37 *DEFAULT
SETTINGS
LIVE 24 VDC ** INDICATED;THESE
INPUTS &/OR
ROOM I/O BOARD OUTPUTS ARE
INSTALLER
PROGRAMMABLE
FOR THE JUMPERS ASSOCIATED WITH OUTPUTS ON THE ROOM I/O BOARD
* * * * (JW1 TO JW5, JW19, 21, 23. 24):
DRAWN DATE
1 1 G. SANWALD/J. LAPE 18 MAR 2013 ROOM
LIVE POSITION:
1 1
SHORTING JUMPERS SHORTING JUMPER JW1 to JW5: 24 VDC, 110 VAC, OR 220 VAC WILL BE OUTPUT WHEN THE CORRESPONDING RELAY CLOSES
CHECKED INTERFACE
IN “LIVE” POSITION IN “DRY” POSITION JW19, 21, 23, 24: 24 VDC WILL BE OUTPUT WHEN THE CORRESPONDING RELAY CLOSES
SHORTING JUMPER SHORTING JUMPER (JW19, 21, 23, 24)
(JW19, 21, 23, 24) DES.\MFG.\AUTH.
IN “LIVE” CONTACT IN “DRY” CONTACT DRY POSITION: MD-0977 REV A
POSITION (JW1 to JW5) POSITION (JW1 to JW5) A DRY CONTACT CLOSURE WILL BE PROVIDED WHEN THE RELAY ASSOCIATED L. FOSKIN
WITH THE SELECTED OUTPUT CLOSES SHEET 4 OF 8
*DEFAULT
SETTINGS
+24V INT REFER TO MD-0975 FOR C23 R57 JW20 INDICATED;THESE
THE +24V INT SOURCE INPUTS &/OR
TB11-7 OUTPUTS ARE
INSTALLER
PROGRAMMABLE
K9 TB11-8
R155
K10 OUTPUT 9
+24V
DS21 TB11-6
OUT 10
U65 U70 JW21 1 2 3 4
C29
C22 R56 JW18 DRY ** JW36
R130
LIVE 24 VDC **
K10 TB11-11
R161
K12
R162
TB11-12
DS20 K9 OUTPUT 10
OUT 9 +24V
DS29
TB11-10
OUT 14
DRIVER JW19 1 2 3 4 TB12-3 OUTPUT 16 (COMM)

C28
TUBE 1 / TUBE 2
DRY ** R129 JW35 K15 TB12-1
OUTPUT 16 (TUBE 1)
K13 LIVE 24 VDC **
R163
TB12-2
K14 OUTPUT 16 (TUBE 2)
R164
DS14 TB12-7
OUT 13
CAN DATA LINK K14 OUTPUT 12
MICRO DS17
REFER TO
CONTROLLER OUT 12 TB12-6 MAG MODE 1*
MD-0990
TB12-9
K13 OUTPUT 13
TB12-8 MAG MODE 2*
K15
R159
TB12-11
DS27 OUTPUT 14
K16 K12
OUT 16 TB12-10 MAG MODE 3*
K16 +24V
TB12-12
R168
+24V INT
R152
Q3
JW24 1 2 3 4
R86
D22 D35 TB13-11
DS19
OUT 15 DRY ** X-RAY ON
U69 1 4 TB13-12
LIVE 24 VDC **
U61
DRIVER TB14-1
2 3
Q5 ALE
U70 TB14-2 OUT
R87
DRIVER
D26 D36
110 VAC
TB5-1
HV ON TB5-2
J3-19 J6-19
FROM MD-0980 110 VAC OUT
TB5-3
PG 1 MAX LOAD 1.5A
TB5-4
TP1 TP4 TP8 TP9

220 VAC
TB1-1
TB1-2
220 VAC OUT
TB1-3
MAX LOAD 1A
TB1-4
GENERATOR CONTROL BOARD ROOM I/O BOARD
DRAWN DATE
CHECKED INTERFACE
DES.\MFG.\AUTH. MD-0977 REV A
L. FOSKIN
SHEET 5 OF 8
*DEFAULT
SETTINGS
+24V +24V
INDICATED;THESE
INPUTS &/OR 1 4 1 4
OUTPUTS ARE 1 4 LIH Circuit
INSTALLER U62 (U59, C68, U63
A
PROGRAMMABLE U57 U68 U18 R205-207)
2 3 2 3
2 3 DATA
DRIVER D41 to D47
LATCH
D40
+3.3V
D39 D49 D50 D51 D48 D53 D52 D38
TO A,
SHEETS
R176
U14 6&7
JW45 JW48 JW49 JW50 JW47 JW52 JW51 JW46
DATA
BUFFER
1 4
U38
2 3 EXP EN
FROM
1 4 TO B, TO C, TO D,
SHEET 7
A SHEET 7 SHEET 7 SHEET 7
U53 U68 U18
DS8 2 3 DATA
HS_IN7 DRIVER
LATCH
+3.3V
R88
J6-14 J3-14 EXPOSURE ENABLE

TO MD-0979
R177
PAGE 1
R109
U14
TB16-7 DATA
BUFFER
HS INPUT 1 4
7
U39
1 4
R114 R89 2 3
HS INPUT 6 TB16-6 A
U47 U68 U18
TOMO EXPOSURE* DS9 U44
2 3 DATA J6-3 J3-3 R19 J31-11 J11-11
HS_IN6 DRIVER
LATCH R18
J6-4 J3-4 J31-41 J11-41
+3.3V
J6-5 J3-5 R17 DATA J31-12 J11-12
TB16-9
R16 BUFFER
J6-6 J3-6 J31-42 J11-42
R175
TB16-10
U14 R15
J6-7 J3-7 J31-13 J11-13
DATA
BUFFER
1 4
U52
2 3 DATA & CONTROL
1 4 BUS
HS INPUT 4 TB16-4 R91 R102 A
U58 U68 U18
PULSED FLUORO SEL* DS11
HS_IN4 2 3 DATA
DRIVER
LATCH
+3.3V
R173
U14
DATA
BUFFER
1 4
U54
2 3 1 4
TB16-3 R119 R100 A
HS INPUT 3 U40 U68 U18
REMOTE FLUORO EXP* DS7
HS_IN3 2 3 DATA
DRIVER
LATCH
+3.3V
R174
U14
DATA
GENERATOR CONTROL BOARD CPU BOARD
BUFFER
1 4 Use and disclosure is subject to the restrictions on the title page of this CPI document.
U51
2 3 DRAWN DATE
TB16-5 R90 R101 G. SANWALD/J. LAPE 18 MAR 2013 ROOM
HS INPUT 5
HI-LEVEL FLUORO SEL* DS10
CHECKED INTERFACE
HS_IN5
L. FOSKIN
ROOM I/O BOARD SHEET 6 OF 8
*DEFAULT
SETTINGS
INDICATED;THESE
INPUTS &/OR
OUTPUTS ARE
INSTALLER
PROGRAMMABLE
B, FROM
SHEET 6
1 4
A, FROM
U74 SHEET 6 EXP EN
U68 U18
TO SHEET 6
2 3 DATA
DRIVER
LATCH
+3.3V
R199
U14
DATA
BUFFER
1 4 C, FROM
SHEET 6
U77
2 3 1 4
TB16-1 R201 R200 A, FROM
HS INPUT 1 U75 SHEET 6 U68 U18
REMOTE PREP* DS32
HS_IN1 2 3 DATA
DRIVER
LATCH
+3.3V
TB16-11
R202
TB16-12
U14
DATA
BUFFER
1 4 D, FROM
SHEET 6
U78
2 3 1 4
HS INPUT 2 TB16-2 R204 R203 A, FROM
U73 SHEET 6 U68 U18
REMOTE EXP (RAD)* DS33 U44
HS_IN2 2 3 DATA J6-1 J3-1 R21 J31-10 J11-10
DRIVER
LATCH R20
J6-2 J3-2 DATA J31-40 J11-40
+3.3V BUFFER
J6-8 J3-8 R19 J31-43 J11-43
R196
U14
DATA
BUFFER DATA & CONTROL
1 4 BUS
U76
2 3
HS INPUT TB16-8 R198 R197
8 DS31
HS_IN8
DRAWN DATE
CHECKED INTERFACE
L. FOSKIN
ROOM I/O BOARD SHEET 7 OF 8
U36
J14-133 J21-133 DATA R9 J3-25 J6-25 +5V

FROM FPGA
BUFFER
U53
3.3V - 5V
ADDRESS / DATA BUS

TO PAGE 4
Q6 TP16
+3.3V +3.3V J8
+12V +12V
EXP SOUND
R126
R148
Q7 OUT
SPEAKER
DRIVER
1 4 1 4
U44 U55
2 3 2 3
+24V
TB17-9
+24V +24 V
TB17-10
+3.3V +3.3V U67 +24 V
+12V +12V TB17-1
HS OUT 1
R125
R127
TB17-2
HS OUT 2
TB17-3
1 4 1 4 HS OUT 3
TB17-4
U49 U50 HS OUT 4
DRIVER TB17-5
2 3 2 3 HS OUT 5
TB17-6
HS OUT 6
TB17-7
HS OUT 7
TB17-8
HS OUT 8
TB17-11
+3.3V +3.3V FW DIODE
+12V +12V TB17-12
GND
R149
R128
U44 U19
J11-10 J31-10 R21 J3-1 J6-1
NOTE: HS OUTPUT
J11-40 J31-40 R20 J3-2 J6-2 ASSIGNMENTS
1 4 1 4 ARE INSTALLER
J11-11 J31-11 R19 J3-3 J6-3 PROGRAMMABLE
U56 U48
J11-41 J31-41 R18 J3-4 J6-4
DATA 2 3 2 3 26 VAC
BUFFER DATA
J11-12 J31-12 R17 J3-5 J6-5
3.3V - 5V LATCH TB18-1
J11-42 J31-42 R16 J3-6 J6-6 COLLIMATOR
TB18-2
R15 LAMP 6.7A
J11-13 J31-13 J3-7 J6-7
TB18-3
J11-43 J31-43 R14 J3-8 J6-8
TB18-4 GROUND
+3.3V +3.3V
+12V +12V
DATA & CONTROL
R132
R147
BUS
+24V
1 4 1 4
TB19-1
U45 U46 ELECTRIC
TB19-2
2 3 2 3 LOCKS 4A
TP8 TP9 TB19-3
TB19-4 GROUND
CPU BOARD GENERATOR CONTROL BOARD ROOM I/O BOARD
DRAWN DATE
CHECKED INTERFACE
L. FOSKIN
SHEET 8 OF 8
+12V
THERMAL SENSOR BOARD
R173
(LOCATED ON INVERTER HEAT SINK)
R162
J1-3 J7-1 J16-16 J4-16
- R168
TEMP J1-2 J7-2 J16-18 J4-18 R196 R207
+
SENSOR
U31A
J7-3
R163
J1-1 +12V C97
U5
R174
R213
J7-4 J16-19 J4-19 R88
- R212 MICRO CAN DATA LINK
J7-5 J16-20 J4-20 R197 R208 REFER TO
+ CONTROLLER
MD-0990
U31B
J7-6
R211
+12V C99
R153
R198
J16-21 J4-21
- R206
J1-3 J7-7 J16-22 J4-22 R200 R199
+
J1-2 J7-8 U32A

TEMP
R209
C94
SENSOR
J1-1 J7-9
THERMAL SENSOR BOARD

(LOCATED TO THE RIGHT OF THE INPUT DISTRIBUTION BOARD AUXILIARY CPU BOARD
IDB MOUNTED ON THE CHASSIS)
INVERTER / AMBIENT TEMPERATURE SENSE
TUBE 1
STATOR
TERMINAL
+24V
BLOCK
J11-1 R3 J16-40 J4-40
R145
THERMAL
SWITCH
1 4 +3.3V +3.3V
U29
R51
R48
2 3 U5
TUBE 2
STATOR
TERMINAL
BLOCK +24V MICRO CAN DATA LINK
CONTROLLER REFER TO
J11-2 R7 J16-39 J4-39 MD-0990
R146
THERMAL
SWITCH J11-3
1 4
U30
R8
2 3
INPUT DISTRIBUTION BOARD AUXILIARY CPU BOARD
TUBE THERMAL SWITCH INPUTS
DRAWN DATE
G. SANWALD/J. LAPE 18 MAR 2013 FANS, INTERLOCKS,
CHECKED TUBE 1 / TUBE 2
SELECT, ETC
L. FOSKIN
MD-0978 REV A
SHEET 1 OF 2
J6-1 J19-1 J2-8 FAN 1 PIN 1
J2-1 FAN 1 PIN 3 FAN 1
U5 INVERTER 1 &
J5-39 J18-39 J2-4 FAN 1 PIN 2 INVERTER 2
R75
J6-3 J19-3
R68
+3.3V +3.3 +3.3V +3.3V +3.3V +3.3V J2-9 FAN 2 PIN 1
J2-2 FAN 2 PIN 3 FAN 2
J5-36 J18-36 INVERTER 1 &
R157
R159
R156
R155
R158
R160
U24 J2-5 FAN 2 PIN 2 INVERTER 2
R187
J6-4 J19-4
R189
J2-10 FAN 5 PIN 1
CAN DATA LINK MICRO R186 FAN 5
J5-35 J18-35 J2-3 FAN 5 PIN 3
REFER TO CONTROLLER RESONANT
MD-0990 MUX R188
J2-6 FAN 5 PIN 2 ASSEMBLY
R185 J6-6 J19-6
R190 TP1
J3-10 FAN 3 PIN 1
J6-2 J19-2 OV RTN
NOTE 1 FAN 3
J3-1 FAN 3 PIN 3
TP13 INVERTER 3
FAN GATE DR +24V J3-4 FAN 34 PIN 2 (IF APPLICABLE)
R184
J3-11 FAN 4 PIN 1

NOTE 2
J3-2 FAN 4 PIN 3
FAN 4
U4 TP8 INVERTER 3
FAN P/S J3-5 FAN 4 PIN 2 (IF APPLICABLE)
D30 Q8 +12V
J5-30 J18-30
PWM L1
J3-12 FAN 6 PIN 1

D18
FAN 6
J3-3 FAN 6 PIN 3
SPARE
FAN DRIVER CIRCUIT J3-6 FAN 6 PIN 2 (NOT USED)
NOTE 1: THE WAVEFORM AT THIS

AUXILIARY CPU BOARD INPUT DISTRIBUTION BOARD
POINT WILL BE A PULSE TRAIN
VARYING FROM 0 TO 50% DUTY
FAN DRIVER CIRCUIT CYCLE (0% DUTY = FANS OFF,
50% DUTY = FANS AT HIGH SPEED)
NOTE 2: THIS IS THE DRIVE VOLTAGE

FOR THE FANS. IT WILL VARY FROM
0 TO 12 V (0 V = FANS OFF,
NOTE: TP25 WILL NORMALLY BE HIGH +12V. IT WILL PULSE LOW FOR APPROXIMATELY APPROXIMATELY 6 V = FANS LOW,
+12V
100 MS IN ORDER TO BRIEFLY TURN ON Q11 & Q12 ON THE INPUT TP25 12 V = FANS HIGH)
DISTRIBUTION BOARD WHEN TUBE 2 IS SELECTED. TUBE SEL REL R56 R54 J22-2 J5-2
+12V (SEE NOTE)
J22-6 J5-6
U5 J5-26 J18-26
R10
J22-1 J5-1
DS11 +130V +24V
+3.3V HOLD
TUBE
SEL RAIL
U10 HLD +3.3V R51
R24
DRIVER CIRCUIT FOR

CAN DATA LINK MICRO 4 1 TUBE 1 / TUBE 2 R64
DRIVER PULL J22-4 J5-4
REFER TO CONTROLLER J5-25 J18-25 SELECT RELAY
MD-0990 U9 DS4
Q11, Q12, Q14, D52
J18-23 3 2
J5-23 TUBE 2
HV MODULE
J5-27 J18-27
4 1
R52
U8
3 2 DRAWN DATE
G. SANWALD/J. LAPE 18 MAR 2013 FANS, INTERLOCKS,
AUXILIARY CPU BOARD INPUT DISTRIBUTION BOARD
CHECKED TUBE 1 / TUBE 2
SELECT, ETC
TUBE 1 / TUBE 2 DRIVER AND FEEDBACK CIRCUIT DES.\MFG.\AUTH.
L. FOSKIN
MD-0978 REV A
Use and disclosure is subject to the restrictions on the title page of this CPI document. SHEET 2 OF 2
+24V
EXPOSURE ENABLE
1 4 1 4 FROM MD-0977
PAGE 6
U105 U104
LAST IMAGE 2 3 EXPOSURE ENABLE
2 3
HOLD CIRCUIT FROM MD-0987
(U9, C10, ETC.) PAGE 1
D88
EXPOSURE
1 4 ENABLE
TP4 LOW = FLUORO EXPOSURE REQUESTED. TP4 HIGH (24 V) = NO FLUORO EXPOSURE REQUEST. TO PAGE 5
TP5 LOW = PREP REQUESTED. TP5 HIGH (24 V) = NO PREP REQUEST. U106
TP6 LOW = X-RAY REQUESTED. TP6 HIGH (24 V) = NO X-RAY REQUEST. 2 3
U32
TP4 TP5 TP6 +5V DATA

Q52
LATCH
R15
R16
R14
R80
U55
J5-6 J9-6 J13-1 J4-1 R276
DATA
BUFFER
J5-7 J9-7 J13-7 J4-7 1 4
R263
J5-8 J9-8 J13-9 J4-9
DS3 2 3 U107
+5V +5V +5V J5-9 J9-9 J13-10 J4-10 FLUORO
R11
R12
R13
U18 +5V
J13-11 J4-11
R304
FPGA
U49
R321
U58
+24V
DATA J31-40 J11-40
DATA
BUFFER FPGA U53
BUFFER
5V - 3.3V
R322
1 4
J3-11 U103
4 1
FROM 2 3
DATA BUS U3 MINI J3-12 +24V
D0..D7 4 1 DS13
3 2 CONSOLE PREP
U2 (PAGE 2) J3-14
1 4
3 2
R275
J13-7 U109
FLUORO 2 3
FOOT 4 1 U32
SWITCH J13-9
DATA
U4 +5V Q53
LATCH
R262
3 2
J13-3
PREP
R79
HAND J13-1
X-RAY
SWITCH U33 U49
1 4
J13-5 DATA J31-10 J11-10
U110 DATA
COM BUFFER FPGA U53
CONSOLE BOARD BUFFER
5V - 3.3V
R&F MEMBRANE 2 3
CONSOLE J3-18 J3-19 J3-20
DS4
XRAY
REFER TO PAGES 3 FOR
THETOUCHSCREEN CONSOLES P1-18
PREP P1-19
X-RAY
P1-20
GENERATOR CPU BOARD
DRAWN DATE
G. SANWALD/J. LAPE 10 APR 2013 PREP & X-RAY
KEYBOARD ASSEMBLY CHECKED EXPOSURE
CONSOLE CONNECTOR
R&F MEMBRANE CONSOLE BOARD GENERATOR CONTROL BOARD DES.\MFG.\AUTH.
MD-0979 REV C
L. FOSKIN
HAND
SWITCH
X-RAY
PREP
COM
J2-1 J2-2 J2-3
J1-11
J1-12
TO J3 ON CONSOLE
PREP CONNECTOR BOARD (PG 1)
X-RAY
J1-14
MINI-CONSOLE BOARD
X-RAY MINI-CONSOLE
DRAWN DATE
CHECKED EXPOSURE
DES.\MFG.\AUTH.
MD-0979 REV C
L. FOSKIN
HAND
SWITCH
X-RAY
PREP
COM
J2-1 J2-2 J2-3
HS INPUT 3
TB16-3 R119 R100 SEE MD-0977
FLUORO DS7 PAGE 6
FOOT HS_IN3
J1-11 TB16-10
SWITCH
J1-12
TO J3 ON CONSOLE
PREP CONNECTOR BOARD (PG 1)
X-RAY
J1-14
REMOTE FLUORO EXPOSURE INPUT
(DEFAULT TB16-3, 10)
MINI-CONSOLE BOARD
SEE MD-0977 AND CHAPTER 3B
FOR MORE INFORMATION
X-RAY MINI-CONSOLE
TOUCHSCREEN CONSOLE
(PREP & EXPOSURE CONNECTIONS)
TOUCHSCREEN CONSOLE
(USE MINI-CONSOLE FOR PREP &
EXPOSURE. SEE CHAPTER 3-OPERATOR’S
MANUAL FOR MORE INFORMATION)
DRAWN DATE
CHECKED EXPOSURE
DES.\MFG.\AUTH.
MD-0979 REV C
L. FOSKIN
+3.3V
+24V
R260
R226
J3-9 J22-12 R225
TP19 0 V = EXPOSURE ENABLE requested

J3-7 J22-10 1 4 5 V = EXPOSURE ENABLE not requested
DM EX EN#
U127
2 3 EXPOSURE ENABLE
FROM PG 1 +5V +5V
H.V. MODULE
0 V = HV Module connected +5V D112

5 V = HV Module disconnected Q32 0 V = Gate drive pulses inhibited (no exposure)
>2 V = Gate drive pulses enabled
TP43
R387
R125
TANK CBL Q31
TP18
INTLK XRAY EN
R440
R389
R545
R142
U96
J14-33 J32-33 R540 0 V = No Fault
TO FPGA U53
TP21 3 V = Fault detected,
FAULT exposure inhibited DRIVE ENABLE
TO MD-0980
SHEET 1
R362
R414
R413
R412
J14-47 J32-47 R404
FROM FPGA U53 Q29
R403
D103 D104 D109
R386
TP20 0 V = Ready to expose

XRAY EXP 5 V = Inhibit exposures
R402
R166
+5V
R411
Q27 Q28
J11-21 J31-21 R563
R401
R400
FROM FPGA U53 Q47
+15V_A +15V_A
R456
R451
Q34
R445
Q33 R212 D56 KV INHIBIT
TO MD-0980
R457
SHEET 1
CPU BOARD GENERATOR CONTROL BOARD
DRAWN DATE
CHECKED EXPOSURE
DES.\MFG.\AUTH.
MD-0979 REV C
L. FOSKIN
NOTE 1: A narrow pulse will be present at TP42 if a over-voltage condition has been detected.
This pulse may be very difficult to detect as the high voltage will be shut down when the over-voltage R460
condition is detected, thus removing the fault condition.
R459 R205 -
R458 J22-9
+
NOTE 1 1V = approx. 20 kV
TP42 +15V_A U73A
+3.3V TP39
OVP TRIP
**THIS JUMPER KV FBK
R200
SHOULD MATCH C93
R511
JW23
R461
R259
R513
THE GENERATOR
R479
R478
POWER LEVEL. DO J22-5
NOT MOVE
J14-7 J32-7 - INADVERTENTLY.
TO FPGA U53 R496 -
JW23, JW24 installed for single ended tubes,
+ J22-10
KV FEEDBACK
+ removed for double ended X-ray tubes
U82 1 *DO NOT FROM PAGE 3
*
R512
R477
KV FBK
U77A
ADJUST
R195
125 kV R504
2
150 kV 3 JW24
R204
- C102
JW25 ** R463
R480
U62 +
J11-46 J31-46 R164 U122 R462 R465 -

A/D R464 J22-11
TO FPGA U53
CONV +
R165
U73B
+3.3V +5V NOTE 3: Should be a 50% duty cycle square wave ranging in
U4 frequency from approx 80 kHz to approx 250 kHz.
CPU POWER
SUPPLY J11-5 J31-5 NOTE 3
SUPERVISORY TP14 TP13
CIRCUIT GATE A GATE B
TP34 1V = 15 kV
KV REF Q46
R363
R89
R485
Q45 U45B U37
R486
U86 DUAL
J14-5 J32-5 DRIVE PULSES
FROM FPGA U53 - R497 R498 INVERTER/ CONTINUED ON
J14-6 J32-6 D/A DRIVER PAGE 2
FROM FPGA U53 +
CONVERTER
J14-45 J32-45 U80A
FROM FPGA U53
R503
-
R499 U45C
+
U77B
R476
TP27 = kV error signal. Approx -0.7V = no kV
demand, approx +15V = maximum kV demand.
TP27
RAD ERR AMP
TP37 High (5V) = HV on D116
HV ON Low = HV off
ERROR AMPLIFIER
R191
HV ON R441
TO MD-0977 R455 Q
(PG 5) AND
-
- VCO
- MD-0987 + -
- + Q
(PG 1) U72A R443 INCLUDES U45,
+ Q35 D49 +
+ U72B U46, U47, U115, U116,
U76A U68A
R180
U76B U117, Q26
TP30 = rectified inverter

“HV ON” CIRCUIT KV INHIBIT current. Frequency approx
FROM MD-0979 160 kHz to approx 500 kHz.
PG 5 DRIVE ENABLE
TP30 C202 FROM MD-0979
+3.3V IR FBK PG 5
NOTE 2
TP16 D98-D101
R256
IR TRIP CURRENT SENSE

J14-43 J32-43 -
CURRENT LIMIT
TO FPGA U53
+ Vref -6V T4 T5
U118
NOTE 2: A narrow pulse will be present at TP16 if an
inverter over-current condition has been detected. This COMPARATOR CIRCUIT
pulse may be very difficult to detect as the high voltage
will be shut down when the over-current condition is J20-1 J20-3 J20-2 J20-4
CPU BOARD detected, thus removing the fault condition. GENERATOR CONTROL BOARD
DRAWN DATE
HT PRIMARY CURRENT SENSE
G. SANWALD/J. LAPE 22 MAR 2013 KV CONTROL &
FROM PAGE 2 CHECKED FEEDBACK
DES.\MFG.\AUTH.
L. FOSKIN
MD-0980 REV B
SHEET 1 OF 3
E1: 280 / 340 VDC (+)
* K1 USED ON R&F
GENERATORS ONLY
J2-1
TO J10-8 INVERTER 1 FAULT REFER TO MD-0984 (SHT 2)
J2-3 TO PAGE 3
TO J10-4 FOR K1 DRIVE CIRCUITS
K1 *
J8-3 J1-1 MOSFET MOSFET
J8-9 J1-2 SWITCHES SWITCHES
E3
J8-4 J1-3
SWITCHES SWITCHES
*
E4
INVERTER BOARD #1 E2: 280 / 340 VDC (-)
E1: 280 / 340 VDC (+)
J2-1
TO J10-6 INVERTER 2 FAULT
J2-3 TO PAGE 3
TO J10-7

GATE DRIVE CIRCUIT HT PRIMARY CURRENT
E3 CONTINUED ON PAGE 3
FOR MOSFET INVERTER
(INCLUDES Q10 TO Q17) J8-6 J1-3
SWITCHES SWITCHES
E4
INVERTER BOARD #2 E2: 280 / 340 VDC (-)
T1
E1: 280 / 340 VDC (+)

J2-1
TO J10-1 INVERTER 3 FAULT
J2-3 TO PAGE 3
TO J10-5
K2 J8-1 J1-1 MOSFET MOSFET

K2
E3
J8-2 J1-3
DRIVE PULSES SWITCHES SWITCHES K2
FROM PAGE 1
E4
REFER TO MD-0984 SHT 2
K2
FOR K2 DRIVE CIRCUITS
REFER TO MD-0984 SHT 2 E2: 280 / 340 VDC (-)

FOR K2 DRIVE CIRCUITS
GENERATOR CONTROL BOARD INVERTER BOARD #3 RESONANT ASSEMBLY
INDICO IQ GENERATORS USE ONE, TWO, OR THREE INVERTER

MODULES DEPENDING ON GENERATOR OUTPUT POWER HT PRIMARY CURRENT TO J13-1
SENSE, TO PAGE 1 TO J13-4
DRAWN DATE
CHECKED FEEDBACK
DES.\MFG.\AUTH.
L. FOSKIN
MD-0980 REV B
SHEET 2 OF 3
HV ANODE
BOARD
NOTE 4
TP7 ANODE
TRIP1
T3 C S
J10-4 L
J14-31 J32-31 - Vref 5V
TO FPGA U53 INVERTER 1 FAULT
+
J10-8 FROM PAGE 2
U10
J3-8
TO J22-11 HV MULT
ASSY +
J3-7 (ANODE)
KV TO J22-10
FEEDBACK
TO PAGE 1 J3-5
TO J22-5
J3-6
TO J22-9
NOTE 4
TP3
TRIP2
T2
J10-7
J14-30 J32-30 - Vref 5V
TO FPGA U53 INVERTER 2 FAULT
+
J10-6 FROM PAGE 2
U6 E9
HV MULT
ASSY-
E10 (CATHODE)
NOTE 4
TP1
TRIP3
T1
J10-5 HT PRIMARY CURRENT
J14-32 J32-32 - Vref 5V FROM PAGE 2
TO FPGA U53 INVERTER 3 FAULT L
+
J10-1 FROM PAGE 2 C
U2 S
HV CATHODE CATHODE
TANK LID
BOARD
BOARD
CPU BOARD GENERATOR CONTROL BOARD PART OF HV MODULE
INVERTER FAULT CIRCUITS ** ONE TUBE H.T. OUTPUTS ARE SHOWN. TWO TUBE
HV MODULES WILL HAVE A SECOND PAIR OF H.T. OUTPUTS
NOTE 4: A narrow pulse will be present at TP7, TP3 or TP1 if an inverter over current or shoot-through condition has HT PRIMARY CURRENT / HV MODULE
been detected. This pulse may be very difficult to detect as the high voltage will be shut down when the over current / shoot-through
condition is detected, thus removing the fault condition.
DRAWN DATE
CHECKED FEEDBACK
DES.\MFG.\AUTH.
L. FOSKIN
MD-0980 REV B
SHEET 3 OF 3
J26-6 J2-6
FILAMENT REFERENCE
J26-5 J2-5 (LARGE / SINGLE BOARD
FILAMENT SUPPLY)
TP38
U49
1V = 1A
U31 FIL 1 FBK
J11-41 J31-41
TO FPGA U53
DATA
DATA
R244
BUFFER
J11-12 J31-12 BUFFER
TO FPGA U53 5V-3.3V
R514
J26-1 J2-1
FILAMENT FEEDBACK
- (LARGE / SINGLE BOARD
TP29 R518 J26-2 J2-2 FILAMENT SUPPLY)
1V = 1A
FIL1 REF
U90A
R515
R519
R224
J26-11 J2-11 DRIVE FOR RELAY K1
R507 +12V (SINGLE BOARD FILAMENT
+5V SUPPLY ONLY)
- R506
R242
R250
+ J26-10 J2-10 FILAMENT FAULT
U83A (LARGE / SINGLE BOARD
R505
FILAMENT SUPPLY)
DS23
U86 TP35 FIL 1 READY
J14-5 J32-5 1V = 1A 4 1
FROM FPGA U53 FIL2 REF LARGE / SINGLE BOARD FILAMENT SUPPLY
J14-6 J32-6 D/A U129 CONTINUED ON PAGE 2
FROM FPGA U53
R223
CONVERTER
J14-45 J32-45 3 2
FROM FPGA U53
R509
- R508 J28-8 J2-8

+
FILAMENT REFERENCE
J28-7 J2-7 (SMALL FILAMENT
U83B BOARD)
R510
TP36
1V = 1A
FIL2 FBK
+3.3V +5V
R213
R236
Q19
R517
J28-3 J2-3
R235
U85 FILAMENT FEEDBACK
- (SMALL FILAMENT
Q46 FLIP- R521 J28-4 J2-4 BOARD)
FLOP
U4 U90B
Q45
R516
R520
CPU POWER D69
SUPPLY J11-5 J31-5 R238
SUPERVISORY Q20
+12V
CIRCUIT +5V
R237
D70
R241
J28-10 J2-10 FILAMENT FAULT
R249
(SMALL FILAMENT
BOARD)
U25 D80
DS22
4 1
FIL 2 READY SMALL FILAMENT SUPPLY
CONTINUED ON PAGE 2
FROM CPU
ADDRESS BUS } DATA
LATCH
D72 U128
3 2
+12V
DS21
FIL 1
+12V SM/LRG
U62
R177
R248
R173 D7
J11-46 J31-46 A/D

R176
R172
TO FPGA U53 FLUORO MA F/B FROM PG 3

CONV R246
RAD (HIGH) MA F/B FROM PG 3 Q22
R247
RAD (LOW) MA F/B FROM PG 3
J14-36 J32-36 DRAWN DATE

FROM FPGA U53 G. SANWALD/J. LAPE 22 MAR 2013 FILAMENT DRIVE
CHECKED & MA CONTROL
CPU BOARD GENERATOR CONTROL BOARD DES.\MFG.\AUTH. MD-0981 REV A
L. FOSKIN
HVM LID
JW1 BOARD
R73 R74 3 +35V
R75
2 6.5 A
- SET IMAX
U1A
R48
R44
D6 R76 5.5 A
R72 1
-12V -12V R43 R47
J2-6 R65
- R95 R77 +12V +12V
J2-5 R66 +
Q6 Q12
U1B 25 uSec
FEEDBACK CURRENT R20 Q2 Q8
LOW FILAMENT
(1V=1A) C10 GATE 12 V
DRIVE * CURRENT
R71
R29
R33
TP4 R85
- TP3 0V
+IN
+
R84
U4B PWM 12 V HIGH FILAMENT
J2-1 R70 CURRENT
R91 REGULATOR
J2-2 R69 0V
Q9
R21
U3 Q3
+12V R90 -
Q7 Q13
* GATE DRIVE WAVEFORM @ TP3
ON FILAMENT BOARD(S)
R52
R51
12 VDC = FIL FAULT -
U2B
0 VDC = NO FIL FAULT
R88 U4A
R45 R49
R92
TP1 FILAMENT
R89
C22
R46
R50
FAULT
R13
R83
J2-10 R56
D27 -35V
R87 -
Q1 T1
RMS CONVERSION D12 J5-2 J4-2
U2A (U7, U8, D26, R55,
R58
R10 R57, R93, R94) CATHODE
D13 R97 * J5-1 J4-1 L
+12V D28 C L
K1 * J5-4 S
K1
J2-11 * K1: SINGLE BOARD FILAMENT ONLY J5-3
(SINGLE BOARD R97: LARGE FILAMENT BOARD ONLY
FILAMENT ONLY) FILAMENT SUPPLY (LARGE / SINGLE BRD.)
JW1
R73 R74 3 +35V
S
R75
2 6.5 A
- SET IMAX
U1A
R48
R44
D6 R76 5.5 A
R72 1 FILAMENT MOUNTING
-12V -12V R43 R47 BOARD
J2-8 R63
- R95 R77 +12V +12V
J2-7 R64 +
Q6 Q12
U1B FEEDBACK CURRENT Q2 Q8
C10 R20 GATE
(1V=1A)
DRIVE *
R71
R29
R33
TP4 R85
- TP3
+IN
+
R84
U4B PWM
J2-3 R68
R91 REGULATOR
J2-4 R67 Q9
R21
U3 Q3
+12V R90 -
Q7 Q13
R52
R51
12 VDC = FIL FAULT -

U2B
0 VDC = NO FIL FAULT
R88
R45 R49
U4A
R92
TP1 FILAMENT
R89
C22
R46
R50
FAULT
R13
R83
J2-10 R56
D27 -35V
R87 -
Q1 T1 PART OF HV MODULE
RMS CONVERSION D12 J5-4 J4-4
U2A (U7, U8, D26, R55,
R58
R10 R57, R93, R94)

D13 R96 J5-3 J4-3
DRAWN DATE
D28 G. SANWALD/J. LAPE 22 MAR 2013 FILAMENT DRIVE
FILAMENT SUPPLY (SMALL) DES.\MFG.\AUTH. MD-0981 REV A
L. FOSKIN
R194
R452 FL mA 1 V = approx. 2.0 mA OF
ANODE CURRENT
TP22
R193 FL MA FBK
NULL
R425
R424
- - R146 TO FLUORO MA F/B
R82 R163
+ (PG 1)
R423 R410
+ U52B
U57
TP52 1 V = approx. 100 mA OF
C234
80 mV = 20 mA ANODE CURRENT
RAD MA FBK
HV ANODE TP23
R589
BOARD R420 R148 R405
ANODE RAD MA FBK
S C
R406
L
- R170 TO RAD (LOW) MA F/B
1 R58 R150
+ (PG 1)
2 U56A
R171
C232
J3-1 J22-1 R426 R437 R436 3
C79 JW30
R439
-
C262
+
R30
J3-2 J22-2 R438 R435 U64B +15V_A +3.3V

NOTE 1
C82 TP24
R434
R431
R257
mA/mAs ANO TRIP
TEST
E18 JACK R395
-
-
R433
R430
- R174 TO RAD (HIGH) MA F/B
VOLTAGE U63
CLAMP + (PG 1)
U52A
R175
R396
+
E17
R432
J3-3 J22-3 R469 R468
U64A
R30
C281
R470
C270 -
+3.3V
J3-4 J22-4 R467 R466 NOTE 1
TP40
R501
R258
R483 -15V_A CATH TRIP J32-3 J14-3
C105 TO FPGA U53
R484
- J32-46 J14-36
TO FPGA U53
R500
L C U78
S
CATHODE R566 R565

HV CATHODE HVM LID
BOARD BOARD R482
R481
-
R567
+
U138
PART OF HV MODULE GENERATOR CONTROL BOARD CPU BOARD
ONE TUBE HV MODULES ARE SHOWN. TWO TUBE HV

MODULES WILL HAVE A SECOND PAIR OF HT OUTPUTS NOTE 1: A narrow pulse will be present at TP24 / TP40 if a anode or cathode over-current condition has been detected.
This pulse may be very difficult to detect as the high voltage will be shut down when the over-current condition is detected,
thus removing the fault condition.
DRAWN DATE
G. SANWALD/J. LAPE 22 MAR 2013 FILAMENT DRIVE
L. FOSKIN
+5V +12V
CS1, U10, U11
R283
SW1 * SW2 * INVERTER
+5V FAULT
R8
U49 U31 DETECTOR
DS1
DS10 560 / 680 VDC (+)
INVERTER
DSS READY FAULT
4 1
R24
DATA
BUFFER DATA U98
5V-3.3V BUFFER 3 2 U17, U18
J2-10 J1-10
U19, U22, U24
IGBT IGBT
+12V DRIVER SWITCH SWITCH
J14-50 J21-50 CIRCUIT AND (Q2) (Q4)
J14-51 J21-51 J2-6 J1-6 R40 FAULT
CURRENT
J14-53 J21-53 1 5 LATCH
J14-54 J21-54 HIGH SPEED (U1-U10, IGBT IGBT
U12 T1-T4, ETC).
SELECT SWITCH SWITCH
2 4 (Q1) (Q3)
J2-14 J1-14 K4
+12V
J2-2 J1-2 R41
+12V +12V
1 5 560 / 680 VDC (-)
PREP
DATA & CONTROL U13
INITIATED
R281
R282
R284
BUS 2 4
DUAL SPEED TUBE 1

STARTER CPU, K1-B TB2-3 SHIFT
U29 U19 DS11 DS8 DS9 BUFFERS, K5
PREP TUBE2 HI/LO R42
DRIVERS
J2-4 J1-4 1 5
K2-A
TUBE 2 K1 D47
SELECT U14
2 4 Q5
DATA J2-16 J1-16
DRIVER TB2-2 MAIN
R31
LATCH
K6 +12V
K2 K5
R32 TB2-1 COMM
J2-8 J1-8 C22
K6
+12V +12V K3
C1 K3
J2-1 J1-1 E5 E8 K1-A
J2-3 J1-3 K4 TUBE 2

K2-B TB3-3 SHIFT
J2-5 J1-5
J2-7 J1-7
E7 E6
J2-9 J1-9
C2 C3 C4
K7
J2-11 J1-11 TB3-2 MAIN
E14
+3.3V
+12V J2-12 J1-12
TB3-1 COMM
J2-13 J1-13
R280
DUAL SPD DUAL SPD

R227
J2-15 J1-15 STARTER ASSY STARTER ASSY

903255-12 903255-13 DUAL SPEED STARTER ASSEMBLY
J14-38 J21-38 J2-17 J1-17 904556-12 904556-13 903255-12 903255-13
TO
FPGA U53 CAPACITOR VALUE VALUE K3 K7 904556-12 904556-13
4 1
C1 30 uF 25 uF LOW SPD (1) CLOSED OPEN 36 uF 30 uF
U97
C2 30 uF 25 uF LOW SPD (2) CLOSED CLOSED 37.5 uF 31 uF
3 2 J2-19 J1-19 C3 15 uF 12.5 uF HIGH SPD (1) OPEN OPEN 6 uF 5 uF
C4 15 uF 12.5 uF HIGH SPD (2) OPEN CLOSED 7.5 uF 6 uF
CPU BOARD GENERATOR CONTROL BOARD DUAL SPEED STARTER BOARD
DSS BOARD PART NUMBER 72887710 * REFER TO CHAPTER 2 OF THE SERVICE MANUAL FOR
THE PROCEDURE TO SET THESE DIP SWITCHES DRAWN DATE
G. SANWALD/J. LAPE 27 MAR 2013 DUAL SPEED
CHECKED STARTER
DES.\MFG.\AUTH.
MD-0983 REV B
SHEET 1 OF 4
SW4 SW5
+5V +12V +12V LS TEST HS TEST
LEGACY MODE TUBE 1 TUBE 1 +12V +3.3V
+3.3V TP13 TP12
R283
R200
SW6 SW7 +3.3V SWITCHING
R8
U49 U31 LS TEST REGULATOR
HS TEST 1 Hz
TUBE 2 (U27, L8, ETC)
DS11 U24 TUBE 2 DS5
U20
DS10
READY
R125
4 1 DRIVER
DATA
DATA U98
BUFFER
BUFFER
5V-3.3V 3 2 J2-10
HIGH SPEED
J1-10
J11-11 J31-11 +12V DS8 1 4
HIGH SPEED CAN DATA LINK
J11-12 J31-12 U12
J2-6 J1-6 R40 REFER TO
J11-41 J31-41 2 3 MD-0990
J11-42 J31-42 J2-14 J1-14 R42
J2-2 R41 DS7

PREP LEGACY +3.3V
J1-2 MODE FIELD
DS9 UPGRADES U19
+12V 1 4 TUBE 2
+12V +12V PREP EEPROM
1 4
2 3 U14
J2-4 J1-4
TUBE 2
R282
R281
R284
DATA & CONTROL U13 MICRO
BUS 2 3 CONTROLLER
R115
+3.3V
U29 U19
DS11 DS8 DS9 J2-16 J1-16 R117 U31
J2-8 J1-8 R116

EEPROM
OFF=LEGACY MODE
ON=CAN bus MODE
DATA
DRIVER
LATCH SW2 * U17 SW8 *
C80 1 R174
R173
+12V +12V
J2-1 J1-1
J2-3 J1-3 SHIFT
J2-5 J1-5 REGISTER
J2-7 J1-7 6**
+3.3V
+12V J2-9 J1-9
8
R280
R227
J2-11 J1-11
J14-48 J32-48 J2-12 J1-12
TO SW1 * U18
J2-13 J1-13 SW3 * U16
FPGA U53 4 1 J2-15 J1-15
J2-17 J1-17
U97
3 2
SHIFT SHIFT
** DS2
J2-19 J1-19 REGISTER REGISTER
TP1 TP6
+12V +12V
1 1 J8
J5 2 2 C56
CANDSS
CPU BOARD GENERATOR CONTROL BOARD SUPPLY
LOW SPEED STARTER 2/DUAL SPEED STARTER 2 BOARD 903132-00 IN NON-CAN BUS MODE
* REFER TO CHAPTER 2 OF THE SERVICE MANUAL FOR

THE PROCEDURE TO SET THESE DIP SWITCHES DRAWN DATE
G. SANWALD/J. LAPE 27 MAR 2013 LOW SPEED/DUAL SPEED
** REFER TO CHAPTER 5 OF THE SERVICE MANUAL FOR THE CHECKED STARTER 2
DESCRIPTION OF LED DISPLAY OPERATION.
DES.\MFG.\AUTH.
MD-0983 REV B
SHEET 2 OF 4
SW4 SW5
LS TEST HS TEST
TUBE 1 TUBE 1 +3.3V
SW6 SW7
LS TEST
TUBE 2
HS TEST
TUBE 2 DS5
1 Hz HEARTBEAT
U20
R125
3.3V
J5-1 D20 D14

4 1
U30
R59
3 2 3.3V CAN DATA LINK
3.3V
REFER TO
D47 MD-0990
D12
DS4
CAN RX
U21
J5-5 U22 DS3
FROM J4 ON PAGE 1 OF MD-0990 CANH CAN TX
CAN-SPI
CAN CONTROLLER
J5-4 TRANSCEIVER
MICRO
J5-3 CANL CONTROLLER
J5-6
+12V +3.3V
TP13 TP12
+3.3V SWITCHING
REGULATOR
(U27, L8, ETC) DS6 C80
SW8 * R174
1
R173
SET WHEN OPERATING IN LOCAL

CONFIGURATION MODE.
SW2 * U17
6**
8
SHIFT
REGISTER
SW3 * U16
**7- segment LED display

DS2
SHIFT
REGISTER
SW1 * U18
+12V
J8-1 TP1 TP6

FROM J5 ON GENERATOR CONTROL BOARD J8- 2 C56
SHIFT
REGISTER
LOW SPEED STARTER 2/DUAL SPEED STARTER 2 BOARD 903132-00 AND 90313-03 IN CAN BUS MODE
* REFER TO CHAPTER 2 OF THE SERVICE MANUAL FOR

THE PROCEDURE TO SET THESE DIP SWITCHES
** REFER TO CHAPTER 5 OF THE SERVICE MANUAL FOR THE
DESCRIPTION OF LED DISPLAY OPERATION.
DRAWN DATE
CHECKED STARTER 2
DES.\MFG.\AUTH.
MD-0983 REV B
SHEET 3 OF 4
+12V
E18 E9 F2 L1
560 / 680 VDC (+) VBUS
R154
TP2
DC BUS VOLTAGE 560 / 680 VDC (-) 560 / 680 VDC (+)
560/680 VDC D49 R157
E19 E10 F1 K4 K2
560 / 680 VDC (-) K5
R61
K3 K1 K7
U24 D48 D50 U26A

U20
DRIVER
TB2
K1-A SHIFT 3 TUBE 1
K1-B
BUS VOLTAGE
MAIN 2
RECTIFIER BOARD +5V COMM 1
I MAIN
TP3
GND 4
MAIN CURRENT
I SHIFT K2-B
U36 Vref
TP4
SHIFT CURRENT
+3.3V I DC+ +5V

IDC TRIP TP18 I SENSE TB3 * FOR FUTURE
USE ONLY, NOT
560 / 680 VDC (+) APPLICABLE AT
TP20 U35 SHIFT 3 TUBE 2 THIS TIME
INVTRIP
I DC- K2-A
U10 U43 Vref U41 Vref U39 I SENSE
TP19
+12V
+
MAIN 2
+3.3V COMM 1 -
MICRO IGBT
CONTROLLER
DS1
SWITCH GND 4
(Q4) K4
INVERTER
FAULT J6 * R68
R24
1
IGBT U34 2
SWITCH IGBT 3
(Q2) SWITCH I SENSE R70
FET DRIVER (Q3) 4
CIRCUIT AND
ENABLE FAULT
R71
CURRENT
R69
TP10 E6
LATCH
DRIVER 1 GATE DRIVE
(U1-U11, U28,
TP11 T1-T4, ETC). IGBT
DRIVER 2 GATE DRIVE SWITCH
1 4 1 4
(Q1) E5/E7
SHIFT CAPACITORS
U23 U25
ENABLED 2 3 2 3
U40 I SENSE
560 / 680 VDC (-)
THERMAL 2 (FOR FUTURE USE ONLY, NOT APPLICABLE AT THIS TIME)
THERMAL 1 (FOR FUTURE USE ONLY, NOT APPLICABLE AT THIS TIME)
LOW SPEED STARTER 2/DUAL SPEED STARTER 2 BOARD 903132-00 AND 90313-03
DRAWN DATE
CHECKED STARTER 2
DES.\MFG.\AUTH.
MD-0983 REV B
SHEET 4 OF 4
FROM HV MODULE IN X-RAY C S C S
GENERATOR (CATHODE SIDE) L L
-TRANSFORMER - -TUBE CATHODE-
LOAD RESISTOR BOARD
+5V +5V DS3

+24V V+
R23
R22
J7-1 J3-1
U49 U31
J11-13 J31-13 +24V HIGH VOLTAGE
POWER SUPPLY
TO FPGA U53 J7-2 J3-2 SWITCH
CIRCUITS
+24V CIRCUITS
4 1
U100 J7-5 J3-5 DS1
J11-43 J31-43 +24V 3 2
TO FPGA U53 D4
J7-9 J3-9
4 1
FEEDBACK
U99 CIRCUITS
DATA
DATA 3 2 V+
BUFFER
LATCH
5V-3.3V J7-8 J3-8
+5V V+
TRIGGER
R24
J7-4 J3-4 CIRCUITS

J11-42 J31-42 1 JW6
TO FPGA U53 DS2
2 ADR ACTIVE
ADR INACTIVE
3
(No ADR tank)
J7-3 J3-3
R29
J7-6 J3-6
Q2
J7-7 J3-7
R30
J11-28 J31-28
FROM FPGA U53
LID, ADR MODULE H.V SWITCH BOARD
CPU BOARD GENERATOR CONTROL BOARD PART OF ADR MODULE
ADR (ADVANCED DOSE REDUCTION) MODULE CIRCUITS
DRAWN DATE
G. SANWALD 22 MAR 2013
ADR, FLUORO
CHECKED
SELECT, & POWER
MODE SELECT
DES.\MFG.\AUTH.
MD-0984 REV A
L. FOSKIN
SHEET 1 OF 2
NOTE: TP24 WILL NORMALLY BE HIGH AT APPROXIMATELY +12V.
IT WILL BRIEFLY PULSE LOW FOR APPROXIMATELY 100 MS
TO QUICKLY PULL IN THE RESONANT CONTACTOR.
TP24
RES CON PULL IN
(SEE NOTE)
J4-1 J16-1
+12V
J4-4 J16-4
R11
+12V +24V
U5 HOLD PULL
DS12
RES CON
U10 HLD DRIVER CIRCUIT FOR
FLUORO / RESONANT
CAN DATA LINK CONTACTOR
MICRO (U11, Q16, Q18,
REFER TO DRIVER
CONTROLLER R96, R98, R101,
MD-0990 J6-1
R102, C54, D6, etc.) K1
REFER TO
MD-0980
R108 J6-3 SHEET 2
DS2 FLUORO FLUORO / RESONANT

CONTACTOR CONTACTOR
AUXILIARY CPU BOARD INPUT DISTRIBUTION BOARD RESONANT BOARD
DRIVE FOR RESONANT CONTACTOR
U49 U29
J11-11 J31-11 DATA R59
DATA
FROM FPGA U53 BUFFER Q44
LATCH
3.3V-5V
R7
+12V +24V
ENERGIZING K2 ON GENERATOR +12V
CONTROL BOARD ENABLES PULL
DRIVE TO INVERTER BOARD
# 3 (MD-0980 SHT 2) K2 DRIVER CIRCUIT ENERGIZING K2 ON RESONANT
+12V TO ENABLE BOARD ENABLES OUTPUT OF
HOLD
INVERTER INVERTER BOARD # 3
BOARD #3 J13-1 (MD-0980 SHT 2)
(U141, Q51, Q56,
D27 Q57, R6, R88, R502,
C355, D79, etc.)
R590
K2
U131
J11-18 J31-18 R51 J13-2
FROM FPGA U53 Q3 DS24
INV3
R46
REFER TO MD-0980
PAGE 2 FOR K2 CONTACTS
CPU BOARD GENERATOR CONTROL BOARD RESONANT ASSEMBLY DRAWN DATE

ADR, FLUORO
POWER MODE SELECT CIRCUIT (USED ON 80 AND 100 KW UNITS ONLY) CHECKED
SELECT, & POWER
MODE SELECT
DES.\MFG.\AUTH.
MD-0984 REV A
L. FOSKIN
SHEET 2 OF 2
REFER TO PAGE 10 FOR LOGIC LEVELS, +24V
NOTES, ETC, REFERENCED BY
HEXAGONAL SYMBOL: +12V J24-19
J24-21
J24-13
J24-14
J24-23
J24-11
J24-12
J24-22
J24-16
J24-17
-12V J24-18
-24V J24-20
J24-31
J24-32
J24-33
J24-34
U49 U41 U42

J11-10 J31-10 J24-2
CHAMBER 4
J11-40 J31-40 J24-3
CHAMBER 3
J11-11 J31-11 J24-4 4
CHAMBER 2
J11-41 J31-41 J24-5
DATA CHAMBER 1
DATA
J11-12 J31-12 BUFFER DRIVER J24-6
BUFFER
3.3V - 5V START 7
J11-42 J31-42 J24-7
LEFT TO AEC BOARD
J11-13 J31-13 J24-8 (FOLLOWING PAGES)
MIDDLE 5
J11-43 J31-43 J24-9
RIGHT
TP33
PT REF 3
DATA & CONTROL
R209
BUS
U86 R487
J14-5 J32-5
- J24-10 PT
FROM J14-6 J32-6
DAC + REFERENCE
FPGA U53 J14-45 J32-45 U80B
R488
TP32
PT RAMP
2
U62
R208
TO FPGA J11-46 J31-46 A/D R189 J24-15 PT

U53 CONV RAMP
R188
TP31
PT STOP 1
+5V
R214
R210
J11-58 J31-58 R211 J24-1

TO FPGA
PT STOP
U53
U79A
5V - 3.3V
DRAWN DATE
G. SANWALD 10 APR 2013
CHECKED AEC
CPU BOARD GENERATOR CONTROL BOARD DES.\MFG.\AUTH.

L. FOSKIN
MD-0985 REV A
SHEET 1 OF 10
+500V
TP10 LEFT +/-300V
J1-2
+/-300 V AEC CH 1
+12V +12V +12V +12V +12V
12 J11-1
JW8 H.V. J1-1
+12V 1 +/-300/+500 V
RN6C
RN6D
RN6B
RN6A
RN6E
TP22 2 J1-3
+/-300V +45V +45 V
TP24 * H.V. 3 J11-4
START J1-8
DS5 DS1 DS2 DS3 DS4 RIGHT RESET/START
J11-3
MIDDLE J1-10
RN4A JW7 M FIELD SEL
J5-2 D6 J11-2
CH 4 1 L/R J1-9
TP9 2 R FIELD SEL
U3C 3 J11-6
J5-3 RN3D CONVERTER R/L J1-11
D5 L FIELD SEL
CH 3 +12V +24V CIRCUIT J11-5
R66
12 VDC TO 45 VDC TP11 J1-12
U3B R89 CHAMBER O/P
J5-4 D12 RN3C AND +/-300 / +500 VDC 13 J11-9
CH 2 J1-7
+45V CH 1 GROUND
J5-5
U3F
RN3A * INCLUDES U7 AND T1
D4
CH 1 S1D R90
D16
U3D
J5-6 D11 RN3B Q1
SET
R79
STRT
VALUE 11 LEFT +/-300V
J2-2
+/-300 V AEC CH 2
U3E U3A * START J12-1
JW6 H.V. J2-1
1 +/-300/+500 V
2 J2-3
+12V +24V +12V +24V +12V +24V +45V +45 V
3 J12-4
START J2-8
RIGHT RESET/START
J12-3
MIDDLE J2-10
JW5 M FIELD SEL
J5-7
* * * 1 J12-2
L/R J2-9
2 R FIELD SEL
D30 D40 D65 3 J12-6
J5-8 R/L J2-11
Q2 Q3 Q4 L FIELD SEL
J12-5
J5-9 TP12 J2-12
* * * R67 CHAMBER O/P
RIGHT MIDDLE LEFT 13 J12-9
J2-7
CH 2 GROUND
FROM
PAGE 1 S1C R68
LEFT +/-300V
J3-2
+/-300 V AEC CH 3
TP18 J13-1
TP17 2 TP20 8 JW4 H.V. J3-1
J5-19 CH 1 1 +/-300/+500 V
+24V J3-3
2 +45V +45 V
TP23 - STRT R1 S2A 3 J13-4
START J3-8
-
CH 2 RESET/START
J5-13 TP5 TP6 TP7
+
S4 RIGHT
+12V + J13-3
U4A MIDDLE J3-10
J5-17 U4B R2 S2B JW3 M FIELD SEL
R32 J13-2
C11 CH 3 1 L/R J3-9
* 2 R FIELD SEL
TP4 3 J13-6
C4 S2C R/L J3-11
R3 L FIELD SEL
J5-11 CH 4 J13-5
-12V CH 1 R53 TP13 J3-12
TP21 -
13 R57 CHAMBER O/P
S2D J13-9
J5-16 S3A
+ R4 J3-7
-24V CH 3 GROUND
U2B
R11 CH 2 S1B R58
TP3 3 TP19 9
TP2 10
S3B
J5-15 R54 LEFT +/-300V
J4-2
+/-300 V AEC CH 4
R12 J14-1
RN4C CH 3 JW2 H.V. J4-1
J5-10 +/-300/+500 V
1
2 J4-3
J5-1 S3C +45V +45 V
3 J14-4
START J4-8
R13 CH 4
-
RIGHT RESET/START
+12V
- J14-3
D27 MIDDLE J4-10
R56
+
+ JW1 M FIELD SEL
S3D U1A 1 J14-2
U2A L/R J4-9
RN4D
RN4B STRT 2 R FIELD SEL

3 R14 J14-6
3
-
7 R/L J4-11
+ 2 L FIELD SEL
J14-5
U6 TP14 J4-12
R35 CHAMBER O/P
SAMPLE 13 J14-9
J4-7
D22 & HOLD CH 4 GROUND
S1A R36
AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734614 DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE DRAWN DATE
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 10 APR 2013
CHECKED AEC
THE -24V OUTPUTS ON J1 TO J4 AND THE +/- 12V OUTPUTS ON J1 TO J4 DESIGNATES A FACTORY CONFIGURED LOGIC OR SIGNAL LEVEL. AEC
AND J11 TO J14 ARE NOT SHOWN ON THIS DIAGRAM. THESE ARE BOARDS ARE CONFIGURED AT THE TIME OF ORDER TO BE COMPATIBLE
DETAILED ON THE CONNECTOR PIN OUT TABLES IN CHAPTER 3D.
* WITH THE SPECIFIED AEC CHAMBER(S). FOR EXAMPLE, THE START DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SIGNAL TO THE CHAMBER MAY BE FACTORY CONFIGURED TO BE ACTIVE
LOW (0 V), ACTIVE HIGH +12 V, OR ACTIVE HIGH +24 V. SHEET 2 OF 10
AEC CH 1 AEC CH 3
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW1 JW5
RIGHT 3 R5 RN1 RN1 RIGHT 3 R6 RN2 RN2
3 6 7 2 J1-2 3 6 7 2 J3-2
SELECT ANODE (L) SELECT ANODE (L)
2 J1-5 2 J3-5
R69 -
CATH (L) R70 - CATH (L)
1 RN1 RN1 1 RN2 RN2
3 4 5 8 1 J1-1 3 4 5 8 1 J3-1
ANODE (M) ANODE (M)
+ +
U4A U5A
U2A J1-6 U3A J3-6
CATH (M) CATH (M)
R10
R50
J1-3 J3-3
ANODE (R) ANODE (R)
J1-4 J3-4
CATH (R) CATH (R)
MIDDLE MIDDLE
SELECT J1 (shell) SELECT J3 (shell)
R13 RN7 RN7 GROUND R14 RN8 RN8 GROUND
3 6 7 2 3 6 7 2
R9 - 6 R11 - 6
7 RN7 RN7 7 RN8 RN8
+ 5 4 5 8 1 + 5 4 5 8 1
U4B U5B
U2B U3B
R7
R8
RIGHT 1 J11-5 RIGHT 1 J13-5
ANODE (L) ANODE (L)
SELECT J11-6 SELECT J13-6
2 CATH (L) 2 CATH (L)
JW2 J11-3 JW6 J13-3
3 ANODE (M) 3 ANODE (M)
LEFT R27 RN9 RN9 J11-4 LEFT R28 RN10 RN10 J13-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
2 J11-1 2 J13-1
R22 - ANODE (R) R23 - ANODE (R)
1 RN9 RN9 1 RN10 RN10
3 4 5 8 1 J11-2 3 4 5 8 1 J13-2
U4C
+
CATH (R) U5C
+
CATH (R)
U8A J11-7 U9A J13-7
R16
R17
CH 1 CH 3
SELECT U4D SELECT U5D
CH 1 CH 3
OUT OUT
(NEXT PG) (NEXT PG)
AEC CH 2 AEC CH 4
LEFT 1 LEFT 1
SELECT SELECT
2 2
JW3 JW7
RIGHT 3 R43 RN11 RN11 RIGHT 3 R44 RN12 RN12
3 6 7 2 J2-2 3 6 7 2 J4-2
SELECT ANODE (L) SELECT ANODE (L)
6 J2-5 6 J4-5
R40 - CATH (L) R41 - CATH (L)
7 RN11 RN11 7 RN12 RN12
5 4 5 8 1 J2-1 5 4 5 8 1 J4-1
ANODE (M) ANODE (M)
+ +
U14A U15A
U8B J2-6 U9B J4-6
CATH (M) CATH (M)
R33
R34
J2-3 J4-3
ANODE (R) ANODE (R)
J2-4 J4-4
CATH (R) CATH (R)
MIDDLE MIDDLE
SELECT J2 (shell) SELECT J4 (shell)
R51 RN13 RN13 GROUND R52 RN14 RN14 GROUND
3 6 7 2 3 6 7 2
R47 - 2 R49 - 2
1 RN13 RN13 1 RN14 RN14
+ 3 4 5 8 1 + 3 4 5 8 1
U14B U15B
U16A U17A
R45
R46
RIGHT 1 J12-5 RIGHT 1 J14-5
ANODE (L) ANODE (L)
SELECT J12-6 SELECT J14-6
2 CATH (L) 2 CATH (L)
JW4 J12-3 JW8 J14-3
3 ANODE (M) 3 ANODE (M)
LEFT R57 RN15 RN15 J12-4 LEFT R58 RN16 RN16 J14-4
3 6 7 2 CATH (M) 3 6 7 2 CATH (M)
SELECT SELECT
6 J12-1 6 J14-1
R55 - ANODE (R) R56 - ANODE (R)
7 RN15 RN15 7 RN16 RN16
5 4 5 8 1 J12-2 5 4 5 8 1 J14-2
U14C
+
CATH (R) U15C
+
CATH (R)
U16B J12-7 U17B J14-7
R54
R53
CH 2 CH 4
SELECT U14D SELECT U15D
CH 2 CH 4
OUT OUT
(NEXT PG) (NEXT PG)
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE INPUT CIRCUITS; THE SIGNAL PROCESSING THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE CONTINUED ON THE NEXT PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 10 APR 2013
CHECKED AEC
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SHEET 3 OF 10
+5V +5V +5V +5V
8 7 6 5
RN3
RN3
RN3
RN3
1 2 3 4 U6
DS4 DS3 DS2 DS1
R67 CH 1 OUT
J5-2 2 18
CH 4 SELECT (FROM PREVIOUS
PAGE)
J5-3 R66 3 17
CH 3 SELECT
J5-4 R65 4 16
CH 2 SELECT
J5-5 R64 5 15
CH 1 SELECT
INVERTING
BUFFER
J5-6 D28 6 14
J5-7 R63 7 13
RIGHT SELECT
J5-8 R62 8 12
MIDDLE SELECT CH 2 OUT
J5-9 R61 9 11 (FROM PREVIOUS
LEFT SELECT PAGE)
+5V
R15
R36
TP1 15 R18
FROM +12V +5V

PAGE 1 U1 R21
R39
Q2
+5 V TP2 14
REGULATOR
R35
- 2
J5-13 1
+ 3 CH 3 OUT
TP6 TP7 U12A (FROM PREVIOUS
J5-17
PAGE)
R38
J5-11 R25
-12V
R42 R29
- 6
7
CH 1 + 5
SELECT U11B
R59 R1
TP4 2 TP3 6- R32
PT REF
3 CH 2 7
PT RAMP SELECT 5+
R31
C31
R26 U12B
J5-15
R37
R60 R2
- 2
J5-10 1 CH 3 CH 4 OUT
3 SELECT (FROM PREVIOUS
+
J5-1 U11A PAGE)

+12V R3
CH 4
R19
+5V SELECT
R20
6 SAMPLE
R4 & HOLD
TP5 D37
R12
R24
PT STOP
D38 R30
- 3
7
+ 2
U10
AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 737992. THIS DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
PAGE SHOWS THE SIGNAL PROCESSING CIRCUITS; THE INPUT THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. LOGIC LEVEL (0V = OFF, 5V = ON). G. SANWALD 10 APR 2013
CHECKED AEC
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS.
DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SHEET 4 OF 10
LEFT AEC CH 1
+5V +5V +5V +5V SELECT
JW8 NO CONNECTION N/C
+5V 1
J1-2
R51
R49
R50
R52
2 LEFT/RIGHT
3 J1-6
U6 RIGHT RIGHT/LEFT
R39
DS1 DS2 DS3 DS4 SELECT MIDDLE J1-3
R61 +12V JW7 MIDDLE
J5-2 2 18 SELECT
+12V
CH 4 SELECT START/ 1 J1-4
START RESET/START
2
R62 R40 D12 3 TP1 J1-8
J5-3 3 17 Q5 +12V
CH 3 SELECT 13
R1 J1-5
START CHAMBER O/P
J5-4 R63 4 16
CH 2 SELECT R38 CH 1 J1-7
Q4 SELECT -12V
J5-5 R64 5 15 J1-9
GROUND
CH 1 SELECT U1D R2
INVERTING -12V
BUFFER
LEFT AEC CH 2
SELECT
J5-6 D20 6 14 JW6 NO CONNECTION N/C
R66 1
J5-7 7 13 J2-2
2 LEFT/RIGHT
R67 3 J2-6
J5-8 8 12 RIGHT/LEFT
RIGHT
J5-9 R68 9 11 SELECT MIDDLE J2-3
JW5 MIDDLE
SELECT
+12V
1 J2-4
START RESET/START
2
+12V +12V +12V 3 TP2 J2-8
13 +12V
R3 J2-5
CHAMBER O/P
+12V +5V D11 D10 D9
CH 2 J2-7
R37
R36
R35
U3 LEFT MIDDLE RIGHT SELECT -12V
SELECT SELECT SELECT J2-9
+5 V GROUND
FROM U1C R4 -12V
REGULATOR Q3 Q2 Q1
PAGE 1
J5-13
LEFT AEC CH 3
SELECT
TP11 TP12 JW4 NO CONNECTION N/C
1
J5-17 J3-2
2 LEFT/RIGHT
TP7 8 CH 1 SELECT 3 J3-6
RIGHT RIGHT/LEFT
J5-11 SELECT MIDDLE J3-3
-12V - R11 JW3 MIDDLE
CH 2 SELECT SELECT
START/ +12V
+
1 J3-4
START RESET/START
U4A 2
R12 3 TP3 J3-8
CH 3 SELECT 13 +12V
* R5 J3-5
CHAMBER O/P
R13 CH 3
CH 4 SELECT J3-7
SELECT -12V
- J3-9
R14 GROUND
TP9 2 TP8 + U1B R6 -12V
3 U8B
J5-15 R30 - LEFT AEC CH 4

+ TP5 10 SELECT
J5-10 TP6 JW2 NO CONNECTION N/C
U4B
9 1
J4-2
J5-1 2 LEFT/RIGHT
+5V +12V 3 J4-6
- RIGHT RIGHT/LEFT
SELECT
-
R32
R31
+ MIDDLE J4-3
JW1 MIDDLE
R69
R34
+
SELECT
U7A +12V
U8A 1 J4-4
START/ START RESET/START
6 2
D25 3 TP4 J4-8
R33 +12V
TP10 13
R7 J4-5
CHAMBER O/P
D27 3
7
-
SAMPLE CH 4 J4-7
+ 2 & HOLD SELECT -12V
U9 J4-9
GROUND
U1A R8 -12V
AEC BOARD
CHECKED AEC
DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SHEET 5 OF 10
+12V +12V +45V TP4
+500V
AEC CH 1
J1-3 J5-3 +12V J1-1
U1E U1F +300V +500V +500 V
J1-19 J1-19 J1-2
R22 R47 +300V +300 V
R31
J1-15 J1-15 +12V J1-3
+45V +45 V
J1-17 J1-17 J1-4
R27
+12V +12 V
J1-1 J5-1 J1-5
-12V -12 V
16 J1-6
R15
+12V J1-4 J5-4
R32
-24V -24 V
+12V +12V +12V +12V J1-7
-12V J1-2 J5-2 -12V TP3 GND
6-
7 J1-8
R23
-24V -24V R28 5+ FEEDBACK RESET/START
D45 D46 D47 START 1
R16
R18
R20
R21
J1-9
U1B RIGHT 1 RIGHT
CONVERTER CIRCUIT J1-10
U1D 12 VDC TO 45 VDC, MIDDLE 1 MIDDLE
CH 4 300 VDC, 500 VDC, J1-11
J5-2 D44 AND -1000 VDC LEFT 1 LEFT
D43 J1-12
U1C SIGNAL 1 CHAMBER O/P
CH 3 INCLUDES U3, Q1-Q4,
U2C
U2D
U2A
J5-3 D37 TO D1-D6, D12-D21,
D42
U1B SHT 8 AND T1 AEC CH 2
CH 2
J5-4 D38 5.1V REFERENCE J2-1
D41 +500V +500 V
U1A J2-2
CH 1 +300V +300 V
R19
R10
R24
J5-5 D39 J2-3
D40 +45V +45 V
J2-4
+12V +12 V
+12V J2-5
-1000V -12V -12 V
J2-6
-24V -24 V
J2-7
R14
START 1~ J2-1 J6-1 GND
START 1
D36 NEXT PG. J2-8
J2-3 J6-3 START 2 RESET/START
J5-6 TO START RIGHT 1_ RIGHT 1 J2-9
SHT 8 FROM J2-5 J6-5 RIGHT 2 RIGHT
MIDDLE 1_ MIDDLE 1 J2-10
SHT 7 J2-7 J6-7 MIDDLE 2 MIDDLE
+12V +24V LEFT 1_ J2-11
LEFT 1
LEFT 2 LEFT
J2-9 J6-9 J2-12
SIGNAL 1_ TO SHT 8 SIGNAL 1 SIGNAL 2 CHAMBER O/P
R29*
R90*
START 2~ J2-11 J6-11
START 2
NEXT PG. J2-13 J6-13
RIGHT 2_ RIGHT 2 AEC CH 3
R42 FROM J2-15 J6-15
FROM MIDDLE 2_ MIDDLE 2 J3-1
PAGE 1 D69* SHT 7 +500V +500 V
R43 J2-17 J6-17 J3-2
LEFT 2_ LEFT 2 +300V +300 V
Q4 J3-3
J2-19 J6-19
SIGNAL 2_ TO SHT 8 SIGNAL 2 +45V +45 V
D34 TO AEC INPUT J3-4
START 3~ J2-2 J6-2 +12 V
J5-15 START 3 CONNECTORS J1 -J4 +12V
NEXT PG. J3-5
JW29 J2-4 J6-4 -12V -12 V
J5-10 FROM RIGHT 3_ RIGHT 3 J3-6
D33 FROM J2-6 J6-6 -24V -24 V
SHT 8 JW30 MIDDLE 3_ MIDDLE 3 J3-7
J5-1 SHT 7 GND
J2-8 J6-8
LEFT 3_ LEFT 3 J3-8
D22 START 3 RESET/START
J2-10 J6-10 J3-9
SIGNAL 3_ TO SHT 8 SIGNAL 3 RIGHT 3 RIGHT
JW31 START 4~ J2-12 J6-12 J3-10
J5-19 START 4 MIDDLE 3 MIDDLE
+24V D24 NEXT PG. J2-14 J6-14 J3-11
JW32 RIGHT 4_ RIGHT 4 LEFT 3 LEFT
J3-12
TP1 FROM J2-16 J6-16 SIGNAL 3 CHAMBER O/P
MIDDLE 4_ MIDDLE 4
J5-13 TP2 D26 SHT 7 J2-18 J6-18
+12V LEFT 4_ LEFT 4
J5-17 JW33 J2-20 J6-20 AEC CH 4
SIGNAL 4_ TO SHT 8 SIGNAL 4
D28 J4-1
JW34 +500V +500 V
TP5 J4-2
+300V +300 V
J5-11 J4-3
-12V D30 +45V +45 V
J4-4
+12V +12 V
J5-16 JW35 J4-5
-24V D32 -12V -12 V
JW36 J4-6
-24V -24 V
J4-7
TP5 GND
J4-8
START 4 RESET/START
-1000V J4-9
RIGHT 4 RIGHT
J4-10
MIDDLE 4 MIDDLE
J4-11
LEFT 4 LEFT
J4-12
SIGNAL 4 CHAMBER O/P
AEC BOARD J7-1 J7-2 J7-3 J7-4 AEC INTERFACE BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD DRAWN DATE
SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 10 APR 2013
734630. THE AEC BOARD CIRCUITS ARE CONTINUED ON PAGES CHECKED AEC
7 AND 8.
* NOT FITTED ON ALL MODELS. REFER TO SUP734654 IN THE FRONT OF
THIS MANUAL FOR DETAILS DES.\MFG.\AUTH.
REFER TO CHAPTER 3D FOR INSTALLATION AND CALIBRATION DETAILS. L. FOSKIN
MD-0985 REV A
SHEET 6 OF 10
J5-7
FROM J5-8
PAGE 1
J5-9
+12V +24V +12V +24V +12V +24V
R29*
R29*
R29*
R90*
R90*
R90*
R28 R26 R27
R9 R8 R5
Q2 Q1 Q3
D31 D9 D17
JW5 JW13 JW21

D19 LEFT 1_ D1 MIDDLE 1_ D8 RIGHT 1_
JW6 JW14 JW22
D20 D2 D10
JW7 JW15 JW23

JW8 JW16 JW24
J2 J2 J2
D23 SHT D4 SHT D11 SHT
6 6 6
JW9 JW17 JW25
JW10 JW18 JW26
D27 D6 D15
JW11 JW19 JW27

JW12 JW20 JW28
R12 R6 R10
D35 D13 D18
R111 JW73 R110 JW72 R109 JW71

U19C U19B U19A
R104 JW68 R103 JW67 R112 JW74

U17B U17A U19D
R99 JW63 R107 JW70 R105 JW69

U16D U16C U16B
R102 JW66 R101 JW65 R100 JW64

U16A U17D U17C
R66 R65 R47 R48 R62 R69 R57 R64
2- 6- 2- 6-
JW47 R88, R67 1 S/S OUT 1 JW52 R74, R46 7 S/S OUT 2 JW57 R73, R80 1 S/S OUT 3 JW62 R87, R54 7 S/S OUT 4
START 1~ 3+ SHT 8 START 2~ 5+ SHT 8 START 3~ 3+ SHT 8 START 4~ 5+ SHT 8
SHT 6 U6A SHT 6 U6B SHT 6 U14A SHT 6 U14B
R38
R44
R68
R59
AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES” THAT ARE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD DRAWN DATE
SWITCHED ON / OFF BY APPLYING THE APPROPRIATE LOGIC LEVEL. G. SANWALD 10 APR 2013
6 AND 8.
* NOT FITTED ON ALL MODELS. REFER TO SUP734654 IN THE FRONT OF
THIS MANUAL FOR DETAILS DES.\MFG.\AUTH.
MD-0985 REV A
SHEET 7 OF 10
START
FROM SHT 6 R50E R52 JW43
R50A
R36 U4C
R50F
R50B - 6
- 6 7
JW2 C4 7 5 JW44 R86
+ 5
+
SIGNAL 1_
R1 R50D START R50G JW45 FROM SHT 6
U7B
R41
U5B FROM SHT 6
R37
JW3 R45
- 2 JW46 S/S OUT 1
R50C
1
R50H
CH 1 3 FROM SHT 7
D51
+
FROM SHT 6 U4A

U7A
R120 R34 2
1
-
C9
+ 3
C39 U3B
R121 U5A R40
R91
C48
START
R118 FROM SHT 6 R51A R75 JW48
R51E
R114 R58 U4D
R51B
R116 2 R51F - 6
6 1
-
- 6 7
7
-
3 JW39 C12 7 5 JW49 R85
+
5
+
SIGNAL 2_
5 +
R51H FROM SHT 6
+
R2 START U11B R51C JW50
R39
U18A
U10B FROM SHT 6
R31
U18B JW40 R49
- 2 JW51 S/S OUT 2
R51G
1
R51D
CH 2 3 FROM SHT 7
D56
+
FROM SHT 6 U4B

U11A
R113 R32 2
1
-
C20
+ 3
C36 U3A
R108 U10A R60
R92
START
FROM SHT 6 R70A R71 JW53
R70E
R76 U12C
R70B
R70F - 6
+12V 2 - 6 7
JW37 C14 7 5 JW54 R84
5
+
SIGNAL 3_
3 TP4 R3
+
R70H START FROM SHT 6
U8B R70C JW55
R56
U9B
R25
FROM SHT 6
R30
TP3 JW38 R72
2
- JW56 S/S OUT 3
R70G
1
R70D
R53 CH 3 3 FROM SHT 7
D59
+
PT RAMP FROM SHT 6 U12A
R17 U8A
TO R98 R33 2
PT REF 1
-
C19
SHT 6 + 3
PT STOP C33 U3C
R97 U9A R55 +12V
R93
R106
D49 START
R24
FROM SHT 6 R82A R81 JW58
R82E
R19 R77 U12D
3
7
-
R82B
2 R82F - 6
+
- 6 7
JW41 C15 7 5 JW59 R83
SIGNAL 4_
R22
+
U2 + 5
D50 R4 R82H START R82C JW60 FROM SHT 6
U15B
R63
U13B FROM SHT 6
R79
JW42 R61
- 2 JW61 S/S OUT 4
R82G
1
R82D
CH 4 3 FROM SHT 7
D65
+
FROM SHT 6 U12B

U15A
R96 R35 2
1
-
C21
+ 3
C32 U3D
R95 U13A R78
R94
AEC BOARD
THIS SHEET APPLIES TO AEC BOARD ASSEMBLY 734654, WHICH DESIGNATES AN ANALOG SWITCH. THESE ARE I.C. “SWITCHES”
THAT ARE SWITCHED ON / OFF BY APPLYING THE APPROPRIATE DRAWN DATE
CONSISTS OF AEC INTERFACE BOARD 728399 AND AEC BOARD LOGIC LEVEL (0V = OFF, 12V = ON). G. SANWALD 10 APR 2013
6 AND 7.
DES.\MFG.\AUTH.
MD-0985 REV A
SHEET 8 OF 10
+5V LEFT +12V
+5V +5V AEC CH 1
+12V JW8
1 J1-8
+12 V
R39
2
R49
R50
D29 3 J1-2
LEFT/RIGHT
U6 STRT RIGHT J1-6
DS1 DS2 INVERTED RIGHT/LEFT
R40 JW7
J5-2 R61 2 18 R71 Q5 J1-4
Q7 1 START RESET/START
+12V +12V 2 J1-3
R62 3 MIDDLE MIDDLE
J5-3 3 17
J1-11
D28 D12 13 TP1 PORTRAIT PORTRAIT
J5-4 R63 4 16 J1-13
CH 2 INVERTED INVERTED
PORTRAIT START CH 1
R2 R1 J1-5
R64 R70 R38 CHAMBER O/P
J5-5 5 15 Q6 Q4 U1D
CH 1 J1-7
INVERTING -12 V
BUFFER J1-9
GROUND
-12V
J5-6 D20 6 14
J5-7 R66 7 13 LEFT +12V AEC CH 2

J5-8 R67 8 12 JW6
1 J2-8
R68 +12 V
J5-9 9 11 2
3 J2-2
LEFT/RIGHT
+12V +12V +12V
RIGHT J2-6
RIGHT/LEFT
JW5
D11 D10 D9 J2-4
1 START RESET/START
R37
R36
R35
J5-19 2 J2-3
+24V LEFT MIDDLE RIGHT 3 MIDDLE MIDDLE
J2-11
J5-13 Q3 Q2 Q1 13 TP2 PORTRAIT PORTRAIT
+12V TP11 TP12 J2-13
FROM INVERTED INVERTED
J5-17 CH 2
PAGE 1 R4 R3 J2-5
CHAMBER O/P
U1C J2-7
J5-11 -12 V
-12V
J2-9
GROUND
J5-16 -12V
-24V 8 TP7
STRT
R11 S2B
TP8 2 CH 1
TP9 3
U2A
J5-15 R30 R12
CH 2
J5-10 R32 -
+ R4 U2B
U8B
TP6 9
+5V TP5 10
R69
-
-
J5-1 +
+
U4A
U4B -
D27
-
+12V +
+
U7A
D25 R33 U8A STRT
R34
R31
- 3
7
+ 2
SAMPLE
U9 & HOLD
TP10 6
AEC BOARD
CHECKED AEC
DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SHEET 9 OF 10
NOTE
REMARKS
REFERENCE
1 “HIGH” (APPROXIMATELY 3.3 VDC) = NO PTSTOP (PHOTOTIMER STOP) SIGNAL RECEIVED FROM AEC BOARD. “LOW” (APPROXIMATELY 0 VDC) = PTSTOP SIGNAL RECEIVED FROM AEC BOARD.
2 AEC RAMP. THIS IS A SIGNAL RAMPING FROM 0 TOWARD +10 VDC. THE ACTUAL MAGNITUDE WILL DEPEND ON THE AEC TECHNIQUE.
3 AEC REFERENCE VOLTAGE, 0 TO +10 VDC, DEPENDING ON AEC TECHNIQUE. THE LENGTH OF THE AEC EXPOSURE WILL BE PROPORTIONAL TO THE AEC REFERENCE VOLTAGE.
4 “HIGH” (> 10 VDC) = AEC CHANNEL DESELECTED, “LOW” (APPROXIMATELY 0 VDC) = AEC CHANNEL SELECTED.
5 “HIGH” (> 10 VDC) = L, M, R, FIELD DESELECTED, “LOW” (APPROXIMATELY 0 VDC) = L, M, R, FIELD SELECTED.
6 “HIGH” (> 10 VDC) = NO AEC STOP REQUEST (INSUFFICIENT RAMP TO TERMINATE AEC EXPOSURE), “LOW” (APPROXIMATELY 0 VDC) = AEC STOP REQUESTED (AEC EXPOSURE TERMINATED).
7 “HIGH” (> 10 VDC) = AEC START NOT REQUESTED, “LOW” (APPROXIMATELY 0 VDC) = AEC START REQUESTED.
8 THE VOLTAGE AND MAGNITUDE OF THE RAMP AT THIS POINT SHOULD BE APPROXIMATELY THE SAME AS THE PT RAMP OUTPUT, NOTE REFERENCE 2 .
9 THIS WILL BE A NEGATIVE DC VOLTAGE OR RAMP, DEPENDING ON AEC CHAMBER OUTPUT. THE MAGNITUDE OF THE DC VOLTAGE OR RAMP IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
10 THIS WILL BE A POSITIVE DC VOLTAGE OR RAMP, DEPENDING ON AEC CHAMBER OUTPUT. THE MAGNITUDE OF THE DC VOLTAGE OR RAMP IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
11 R79 ADJUSTS THE +45V, +300V, AND +500V OUTPUTS FROM THE DC TO DC CONVERTER CIRCUIT. REFER TO CHAPTER 3D FOR DETAILS.
12 THE VOLTAGE AT TP22 SHOULD BE APPROXIMATELY AS SHOWN IN FIGURE 1 (BELOW). THE MAXIMUM DUTY CYCLE WILL BE APPROXIMATELY 45%, DEPENDING ON THE LOAD ON THE HV SUPPLIES.
13 THE VOLTAGE AT THIS TEST POINT IS THE OUTPUT OF THE AEC CHAMBER. REFER TO THE AEC CHAMBER MANUFACTURERS DOCUMENTATION FOR DETAILS.
14 THIS WILL BE A POSITIVE DC VOLTAGE. THE MAGNITUDE OF THE DC VOLTAGE IS DEPENDENT ON THE AEC TECHNIQUE IN USE.
15 THIS IS THE START SIGNAL. “HIGH” (5 VDC) = START = ANALOG SWITCHES CLOSED, “LOW” (0 VDC) = START = ANALOG SWITCHES OPEN.
16 THIS WILL BE A VOLTAGE BETWEEN 0 AND 5.1 V, DEPENDING ON THE SETTING OF THE ACTIVE POTENTIOMETER R10, R19, OR R24..
200 kHz
12 VDC
0 VDC
FIGURE 1
DRAWN DATE
CHECKED AEC
DES.\MFG.\AUTH.
L. FOSKIN
MD-0985 REV A
SHEET 10 OF 10
NOTE 1: THIS WILL BE A POSITIVE DC VOLTAGE. THE MAGNITUDE WILL
VARY DEPENDING ON THE DOSE VALUE.
U25
DIG I/O BRD ABS

FROM MD-0987 U12A
RM I/O BRD ABS DATA

FROM MD-0977 LATCH U49
U12B J31-43 J11-43
FROM FPGA U53
U12C J31-11 J11-11

JW4 * R300 NOTE 1 FROM FPGA U53
TP10
JW5 * R301
R288
U12D
U28
J31-41 J11-41
DATA FROM FPGA U53
JW3 * BUFFER
1 C146 3.3V-5V
U102A J31-12 J11-12
R299 R298
2 - FROM FPGA U53
R309 DATA
+
3 R292 R294 LATCH
JW8 * U1A U102B J31-42 J11-42
4 FROM FPGA U53
JW7 *
R293
R308
U102C J31-13 J11-13
+12V
R270
FROM FPGA U53
R286
J1-5 TP5
D9
R269 ABS NOTE 2
J1-2 R287
PMT / PHOTO DIODE / U62
J1-4
R305
PROPORTIONAL DC - R295 U102D
VIDEO INPUT & J1-3 C14
+ SAMPLE AND HOLD
AEC OUTPUT -12V -
CIRCUIT (U70, U75, A/D J31-46 J11-46
U1B TO FPGA U53
+ CONVERTER
R296
J1-1 U139 ETC.)
U101B
R35
1 NOTE 2: A DC VOLTAGE WILL BE PRESENT FROM TP5 TO GROUND WHEN OPERATING
J6
2 JW1 *
WITH ABS ON. THIS VOLTAGE WILL TYPICALLY RANGE FROM 0.5 TO 5 VDC, AND WILL
COMPOSITE VIDEO VARY DEPENDING ON THE NOMINAL DOSE VALUE.
INPUT 3 R26
C135 R4
D6
-
R3
+
J31-52 J11-52
FROM FPGA U53
C134 R5 U101A DIGITAL J31-23 J11-23
FROM FPGA U53
POTENTIOMETER
* J31-53 J11-53
*
R267
R278
R268
REFER TO CHAPTER JW2 * FROM FPGA U53

JW10
JW9
3E OF SERVICE MANUAL U5
FOR DETAILS ON
ABS INPUT CONNECTIONS
* REFER TO CHAPTER 3E OF THE SERVICE MANUAL TO DETERMINE REQUIRED JUMPER

POSITIONS FOR THESE CONNECTORS. THE DEFAULT JUMPER SETTINGS WHEN THE UNIT
IS SHIPPED ARE SHOWN ABOVE INDICATED BY , , , , OR OPEN SUCH AS JW10.
DRAWN DATE
ABS
G. SANWALD/J. LAPE 28 FEB 2013
(AUTOMATIC BRIGHTNESS
CHECKED STABILIZATION)
DES.\MFG.\AUTH.
L. FOSKIN
MD-0986 REV A
SHEET 1 OF 1
+5V
+15V_A
+24V J25-11
J25-13
J25-17
J25-15
J25-9
J25-21
-15V_A J25-23
U84
J11-6 J31-6 R523 J25-10
J11-35 J31-35 R522 J25-12
DATA
BUFFER
3.3V - 5V
J11-3 J31-3 R232 J25-18
U92
J11-10 J31-10 R531 J25-1
J11-40 J31-40 R530 J25-2 CONTINUED
ON PAGES
J11-11 J31-11 R529 J25-3
2 TO 19
J11-41 J31-41 R528 J25-4
DATA
J11-12 J31-12 BUFFER R527 J25-5
3.3V - 5V
J11-42 J31-42 R526 J25-6
J11-13 J31-13 R525 J25-7
J11-43 J31-43 R524 J25-8
EXPOSURE ENABLE J25-14

DATA & CONTROL TO MD-0979 PAGE 1
BUS
HV ON FROM J25-19
MD-0980 PAGE 1
DIG I/O BRD ABS J25-20

TO MD-0986
D8 J25-22
+3.3V
R583
+5V
U69
DS20
R184
DIO
BOARD
TO FPGA J11-60 J31-60
U53 12 mA
U74
5V - 3.3V
DRAWN DATE
G. SANWALD 10 APR 2013 DIGITAL
CHECKED INTERFACE
DES.\MFG.\AUTH.
L. FOSKIN MD-0987 REV A
SHEET 1 OF 19
+5V +15V +24V
J1-11
J1-13 J3-7
J1-17
J3-1
J1-15
J3-3
TP1 TP2
-15V U7
+24V
R2 J2-20
J1-20
MUX R3 J2-21
R11
+24V J3-9
J1-14
1 5
R1
U16
3 +24V +24V +24V +24V +24V +24V +24V
2 4
5 1 J3-10
2
U3B JW1 U10 F1 J2-1
R10
R12
R13
R14
R15
R16
4 6 1
J1-19 5 4 2 +24V
DS4 DS6 DS7 DS8 DS9 DS10
FROM
R17
PAGE 1 EXON PFL HCF PREP GEN TOMO
J1-1 U4 U6 J3-5
READY
J1-2 J2-7
1 5
J1-3
J1-4 J2-3 U14
J1-5 DATA DRIVER J2-4 2 4

LATCH J3-6
J1-6 J2-5
ADDRESS DECODER
J1-7 CIRCUITS J2-6
(U1, U2, U3A, U6A) J2-22
J1-8
J1-10 J3-2
J1-12
+24V J3-4
+24V
J1-18 J3-8
U8
R6
R7
J2-9
BUFFER 5 1 DS1
J1-9 U13
OFL
J1-21 4 2 +24V
+24V
J1-23
R5
U9 SW1
R8
J2-23
5 1 DS2
BUFFER U12
STOP J2-2
4 2 EXP. +24V
+24V J2-10
R4
J2-12
R9
5 1 DS3
U11
O.EXP
4 2
J2-11
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 733752.

DRAWN DATE
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL G. SANWALD 10 APR 2013 DIGITAL
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J3. CHECKED INTERFACE
DES.\MFG.\AUTH.
SHEET 2 OF 19
+24VR +24VR
+5V +15V +24V +24VR
J3-25 J2-1
J1-11 J3-27 J2-3
J1-13 J3-29 J2-5

D6 J3-31 J2-7
J1-17 F1
J3-33 J2-9
J1-15 D5 J3-35 J2-11
R10
Q1 J2-13
J2-17
-15V
R9
D3 U17
12 U10D 11 J2-19
J1-19 MONOSTABLE
13 TIMER J2-18
D4 J2-20
U14 U16
J2-14
J1-1
J2-12
J1-2
J2-10
J1-3
J2-8
J1-4 DATA
DRIVER J2-6
J1-5 LATCH
J2-4
J1-6 ADDRESS DECODER +24V +24VR
J2-2
J1-7 CIRCUITS
(U1, U2, U9, U10C)
J1-8
R15
J1-10
U13 U15 R13 J3-34
J1-12 Q2 J2-23
J3-32
J1-18 J3-30
D1 J3-28
DATA DRIVER J3-26
LATCH
J3-36
FROM
PAGE 1
+24V +24VR
+24VR +24VR +24VR
U12
R14
R12
J1-9 Q3
BUFFER 5 1 R1 5 1 R2 5 1 R3 J2-16
J3-47
J1-21 J2-22
U3 U4 U5
J1-23 D2
4 2 4 2 4 2 J3-41
J3-39
U11 SW1
J3-37
J3-38
BUFFER J3-40
J3-42
J3-44
5 1 R4 5 1 R5 5 1 R6 J3-46
U6 U7 U8
4 2 4 2 4 2 J2-15
+24VR
J3-45
J3-43
R16
J2-24
J1-22 J3-48
J1-20 J2-21
DIGITAL I/O BOARD

DRAWN DATE
DES.\MFG.\AUTH.
SHEET 3 OF 19
+24VR +24VR
+5V +15V +24V +24VR
J3-25 J2-1
J1-11 J3-27 J2-3
J1-13 J3-29 J2-5

D6 J3-31 J2-7
J1-17 F1
J3-33 J2-9
J1-15 D5 J3-35 J2-11
R10
Q1 J2-13
J2-17
-15V
R9
D3 U17
12 U10D 11 J2-19
J1-19 MONOSTABLE
13 TIMER J2-18
D4 J2-20
U14 U16
J2-14
J1-1
J2-12
J1-2
J2-10
J1-3 J4-1 J5-3
J2-8
J1-4 DATA
DRIVER J2-6 J4-2 J5-7
J1-5 LATCH
J2-4
J1-6 ADDRESS DECODER +24V +24VR
J2-2
J4-4 J5-2
J1-7 CIRCUITS
(U1, U2, U9, U10C) J4-5 J5-8
J1-8
R15
J1-10 J4-7 PREP SW J5-5
J1-12 U13 U15 R13 J3-34 J2-23
FROM J9 ON
Q2
J3-32 CONSOLE J4-8 X-RAY SW
J1-18 J3-30 CONNECTOR J4-10 “ON” SW
D1 J3-28 BOARD
DATA DRIVER J3-26
J4-11 “OFF” SW
LATCH
J3-36 J4-12 COMMON
J4-3
+24V +24VR J4-9
+24VR +24VR +24VR
U12
R14
R12
J1-9 Q3
BUFFER 5 1 R1 5 1 R2 5 1 R3 J2-16
J3-47
J1-21 J2-22
U3 U4 U5
J1-23 D2
4 2 4 2 4 2 J3-41
FROM J3-39
PAGE 1 U11 SW1
J3-37
J3-38
BUFFER J3-40
J3-42
J3-44
5 1 R4 5 1 R5 5 1 R6 J3-46 +15V
U6 U7 U8
4 2 4 2 4 2 J2-15 J6-1
+24VR
J3-45 J6-2
J3-43
J6-3
R16
J2-24
J1-22 J3-48 J6-4

J1-20 J2-21
J6-6
J6-7
THE CIRCUITS WITHIN THE DASHED LINES ARE IDENTICAL TO THOSE J6-8
ON PAGE 3. REFER TO PAGE 3 FOR THE FULL SIZED DIAGRAM TO X-RAY
MINI-CONSOLE.
(SHEET 5)
J6-11
+15V
J6-12
J7-2 J6-9
J6-10
J7-3
J6-13
J7-1 TO MINI-CONSOLE X-RAY
EXPOSURE INDICATOR. J6-5
J7-4
(SHEET 5) J6-14
J7-5
U18 U19
J7-7
DATA
DRIVER
LATCH
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 735921. DRAWN DATE
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J3, J5.
DES.\MFG.\AUTH.
SHEET 4 OF 19
J1-1
J1-2 DS1 DS2 DS3 DS4
RAD FLUORO PREP PWR

EXP EXP ON
LS1 LS2
J1-4
J1-6
J1-3
J1-5
J1-7
FROM J6 J1-8
(SHEET 4)
J1-9
J1-10
ON
OFF
J1-13
J1-11 J2-1
J2-2
J1-12
HAND
PREP J2-3 SWITCH
(OPTIONAL)
X-RAY
J1-14 J2-4
X-RAY MINI CONSOLE
J3-2
J3-3 DS1 DS2
RAD FLUORO
EXP EXP
LS1 LS2
FROM J7
(SHEET 4) J3-1
J3-5
J3-7
J3-4
MINI CONSOLE X-RAY EXPOSURE INDICATOR
DRAWN DATE
THE OPTIONAL “X-RAY MINI CONSOLE” AND OPTIONAL “MINI CONSOLE X-RAY EXPOSURE INDICATOR” CHECKED INTERFACE
ARE TYPICALLY USED WITH DIGITAL IMAGING SYSTEMS THAT HAVE INTEGRATED GENERATOR
CONSOLE CONTROL FUNCTIONS. DES.\MFG.\AUTH.
SHEET 5 OF 19
+24V
F1 J2-14
+5V +15V +24V +5V(A)
J1-11 U12
J1-13 +5 V J2-21
REGULATOR
J1-17
+15V J2-8
J1-1
1 5
J1-2
GENERATOR U7 +15V J2-22
J1-3
U4 U6
READY
J1-4 2 4 1 5
DS4
J1-5 EXPOSURE IN U10
R2 PROCESS (EIP)
J1-6 ADDRESS DECODER 2 4
J1-7 CIRCUITS DATA DS3
FROM (U1, U2, U3A, U5A) DRIVER
LATCH R1 J2-11
PAGE 1 J1-8
J1-10 +24V J2-13
J1-12
R9
J1-18
X-RAY
DS2 J2-15
R8
J1-14
J2-4
R6
5 1
J3-1
U16
J2-5
R7
4 2
J3-4
U8 5 1 J2-6
U14 J3-3
J1-9
4 2 J2-16
J1-21 J3-10
BUFFER
J1-23 5 1 J2-18
U15 J3-11
+5V(A) 4 2 J2-17
U9 SW1
5 1
J2-19
EXPOSE
U11
+24V RDY
BUFFER 4 2 J3-12
DS5
5 1
R3
U13 J2-9
4 2 DS1 J2-12
R4 R5 PREP
DIGITAL I/O BOARD

DRAWN DATE
DES.\MFG.\AUTH.
SHEET 6 OF 19
+24V
F1 J2-13
+5V +15V +24V J2-7

J2-8
J1-11 J2-9
J1-13 J2-12
J1-17 J2-5
J4-3
J2-6
J4-2
+15V J2-20
J4-5
1 5 +15V J2-24
J1-1 U10
1 5 +15V J2-22
J1-2 U6 2 4
DS3 U7
J1-3 U4 1 5 +15V J2-21
R1 2 4
J1-4 DS4 U13
1 5 +15V J2-23
J1-5 R2 2 4
J1-6 DATA DS7 U14
ADDRESS DECODER DRIVER 1 5
J1-7 CIRCUITS LATCH R7 2 4
FROM (U1, U2, U3A, U5A) DS8 U15
PAGE 1 J1-8
R8 2 4
J1-10 DS9 J2-1
J1-12 J3-2
R9
J2-2
12
J1-18 9 11 DS3 EXPOSURE IN PROCESS (EIP) J3-1
8 13
10
U3D DS4 GENERATOR PREPPED J2-3
U3C
DS7 RAD HANGMODE J3-4
J1-19
DS8 BUCKY START J2-4
J3-5
DS9 X-RAY ON
J2-11
J3-6
U8 J2-15
J3-8
J1-9
J2-16
J1-21
BUFFER J3-7
J1-23
J2-17
J3-12
J2-18
U9 SW1
J3-11
+24V
J2-19
BUFFER 5 1
J3-10
U11
+24V
4 2 DS5 J2-10
5 1 R3 R4 BUCKY IN MOTION
U12
4 2 DS6 J2-25
R5 R6 SPARE INPUT
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 736153

DRAWN DATE
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J3, J4. CHECKED INTERFACE
DES.\MFG.\AUTH.
SHEET 7 OF 19
+5V +15V +24V U1 +24V
U12
RATE 0 J2-8 F1 J3-16
J1-11
* DS38 RATE 1 J2-21 J3-17
J1-13 * DS40 RATE 2 J2-9 +24V J3-1
DRIVER
J1-17 * DS41 RATE 3 J2-22 J3-2
J2-13
J1-15 * DS43 SPARE I/P J2-23 J3-3
J2-1
* DS45 U9
SELECT DIGITAL RADIOGRAPHY J3-8 J2-2 J3-4
-15V U11 * DS16 SELECT TOMO J3-27 J2-3 J3-5

TABLE STEP SELECT J2-17 * DS18 J3-6
SPARE INPUT 1 J3-9 J2-4
EXPOSURE ON J2-4
* DS20 SPARE INPUT 2 J3-28 J2-5 J3-7
GENERATOR RDY J2-16 DRIVER
* DS21 MAG MODE 0 J3-10 J2-6 J3-8
TOMO SELECT J2-3
DRIVER EXP SAFETY ITLK J2-15 MAG MODE 1 * DS22
J3-29 J2-7 J3-9
J1-1
EXPOSURE REQ J2-2 MAG MODE 2 * DS23
J3-31 J2-8 J3-10
J1-2
PREP REQ J2-14 * DS24 J2-9 J3-20
J1-3
J2-1 J3-21
J1-4 J2-10
U3
J1-5 DS27 DS29 DS31 DS33 DS35 DS36 DS37 DS39 SPARE O/P 4 J2-11 J3-22
FLUORO J3-23
J1-6 REQUEST SPARE O/P 3 J3-4 J2-12 J3-23
J1-7 * * * * * * * * SPARE O/P 2 J3-24
CPLD J3-22 J2-14
J1-8 U10 SPARE O/P 1 J3-3
STEP TABLE J2-5 J2-15 J3-25
J1-10 DRIVER TABLE TUBE SELECT J3-21
* DS25 CINE TIME SEL 0 J2-18 J2-16 J3-26
J1-12 GENERATOR READY J3-2
* DS26 CINE TIME SEL 1 J2-6 J2-17 J3-27
J1-18 X-RAY ON J3-20
J1-19 * DS28 CINE TIME SEL 2 J2-19 J3-1 J2-18 J3-28
DRIVER
J1-22 * DS30 SELECT HCF J2-7 J2-19 J3-29
DS4 DS6 DS8 DS11 DS13 DS14 DS17 DS19
SELECT CINE * DS32 J2-20 TABLE STEP J2-20 J3-30
REQUEST
* DS34 * * * * * * * * J2-21 J3-31
FROM
+24V +24V
PAGE 1 U2 J2-22 J3-32
U17 AEC CENTER FIELD SELECT J3-5
J2-23 J3-33
* DS1
R77
SELECT TABLE STEPPING J3-24
J2-24
R78 * DS3 SELECT STEP DIRECTION J3-6
Q1 J2-25
DRIVER DS46 DRIVER * DS5 TOMO TIME SELECT 0 J3-25
R72
TOMO TIME SELECT 1 * DS7 J3-7
D3 TOMO TIME SELECT 2 * DS10 J3-26
* DS12
J3-34
J3-35
J3-36
J2
J3-37
-1
+15V
1
0
3
-1
-3
-3
-2
-1
-3
U
U
J2
J3
J3
J2
J2
J3
1
1
D1
R63 DS2 DS9 DS44 DS42 DS15
J1-20
5 1 5 1 5 1 5 1 5 1
D2 U4 TABLE X-RAY U6 TABLE FLUORO U15 READY ACQUIRE U13 READY ACQUIRE U8 TABLE PREP +24V
REQUEST REQUEST FLUORO RAD/CINE/HCF REQUEST
4 2 4 2 4 2 4 2 4 2 R30 K1
-15V
J1-14
J1-9 5 1 5 1 5 1 5 1
J5-1
J1-21 U5 U7 U16 U14 24V FROM
ROOM INTERFACE J5-3
J1-23 4 2 R17 4 2 R25 4 2 R69 4 2 R68 J3-18
J3-19
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 736894

DRAWN DATE
* DUE TO SPACE RESTRICTIONS, SERIES RESISTORS ARE NOT SHOWN FOR THE INDICATED LED’S G. SANWALD 10 APR 2013 DIGITAL
CHECKED INTERFACE
REFER TO THE DIGITAL IMAGING SUPPLEMENT IN THE SERVICE MANUAL
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J3. DES.\MFG.\AUTH.
SHEET 8 OF 19
+5V +15V +24V
J1-11
+5V
J1-13
DS1 +15V
JW103
J1-17 J7-2
XRAY ON X-RAY ON TO PAGE 10
J7-3 +15V
R10
U10 J6-1
6 J2-20 (-) J7-1
U3C J6-2
U7 U3B 9 8 4
4 J7-4
12 U3D 11 6 10 DRIVER 7 J2-19 (+) J6-5
J1-19 MONOSTABLE 5 J7-5
13 TIMER J6-14
J7-7
U17 U18
J6-3
J1-1
J6-4
J1-2
J6-6
J1-3
J6-7
J1-4 DATA
DRIVER J6-8
J1-5 LATCH
J1-6 ADDRESS DECODER
J1-7 CIRCUITS JW101 J4-10
(U1, U2, U3A, U5)
J1-8 X-RAY RQST TO PAGE 10 J6-9
J1-10
J4-11
J1-12 U13
U4 6 J2-17 (+) J6-10
4
J1-18 DRIVER 7 J2-18 (-) J4-7
DATA J6-11
U11
LATCH 6 J2-13 (+)
4 J4-8
FROM DRIVER 7 J2-14 (-) J6-12
PAGE 1
R8
R6
J4-12
U12
U6 6 J2-15 (+) J6-13
XRAY DS4 DS2 PREP
4
DRIVER 7 J2-16 (-) J4-3
DATA U14 J4-9
LATCH 6 J2-21 (+)
4
J1-9 DRIVER 7 J2-22 (-)
J1-21
R7
R9
J1-23 U8
GENRDY DS3 DS5 *
J2-1 (+)
U15 J4-1
BUFFER 6 J5-3
1
R4
DRIVER 7 J4-2
J2-2 (-) J5-7
U9 SW1 +5V J4-4

J5-2
DS7
R5
J4-5
BUFFER
DS6 * XRAYEN J5-8
+5V
R12
J2-25 (+) J5-5
5 1
R11
U16
4 2 J2-26 (-)
Q1 JW102
X-RAY EN FROM PAGE 10
* THE INPUTS / OUTPUTS MARKED “*” ARE SPARE, AND HAVE NOT BEEN ASSIGNED DIGITAL I/O BOARD

THIS SHOWS THE CONNECTIONS TO J2, J4, J5, J6 AND J7. THE DRAWN DATE
REMAINING CIRCUITS ARE SHOWN ON THE NEXT PAGE. G. SANWALD 10 APR 2013 DIGITAL
CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J2, J4, J5, J6, AND J7. DES.\MFG.\AUTH.
SHEET 9 OF 19
+24V_EXT +24V_EXT +24V_EXT
+24V_EXT
R112
R110
R111
+5V
R102
DS101 DS102 DS103
R101
1 5
U103
2 4 +24V_EXT +24V_EXT
J101-5
U101 +5V
R107
1 2 EXP_ACQ J101-2
X-RAY RQST
R105
EXP_END J101-6 TO DIGITAL
FROM SYSTEM
PAGE 9 4 U104
EXP_REQ J101-8
3 DATA 5 2 MONOSTABLE 3 R106
X-RAY ON LATCH TIMER
Q101 J101-1
U102
+5V +5V
R114
R115
U105
TO R113 6 4
PAGE 9 X-RAY EN DRIVER +24V_EXT
5 1
U106 J102-1 FROM
J102-3 DIGITAL
4 2 SYSTEM
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 737950. THIS SHOWS
THE CONNECTIONS TO J101 AND J102. THE REMAINING CIRCUITS ARE SHOWN ON THE
PREVIOUS PAGE.
FOR DETAILS REGARDING THE CONNECTIONS J101 AND J102.
DRAWN DATE
CHECKED INTERFACE
DES.\MFG.\AUTH.
SHEET 10 OF 19
+5V +15V +24V +24V
U9
J6-16
J8-11
F1 J6-17
U7
J8-13 J6-1
J6-2
J8-17
J6-3
J8-15
J6-4
DRIVER J6-20
J6-21
-15V
J6-22
J8-1 J6-23
J8-2
J8-3 U8
J8-4 R14 J6-5
J8-5 R16 J6-6
CPLD R18 J6-7
J8-6
J8-7 DRIVER R15 J6-24
J8-8 R17 J6-25
J8-10 R19 J6-26
J8-12
U10
J8-18 R20 J6-8
R22 J6-9
R24 J6-10
R21 J6-27
DRIVER
J8-9 R23 J6-28
R25 J6-29
J8-21
R26 J6-31
J8-23 J6-32
FROM
PAGE 1 J6-12
J6-30
U20
J6-33
+3.3V J6-14
R54 -
2
A/D 1 R46 J6-15
CONVERTER +
3
R35
J6-18
R53
U23A
+3.3V J6-19
DS3
R30 +3.3V
5 1 +24V +24V
R27 J9-1
U19
DS2 24V FROM
5
R43
1 4 2 J9-3 ROOM I/O BOARD
J8-14 R36
U14 1 5 DS1
5 1 Q3
2 4 U12
U15 5 1 +24V
R42
2 4 U11
4 2 R31 U11 R44
U13
4 2 U11 U11 DRIVER
DRIVER R28
K1
DRIVER DRIVER
J8-22 R45 J6-34

J6-35
J6-36
FROM J7-3, J7-5 (SHT 12) J6-37
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738947. THIS SHOWS THE CONNECTIONS
TO J6 AND J9; THE REMAINING CIRCUITS ARE SHOWN ON THE NEXT PAGE. DRAWN DATE
CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J6, J9. DES.\MFG.\AUTH.
SHEET 11 OF 19
+3.3V +2.5V
U16 +24V
J8-11 3.3V
REGULATOR J2-1
+24V +24V R6 J2-2
U22 J2-3
J4A-1 J4E-1
R8 VOLTAGE R5 J2-4
REGULATOR J4A-2 J4E-2
U2 J2-5
J4A-3 J4E-3
+10V R4 J2-6
J4A-4 J4E-4
U9 U6 J4A-5 U4 J4E-5
+24V
J4A-6 J4E-6
R48
DRIVER
U21 J4A-7 J4E-7 J3-1
J8-13 R49 VOLTAGE J4A-8 J4E-8 R9 J3-2
REGULATOR DRIVER DRIVER J3-3
R47
+24V +24V
J3-4
J4B-1 J4F-1 J3-5
J4B-2 J4F-2 R7 J3-6
J8-1 J4B-3 J4F-3

J11-2
J8-2 J4B-4 J4F-4
J8-3 J11-1
J4B-5 J4F-5
J8-4
J4B-6 J4F-6
J8-5 +24V
CPLD J4B-7 J4F-7
J8-6
J4B-8 J4F-8 J1-1
J8-7
R3 J1-2
J8-8
J8-10 +24V +24V J1-3
J8-12 R2 J1-4
FROM J4C-1 J4G-1
PAGE 1 U1 J1-5
J4C-2 J4G-2
J8-18 R1 J1-6
J4C-3 J4G-3
J4C-4 J4G-4
U5 J4C-5 U3 J4G-5 +24V
DRIVER
J4C-6 J4G-6
J10-1
J4C-7 J4G-7
R50 J10-2
J4C-8 J4G-8
J10-3
DRIVER DRIVER
+24V +24V R51 J10-4
+24V +24V +24V +24V
J10-5
J4D-1 J4H-1
R52 J10-6
R12
R10
J4D-2 J4H-2
Q2 Q1 J4D-3 J4H-3
J4D-4 J4H-4 +24V +24V +24V +24V
R13
R11
J4D-5 J4H-5
R37
R39
U11 J4D-6 J4H-6
J4D-7 J4H-7
DRIVER Q4 Q5
J4D-8 J4H-8
J7-6
R38
R40
J7-4
J7-1
D2 U11
J7-3
U18B U17 R41 DRIVER J7-5
4 6 J7-2
MONOSTABLE D1
J8-19 5 TIMER
D3 D4
J8-20 TO J8-22
(SHT 11)
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738947. THIS SHOWS THE CONNECTIONS TO J1 TO J4, J7, J10, J11, AND
THE VOLTAGE REGULATOR CIRCUITS; THE REMAINING CIRCUITS ARE SHOWN ON THE PREVIOUS PAGE. DRAWN DATE
CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J1-J4, J7, AND J10. DES.\MFG.\AUTH.
SHEET 12 OF 19
+5V +24V
U10 +24V
+24V(A)
+15V
J8-11
J3-11
R17
J8-13 J3-12
F1 J3-9
J8-17 DS
U14 15 J3-10
J8-15 J6-20
J3-13
J6-17
J6-21
-15V
J6-18
DRIVER +24V J6-19 J4-7
J8-1 PREP SW
+24V J6-22 J4-8
J8-2 X-RAY SW
R26
1 4 J6-16 J4-10
J8-3 PWR ON
1 4 U18 +5V J6-14 J4-11
J8-4 +5V PWR OFF
2 3 J6-7 J4-12
J8-5 U26 PWR COMM
RN7D
CPLD DS29 J6-2 J4-1
RN7C
J8-6 2 3 RXD
R18
J6-23 J4-2
J8-7 CTS
R33 J4-4
J8-8 +5V DS21
1 4 TP1 TXD
J4-5
J8-10 U16 RTS
4 1 J4-3
4 1 DS16
RN6D
J8-12 2 3
U31 J4-9
U29
3 2
J8-18
R11
3 2
+24V
J8-19 J1-3
+5V 4 1 J1-7
4 1
TP3 J1-2
U21
U32
RN6B
4 1 J1-8
J8-9 3 2
U30 3 2 J1-5
J8-21
3 2
FROM
J8-23
PAGE 1 +24V
4 1
R32 DS28 J7-16
1 4 U23
U20 3 2 J7-24
2 3 DS19 J7-23
R24
J8-14
R34
4 1 TP4
U22
J7-14
3 2
R23 J7-21
DS18 J7-2
R21
U24
J7-7
J8-22
J7-20
MUX
U27 THIS GROUND

CONNECTS TO
D1 D3 THE SHELLS
R29 DS27
OF J1 TO J4
DRIVER D2 D4
R28 DS26 SW1
+24V(A)
R31
R30
J9-1
24V FROM
J8-20 J9-3 ROOM I/O BOARD
DIGITAL I/O BOARD
THIS SHEET APPLIES TO DIGITAL I/O BOARD ASSEMBLY 738114. THE CIRCUITS FOR THIS BOARD ARE SPLIT BETWEEN SHEETS 13, 14, AND 15.
DRAWN DATE
CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J6, AND J7. DES.\MFG.\AUTH.
U10
+15V +15V
J3-1 J2-2
J3-2 J2-3
U2
J3-3 J2-1
J3-4 J2-5
J8-1
J3-6 J2-7
J8-2 DRIVER
J3-7 J2-4
J8-3
J3-8
J8-4
J8-5 J3-5
CPLD J3-14
J8-6 +5V
FROM
PAGE 1 J8-7
+5V +5V
RN3B
J8-8
J8-10 J6-1
J8-12 +24V J6-3
J6-4
J8-18 4 1 J6-5
J8-19 +5V U3 J6-6
RN5C
3 2 DS2
R2
RN3D
+24V J6-24
+24V
4 1
RN3C
U11 J7-1
4 1
+24V J7-3
U5 3 2 DS10
+5V R10 J7-4
3 2 DS4 J7-5
R4 4 1
RN2B
+5V U4
+24V +5V
3 2 DS3
R3
RN2A
RN5D
4 1 +5V
+24V
+5V U7 +24V
RN6C
3 2 DS6
R6 4 1
RN2D
+24V 4 1
+5V U6
+24V +5V U12
3 2 DS5
4 1 R5 3 2 DS9
RN2C
R9 J7-6
RN6A
4 1 +5V U25
3 2 DS20 +24V
U9 +24V
RN3A R25
3 2 DS8
R8 4 1
+24V 4 1
U8
U17
3 2 DS7
4 1 R7 3 2 DS17
R22 J7-22
U1
3 2 DS1
R1
DIGITAL I/O BOARD
DRAWN DATE
CHECKED INTERFACE
SHEET 14 OF 19
U10
J8-1
J8-2
J8-3
U19
J8-4 J6-12
J8-5 J7-12
CPLD
J8-6 J6-11
FROM
PAGE 1 J8-7 J7-11
J8-8 DRIVER J6-10
J8-10 J7-10
J8-12 J6-9
J7-9
J8-18
J8-19
DS11 DS12 DS13 DS14 DS22 DS23 DS24 DS25
R12
R13
R14
R15
R16
R19
R20
R27
DIGITAL I/O BOARD
DRAWN DATE
CHECKED INTERFACE
SHEET 15 OF 19
+5V +24V
U10 +24V
+15V
J8-11 +24V(A)
J3-11
R17
J8-13 F1 J10-17 J3-12
J8-17 J12-2 J3-9
DS15
U14 LIH J3-10
J8-15
J3-13
J12-10
J10-2
-15V
DRIVER +24V +24V J11-6 J4-7

J8-1 PREP SW
+24V J10-16 J4-8
J8-2 X-RAY SW
R26
1 4 J12-5 J4-10
J8-3 PWR ON
1 4 U18 +5V J11-9 J4-11
J8-4 +5V PWR OFF
2 3 J10-11 J4-12
J8-5 U26 PWR COMM
RN7D
CPLD DS29 J11-8 J4-1
RN7C
J8-6 2 3 RXD
R18
HAFLU J4-2
J8-7 J10-10 CTS
R33 J4-4
J8-8 +5V DS21
1 4 TP1 TXD
J4-5
J8-10 XRAYON DS16 U16 RTS
4 1 J4-3
4 1 GENRD
RN6D
J8-12 2 3
U31 J4-9
U29
3 2
J8-18
R11
3 2
+24V
J8-19 J1-3
+5V 4 1 J1-7
4 1
TP3 J1-2
U21
U32
RN6B
4 1 J1-8
J8-9 3 2
U30 3 2 J1-5
J8-21
3 2
FROM
J8-23
PAGE 1 +24V
4 1 DS28
R32 HARAD J12-8
1 4 U23
U20 3 2 DS19 J12-11
2 3 EXP J12-12
R24
J8-14
R34
4 1 TP4
U22
J11-10
3 2
R23 J12-7
DS18 J12-3
FLEXP
JW2-1
R21
U24
JW2-2
J8-22
JW2-3
MUX
U27
DS27 D1 D3
R29 HSHCF
DRIVER D2 D4
R28 DS26 HSTEP SW1
+24V(A)
R31
R30
J9-1
24V FROM
J8-20 J9-3 ROOM I/O BOARD
DIGITAL I/O BOARD
DRAWN DATE
CHECKED INTERFACE
FOR DETAILS REGARDING THE CONNECTIONS TO J1, J2, J3, J4, J10, J11 AND J12. DES.\MFG.\AUTH.
U10
+15V +15V
J3-1 J2-2
J3-2 J2-3
U2
J3-3 J2-1
J3-4 J2-5
J8-1
J3-6 J2-7
J8-2 DRIVER
J3-7 J2-4
J8-3
J3-8
J8-4
J8-5 J3-5
CPLD J3-14
J8-6 +5V
FROM
PAGE 1 J8-7
+5V +5V
RN3B
J8-8
J8-10 J10-9
J8-12 +24V J10-18
J10-19
J8-18 4 1 J10-7
J8-19 +5V U3 J11-4
DS2
RN5C
3 2 FLMA
R2
RN3D
+24V J12-13
+24V
4 1
RN3C
U11 J10-20
4 1
+24V J10-21
U5 3 2 DS10
+5V R10 J10-22
DS4
3 2 TS1 J10-23
R4 4 1
RN2B
+5V U4
+24V DS3 +5V
3 2 TA20
R3
RN2A
RN5D
4 1 +5V
+24V
+5V U7 +24V
DS6
RN6C
3 2 TS2
R6 4 1
RN2D
+24V 4 1
+5V U6
+24V DS5 +5V U12
3 2 TA30 DS9
4 1 R5 3 2
RN2C
EXINH
R9 J10-8
RN6A
4 1 +5V U25
DS20
3 2 +24V JW1-1
U9 PREP
R25 +24V
DS8 RN3A
JW1-2
3 2 TOMO
R8 4 1
JW1-3
+24V 4 1
U8
DS7 U17
3 2 TA40 DS17
4 1 R7 3 2 PFSEL
R22 J12-14
U1
DS1
3 2 TA7
R1
DIGITAL I/O BOARD
DRAWN DATE
CHECKED INTERFACE
SHEET 17 OF 19
U10
J14-1 J10-14
J14-2 J10-15
J14-3 J10-3
TO ROOM
J14-4 J10-4
I/O BOARD
J14-5 J10-5
J14-6 J10-6
J8-1
J8-2
J8-3
U19
J8-4 J11-5
J8-5 J11-1
CPLD
J8-6 J11-3
FROM
PAGE 1 J8-7 J11-2
J8-8 DRIVER J11-7
J8-10 J12-6
J8-12 J12-4
J10-1
J8-18
J8-19 DS11 DS12 DS14 DS22 DS23 DS24 DS25
DS13
HFL HPREP HCON HTOMO HGRDY HEXP RDYAQ
R12
R13
R14
R15
R16
R19
R20
R27
TO J14-1, J14-2 J13-1 J10-24
INPUT DISTRIBUTION J13-2 J10-25
BOARD
J10-12
J10-13
DIGITAL I/O BOARD
DRAWN DATE
CHECKED INTERFACE
SHEET 18 OF 19
TP1
R2 J2-16 DOSE
FEEDBACK
+5V +5V
+5V +5V +5V +5V +5V +5V
R21
R18
R19
R20
R1
R3
R4
Q1
R22
DS1 DS2 DS3 DS4 DS5 DS6
U4 U6
+5V +24V J2-12
X-ON
J2-7
+15V TRIGGER 0
J1-11 J2-8
TRIGGER 1
J1-13 J2-9
DATA TRIGGER 2
DRIVER J2-10
J1-17 LATCH TRIGGER 3
J2-11
J1-20 TRIGGER CLOCK
J1-19 J2-14
REMOTE ON
J1-1
J1-2 DS7 +15V +15V +24V +24V
J1-3
R23
R25
J1-4
R34
R36
FROM
PAGE 1 +5V +5V
J1-5
Q2
J1-6
R16
R15
R35
R5
J1-7 DS8
J1-8
R28
R24
J1-22
J1-15 Q4 J2-4
U8 READY
J1-9
+24V +24V
R29
J1-21
BUFFER
J1-23 -15V
R31
R26
Q5
SW1
DS9 Q3
U9
R27
BUFFER
R30
J2-1 TRIGGER
R32
ACKNOWLEDGE
J2-2
Q6
J2-13
R33
J2-15
DIGITAL I/O BOARD

DRAWN DATE
CHECKED INTERFACE
FOR DETAILS REGARDING CONNECTIONS TO THIS BOARD. DES.\MFG.\AUTH.
SHEET 19 OF 19
+5V
+15V_DAP
+15V_DAP
R333
+5V +5V
R335
R62
Q24
R75
R63
R99
R98
Q4
R64
Q8
R68
R70
DS18 DS19 D28
J12-10
DAP DAP U112
CH 1 CH 2 J12-8
J12-6
J12-2
J12-4
J14-10 J32-10
TO FPGA U53
J12-18
J12-20
J12-3
R347
U49 U26 U17
J12-5
5 1
DRIVER U23
4 3 L11
J11-10 J31-10
J11-40 J31-40 DATA +5V
DATA
J11-11 J31-11 BUFFER
LATCH TO J15 CONSOLE CONNECTOR
3.3V-5V +15V_DAP
J11-41 J31-41 R346 BOARD (PG 2)
J11-42 J31-42 +15V_DAP
R334
J11-13 J31-13
R336
R67
J11-43 J31-43 Q25
R76
R66
Q5
R65
Q9
R71
R69
U24 D29
J12-17
DATA & CONTROL U111
BUS J12-15
J12-13
J12-11
J12-7
J12-14
J12-16
J12-9
R339
J12-12
5 1
U22
4 3 L12
R72
DRAWN DATE
CHECKED DAP
DES.\MFG.\AUTH.
MD-0988 REV A
L. FOSKIN
SHEET 1 OF 2
J15-10 J2-1
SWITCHED +15V
J15-8 J2-2
+ DOSE
J15-6 J2-3
- DOSE
J15-2 J2-4
OPTO
J15-4 J2-5 DAP
RELAY CHAMBER
J15-18 J2-6 #1
TEST +15V
J15-20 J2-7
CURRENT LOOP IN
J15-3 J2-8
GROUND
J15-5 J2-9
GROUND
FROM J12 GENERATOR

CONTROL BOARD
(PG 1)
J15-17 J1-1
SWITCHED +15V
J15-15 J1-2
+ DOSE
J15-13 J1-3
- DOSE
J15-11 J1-4
OPTO
J15-7 J1-5 DAP
RELAY CHAMBER
J15-16 J1-6 #2
TEST +15V
J15-14 J1-7
CURRENT LOOP IN
J15-9 J1-8
GROUND
J15-12 J1-9
GROUND
CONSOLE CONNECTOR BOARD
DRAWN DATE
CHECKED DAP
DES.\MFG.\AUTH.
MD-0988 REV A
L. FOSKIN
SHEET 2 OF 2
+3.3V
+5V +5V
R47
DS41 DS42
CONSOLE CONNECTOR BOARD
DS45
TXD RXD
1 Hz U8
U18
R20
R19
DATA
BUFFER U1
3.3V-5V
R2 J5-1 J9-1 J13-17
R21 J5-2 J9-2 J13-15

TO J4 GENERATOR
U16 CONTROL BOARD
R8 J5-4 J9-4 J13-16
DATA
(SHT 2)
BUFFER R10 J5-5 J9-5 J13-18
FPGA 5V-3.3V
RS-232
+5V +5V
DS44 DS43
SERIAL (RS-232)
TXD RXD TO USB COMM1
(USB PORT)
RS-232 CONVERTER
(LAPTOP)
R18
R17
J2
19” TOUCHSCREEN CONSOLE
U5
U8
R5
DATA 3 TXD
BUFFER R4
3.3V-5V 7 RTS
U16
R3
DATA BUS DATA 2 RXD
D0..D7 BUFFER R9
5V-3.3V 8 CTS
COMM1
RS-232 5 (USB PORT)
15.6” TOUCHSCREEN CONSOLE

CONSOLE BOARD (R&F MEMBRANE CONSOLE)
DRAWN DATE
G. SANWALD/J. LAPE 10 APR 2013 SERIAL
CHECKED COMMUNICATIONS
DES.\MFG.\AUTH.
L. FOSKIN
MD-0989 REV C
SHEET 1 OF 3
+3.3V +5V
R53
R52
DS14 DS15
CON CON U39A
U113 TX RX 5V - 3.3V
R50 J31-26 J11-26
TO FPGA U53
R47 U39B
5V - 3.3V
J31-56 J11-56
TO FPGA U53
J31-55 J11-55
FROM FPGA U53
U8
J31-25 J11-25
R49 FROM FPGA U53
R48
JW11
1
2 RS-232
U15 RS-422
3
RS-422
U14
J4-17 RS-422
J4-15
FROM J13 CONSOLE
CONNECTOR BOARD J4-16
(SHT 1)
J4-18
JW14 JW12 JW13 JW15

1 1 1 1
RS-232 RS-232 RS-232 RS-232
2 2 2 2
RS-422 RS-422 RS-422 RS-422 3
3 3 3
DRAWN DATE
DES.\MFG.\AUTH.
L. FOSKIN
MD-0989 REV C
SHEET 2 OF 3
+3.3V +3.3V
DS10 DS11
RX1 TX1 U66 U27

J3-8 J11-8 J5-3
TXD
J3-6 J11-6 J5-7
RTS
DIGITAL
ISOLATOR J3-4 J11-4 J5-2 COMM
RXD PORT 1
J3-10 J11-10 J5-8
(RS-232)
CTS
J3-11 J11-11 J5-5
RS-232
+3.3V +3.3V
DS12 DS13 J3-7 J11-7 J8-3 TXD
RX2 TX2 U65 U69 J3-5 J11-5 J8-7 RTS
J3-3 J11-3
COMM
J8-2 RXD
PORT 2
J3-9 (RS-232)
DIGITAL J11-9 J8-8 CTS
ISOLATOR
J3-1 J11-1 J8-5
RS-232
CPU CORE J1
AND
SUPPORT
CHIPS
10/100/1000 ACCESSIBLE
Ethernet FROM REAR
PANEL ON
J2 GENERATOR
USB
DS5
+3.3V +3.3V +5V_ISOL +5V_ISOL
USB VBUS
CAN BUS
U29 PORT 1
J4-6 J10-6 J6-2
CAN LOW
CAN
DS8 DS6 DS7 DS9 J4-8
TRANCEIVER J10-8 J6-7
CAN HIGH
CAN CAN CAN CAN J4-10
RX2 RX1 TX1 TX2 J10-10 J6-3
1 4
U67 2 3 J4-4 J10-4 J6-6
SW1
CAN BUS
DIGITAL U28 PORT 2
ISOLATOR J4-5 J10-5 J7-2
CAN LOW
CAN
TRANCEIVER J4-7 J10-7 J7-7
CAN HIGH
J4-9 J10-9 J7-3
1 4
2 3 J4-3 J10-3 J7-6
SW2
DRAWN DATE
CONSOLE CONNECTOR
CPU BOARD BOARD
DES.\MFG.\AUTH.
L. FOSKIN
MD-0989 REV C
SHEET 3 OF 3
+3.3V +3.3V
R170
R169
U65 U64 DS15 DS26 U66
CAN RX CAN TX
CAN-SPI CAN
CONTROLLER TRANCEIVER
MICRO
CONTROLLER
+3.3V
R179
D12 D33
4 1
U60
3 2
+3.3V
+24V D21 D34
R255
U94A
J14-25 J32-25
TO FPGA U53
4 1
U108
3 2
+3.3V +3.3V
R271
R272
R327
J11-2 J5-2 J4-2
R328
U130 DS1 DS2 U16
CAN RX CAN TX
J11-5 J5-5 J4-5
CAN-SPI CAN J11-1 J5-1 J4-1

CONTROLLER TRANCEIVER TO J5 OF THE DSS
BOARD (PG 2)
J11-3 J5-3 J4-3
J14-21 J32-21 U94
FROM FPGA U53
J14-22 J32-22 J11-6 J5-6 J4-6
TO FPGA U53
J14-23 J32-23
FROM FPGA U53
J14-61 J32-61
FROM FPGA U53 J11-4 J5-4 J4-4
J14-63 J32-63
TO FPGA U53
CPU BOARD GENERATOR CONTROL BOARD ROOM I/O BOARD
DRAWN DATE
G. SANWALD/J. LAPE 18 MAR 2013 INTERNAL
CHECKED CAN BUS
DES.\MFG.\AUTH.
L. FOSKIN
MD-0990 REV A
SHEET 1 OF 2
+3.3V +3.3V +3.3V +3.3V
R121
R119
R1
R2
U20 U21 DS3 DS4 U22 U5 U18 DS2 DS3 U23
CAN TX CAN RX CAN RX CAN TX
CAN-SPI CAN CAN-SPI CAN

CONTROLLER TRANCEIVER CONTROLLER TRANCEIVER
MICRO MICRO
CONTROLLER CONTROLLER
+3.3V +3.3V
R144
D20 D14 D55 D54
4 1 4 1
U30 U28
R59
3 2 3 2
D47 D12 D57 D56
J5-2 J4-2 J12-2 J16-28 J4-28
J5-5 J4-5 J12-5 J16-26 J4-26
J5-1 J4-1 J12-1 J16-27 J4-27

FROM J4 OF THE
ROOM I/O
BOARD (PG 1) J16-12 J4-12
J5-3 J4-3 J12-3
J16-13 J4-13
J5-6 J4-6 J12-6
J16-14 J4-14
J5-4 J4-4 J12-4 J16-25 J4-25
DUAL SPEED STARTER BOARD INPUT DISTRIBUTION BOARD AUXILIARY CPU BOARD
DRAWN DATE
G. SANWALD/J. LAPE 18 MAR 2013 INTERNAL
CHECKED CAN BUS
DES.\MFG.\AUTH.
L. FOSKIN
MD-0990 REV A
SHEET 2 OF 2

Cpi Indico IQ Drawings

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Cpi Indico IQ Drawings

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GENERATOR INDICO IQ

Service Manual - Drawings

2 4*** J9 J24 J21 J23

SCHEDULES ARE OBSERVED.

J12 R/F console

EQUIPMENT THAT CAN

J7 TEMP E1 BE ATTACHED HERE.

TEMPERATURE SENSORS: +12VDC

TERMINAL SIGNAL INVERTER GATE DRIVE: 734614-xx

FILAMENT CONTROL: +/-12VDC

560/680VDC FILAMENT CONTROL: +/-12VDC

CAPS ASSY 901531-01 FILAMENT FILAMENT

E9 50 kW (-00) HV Cables -TUBE 1 +

CONT. COIL Lid Ground

TO PROTECTIVE -02 (80/100 kW) 1 PER

J4 REM FLUORO CONTROLLER - + - +

TABLE SIDE FLUORO CONTROLLER AUX

USB HOST (USB A)

THIS X-RAY UNIT MAY BE DANGEROUS TO PATIENT

USB HOST (USB A)

TOUCH SCREEN CONSOLE CONNECTIONS

~ + C10 C12 C14

F12 DS3 (Q1, D8, D9, BUZZER R27

ROOM POWER TRANSFORMER

INPUT DISTRIBUTION BOARD, 400-480 VAC 3 PHASE (50 KW)

400-480 VAC 3-PHASE 50 KW GENERATOR

~ + C10 C12 C14

ROOM POWER TRANSFORMER

400-480 VAC 3-PHASE 65, 80 & 100 KW GENERATORS

R70 R71 ~ D33, 36, 40, 41 - 0V RTN TP5

J18-6 400-480 V GENERATORS CONNECTED

FROM J23-16 GENERATOR J8-16

INPUT DISTRIBUTION BOARD

R44, 45, 193

AUXILIARY CPU BOARD

U11A MICRO CAN DATA LINK

AUXILIARY CPU BOARD

+12V_ISOL +5V_ISOL +12V_ISOL

DS19 USE ONE OR TWO FILAMENT

-12V_ISOL CIRCUIT ISOL PG

A/D J31-46 J11-46

CPU BOARD J3-9 J6-9

-15V_A -12V J3-23 J6-23

ROOM I/O BOARD

300 VAC J10-1

CONSOLE BOARD (R&F MEMBRANE CONSOLE) LCD DISPLAY ASSEMBLY

J1-13 J3-13 J13-11 J4-11

R&F MEMBRANE CONSOLE

ON J3-2 J5-11 J9-11

CONSOLE CONNECTOR BOARD GENERATOR CONTROL BOARD CPU BOARD

USE DRAWING DC BUS & POWER DISTRIBUTION, MD-0975, IN

R&F CONSOLE AND MINI CONSOLE

J1-13 J3-13 J13-11 J4-11

STARQTM TOUCHSCREEN CONSOLE

(SEE CHAPTER 3-OPERATOR’S MANUAL FAULT LATCH

USE DRAWING DC BUS & POWER DISTRIBUTION, MD-0975, IN

TOUCHSCREEN CONSOLE DRAWN DATE

S.I.D. TP5 TP14

4 3 2 1 JW14 +3.3V R103

ROOM I/O BOARD GENERATOR CONTROL BOARD

+3.3V ROOM INPUTS

26V J2-3 +3.3V

ROOM I/O BOARD