Lecture No.

11
Computer Logic Design
Combinational Logic Circuits

1
 Combinational Logic
• Various Logic Implementations:
– SOP
– POS
– NAND (Universal Gate)
– NOR (Universal Gate)

2
SOP Implementation

OR Gate
level

AND
Gate
NOT level
Gate
level 3
POS Implementation

AND
Gate
level

OR Gate
level
NOT
Gate
level 4
NAND Implementation

NAND
Gate
level

NAND
Gate
level

5
NOR Implementation

NOR
Gate
level

NOR
Gate
level

6
 NAND/NOR Circuits
• Practical considerations enforce designing
using NAND/NOR gates
• Replace all basic gates with NAND/NOR
definitions

7
 Universal Property of NAND Gate

• NOT Gate

1 2
• AND Gate

• OR Gate
8
Universal Property of NOR Gate

• NOT Gate

• OR Gate

• AND Gate
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 NAND/NOR Circuits
Example:
F  X.Y  X.Z  Y.Z
Original circuit NAND equivalent


10
 Ex: Adjacent 1s Detector Function
Input Output Input Output

A B C D F A B C D F
0 0 0 0 0 1 0 0 0 0
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 1 0 0
0 0 1 1 1 1 0 1 1 1
0 1 0 0 0 1 1 0 0 1
0 1 0 1 0 1 1 0 1 1
0 1 1 0 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 11
SOP Implementation
A
B
C
D

12
SOP Expression Simplification

AB\CD 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 1 1 1 1

10 0 0 1 0

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SOP based Simplified Circuit
A
B

C
D F

14
 NAND based Implementation
A
B

C
D F

A
B

C
D F

15
POS Implementation
A
B
C
D

16
POS Expression Simplification
AB\CD 00 01 11 10

00 0 0 1 0

01 0 0 1 1

11 1 1 1 1

10 0 0 1 0

17
POS based Simplified Circuit
A
C

B
D F

18
 NOR based Implementation
A
C

B
D F

A
C

B
D F

19
 NAND/NOR Circuits
• Implement as NAND/NOR circuits:

• Example 1: F = A(CD+B) +BC’

• Example 2: F = (X’+Y)(X+Z)+XY’Z

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 Operation of Circuit
• Represented through a timing diagram
• Timing diagram divided into intervals
• Each interval representing a new input

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 Timing Diagram

A
1
C

B
D 2 F

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 Timing Diagram
D

t0 t1 t2 t3 t4 t5 t6 t7 t8

23
 NAND Logic Diagrams
• Use NAND / Invert-OR dual symbols to improve
circuit readability and timing diagram determination
• Example:

L L.M L.M.N L.M.N.P

M N
P
X=
Q L.M.N.P.Q.R
R
Q.R
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 NAND Logic Diagrams

L.M L.M  N (L.M  N).P

L
M
N
P
X=
Q (LM  N).P  Q.R
R
Q.R

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 NOR Logic Diagrams
• Use NOR / Invert-AND dual symbols to improve
circuit readability and timing diagram determination
• Example:

LM
L
LMN LMNP
M N
P
X=
QR
Q
R LMNPQR
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 NOR Logic Diagrams

LM (L  M ).N (L  M ).N )  P

L
M N
P
X=
Q ((L  M ).N  P).(Q  R
R
QR

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