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Lab-9
DC BIASING - BIPOLAR
JUNCTION TRANSISTORS (BJTs)
Emitter Bias and Collector
Feedback Bias
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Recap
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Recap
• Emitter Bias
• Collector Feedback Bias
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Biasing and the Three States of Operation
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Emitter Bias
• Use both a positive and a negative supply voltage on emitter or it just contain an
emitter resistor to improve stability level over fixed – bias configuration.
Fig. 4.17 BJT bias circuit with emitter resistor. FIGURE 5-21 An npn transistor with emitter bias.
Polarities are reversed for a pnp transistor. Single
subscripts indicate voltages with respect to ground. 5
Emitter Bias – only RE
Collector – Emitter loop
RC RE
Base – Emitter loop
VCC – IBRB – VBE – IERE = 0 Since IC = IB, so IC also equivalent to
IE = ( + 1) IB (VCC VBE)
Then, VCC – IBRB – VBE – ( + 1)IBRE = 0. IC
VCC VBE
RB ( 1) RE
IB
RB ( 1) RE
Less sensitivity to beta
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Emitter Bias – RE + DC Voltage Supply
Collector – Emitter loop
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Collector Feedback Bias (DC Bias with Voltage
Feedback)
• An improved level of stability can also be obtained by introducing a
feedback path from collector to base.
• If IC tries to increase, it drops more voltage across RC, thereby causing VC
to decrease. When VC decrease, there is a decrease voltage across RB,
which decrease IB. The decrease in IB produce less IC which in turn, drops
less voltage across RC and thus offsets the decrease in VC.
• These feedbacks keep the Q-point stable.
VC
IC VRC VC VRB IB
IC VRC offset the
decrease in VC
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Collector Feedback Bias (DC Bias with Voltage
Feedback)
Base – Emitter Loop
VCC – IC'RC – IBRB – VBE – IERE = 0
VCC VBE
IB
RB ( RC RE )
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Collector Feedback Bias (DC Bias with Voltage
Feedback)
Collector – Emitter Loop
VCC – IC'RC – VCE – IERE = 0
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Summary
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Summary
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