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Acer Predator Helios 300 PH315-51 - PH317-52 Compal DH63F LA-F991P Rev.1C
Acer Predator Helios 300 PH315-51 - PH317-52 Compal DH63F LA-F991P Rev.1C
1 1
Compal Confidential 2
Rev : 1.C
2018.02.13
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DH53F M/B LA-F991P 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date Tuesday February 13 2018 Sheet 1 of 73
A B C D E
A B C D E
page 50
Interleaved Memory
page 38
page 37 Memory BUS 260 pin DDR4-SO-DIMM X1
BANK 0, 1, 2, 3 page 23
eDP
Dual Channel
CoffeeLake H PROCESSOR
1.2V DDR4 2400/2666 260pin DDR4-SO-DIMM X1
BGA1440 BANK 4, 5, 6, 7 page 24
Nvidia N17E-G1
PEG x16
8GT/s
(42X28) (CFL-H_6+2)
HDMI x 4 lanes
with gDDR5 x6
page 25~36 Processor page 07~14
page 15~22
CLK=24MHz
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THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 2 of 73
A B C D E
A B C D E
PCH PCH@
CPU i5@/i7@
BOM table
43 Level Description BOM Structure
431AB2BOL05~08
431AB2BOL53_54
431AB1BOL67
X4EAB2BO001
X4EAB2BO051
X76730BOL56 ALT. GROUP PARTS N17E6G SAM 256M32 DH7VF
X76730BOL57 ALT. GROUP PARTS N17E6G HYN 256M32 DH7VF
X76730BOL58 ALT. GROUP PARTS N17E6G MIC 256M32 DH7VF
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/07/20 Deciphered Date 2018/07/20 T tle
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
Notes List
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 3 of 73
A B C D E
5 4 3 2
EN:DGPU_PWR_EN
UG27 +1.8VSDGPU_AON
DC_IN GPU
PL101 +1.8VSDGPU_MAIN
PJP101
+19V_VIN EN:1.8VSDGPU_MAIN_EN
GPU
AC CONN.
EN : 1VSDGPU_EN +1.8VS
+12.6V_BATT+ +1.8VDDA
+12.6V_BATT +1.0VSDGPUP +1.0VSDGPU UQ2 RA3
BATTERY PU1801 PJ1802 GPU CODEC
PL201,PL202
PJP201 +3.3V_CC
RS1 DIMM1 +1.8VALW_PRIM
D +1.8VALW D
IMVP8 PJ7107 RH100
+VCC_CORE PU7102 PJ7103 +2.5V DIMM2
PCH
PU8102 CPU DDR4
PU301 +19VB PU8103 PL8101,PL8306,PL8305,PL8106 +1.8VALWP +1.8V_PHVLDO
RH100
PU8104 PU7105 PCH
PU8105 +3VS
EN:VR_ON UQ1 JPQ1
UO1 SATA Re-driver
PQ8105 R19 +3VALW_TPM U5
CHARGER +VCC_GT TPM RZ1 G-SENSOR
+19VB
PU8106 PL8107 CPU +3VS_WLAN
EN:DRON UM1 JNGFF1 WLAN CARD (IOAC) UF1 THERMAL SENSOR
+3V_LAN
UL1 UL2 LAN RM11 +3VS_WLAN JNGFF1
WLAN
PQ8301 +3VALW_DSW
PL8301 +VCC_SA CPU RH99 PCH RM1 +3VS_SSD_NGFF JSSD1
+19VB SSD
EN:DRON
RH97 +3VALW_PCH_PRIM RH98 +3VALW_SPI UH3 +3VS_TPM
SPI R20 U5 TPM
RH101 +3VALW_HDA +TS_PWR
EN:3V_EN +3VALW
PCH RX6 JEDP1
TS
PJ401
PU401 UK1 +3V_PTP JTP1
+19VB TP UX1 +LCDVDD JEDP1
C
EC,LID +3VLP PANEL C
RK14 1.8VSDGPU_MAIN_EN
+1.2V_VDDQ_CPU UG20 +3VSDGPU GPU
+1.2V
JPC1,C2 CPU
+1.2V_VDDQ UK2 JEP1 +3VS_DVDDIO
EN:SYSON PJ501 +FP_VCC FP RA2 +3VS_DVDDIO CODEC
JDIMM1,2
+19VB DIMM +3VS_DVDD
+0.6V_DDRB_VREFCA RA4
PU501 RD19,21,20 +3VS_DVDD CODEC
EN:SM_PG_CTRL +0.6V_B_VREFDQ CPU +3VS_DIMMA
+0.6VSP +0.6VS_VTT
PJ502 +1.05VALW_PCH_PRIM
RH92 PCH
RH93 +1.05VALW _VCCMPHY PCH
PU601 +1.05VALWP +1.05VALW
+19VB PJ601 RH94 +1.05VALW_PCH PCH
EN:+3VALW
+1.05VALW_VCCAZPLL
RH102
+1.05VALW_VCCAMPHYPLL
PCH
RH103
+1.05VALW _XTAL
PCH
RH105
+1.0VS_VCCIOP
PCH
PU7201 PJ7201 +VCCIO CPU UQ2 RQ5 +1.05V_VCCST
+19VB
EN:SUSP# CPU
RK15 +1.05VS_VCCSTG
UC4 RQ6
B B
+5V_CC
US2
EN:1.35VSDGPU_EN GPU
PJ1701 +1.35VSDGPU
+19VB_1.35VSDGPUP
PQ1701
+19VB
LX1 +INVPWR_B+
JEDP1
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PANEL
Security C assi ica ion
20 7 07 20
Compal Secret Da a
20 8 07 20 i le
Compal Electronics, Inc.
Issued Date Deciphered Da e
H S SHEE O ENG NEER NG DRAWING IS HE RO R E AR RO ER O COM A E EC RON CS NC AND CON A NS CON DEN A
Power Map
AND RADE SECRE IN ORMA ION H S SHEE MA NO BE RANS ERED ROM HE CUS OD O HE COM E EN D VIS ON O R&D Size Document Numbe ev
DE AR MEN EXCE AS AU HORIZED B COM A E EC RONICS NC NEI HER HIS SHEE NOR HE N ORMA ON I CON AINS Custom A
MA BE USED B OR D SC OSED O AN H RD AR WI HOU R OR WRI EN CONSEN O COM A E EC RON CS NC DH53F M/B LA-F991P
Date uesday eb ua y 3 20 8 Sheet 4 o 73
5 4 3 2
5 3 2 1
Plug in
+3VLP
D +3VLP D
EC_ON
EC_ON
+5VALW
→
+5VALW
ON/OFFBTN#
ON/OFFBTN#
→ →
+3VALW 90.77ms 8.969s +3VALW
→ →
+1.8VALW 92.67ms 8.97s +1.8VALW
→ →
+1.05ALW 93.73ms 8.97S +1.05ALW
→ →
EC_RSMRST# 21.45ms 8.497S EC_RSMRST#
→ ←
20ms
→
PBTN_OUT# ← → 8.497S PBTN_OUT#
130.8ms
→ →
17.32ms 439.9us PM_SLP_S4#
PM_SLP_S4#
C → → C
17.36ms 291us → 291.9us PM_SLP_S3#
PM_SLP_S3#
A A
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
Power Map
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 5 of 73
5 3 2 1
5 3 2 1
2.2K 2.2K
+3VALW_PCH_PRIM
+3VS
2.2K +3VS 2.2K
PCH_SMBCLK D_CK_SCLK
2N7002DW
PCH_SMBDATA D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
G-Sensor
+3VALW_PCH_PRIM 2.2K
D
PCH_SML0DATA 499 D
CannonLake-H 2.2K 1.8K 1.8K
+1.8VSDGPU_AON
PCH 2.2K
+3VALW_PCH_PRIM +1.8VSDGPU_AON
+3VSDGPU
2.2K +1.8VSDGPU_MAIN 1.8K 1.8K
+1.8VSDGPU_MAIN
PCH_SML1CLK VGA_SMB_CK2 I2CC_SCL_R I2CC_SCL
PJT138KA PJT138KA
PCH_SML1DATA VGA_SMB_DA2 N17E-G1 I2CC_SDA_R I2CC_SCL Current Sensor
4.7K
2.2K
+3VLP_EC +3.3V_CC
2.2K 4.7K
+3.3V_CC
EC_SMB_CK1 100 ohm EC_SMB_CK1 1
BATTERY
2N7002DW
EC_SMB_DA1 100 ohm EC_SMB_DA1 1 CONN USB CC EJ179F
2N7002DW
C THERMAL SENSOR C
B B
A A
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THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
N17E-GDDR5 D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 6 of 73
5 3 2 1
A B C D E
CFL-H
UC1D
3 CFL-H_BGA1440 3
CFL-H_BGA1440
CFL-H_BGA1440
S IC CL8068403373522 SR3Z0 U0 2.3G ABO!
S IC CL8068403359524 SR3YY U0 2.2G ABO!
SA0000BPJ40
SA0000BPZ40
5@
i7@
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(1/8)DDI/eDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 7 of 73
A B C D E
A B C D E
CHANNEL-A
Interleaved Memory
UC1A
CFL-H
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR (IL)/LP3-DDR (NIL) LP3/DDR
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_W E# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4 DDR_A_MA1 <23>
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2
DDR_A_D35 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 DDR_A_MA3 DDR_A_MA2 <23>
AA5 AP5 DDR_A_MA3 <23>
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <23>
AB4 AP1 DDR_A_MA5 <23>
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8
DDR_A_D41 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA9 DDR_A_MA8 <23>
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
DDR_A_D43 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR_A_MA11 DDR_A_MA10 <23>
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
DDR_A_D45 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR_A_MA13 DDR_A_MA12 <23>
V4 AE3 DDR_A_MA13 <23>
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23>
U4 AU3 DDR_A_ACT# <23>
DDR_A_D48 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT#
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5 DDR_A_ALERT# <23>
DDR_A_D51 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT#
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR (IL)/LP3-DDR (NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
DDR_A_D58 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR_A_DQS#5 DDR_A_DQS#4 <23>
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
DDR_A_D60 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR_A_DQS#7 DDR_A_DQS#6 <23>
M5 L3 DDR_A_DQS#7 <23>
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3 DDR_A_DQS1 <23>
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR BC3 DDR_A_DQS3 <23>
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS5 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5 <23>
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8
1 OF 3
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
@
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(2/8)DIMMA
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 8 of 73
A B C D E
A B C D E
CHANNEL-B
Interleaved Memory
UC1B
CFL-H
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(3/8)DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 9 of 73
A B C D E
A B C D E
PEG&DMI
To DGPU
1 To DGPU PEG Lane Reversed
1
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<15> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <15>
<15> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <15>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<15> DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 <15>
<15> DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 <15>
DMI_RXN_1 DMI_TXN_1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
<15> DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 <15>
<15> DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2 <15>
DMI_RXN_2 DMI_TXN_2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<15> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <15>
<15> DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3 <15>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
@
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
PEG/DMI
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 10 of 73
A B C D E
A B C D E
CFL-H
UC1E
1
Near CPU side RC23 RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
CC69 PCH_JTAG_TCK1 <19>
follow 1050 Request UC3 330K_0402_5%
1 5 2 1 RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
8/21 NC VCC
2
+1.05V_VCCST DDR_PG_CTRL 2 .1U_0402_16V7K
RH1 1 2 1K_0402_5% H_THERMTRIP# A 4 SM_PG_CTRL
Y SM_PG_CTRL <56>
3
3 GND 3
PU 330K follow CRB
74AUP1G07GW _TSSOP5
8/21
+1.05VS_VCCSTG
1
RC21 SVID
1K_0402_5%
2
+1.05V_VCCST
RC14 1 2 499_0402_1% H_PROCHOT#_R
<43,54> H_PROCHOT#
+1.05V_VCCST
1
RC19 RC20
1
56_0402_1% 100_0402_1%
RC22
2
1K_0402_5%
2
RH2
@ 13_0402_5%
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(5/8)CFG,SVID
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 11 of 73
A B C D E
A B C D E
GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
AT37 VCCGT7 VCCGT86 BE36 AA37 VCC7 VCC70 AJ29 N32 VCC7 VCC70 Y32
AT38 VCCGT8 VCCGT87 BE37 AA38 VCC8 VCC71 AJ30 N35 VCC8 VCC71 Y33
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AV35 VCCGT24 VCCGT103 BG33 AC34 VCC24 VCC87 AL29 R32 VCC24
AV36 VCCGT25 VCCGT104 BG34 AC35 VCC25 VCC88 AL30 R33 VCC25
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW33 VCCGT29 VCCGT108 BH34 AD31 VCC29 VCC92 AL36 R37 VCC29
AW34 VCCGT30 VCCGT109 BH35 AD32 VCC30 VCC93 AL37 R38 VCC30
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY36 VCCGT40 VCCGT119 BJ24 AE31 VCC40 VCC103 AM35 U30 VCC40
AY37 VCCGT41 VCCGT120 BJ26 AE32 VCC41 VCC104 AM36 U31 VCC41
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA32 VCCGT48 VCCGT127 BK20 AF31 VCC48 VCC111 AN35 V14 VCC48
BA33 VCCGT49 VCCGT128 BK21 AF32 VCC49 VCC112 AN36 V31 VCC49
BA34 VCCGT50 VCCGT129 BK23 AF33 VCC50 VCC113 AN37 V32 VCC50
BA35 VCCGT51 VCCGT130 BK24 AF34 VCC51 VCC114 AN38 V33 VCC51
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB34 VCCGT58 VCCGT137 BL24 AG32 VCC58 VCC121 AP37 W14 VCC58
BB35 VCCGT59 VCCGT138 BL25 AG33 VCC59 VCC122 AP38 W29 VCC59
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 VCCGT66 VCCGT145 @ 3
BC32 BM16 AG37 VCCSENSE
VCCGT67 VCCGT146 VCC_SENSE VCCSENSE <60>
BC35 BM17 9 OF 13 AG38 VSSSENSE
VCCGT68 VCCGT147 VSS_SENSE VSSSENSE <60>
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150 @ 1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
BR16 VCCGT161 VCCGT166 BT17
BR17 VCCGT162 VCCGT167 BT37
VCCGT163 VCCGT168
AH37 VSSGT_SENSE
11 OF VSSGT_SENSE VSSGT_SENSE <60>
3 AH38 VCCGT_SENSE
VCCGT_SENSE VCCGT_SENSE <60>
CFL-H_BGA1440
@ 1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(6/8)VCC_CORE/GT
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 12 of 73
A B C D E
A B C D E
+1.2V_VDDQ_CPU
Max: 3300mA
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6 1 2
K29 VCCSA1 VDDQ1 AE12 1 2
Max: 11100mA VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 AF5 JUMP_43X118
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5 @ JPC2
K33 VCCSA5 VDDQ5 AG9 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12 1 2
K35 VCCSA7 VDDQ7 AL11 JUMP_43X118
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12 RC24 1 @ 2 0_0402_5%
+VCC_IO M35 VCCSA20 VDDQ20 L6
Max: 6400mA VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
M36 R6
VCCSA22 VDDQ22
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23 W6 @
VDDQ24 1 1 1 1
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <61>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <61>
J26 150mA
VCCIO20 VCCIO_SENSE
1U_0201_6.3V6M
1U_0201_6.3V6M
J27 H14
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <59>
J14 1 1
12 OF 13 VSSIO_SENSE VSSIO_SENSE <59>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
@
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
1
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CFL-H(7/8)VCCSA/VCCIO/VDDQ
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 13 of 73
A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 Impedance Spectrum Tool Trigger @ TC7
IST_TRIG E3 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 @ TC8
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
VSS_5 VSS_86 VSS_167 VSS_248 VSS_330 VSS_414 @ TC9 RSVD_TP4
A22 AL34 BA10 BJ30 BP24 F25 @ TC10 D1
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 @ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 @ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <22> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <22> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 @
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 @
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 @
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 @
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 @
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 @
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
VSS_52 VSS_133 VSS_214 VSS_295 VSS_377 VSS_461 @
AG8 AU12 BG37 BM6 D20 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
CFL-H(8/8)GND/RSVD
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 14 of 73
A B C D E
A B C D E
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<10> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <46>
<10> DMI_CTX_PRX_P0 J35 J2 USB3 MB
UH1 DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <46>
<10> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <45>
<10> DMI_CRX_PTX_P0 B33 N15 TYPE C
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <45>
<10> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <48>
<10> DMI_CTX_PRX_P1 F34 K3
DMI_CRX_PTX_N1 DMI1_RXP USB2P_3 USB20_N4 USB20_P3 <48>
<10> DMI_CRX_PTX_N1 C32 M10 USB2 (SUB/B)
DMI_CRX_PTX_P1 DMI1_TXN USB2N_4 USB20_P4 USB20_N4 <48>
<10> DMI_CRX_PTX_P1 B32 L9
DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <48>
CFL-H_BGA1440 <10> DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <37>
S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO! <10> DMI_CTX_PRX_P2 J32 L2 Camera
DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6 USB20_P5 <37>
SA0000BVP10 <10> DMI_CRX_PTX_N2 C31 K7
DMI_CRX_PTX_P2 DMI2_TXN USB2N_6 USB20_P6 USB20_N6 <37>
1 PCH@ <10> DMI_CRX_PTX_P2 B31 K6 TS 1
DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_P6 <37>
<10> DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3 +3VALW _PCH_PRIM
<10> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<10> DMI_CRX_PTX_N3 C29 G4
DMI_CRX_PTX_P3 DMI3_TXN USB2N_8 USB20_P8 USB20_N8 <50>
<10> DMI_CRX_PTX_P3 B29 G5 FingerPrint RPH1
DMI3_TXP USB2P_8 USB20_P8 <50> USB_OC0#
A25 M6 8 1
B25 RSVD USB2N_9 N8 USB_OC1# 7 2
P24 RSVD USB2P_9 H3 USB_OC2# 6 3
R24 RSVD USB2N_10 H2 USB_OC3# 5 4
C26 RSVD USB2P_10 R10
B26 RSVD USB2N_11 P9 10K_0804_8P4R_5%
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
RSVD USB2N_13 FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf
C27 N2
L26 RSVD USB2P_13 E5 USB20_N14
RSVD USB2N_14 USB20_P14 USB20_N14 <41>
M26 F6 BT
RSVD USB2P_14 USB20_P14 <41>
D29
E28 RSVD AH36 USB_OC0#
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <44>
K29 AL40 USB_OC1# <46>
M29 RSVD GPP_E10/USB2_OC1# AJ44 USB_OC2#
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3# +3VALW
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
1
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN USB2_RCOMP RH3
P21 F4 RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE RH5 10K_0402_5%
B18 F3 1 @ 2 0_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
2
2 GPD_7 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID RH6 1 @ 2 0_0402_5%
PCIE3_RXN/USB31_9_RXN USB2_ID
STRAP
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
1
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP RH7
N18 G45
PCIE4_RXN/USB31_10_RXN PCIE24_TXP 10K_0402_5%
R18 G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
PCIE5_RXN PCIE23_TXP X'tal Input:
G20 G49 High: Differential
B21 PCIE5_RXP PCIE23_TXN W44 Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43
K21 PCIE5_TXP PCIE23_RXN H48
J21 PCIE6_RXN PCIE22_TXP H47
D21 PCIE6_RXP PCIE22_TXN U41
C21 PCIE6_TXN PCIE22_RXP U40
B23 PCIE6_TXP PCIE22_RXN F46
C23 PCIE7_TXP PCIE21_TXP G47
J24 PCIE7_TXN PCIE21_TXN R44
L24 PCIE7_RXP PCIE21_RXP T43
F24 PCIE7_RXN PCIE21_RXN
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
3 3
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH(1/8)DMI/PCIE/USB2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 15 of 73
A B C D E
A B C D E
18P_0402_50V8J
RH10 1 2 60.4_0402_1% T3 AH9
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN CLK_PCIE_LAN# <40>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <40>
CH5
CH6
XCLK_BIASREF (PDG) BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14 CLK_PCIE_W LAN#
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN CLK_PCIE_W LAN# <41>
8/24 AE15 NGFF WL+BT(KEY E)
VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <41>
BF31
LAN_CLKREQ# BE31 GPP_B5/SRCCLKREQ0# AE6 CLK_PCIE_NGFF#
<40> LAN_CLKREQ# W LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF CLK_PCIE_NGFF# <39>
<41> W LAN_CLKREQ# AR32 AE7 M2 SSD
SSD_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF <39>
<39> SSD_CLKREQ# BB30
BA30 GPP_B8/SRCCLKREQ3# AC2
PCH_RTCX1 AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
1 2 AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
RH12 10M_0402_5% AC41 GPP_H3/SRCCLKREQ9# W4
AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
32.768KHZ_9PF_X1A000141000200 GPP_H9/SRCCLKREQ15# AC14
1 1 CLKOUT_PCIE_N8
10P_0402_50V8J
10P_0402_50V8J
V2 AC15
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 Trace Space: 15 mil 2 T2 CLKOUT_PCIE_N9 U3
Max Trace Length: 1000 mil T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 CLKOUT_PCIE_P14 AC9 2
AA1 CLKOUT_PCIE_N10 AC11
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
use same part w C5MMH AC7 CLKOUT_PCIE_N11 AE11
+3VS CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
AC6
CLKOUT_PCIE_P12 7 OF 13 R6 REFCLK_CNV
CLKIN_XTAL REFCLK_CNV <41>
CNP-H_BGA874 Rev1.0
1
RPH2 @ 1
8 1 LAN_CLKREQ# RH14
7 2 VGA_CLKREQ# 10K_0402_5% CH51 @ESD@
W LAN_CLKREQ# VGA_CLKREQ# <25>
6 3 4.7P_0201_50V8B
5 4 SSD_CLKREQ# 2
2
10K_0804_8P4R_5%
CNP-H
UH1M
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 16 of 73
A B C D E
A
CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8 DDP[B..F]CTRLDATA
no follow naming GPP_I6/DDPB_CTRLDATA This signal has a weak internal Pull-down.
AT6 AN13
HDMI_HPD_PCH AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10 0 = Port B~D is not detected.
<26,38> HDMI_HPD_PCH GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA 1 = Port B,C,D is detected. (Default)
AP9 AL9 Notes:
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA
1. The internal Pull-down is disabled after
AN40 PCH_PWROK de-asserts.
08/18 GPP_F23/DDPF_CTRLDATA AT49 2. This signal is in the primary well.
GPP_F22/DDPF_CTRLCLK
AP41
EDP_HPD AN6 GPP_F14/PS_ON#
<37> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
CNP-H_BGA874 Rev1.0
remove CIO_PLUG_EVENT#
@
CNP-H
UH1A PLT_RST#
EC_PME#_R PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 BE36 AV29
<40,43> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <19,26,36,43,49>
RH24 0_0402_5%
@ESD@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
CRB PU 20k RSVD1 GPP_K12/GSXDOUT
#571182_CFL_PCH_EDS_Rev1.0 recommend 100k Y48 provided by the PCH to expand the GPIOs
GPP_K13/GSXSLOAD W46 on a platform that needs more GPIOs than the
GPP_K14/GSXDIN ones provided by the PCH.
+3VALW _SPI PDG P348 quad mode support PH1K 0_0402_5% 1 @ 2 RH186 AL37 AA45
AN35 VSS GPP_K15/GSXSRESET#
TH6 @ TP
RH25 2 1 1K_0402_5% PCH_SPI_IO2 PCH_SPI_SI AU41 AL47 DH1
PCH_SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45 RB751V-40_SOD323-2
RH26 2 1 1K_0402_5% PCH_SPI_IO3 PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TP_INT# 2 1 +3VS
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 EC_TP_INT# <43,49>
AW47 BC33
<19> PCH_SPI_CLK SPI0_CLK GPP_B4/CPU_GP3 TYPEC_1P5A <44>
AW48
RH27 2 1 1K_0402_5%PCH_SPI_SI SPI0_CS1# AE44 TP_INT# RH28 2 1 100K_0402_5%
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
+3VALW _PCH_PRIM PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15
RH29 2 1 100K_0402_5% GPP_H15 STRAP SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47
#571182_CNL_PCH_H_EDS_V1_Rev0.7 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK GPP_H12
External pull-up is required. Recommend 100K if pulled BF19 AB47
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <20> +RTCVCC
up to 3.3V or 75K if pulled up to 1.8V. BF18 AD47
571007_CFL_MOW_Archive_WW22_2017 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
STUFF R on GPP_H15 BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
<47> HDD_PW RGT GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
reserve for Optane Memory A 1 M pull-up is used on the customer reference
1 @ board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
+3VALW _SPI
CH10 0.1U_0201_10V6K
UH2 PCH_SPI_CS#0
1 2 1 @ 2
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R +3VS
4 /WP(IO2) CLK 5 PCH_SPI_SI_0_R
GND DI(IO0)
CH11 1 2
W 25Q128FVSIQ_SO8
P/N: SA00005VV20 .1U_0402_16V7K
5
PCH_SPI_SO_0_R RH108 1 2 49.9_0402_1% PCH_SPI_SO UH3
@EMI@ @EMI@ PCH_SPI_IO3_0_R RH109 1 2 49.9_0402_1% PCH_SPI_IO3 PLT_RST# 1
P
PCH_SPI_CLK_0_R 1 2 1 2 PCH_SPI_CLK_0_R RH110 1 2 49.9_0402_1% PCH_SPI_CLK B 4
PCH_SPI_IO2_0_R PCH_SPI_IO2 Y PLT_RST_BUF# <39,40,41>
RH111 1 2 49.9_0402_1% 2
A
G
RH33 CH12
0_0402_5% 68P_0402_50V8J sch checklist 0.7 TC7SH08FU_SSOP5
3
1 device 15 ohm / 2 device 33 ohm
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
PCH(3/8)DDC/SPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 17 of 73
A
A B C D E
#571391_CFL_H_PDG_Rev0p5
‧ eSPI clock and eSPI data mismatched: <500 mils.
‧ eSPI clock and eSPI chip select mismatched: <500 mils.
‧ eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
UH1F
F9 BB39 LPC_AD0
<46> USB3_PTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <43,49>
F7 1.8V AW37 LPC Bus check straps
<46> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <43,49>
USB3 MB <46> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <43,49>
<46> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <43,49>
C3
<45> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<45> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <43,49>
1 USB3 Type C <45> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <43,49> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<45> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <43>
C16
G14 USB31_6_TXP BB36 CLK_LPC RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_TPM CLK_LPC_R <43>
F14 BB34 RH36 2 TPM@ 1 22_0402_5%
USB31_6_RXP GPP_A10/CLKOUT_LPC1 CLK_LPC_TPM_R <49>
C15
<48> USB3_PTX_DRX_N5 USB31_5_TXN
B15 T48
<48> USB3_PTX_DRX_P5 USB31_5_TXP GPP_K19/SMI#
USB3 SUB <48> USB3_PRX_DTX_N5 J13 T47
K13 USB31_5_RXN GPP_K18/NMI#
<48> USB3_PRX_DTX_P5 USB31_5_RXP
G12 AH40
<45> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2
F11 AH35
<45> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <39>
USB3 Type C <45> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47
<45> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37 +3VS
C14 GPP_F8/SATA_DEVSLP6 AN46
<48> USB3_PTX_DRX_P4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
B14 AR47
<48> USB3_PTX_DRX_N4 USB31_4_TXN GPP_F6/SATA_DEVSLP4
USB3 SUB <48> USB3_PRX_DTX_P4 J15 AP48
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
<48> USB3_PRX_DTX_N4 USB31_4_RXN TPM_SERIRQ 2 1 RH37
CNP-H_BGA874 Rev1.0
10K_0402_5%
@
LPC_PIRQA# 1 2 RH38
CNP-H 10K_0402_5%
2 UH1C 2
CL_CLK AR2 G36
TH10 @ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <39>
For Intel CLINK TH11 @ AT5 F36 M.2 SSD PCIE L3
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PRX_DTX_P9 <39>
TH12 @ CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 <39>
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <39>
V47 GPP_K8
V48 GPP_K9 K37
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_N10 <39>
GPP_K11 PCIE10_RXP PCIE_PRX_DTX_P10 <39> M.2 SSD PCIE L2
C35
L47 PCIE10_TXN B35 PCIE_PTX_DRX_N10 <39>
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <39>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <41>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 PCIE_PRX_DTX_P15 <41> NGFF
N48 B40 .1U_0402_16V7K 1 2 CH1
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2
PCIE_PTX_C_DRX_N15 <41> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <41>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<39> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<39> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD PCIE L1 <39> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
G38 K43
<39> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 SATA_PRX_DTX_N4 <47>
AR42 PCIE17_RXP/SATA4_RXP A42 SATA_PRX_DTX_P4 <47>
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_N4 <47>
HDD
AR48 B42
DGPU_PRSNT# AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 <47>
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
3 CH3 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N14 C39 PCIE18_RXP/SATA5_RXP C42 3
<40> PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
CH4 2 1 .1U_0402_16V7K D39 D42 +3VS
<40> PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
GLAN <40> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN
C47 AK48
<40> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <39>
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 RH187 1 PBA@ 2 1K_0402_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 SATA_GP1 RH39 2 1 10K_0402_5%
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5
<39> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 @ TH13
D38 AM47 M.2 SSD PCIE/SATA select pin
<39> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48
<39> PCIE_PRX_DTX_P12 H42 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7
M.2 SSD PCIE L0 <39> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN PCH_BKL_PW M
AU48
GPP_F21/EDP_BKLTCTL PCH_BKL_PW M <26,37>
B44 AV46 ENBKL
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL <26,43>
A44 AV44
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <26,37>
R37 #571391_CFL_H_PDG_Rev0p5.pdf
R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <11>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <11,43>
C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW _PCH_PRIM PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <11>
N42 AG5
PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <11>
M44 AE2
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <11>
1
CNP-H_BGA874 Rev1.0
RH43 @
10K_0402_5% UMA@
2
4 4
DGPU_PRSNT#
1
RH44
GPP_F13 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% VGA@ DGPU PRSNT# 2017/07/20 2018/07/20 Title
Issued Date Deciphered Date
DIS,Optimus 0 PCIE/SATA/USB3/eSPI
2
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
UMA 1 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 18 of 73
A B C D E
A B C D E
+1.2V_VDDQ
<43> ME_EN 1 @ 2
2
RPH7 RH45 0_0402_5%
1 8 HDA_RST# RH46
<42> HDA_RST#_R HDA_BIT_CLK
<42> HDA_BIT_CLK_R 2 7 470_0402_1%
3 6 HDA_SDOUT
<42> HDA_SDOUT_R HDA_SYNC
<42> HDA_SYNC_R 4 5
1
DRAM_RESET# 1 @ 2
DDR_DRAMRST#_R <23,24>
33_0804_8P4R_5% RH47 0_0402_5%
2 1
1 CH13 1U_0402_6.3V6K 1
CNP-H
@
UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
<42> HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# PM_CLKRUN# <49>
del RF reserve cap on HDA BF12
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC @ TH14
HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# @ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 LAN_GPO TYPEC_3A <44>
BE29
RH48 1 CPU_DISPA_SDO GPP_B0/GSPI0_CS1# PCH_GPP_K17 LAN_GPO <40>
2 30_0402_5% AM2 R47 @ TH19
<7> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11
AN3 AP29 @ TH20
<7> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <43,51>
<7> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
FOR Jefferson Peak RESET pin is glitch free,it AV18 BB47 WAKE#
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 PM_SLP_A#
is recommended that a pull-down resistor of 75K CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SLP_LAN# @ TH37
ohm on GPP_D5(CNV_RF_RESET#) <41> CLKREQ_CNV# CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# PM_SLP_S0# @ TH21
BE16 BC28
<41> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <43>
<42> PCH_DMIC_DATA0 BF15 BF42
GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# <43,51>
BD16 BE42
+RTCVCC <42> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <43,51>
TH22 @ AV16 BC42 @ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
PCH_SRTCRST# TH24 @ GPP_D17/DMIC_CLK1/SNDW3_CLK
RH50 1 2 20K_0402_1% BE45 SUSCLK
GPD8/SUSCLK PM_BATLOW # SUSCLK <39,41>
BF44
CH18 1 2 1U_0402_6.3V6K GPD0/BATLOW# BE35 SUSACK#_R
PCH_RTCRST# GPP_A15/SUSACK# @ T207
2 BE47 BC37 1 @ 2 2
<43> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPW RDNACK <43>
CLR ME BD46 RH51 0_0402_5%
Delay 18~25 ms SRTCRST#
PCH_PW ROK AY42 BG44 LAN_W AKE#
PCH_RTCRST# <43,51> PCH_PW ROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R
RH52 1 2 20K_0402_1% <43> EC_RSMRST# BA47 BG42 RH53 1 @ 2 0_0402_5% AC_PRESENT <43>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS# T208
SLP_SUS# PBTN_OUT#_R @ --No Support Deep Sx
CH19 1 2 1U_0402_6.3V6K BE46 1 @ 2 PBTN_OUT# <43>
PCH_DPW ROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# RH54 0_0402_5%
JCMOS1 1 @ 2 0_0603_5% ECLR CMOS PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
Delay 18~25 ms <20> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPW RGD PCH_SPKR <20,42>
BE26 AE3
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <11>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE T209
<20> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 @
BF25 AH4 CPU_XDP_TCK0 <11>
PCH_SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <11>
<20> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <11> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <11>
PCH_SML1DATA BE27 4 OF 13 AJ3
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <11>
CNP-H_BGA874 Rev1.0
@
RH55 2 1 1K_0402_5% W AKE#
QH7B
PM_CLKRUN# 10K_0804_8P4R_5% +3VALW _PCH_PRIM
RH60 2 1 8.2K_0402_5% 2N7002KDW _SOT363-6
PCH_SMBCLK D_CK_SCLK
(DDR,G-Sensor) PCH_VRALERT# RH62 2
3 4 @ 1 10K_0402_5%
S
D_CK_SCLK <23,24,47>
D
QH7A
2N7002KDW _SOT363-6
100K_0402_5% 1 @ 2 RH61 PCH_DPW ROK
+3VS PCH_SMBDATA 6 1 D_CK_SDATA
S
D_CK_SDATA <23,24,47>
@ESD@
D
+3VALW _PCH_PRIM
RPH12
1 8 I2C_1_SCL CNP-H
2 7 I2C_1_SDA UH1K
3 6 I2C_0_SCL
4 5 I2C_0_SDA GSPI1_MOSI BA26 BA20 VGA_ID1
BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 VGA_ID2
2.2K_0804_8P4R_5% EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PROJECT_ID0
<43> EC_SCI# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14 +1.8VALW _PRIM
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<26,36> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29 BF17
<37,43> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 SUB_DET SUB_DET RH185 1 @ 2 1K_0402_5% 1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD check needed? BB24 Pop for USB3.0 DB.
DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<26,43,54> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS AP24
GPU_EVENT# BA24 GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 <26> GPU_EVENT# GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PW R_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<26,36> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL +3VS
AU24 AH48
<26,36> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
GPP_C23/UART2_CTS#
2
UART_2_PRTS_DCTS AW21
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34 RH78
<41> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32 @ 10K_0402_5%
+3VALW _PCH_PRIM <41> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 G_INT
<49> I2C_1_SCL
1
I2C_1_SDA BF21 GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 BD34 CODEC_ID G_INT
RH74 1 @ 2 4.7K_0402_5% GPP_H12 <Touch PAD> <49> I2C_1_SDA I2C_0_SCL BC22 GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 BF35
G_INT <47>
GPP_H12 <17> I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
BF23 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
2
This signal has a weak internal pull-down. STRAP
0 = Master Attached Flash Sharing (MAFS) enabled (Default) BE15 RH79
1 = Slave Attached Flash Sharing (SAFS) enabled.
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
OF 3 @
Notes: GPP_D23/ISH_I2C2_SCL/I2C3_SCL 100K_0402_5%
1. This signal is in the primary well.
Warning: This strap must be configured to ‘ 0’ i f th e CNP-H_BGA874 Rev1.0
1
eSPI or LPC strap is configured to ‘ 0’
@
2 2
+3VALW _PCH_PRIM
+3VALW _PCH_PRIM
RH112 1 @ 2 4.7K_0402_5%
PCH_SMBALERT# <19> CODEC_ID RH188 1 256@ 2 1K_0402_5%
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default) CODEC_ID / GPP_A19
1 = Enable Intel ME (TLS) 0 = 2 DMIC, 255@ (default)
1 = 4 DMIC, 256@
RH113 1 @ 2 4.7K_0402_5%
PCH_SML0ALERT# <19>
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected +1.8VALW _PRIM
+1.8VALW _PRIM
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
PCH(6/8)GPIO/I2C/UART/STRAP
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 20 of 73
A B C D E
A B C D E
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW_PCH_PRIM
+1.05VALW_PCH_PR M UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
AA23 VCCPRIM_1P051 VCCPRIM_3P32
RH92 2 @ 1 0_1206_5% 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT GPPD 1.8V
AB22 BG47 +VCCRTCEXT
VCCPRIM_1P054 DCPRTC2
1U_0402_6.3V6K
1 AB23
AB27 VCCPRIM_1P055 V23 0.095A +3VALW_SPI
VCCPRIM_1P056 VCCPRIM_3P35
GPPE
CH23
.1U_0402_16V7K
AB28 1 3.3V
AB30 VCCPRIM_1P057 AN44 0.05A GPPF
2 VCCPRIM_1P058 VCCSPI +RTCVCC
CH24
AD20
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49 2
AD28 VCCPRIM_1P0511 VCCRTC2
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW_VCCMPHY AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW_VCCMPHY AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518
GPPI 3.3V Only
RH93 2 1 0_0805_5% 6.6A AC35 0.262A
6.6A U26 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A GPPJ 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36 +1.8VALW_PR M
VCCPRIM_1P0525 VCCPGPPEF2
22U_0402_6.3V6M
1U_0402_6.3V6K
1 1 V27
V28 VCCPRIM_1P0526 AN24 0.14A GPD 3.3V Only
VCCPRIM_1P0527 VCCPGPPD +1.8VALW_PRIM
CH25
CH26
V30 AN26
+1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
2 2 VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0402_6 3V6K
1 1
0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
BE48
3-5MM FROM PACKAGE EDGE 0.42A W22 VCCDSW_3P31 BE49 0.113A
VCCDUSB_1P051 VCCDSW_3P32 +3VALW_DSW +3VALW_HDA 2 2
W23
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 @ 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO 1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_ N 2
1U_0402_6 3V6K
.1U_0402_16V7K
CH30
C2 BG5
2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19 RH174 for 571391 CFL H PDG Rev0p71 pdf
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE
VCCMPHY_SENSE VSSMPHY_SENSE @ TH27
0.021A B1 K46 @ TH28
For DDX03 R02
B2 VCCAPLL_1P051 VSSMPHY_SENSE
B3 VCCAPLL_1P052 8 OF 13 +1.24V_PRIM_MAR
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31 @
4.7U_0402_6.3V6M
1
CH32
+1.05VALW_PCH +1.05VALW_PCH 2
+1.05VALW_PCH
1U_0402_6.3V6K
.1U_0402_16V7K
1 1
+3VALW_PCH_PRIM
1U_0402_6.3V6K
1
+3VALW_PCH_PRIM +3VALW_PCH_PRIM
CH33
CH34
2 2
2
1U_0402_6.3V6K
.1U_0402_16V7K
1 1
.1U_0402_16V7K
RH97 1 @ 2 0_0805_5% RH98 1 @ 2 0_0603_5% 1
.1U_0402_16V7K
CH37
CH38
1
CH36
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE 2 2
CH39
+1.8VALW +1.8VALW_PR M
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3 +3VALW_DSW 2
@ 2
RH99 1 @ 2 0_0402_5% RH100 1 @ 2 0_0603_5% @
.1U_0402_16V7K
1
CH40
3 3
1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE
2 FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_PCH +3VALW_HDA
RH102 1 @ 2 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
1P_0402_50V8
1P_0402_50V8
CH41
CH42
1 1
CH43
CH44
2 2
@ @
2 2
@ @ reserve filter folloe CRB
8/21
1-3MM FROM PACKAGE EDGE
+1.05VALW_VCCAMPHYPLL
RH103 1 @ 2 0_0402_5%
22U_0402_6.3V6M
1U_0402_6.3V6K
1 1
CH45
CH46
.1U_0402_16V7K
1 1 4
+1.05VALW_XTAL GND
CH47
CH48
ACES_50271-0020N-001
RH105 1 @ 2 0_0402_5% CONN@
2 2
SP02000RO00
22U_0402_6.3V6M
1
Security Classification Compal Secret Data Compal Electronics, Inc.
CH49
@
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
PCH(7/8)Power
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 21 of 73
A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <11>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <11>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# PCH_TRIGOUT RH106 1 PCH_TRIGOUT_R CPU_XDP_TRST# <11>
AA27 AN38 D8 R16 AK3 2 30_0402_5%
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <14>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <14>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
VSS VSS VSS VSS @
AB19 AR38 E22 R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC17 VSS VSS AT21 E33 VSS VSS T4
AC33 VSS VSS AT24 E35 VSS VSS T49
AC38 VSS VSS AT26 E40 VSS VSS T5
AC4 VSS VSS AT29 E42 VSS VSS T7
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AF25 VSS VSS BA14 J47 VSS VSS W28
AF28 VSS VSS BA44 J48 VSS VSS W30
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
PCH(8/8)GND/RSVD
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 22 of 73
A B C D E
5 3 2 1
<8>
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#0
DDR_A_CS#1
149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS#0 DDR_A_DQS0 <8>
157 11
<8> DDR_A_D[16..31] <8> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <8>
D
162 D
+3VS +3VS +3VS 165 S2#/C0 28 DDR_A_D8
<8> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D 0
<8> DDR_A_D[48..63] <8> DDR_A_ODT0 ODT0 DQ10
1
1
DDR_A_ODT1 161 42 DDR_A_D
<8> DDR_A_ODT1 ODT1 DQ11 DDR_A_D 2
RD4 RD1 RD5 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <8> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
<8> DDR_A_BG1 DDR_A_BA0 BG1 DQ14 DDR_A_D15
111 141 150 37
+1.2V_VDDQ +1.2V_VDDQ <8> DDR_A_BA0
2
2
SA0_CHA_DIM1 SA1_CHA_D M1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <8> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <8>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <8>
VDD4 VDD14 <8> DDR_A_MA0 A0
1
1
123 153 DDR_A_MA 133 50 DDR_A_D16
VDD5 VDD15 <8> DDR_A_MA1 DDR_A_MA2 A1 DQ16 DDR_A_D 7
RD3 RD6 RD2 124 154 132 49
VDD6 VDD16 <8> DDR_A_MA2 DDR_A_MA3 A2 DQ17 DDR_A_D18
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% 129 159 131 62
VDD7 VDD17 <8> DDR_A_MA3 DDR_A_MA4 A3 DQ18 DDR_A_D19
130 160 128 63
VDD8 VDD18 <8> DDR_A_MA4 DDR_A_MA5 A4 DQ19 DDR_A_D20
135 163 126 46
<8> DDR_A_MA5
2
2
+3VS 136 VDD9 VDD19 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 <8> DDR_A_MA6 DDR_A_MA7 A6 DQ21 DDR_A_D22
122 58
<8> DDR_A_MA7 DDR_A_MA8 A7 DQ22 DDR_A_D23
255 258 125 59
VDDSPD VTT +0.6VS_VTT <8> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<8> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2 DDR_A_DQS2 <8>
164 257 146 53
2.2U_0402_6.3V6M
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM +0.6V_DDR_VREFCA VREFCA VPP1 +2.5V <8> DDR_A_MA10 DDR_A_MA11 A10_AP DQS2#(C) DDR_A_DQS#2 <8>
.1U_0402_16V7K
2 2 259 120
VPP2 <8> DDR_A_MA11 DDR_A_MA 2 A11 DDR_A_D24
CD1
119 70
<8> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
CD2
1 99 158 71
VSS VSS <8> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 VSS VSS <8> DDR_A_MA14_WE# DDR_A_MA15_CAS# A14_WE# DQ26 DDR_A_D27
5 103 156 84
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <8> DDR_A_MA15_CAS#
<8> DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<8> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <8> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <8>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <8>1 DDR A ALERT#
240_0402_1% D MM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <8>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<19,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
CD4
CD5
CD6
CD7
CD8
CD9
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <8>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
77 VSS VSS 231 75 DM2#/DBI2# DQ51 211 DDR_A_D52
78 VSS VSS 234 178 DM3#/DBI3# DQ52 212 DDR_A_D53
81 VSS VSS 235 199 DM4#/DBI4# DQ53 224 DDR_A_D54
82 VSS VSS 238 220 DM5#/DBI5# DQ54 225 DDR_A_D55
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <8>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <8>
89 244
VSS VSS
.1U_0402_16V7K
Layout Note: 90 247 2
VSS VSS
CD10
93 248
PLACE THE CAP near JDIMM1. 164 94 VSS VSS 251 237 DDR_A_D56
98 VSS VSS 252 DQ56 236 DDR_A_D57
B VSS VSS 1 DQ57 249 DDR_A_D58 B
@ DQ58 DDR_A_D59
262 261 250
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
CONN@ 246
0.1uF*1 PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) DDR_A_DQS#7 DDR_A_DQS7 <8>
2 2 240
DQS7#(C) DDR_A_DQS#7 <8>
CD11
.1U_0402_16V7K CD12
2.2U_0402_6.3V6M
1 1 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 2 1K_0402_1%
CD13 @
.1U_0402_16V7K
1
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
1uF*8 1 signals
+1.2V_VDDQ +1.2V_VDDQ 2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD24
CD25
CD26
CD27
CD28
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
@ @
1
DDR_B_CS#0 149 13 DDR_B_DQS0
D <9> DDR_B_D[48..63] <9> DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#0 DDR_B_DQS0 <9> D
RD12 RD13 RD14 157 11
<9> DDR_B_CS#1
162 S1# DQS0#(C) DDR_B_DQS#0 <9>
0_0402_5% @ 0_0402_5% @ 0_0402_5% JD MM2B
@ S2#/C0 DDR_B_D8
RESERVE 165 28
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ +1.2V_VDDQ
2
2
SA0_CHB_DIM3 SA1_CHB_DIM3 SA2_CHB_DIM3 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D
117 VDD2 VDD12 147 <9> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D15
VDD3 VDD13 <9> DDR_B_ODT1 ODT1 DQ11
1
1
RD16 123 153 DDR_B_BG0 115 25 DDR_B_D10
124 VDD5 VDD15 154 <9> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
RD15 @ 0_0402_5% RD17
VDD6 VDD16 <9> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
@ 0_0402_5% @ 0_0402_5% 129 159 150 37
130 VDD7 VDD17 160 <9> DDR_B_BA0 DDR_B_BA 145 BA0 DQ15 34 DDR_B_DQS
<9> DDR_B_BA1 DDR_B_DQS1 <9>
2
2
+3VS 136 VDD9 VDD19 DDR_B_MA0 144 DQS1#(C)
VDD10 <9> DDR_B_MA0 DDR_B_MA A0 DDR_B_D16
133 50
<9> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <9> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
<9> DDR_B_MA3 DDR_B_MA4 A3 DQ18 DDR_B_D20
164 257 128 63
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 +2.5V <9> DDR_B_MA4 DDR_B_MA5 A4 DQ19 DDR_B_D22
.1U_0402_16V7K
2 2 259 126 46
VPP2 <9> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
CD33
127 45
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <9> DDR_B_MA6 DDR_B_MA7 A6 DQ21 DDR_B_D23
CD34
1 99 122 58
VSS VSS <9> DDR_B_MA7 DDR_B_MA8 A7 DQ22 DDR_B_D21
2 102 125 59
1 1 VSS VSS <9> DDR_B_MA8 DDR_B_MA9 A8 DQ23 DDR_B_DQS2
5 103 121 55
VSS VSS <9> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <9>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <9> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <9>
VSS VSS <9> DDR_B_MA11 DDR_B_MA12 A11 DDR_B_D30
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <9> DDR_B_MA12 DDR_B_MA13
119
158 A12 DQ24
70
71 DDR_B_D25
VSS VSS <9> DDR_B_MA13 DDR_B_MA14_WE# A13 DQ25 DDR_B_D26
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <9> DDR_B_MA14_WE#
<9> DDR_B_MA15_CAS#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84 DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<9> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D27
23 180 DDR_B_ACT# 114 79 DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 26 VSS
VSS
VSS
VSS
181 <9> DDR_B_ACT#
DDR_B_PAR
ACT# DQ30
DQ31
80 DDR_B_D3
DDR_B_DQS3
27 184 143 76
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <9> DDR_B_PAR
<9> DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<9>
<9>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
VSS VSS <19,23> DDR_DRAMRST#_R RESET# DQ32 DDR_B_D35
Layout Note: Layout Note: 36 192 173
39 VSS VSS 193 DQ33 187 DDR_B_D36
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <19,23,47> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
VSS VSS <19,23,47> D_CK_SCLK SCL DQ36 DDR_B_D38
44 201 169
47 VSS VSS 202 SA2_CHB_DIM3 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 SA1_CHB_DIM3 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 SA0_CHB_DIM3 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <9>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <9>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40 DDR_B_D41
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1 1 1 1 1 1 60 214 91 194
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42 DDR_B_D43
CD35
CD36
CD37
CD38
CD39
CD40
CD41
LOTES_ADDR0070-P009A
CONN@
2
Layout Note: CD44 @
DIMM Side CPU Side
2
.1U_0402_16V7K
Place near JDIMM3 RD19
1
1K_0402_1%
+0 6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 CD45 1
signals
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CD47
CD48
CD49
CD50
CD52
CD53
CD54
0.022U_0402_16V7K
1 2
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD22
24.9_0402_1%
@ @
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/07/20 Deciphered Date 2018/07/20 T tle
WWW.AliSaler.Com
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 24 of 73
5 3 2 1
5 3 2 1
UG1 UG1A
1/23 PCI_EXPRESS
+1.0VSDGPU
BB33
DGPU_PEX_RST# DGPU_PEX_RST#_R PEX_DVDD_1
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1 @ 2 BK26 BB35
<26,36> DGPU_PEX_RST# PEX_RST* PEX_DVDD_2
VGA@ CG7
N17E-G1 R1 RG1 0_0402_5% BB36 1 1 1 1 1 1 2 1
PEX_CLKREQ# PEX_DVDD_3
VGA@ CG1
VGA@ CG2
VGA@ CG3
VGA@ CG4
VGA@ CG5
VGA@ CG6
VGA@ CG8
VGA@ BL26 BC33
PEX_CLKREQ* PEX_DVDD_4 BC35
SA00009PM10 PEX_DVDD_5
BM26 BC36
<16> CLK_PEG_VGA BM27 PEX_REFCLK PEX_DVDD_6 BD33 2 2 2 2 2 2 1 2
D <16> CLK_PEG_VGA# PEX_REFCLK* PEX_DVDD_7 BD36 D
BG26 PEX_DVDD_8
+3VSDGPU +3VSDGPU <10> PEG_CRX_C_GTX_P0 BH26 PEX_TX0
<10> PEG_CRX_C_GTX_N0 PEX_TX0*
<10>
<10>
PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
BL27
BK27 PEX_RX0
PEX_RX0*
Under GPU +1.8VSDGPU_MAIN
2
BF26
<10> PEG_CRX_C_GTX_P1 PEX_TX1
2
BE26 BB26
<10> PEG_CRX_C_GTX_N1 PEX_TX1* PEX_HVDD_1
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
VGA@ RG2 RG3 VGA@ BB27
10K_0201_5% 10K_0201_5% BK29 PEX_HVDD_2 BB29
<10> PEG_CTX_C_GRX_P1 PEX_RX1 PEX_HVDD_3 1 1 1 1 1 1 2 2
1
VGA@ CG9
VGA@ CG10
VGA@ CG11
VGA@ CG12
VGA@ CG13
VGA@ CG14
VGA@ CG15
VGA@ CG16
VGA@ CG17
BL29 BB32
<10> PEG_CTX_C_GRX_N1
1 PEX_RX1* PEX_HVDD_4 BC26
1
BF27 PEX_HVDD_5 BC27
2
<10> PEG_CRX_C_GTX_P2 BG27 PEX_TX2 PEX_HVDD_6 BC29 2 2 2 2 2 2 1 1
<10> PEG_CRX_C_GTX_N2 PEX_TX2* PEX_HVDD_7
2
BC30
G
QG16
<10>
<10>
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
BG29
BH29 PEX_TX3
PEX_TX3*
PEX_HVDD_11
Under GPU
MESS138W-G_SOT323-3 BL30
<10> PEG_CTX_C_GRX_P3 PEX_RX3
VGA@ BK30
<10> PEG_CTX_C_GRX_N3 PEX_RX3*
BF29
<10> PEG_CRX_C_GTX_P4 BE29 PEX_TX4
<10> PEG_CRX_C_GTX_N4 PEX_TX4*
BK32
<10> PEG_CTX_C_GRX_P4 PEX_RX4
BL32
<10> PEG_CTX_C_GRX_N4 PEX_RX4*
BF30
C <10> PEG_CRX_C_GTX_P5 BG30 PEX_TX5 C
@
<10> PEG_CRX_C_GTX_N5 PEX_TX5* BB30 +PEX_PLL_HVDD 1 2
PEX_PLL_HVDD +1.8VSDGPU_MAIN
BM32 RM20 0_0402_5%
<10> PEG_CTX_C_GRX_P5 PEX_RX5
BM33 1
<10> PEG_CTX_C_GRX_N5 PEX_RX5* CG18 VGA@
BG32 0.1U_0201_10V6K
<10> PEG_CRX_C_GTX_P6 BH32 PEX_TX6
<10> PEG_CRX_C_GTX_N6 PEX_TX6* 2
BL33
<10> PEG_CTX_C_GRX_P6 PEX_RX6
BK33
<10> PEG_CTX_C_GRX_N6 PEX_RX6*
BF32
<10> PEG_CRX_C_GTX_P7 BE32 PEX_TX7
<10> PEG_CRX_C_GTX_N7 PEX_TX7*
BK35
<10> PEG_CTX_C_GRX_P7 PEX_RX7
BL35
<10> PEG_CTX_C_GRX_N7 PEX_RX7*
BF33
<10> PEG_CRX_C_GTX_P8 BG33 PEX_TX8
<10> PEG_CRX_C_GTX_N8 PEX_TX8*
BM35
<10> PEG_CTX_C_GRX_P8 PEX_RX8
BM36
<10> PEG_CTX_C_GRX_N8 PEX_RX8*
BG35
<10> PEG_CRX_C_GTX_P9 BH35 PEX_TX9
<10> PEG_CRX_C_GTX_N9 PEX_TX9*
BL36
<10> PEG_CTX_C_GRX_P9 PEX_RX9
BK36
<10> PEG_CTX_C_GRX_N9 PEX_RX9*
BF35
<10> PEG_CRX_C_GTX_P10 BE35 PEX_TX10 22uF 10uF 4.7uF 1uF 0.1uF
<10> PEG_CRX_C_GTX_N10 PEX_TX10*
B BK38 B
<10> PEG_CTX_C_GRX_P10 PEX_RX10
BL38
<10> PEG_CTX_C_GRX_N10 PEX_RX10* PEX_DVDD 1 1 2 4
BF36
<10> PEG_CRX_C_GTX_P11 BG36 PEX_TX11
<10> PEG_CRX_C_GTX_N11 PEX_TX11*
<10> PEG_CTX_C_GRX_P11
BM38 PEX_HVDD 1 2 2 4
BM39 PEX_RX11
<10> PEG_CTX_C_GRX_N11 PEX_RX11*
BG38
<10> PEG_CRX_C_GTX_P12 BH38 PEX_TX12
<10> PEG_CRX_C_GTX_N12 PEX_TX12*
BL39
<10> PEG_CTX_C_GRX_P12 PEX_RX12
BK39
<10> PEG_CTX_C_GRX_N12 PEX_RX12*
BF38
<10> PEG_CRX_C_GTX_P13 BE38 PEX_TX13
<10> PEG_CRX_C_GTX_N13 PEX_TX13*
BK41
<10> PEG_CTX_C_GRX_P13 PEX_RX13
BL41
<10> PEG_CTX_C_GRX_N13 PEX_RX13*
BF39
<10> PEG_CRX_C_GTX_P14 BG39 PEX_TX14
<10> PEG_CRX_C_GTX_N14 PEX_TX14*
BM41
<10> PEG_CTX_C_GRX_P14 PEX_RX14
BM42
<10> PEG_CTX_C_GRX_N14 PEX_RX14*
BH41
<10> PEG_CRX_C_GTX_P15 BG41 PEX_TX15
<10> PEG_CRX_C_GTX_N15 PEX_TX15*
BL42 BL44 PEX_TERMP 2 1
<10> PEG_CTX_C_GRX_P15 PEX_RX15 PEX_TERMP
BK42
A <10> PEG_CTX_C_GRX_N15 PEX_RX15* A
RG4
2.49K_0402_1%
VGA@
@ N17E-G1_BGA2152~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
N17E-G1(1/8) PCIE
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 25 of 73
5 3 2 1
5 3 2 1
UG1W
13 23 MISC 1
NV Carter :Use Main power to prevent Hang issue
+1.8VSDGPU_AON BG5 BJ8 VGA_SMB_CK2 +1.8VSDGPU_MAIN
<36> OVERT# OVERT I2CS_SCL BH8 VGA_SMB_DA2
+1.8VSDGPU_AON I2CS_SDA
1
BF12
RG180 VGA@ TS_VREF BG9 I2CC_SCL_R
10K_0402_5% I2CC_SCL BH9 I2CC_SDA_R +1.8VSDGPU_AON
I2CC_SDA
5
VGA@ CG340 QG3A VGA@
2 1 PJT138KA_SOT363-6
G
2
HDMI_HPD_GPU# BG8 RG5 1 VGA@ 2 1.8K_0402_5% VGA_SMB_CK2 4 3
I2CB_SCL PCH_SML1CLK <19,43,44,48>
D
0.1U_0201_10V6K BF8 RG6 1 VGA@ 2 1.8K_0402_5%
I2CB_SDA
2
QG3B VGA@
D PJT138KA_SOT363-6 D
G
VCC
1
HDMI_HPD_PCH 1 D BJ1 VGA_SMB_DA21 6
<17,38> HDMI_HPD_PCH IN B 4 2 MESS138W-G_SOT323-3 THERMDN PCH_SML1DATA <19,43,44,48>
D
DGPU_PEX_RST# 2 OUT Y G QG5 VGA@ BJ2
GND
IN A THERMDP
S
3
+1.8VSDGPU_AON
3
VGA@ UG28 BD6 DG1 VGA@ +1.8VSDGPU_MAIN
GPIO0 NVVDD1_VID <65>
1.8K_0402_1%
1.8K_0402_1%
VGA@ RG8
VGA@ RG9
NL17SZ08DFT2G_SC70-5 BB5 RB751S40T1G_SOD523-2
GPIO1 GPU_GC6_FB_EN 2 <36>
1
BD1 GPU_EVENT#_1 1
GPIO2 BE4 GPU_EVENT# <20>
GPIO3 BE1 NVVDD2_VID <68>
GPIO4 1.8VSDGPU_MAIN_EN <36>
5
RG198 1 @ 2 0_0402_5% BG2 QG4A VGA@
GPIO5 BD2 PJT138KA_SOT363-6
G
2
2
GPIO6 BD7 GPU_INV_PWM NVVDD1_PSI <65,68> I2CC_SCL_R 4 3
JTAG_TCLK GPIO7 I2CC_SCL <36>
D
@ T38 PAD~D BK24 BH4
JTAG_TCK GPIO8 MEM_VDD_CTL <63>
2
@ T39 PAD~D JTAG_TMS BL23 BJ3 ALERT# QG4B VGA@
@ T40 PAD~D JTAG_TDI BM23 JTAG_TMS GPIO9 BD3 PJT138KA_SOT363-6
G
JTAG_TDO BM24 JTAG_TDI GPIO10 BH3 GPU_ENVDD MEM_VREF <33,34,35> I2CC_SDA_R 1 6
@ T41 PAD~D I2CC_SDA <36>
JTAG_TRST# JTAG_TDO GPIO11 ACIN_BUF
D
BL24 BE6 2 1
JTAG_TRST* GPIO12 BB1 GPU_ENBKL DGPU_AC_DETECT <20,43,54>
DG9 VGA@
GPIO13 BG4 RB751S40T1G_SOD523-2
GPIO14 BG1
+1.8VSDGPU_AON BK23 GPIO15 BE2
NV Carter : ALERT# no function no need
NVJTAG_SEL GPIO16 BH1 GPU_EDP_HPD# DGPU_PEX_RST#
GPIO17
1
BE3
GPIO18
1
1 RG16 VGA@ BD4
CG19 NGPK@ VGA@ RG15 10K_0201_5% GPIO19 BE5
GPIO20
2
G
0.1U_0201_10V6K 10K_0201_5% BA5
GPIO21 BB6
2
2 GPIO22 BG3 GPU_PEX_RST_HOLD# ALERT# 3 1
2
GPIO23 GPU_ALERT <43>
5
BD5
D
C GPIO24 BB2 @ C
VCC
1 GPIO25 BE7
<20,36> DGPU_HOLD_RST# IN B 4 GPIO26 BA4 HDMI_HPD_GPU# QG15
2 OUT Y DGPU_PEX_RST# <25,36> GPIO27 BB4 OC_WARN# MESS138W-G_SOT323-3
GND
5
NL17SZ08DFT2G_SC70-5
<36,43> GPU_OVERT# 2 VGA_SMB_DA2 1 VGA@ 2
RG21 1.8K_0402_5%
VCC
1
<20,36> DGPU_PWR_EN IN B
2
GND
DG4 IN A ALERT# RG25 1 @ 2 10K_0201_5%
10K 0201_5%
NGPK@ RB751S40T1G_SOD523-2 DG3 NGPK@
1
RB751S40T1G_SOD523-2 OC_WARN# RG26 1 VGA@ 2 10K_0201_5%
1
3
2
1 2 1 2 RG202
1
2
6
0.22U_0402_16V7K
1
2
D
2 1VSDGPU_EN <36,64>
G
QG12B
2
S
PJT138KA_SOT363-6
B NGPK@ GPU_GC6_FB_EN RG27 1 VGA@ 2 10K_0201_5% B
1
10K_0402_5%
3
NVVDD1_EN <36,65>
NGPK@
+LCDVDD
1 2 +1.8VSDGPU_AON +1.8VSDGPU_AON
+1.8VSDGPU_AON RG191 1
1
+1.8VSDGPU_AON 1.5K_0402_1%
NGPK@ CG929 NGPK@ RG216 RG215
.1U_0402_16V7K 10K_0201_5% 10K_0201_5%
1
2
0.1U_0201_10V6K
1 DIS@ DIS@
2
CG20
NGPK@
RG45 NGPK@
2
DG2 GPU_EDP_HPD#
10K_0201_5%
G
2 GPU_INV_PWM 1 6
<64> 1VSDGPU_PG PCH_BKL_PWM <18,37>
5
2 1
D
2
1
DGPU_PEX_RST# D
1 PJT138KA_SOT363-6
IN B 4 5 G
D
QG7A NGPK@ BAV70W_SOT323-3 RG29 NGPK@ 2
OUT Y EDP_HPD_R <37>
1
2 PJT138KA_SOT363-6 100K_0201_5% G
GND
NGPK@
S
IN A RG31 S
4
3
UG8 NGPK@ +3VS 10K_0201_5% GPU_ENVDD RG217 2 DIS@ 1 0_0201_5% QG23 DIS@
2
PCH_ENVDD <18,37>
1 NL17SZ08DFT2G_SC70-5 NGPK@ MESS138W-G_SOT323-3
3
6
@ CG937
2
1
GPU_GC6_FB_EN 2 G
D
0.1U_0201_10V6K +3VS
GC6_FB_EN3V3 <20,36> +1.8VSDGPU_AON
S RG34
2 100K_0201_5%
1
1
NGPK@ QG7B NGPK@
6
A 2 A
D
G
QG14B NGPK@ 10K_0201_5%
5
2
NGPK@ GPU_ENBKL 4 3 GPU_ENBKL RG220 1 DIS@ 2 100K_0201_5%
ENBKL <18,43>
3
1 2
<36,65> NVVDD1_PG GPU_GC6_FB_EN 5 D
G
QG22A DIS@
S PJT138KA_SOT363-6
<36,68> NVVDD2_PG
NGPK@ QG14A
Security Classification Compal Secret Data Compal Electronics, Inc.
4
PJT138KA_SOT363-6
Issued Date 2016/12/15 Deciphered Date 2017/12/15 Title
N17E-G1(2/8) GPIO
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 26 of 73
5 3 2 1
5 3 2 1
0.1U_0201_10V6K
BE23 AM7 AW9
TXD1 TXD1 IFPA_L1 MIOA_VREF MIOB_VREF
1
VGA@ CG21
TXD2 TXD2
BF24
IFPA_L0* BG24
TXD2 TXD2 IFPA_L0
2
AT7 BB7
MIOA_CTL3 AM1 MIOB_CTL3 AV5
MIOA_HSYNC AR7 MIOB_HSYNC BA7
MIOA_VSYNC AN1 MIOB_VSYNC AW2
MIOA_DE MIOB_DE
Under GPU SDA IFPB_AUX_SDA*
BG12
BH12 GP104 GP106
SCL IFPB_AUX_SCL AN2 AW1
MIOA_CLKOUT MIOB_CLKOUT
BL18 AM3 MIOB UNUSED AT6
BB17 TXC IFPB_L3* BK18 MIOA_CLKIN MIOB_CLKIN
+1.0VSDGPU BB15 IFP_IOVDD_2 TXC IFPB_L3
IFP_IOVDD_1 @ N17E-G1_BGA2152~D @ N17E-G1_BGA2152~D
BB18 BK20
IFP_IOVDD_3 TXD3 TXD0 IFPB_L2*
BB20 BL20 UG1O
IFP_IOVDD_4 TXD3 TXD0 IFPB_L2
6/23 IFPF
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
Under GPU
VGA@ CG930
1 1 1 1 1 BM20 DVI/HDMI DP
TXD TXD1 IFPB_L1*
VGA@ CG22
VGA@ CG23
VGA@ CG24
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
BK11
TXC IFPF_L3*
VGA@ CG924
VGA@ CG931
1 1 1 BL11
TXC IFPF_L3
VGA@ CG26
@ N17E-G1_BGA2152~D BM11
Under GPU 2 2 2
TXD0
TXD0
IFPF_L2*
IFPF_L2
BM12
UG1R BL12
TXD1 IFPF_L1*
RG52 VGA@ 8/23 IFPC BK12
TXD1 IFPF_L1
1K_0402_1%
2 1 IFPCD_RSET BD20 BK14
IFPCD_RSET TXD2 IFPF_L0*
DVI/HDMI DP FPF TXD2 IFPF_L0
BL14
+IFPX_PLLVDD
BD18 BL9
GPU_DP3_CTRL_DAT <38>
IFPCD_PLLVDD SDA
SCL
IFPC_AUX_SDA*
IFPC_AUX_SCL
BK9
GPU_DP3_CTRL_CLK <38> HDMI 2.0
0.1U_0201_10V6K
@ N17E-G1_BGA2152~D
1 UG1P
VGA@ CG27
22U_0603_6.3V6M
0.1U_0201_10V6K
4.7U_0402_6.3V6M
LG2 VGA@ BF14
TXD0 IFPE_L2*
VGA@ CG921
B PBY160808T-300Y-N_2P BE14 B
1 1 TXD0 IFPE_L2
VGA@ CG28
VGA@ CG30
BB21
IFP_IOVDD_5 SM01000HU00
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 TXD1 BG15
2
2 2 IFPE_L1
FPE
VGA@ CG926
1 1
VGA@ CG29
@ N17E-G1_BGA2152~D TXD2
BG17
IFPE_L0* BH17
TXD2 IFPE_L0
2
2 2 UG1Q
9/23 IFPD +1.0VSDGPU
BC18
BC20 IFP_IOVDD_9
IFP_IOVDD_10
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
DVI/HDMI DP
VGA@ CG933
Under GPU 1 1 1
VGA@ CG31
VGA@ CG32
BF11 @ N17E-G1_BGA2152~D
SDA IFPD_AUX_SDA* BE11 GPU_EDP_AUXN <7>
SCL IFPD_AUX_SCL GPU_EDP_AUXP <7> 2 2 2
TXC BM14
GPU_EDP_TXN3 <7>
22uF 10uF 4.7uF 1uF 0.1uF
IFPD_L3* BM15
TXC IFPD_L3 GPU_EDP_TXP3 <7>
BL15
TXD0
TXD0
IFPD_L2* BK15
GPU_EDP_TXN2
GPU_EDP_TXP2
<7>
<7> IFPx_IOVDD 3 3 12
IFPD_L2
IFPD
TXD1 IFPD_L1*
BK17
BL17
GPU_EDP_TXN1 <7> Under GPU
TXD1
IFPD_L1 GPU_EDP_TXP1 <7>
IFPx_PLLVDD 1 1 3
BM17
TXD2 IFPD_L0* GPU_EDP_TXN0 <7>
BM18
TXD2 IFPD_L0 GPU_EDP_TXP0 <7>
A
+1.0VSDGPU Under GPU BC15 A
BC17 IFP_IOVDD_7
IFP_IOVDD_8
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
VGA@ CG932
1 1 1
VGA@ CG33
VGA@ CG34
@ N17E-G1_BGA2152~D
2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/12/15 Deciphered Date 2017/12/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
N17E-G1(3/8) eDP,HDMI,mDP
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 27 of 73
5 3 2 1
5 3 2 1
UG1B
2/23 FBA UG1C
3/23 FBB
U51 Y51
<33> FBA_D0 U48 FBA_D0 FBA_CMD0 Y52 FBA_CMD1 FBA_CMD0 <33> H32 B35
<33> FBA_D1 U50 FBA_D1 FBA_CMD1 Y49 FBA_CMD2 FBA_CMD1 <33> <34> FBB_D0 D32 FBB_D0 FBB_CMD0 A35 FBB_CMD1 FBB_CMD0 <34>
<33> FBA_D2 U49 FBA_D2 FBA_CMD2 AA52 FBA_CMD2 <33> <34> FBB_D1 A33 FBB_D1 FBB_CMD1 D35 FBB_CMD2 FBB_CMD1 <34>
<33> FBA_D3 R51 FBA_D3 FBA_CMD3 AA51 FBA_CMD3 <33> <34> FBB_D2 B32 FBB_D2 FBB_CMD2 A36 FBB_CMD2 <34>
<33> FBA_D4 R50 FBA_D4 FBA_CMD4 AA50 FBA_CMD4 <33> <34> FBB_D3 E32 FBB_D3 FBB_CMD3 B36 FBB_CMD3 <34>
<33> FBA_D5 R47 FBA_D5 FBA_CMD5 AC50 FBA_CMD5 <33> <34> FBB_D4 G32 FBB_D4 FBB_CMD4 C36 FBB_CMD4 <34>
<33> FBA_D6 U46 FBA_D6 FBA_CMD6 AC51 FBA_CMD6 <33> <34> FBB_D5 J30 FBB_D5 FBB_CMD5 C38 FBB_CMD5 <34>
<33> FBA_D7 V46 FBA_D7 FBA_CMD7 AC52 FBA_CMD7 <33> <34> FBB_D6 F32 FBB_D6 FBB_CMD6 B38 FBB_CMD6 <34>
<33> FBA_D8 Y45 FBA_D8 FBA_CMD8 AC49 FBA_CMD8 <33> <34> FBB_D7 H36 FBB_D7 FBB_CMD7 A38 FBB_CMD7 <34>
<33> FBA_D9 Y47 FBA_D9 FBA_CMD9 AD52 FBA_CMD9 <33> <34> FBB_D8 G36 FBB_D8 FBB_CMD8 D38 FBB_CMD8 <34>
<33> FBA_D10 Y46 FBA_D10 FBA_CMD10 AD51 FBA_CMD10 <33> <34> FBB_D9 J36 FBB_D9 FBB_CMD9 A39 FBB_CMD9 <34>
D <33> FBA_D11 V50 FBA_D11 FBA_CMD11 AD50 FBA_CMD11 <33> <34> FBB_D10 F36 FBB_D10 FBB_CMD10 B39 FBB_CMD10 <34> D
<33> FBA_D12 V47 FBA_D12 FBA_CMD12 AF50 FBA_CMD12 <33> <34> FBB_D11 F33 FBB_D11 FBB_CMD11 C39 FBB_CMD11 <34>
<33> FBA_D13 U52 FBA_D13 FBA_CMD13 AF51 FBA_CMD13 <33> <34> FBB_D12 D33 FBB_D12 FBB_CMD12 C41 FBB_CMD12 <34>
<33> FBA_D14 V51 FBA_D14 FBA_CMD14 AF52 FBA_CMD14 <33> <34> FBB_D13 J32 FBB_D13 FBB_CMD13 B41 FBB_CMD13 <34>
<33> FBA_D15 AJ44 FBA_D15 FBA_CMD15 AN50 FBA_CMD15 <33> <34> FBB_D14 G33 FBB_D14 FBB_CMD14 A41 FBB_CMD14 <34>
<33> FBA_D16 AG48 FBA_D16 FBA_CMD16 AN51 FBA_CMD17 FBA_CMD16 <33> <34> FBB_D15 E45 FBB_D15 FBB_CMD15 B49 FBB_CMD15 <34>
<33> FBA_D17 AJ45 FBA_D17 FBA_CMD17 AN52 FBA_CMD18 FBA_CMD17 <33> <34> FBB_D16 D45 FBB_D16 FBB_CMD16 A49 FBB_CMD17 FBB_CMD16 <34>
<33> FBA_D18 AG49 FBA_D18 FBA_CMD18 AM49 FBA_CMD18 <33> <34> FBB_D17 F45 FBB_D17 FBB_CMD17 A48 FBB_CMD18 FBB_CMD17 <34>
<33> FBA_D19 AF46 FBA_D19 FBA_CMD19 AM52 FBA_CMD19 <33> <34> FBB_D18 G45 FBB_D18 FBB_CMD18 D47 FBB_CMD18 <34>
<33> FBA_D20 AF47 FBA_D20 FBA_CMD20 AM51 FBA_CMD20 <33> <34> FBB_D19 D42 FBB_D19 FBB_CMD19 A47 FBB_CMD19 <34>
<33> FBA_D21 AF48 FBA_D21 FBA_CMD21 AM50 FBA_CMD21 <33> <34> FBB_D20 E42 FBB_D20 FBB_CMD20 B47 FBB_CMD20 <34>
<33> FBA_D22 AD47 FBA_D22 FBA_CMD22 AK50 FBA_CMD22 <33> <34> FBB_D21 F42 FBB_D21 FBB_CMD21 C47 FBB_CMD21 <34>
<33> FBA_D23 AD49 FBA_D23 FBA_CMD23 AK51 FBA_CMD23 <33> <34> FBB_D22 H41 FBB_D22 FBB_CMD22 C45 FBB_CMD22 <34>
<33> FBA_D24 AD48 FBA_D24 FBA_CMD24 AK52 FBA_CMD24 <33> <34> FBB_D23 E41 FBB_D23 FBB_CMD23 B45 FBB_CMD23 <34>
<33> FBA_D25 AC46 FBA_D25 FBA_CMD25 AJ49 FBA_CMD25 <33> <34> FBB_D24 F39 FBB_D24 FBB_CMD24 A45 FBB_CMD24 <34>
<33> FBA_D26 AC47 FBA_D26 FBA_CMD26 AJ52 FBA_CMD26 <33> <34> FBB_D25 E39 FBB_D25 FBB_CMD25 D44 FBB_CMD25 <34>
<33> FBA_D27 AA47 FBA_D27 FBA_CMD27 AJ51 FBA_CMD27 <33> <34> FBB_D26 D39 FBB_D26 FBB_CMD26 A44 FBB_CMD26 <34>
<33> FBA_D28 AA46 FBA_D28 FBA_CMD28 AJ50 FBA_CMD28 <33> <34> FBB_D27 F38 FBB_D27 FBB_CMD27 B44 FBB_CMD27 <34>
<33> FBA_D29 AA45 FBA_D29 FBA_CMD29 AG50 FBA_CMD29 <33> +1.35VSDGPU <34> FBB_D28 E38 FBB_D28 FBB_CMD28 C44 FBB_CMD28 <34>
<33> FBA_D30 Y44 FBA_D30 FBA_CMD30 AG51 FBA_CMD30 <33> <34> FBB_D29 D36 FBB_D29 FBB_CMD29 C42 FBB_CMD29 <34> +1.35VSDGPU
<33> FBA_D31 AW51 FBA_D31 FBA_CMD31 AG52 FBA_CMD31 <33> <34> FBB_D30 E36 FBB_D30 FBB_CMD30 B42 FBB_CMD30 <34>
<33> FBA_D32 BA52 FBA_D32 FBA_CMD32 AF49 <34> FBB_D31 M50 FBB_D31 FBB_CMD31 A42 FBB_CMD31 <34>
<33> FBA_D33 AW50 FBA_D33 FBA_CMD33 Y50 1 2 60.4_0402_1% <34> FBB_D32 P48 FBB_D32 FBB_CMD32 D41
RG184 @
<33> FBA_D34 BA51 FBA_D34 FBA_CMD34 AR50 1 2 60.4_0402_1% <34> FBB_D33 M51 FBB_D33 FBB_CMD33 C35 1 2 60.4_0402_1%
RG185 @ RG186 @
<33> FBA_D35 BA50 FBA_D35 FBA_CMD35 <34> FBB_D34 M49 FBB_D34 FBB_CMD34 B50 1 2 60.4_0402_1%
@
<33> FBA_D36 BB50 FBA_D36 <34> FBB_D35 P47 FBB_D35 FBB_CMD35 RG187
<33> FBA_D37 BA49 FBA_D37 <34> FBB_D36 P52 FBB_D36
<33> FBA_D38 AW49 FBA_D38 AA44 <34> FBB_D37 R46 FBB_D37
<33> FBA_D39 AV48 FBA_D39 FBA_DBG_RFU1 AN44 <34> FBB_D38 P46 FBB_D38 J35
<33> FBA_D40 AT49 FBA_D40 FBA_DBG_RFU2 <34> FBB_D39 L50 FBB_D39 FBB_DBG_RFU1 J41
<33> FBA_D41 AT47 FBA_D41 <34> FBB_D40 L51 FBB_D40 FBB_DBG_RFU2
<33> FBA_D42 AT48 FBA_D42 <34> FBB_D41 L52 FBB_D41
C <33> FBA_D43 AT46 FBA_D43 AG45 <34> FBB_D42 L49 FBB_D42 C
<33> FBA_D44 AV51 FBA_D44 FBA_CLK0 AG46 FBA_CLK0 <33> <34> FBB_D43 M46 FBB_D43 H42
<33> FBA_D45 AV52 FBA_D45 FBA_CLK0* AK46 FBA_CLK0# <33> <34> FBB_D44 L47 FBB_D44 FBB_CLK0 G42 FBB_CLK0 <34>
<33> FBA_D46 AV49 FBA_D46 FBA_CLK1 AK45 FBA_CLK1 <33> <34> FBB_D45 M48 FBB_D45 FBB_CLK0* F47 FBB_CLK0# <34>
<33> FBA_D47 AJ48 FBA_D47 FBA_CLK1* FBA_CLK1# <33> <34> FBB_D46 M47 FBB_D46 FBB_CLK1 E47 FBB_CLK1 <34>
<33> FBA_D48 AJ46 FBA_D48 <34> FBB_D47 D48 FBB_D47 FBB_CLK1* FBB_CLK1# <34>
<33> FBA_D49 AJ47 FBA_D49 <34> FBB_D48 C50 FBB_D48
<33> FBA_D50 AK49 FBA_D50 <34> FBB_D49 C48 FBB_D49
<33> FBA_D51 AM47 FBA_D51 <34> FBB_D50 C49 FBB_D50
<33> FBA_D52 AM46 FBA_D52 <34> FBB_D51 E49 FBB_D51
<33> FBA_D53 AN48 FBA_D53 <34> FBB_D52 E50 FBB_D52
<33> FBA_D54 AN49 FBA_D54 <34> FBB_D53 F49 FBB_D53
<33> FBA_D55 AM44 FBA_D55 U45 <34> FBB_D54 F48 FBB_D54
<33> FBA_D56 AM45 FBA_D56 FBA_WCK01 U44 FBA_WCK01 <33> <34> FBB_D55 F50 FBB_D55 J33
<33> FBA_D57 AN45 FBA_D57 FBA_WCK01* V45 FBA_WCK01# <33> <34> FBB_D56 D52 FBB_D56 FBB_WCK01 H33 FBB_WCK01 <34>
<33> FBA_D58 AN46 FBA_D58 FBA_WCKB01 V44 <34> FBB_D57 J50 FBB_D57 FBB_WCK01* G35 FBB_WCK01# <34>
<33> FBA_D59 AR48 FBA_D59 FBA_WCKB01* AC45 <34> FBB_D58 H48 FBB_D58 FBB_WCKB01 H35
<33> FBA_D60 AN47 FBA_D60 FBA_WCK23 AC44 FBA_WCK23 <33> <34> FBB_D59 H51 FBB_D59 FBB_WCKB01* J39
<33> FBA_D61 AR47 FBA_D61 FBA_WCK23* AD46 FBA_WCK23# <33> <34> FBB_D60 J51 FBB_D60 FBB_WCK23 H39 FBB_WCK23 <34>
<33> FBA_D62 AR46 FBA_D62 FBA_WCKB23 AD45 <34> FBB_D61 H49 FBB_D61 FBB_WCK23* F41 FBB_WCK23# <34>
<33> FBA_D63 FBA_D63 FBA_WCKB23* AV47 <34> FBB_D62 H52 FBB_D62 FBB_WCKB23 G41
FBA_WCK45 AV46 FBA_WCK45 <33> <34> FBB_D63 FBB_D63 FBB_WCKB23* L46
U47 FBA_WCK45* AW48 FBA_WCK45# <33> FBB_WCK45 L45 FBB_WCK45 <34>
<33> FBA_DBI0 Y48 FBA_DQM0 FBA_WCKB45 AW47 C32 FBB_WCK45* M44 FBB_WCK45# <34>
<33> FBA_DBI1 AG47 FBA_DQM1 FBA_WCKB45* AR45 <34> FBB_DBI0 E33 FBB_DQM0 FBB_WCKB45 M45
<33> FBA_DBI2 AC48 FBA_DQM2 FBA_WCK67 AR44 FBA_WCK67 <33> <34> FBB_DBI1 E44 FBB_DQM1 FBB_WCKB45* H47
<33> FBA_DBI3 BB51 FBA_DQM3 FBA_WCK67* AT45 FBA_WCK67# <33> <34> FBB_DBI2 G39 FBB_DQM2 FBB_WCK67 H46 FBB_WCK67 <34>
<33> FBA_DBI4 AV50 FBA_DQM4 FBA_WCKB67 AT44 <34> FBB_DBI3 P49 FBB_DQM3 FBB_WCK67* J47 FBB_WCK67# <34>
<33> FBA_DBI5 <34> FBB_DBI4
<33>
<33>
FBA_DBI6
FBA_DBI7
AM48
AR49
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_WCKB67*
Under GPU <34>
<34>
FBB_DBI5
FBB_DBI6
L48
D50
H50
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_WCKB67
FBB_WCKB67*
J46
1
AR51 AN42 1 2 D51
<33> FBA_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD <34> FBB_EDC6 F51 FBB_DQS_WP6 L38 RG54 VGA@ RG55 VGA@
<34> FBB_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
VGA@ CG35
VGA@ CG36
W49 Y17
SM01000HU00
2
W51 GND_695 Y18 GND_702 FBB_CMD1
GND_696 GND_703 1
CG37 VGA@
W6 Y19
2
1
AF42 RG56 VGA@ RG57 VGA@ RG58 VGA@ RG59 VGA@
FB_REFPLL_AVDD0
0.1U_0201_10V6K
0.1U_0201_10V6K
VGA@ CG39
2
2 2
@ N17E-G1_BGA2152~D
FBA_CMD1
FBA_CMD17 @ N17E-G1_BGA2152~D
Under GPU
FBA_CMD2
FBA_CMD18
A A
1
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 28 of 73
5 3 2 1
5 3 2 1
UG1D UG1E
/23 FBC 5/23 FBD
B D5 AJ3 B
<35> FBC_EDC0 D8 FBC_DQS_WP0 AG2 FBD_DQS_WP0
<35> FBC_EDC1 E17 FBC_DQS_WP1 +FBX_PLLAVDD AA9 FBD_DQS_WP1 +FBX_PLLAVDD
<35> FBC_EDC2 E12 FBC_DQS_WP2 AF4 FBD_DQS_WP2
<35> FBC_EDC3 E30 FBC_DQS_WP3 +1.35VSDGPU E3 FBD_DQS_WP3
<35> FBC_EDC4 B29 FBC_DQS_WP4 H2 FBD_DQS_WP4
<35> FBC_EDC5 G21 FBC_DQS_WP5 U6 FBD_DQS_WP5
<35> FBC_EDC6 E24 FBC_DQS_WP6 L17 M5 FBD_DQS_WP6 V11
<35> FBC_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD FBD_DQS_WP7 FBD_PLL_AVDD
1
1
0.1U_0201_10V6K
0.1U_0201_10V6K
Y25 Y33
Y26 GND_710 RG62 VGA@ RG63 VGA@ Y34 GND_0718
GND_711 1 GND_0719 1
CG40 VGA@
CG41 VGA@
Y27 10K_0402_5% 10K_0402_5% Y35
Y28 GND_712 Y36 GND_0720
Y29 GND_713 Y37 GND_0721
2
FBD UNUSED
@ N17E-G1_BGA2152~D
RG64 VGA@
10K_0402_5%
RG65 VGA@
10K_0402_5%
@ N17E-G1_BGA2152~D
Under GPU
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
N17E-G1(5/8) MEM Interface
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 29 of 73
5 3 2 1
5 3 2 1
+1.8VSDGPU_AON
+1.8VSDGPU_AON
+1.8VSDGPU_AON
1
RG213 @
10K_0402_5%
2
UG1T
15/23 MISC 2
2
RG66 RG67 RG68 RG69 VGA@ RG70 RG71 RG72 VGA@ RG73 VGA@ RG74 VGA@
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% BJ4 ROM_CS# 100K_0402_5% 100K_0402_1% 100K_0402_5%
@ @ @ @ @ ROM_CS*
1
1
D BK2 ROM_SI D
ROM_SI BK4 ROM_SO
STRAP0 BL3 ROM_SO BK3 ROM_SCLK
STRAP1 BL4 STRAP0 ROM_SCLK
STRAP2 BM4 STRAP1
STRAP3 BM5 STRAP2
STRAP3
2
STRAP4 BK5
STRAP5 BJ5 STRAP4 RG75 RG76 RG77
STRAP5 100K_0402_1% 100K_0402_5% 100K_0402_1%
@ @ @
2
2
@
1
BF9 GPU_BUFRST# TG1
RG78 RG79 RG80 RG81 RG82 VGA@ RG83 VGA@ BUFRST* PAD~D
100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1%
@ @ @ @
1
1
@ N17E-G1_BGA2152~D
C C
UG1S
+IFPX_PLLVDD 1 /23 XTAL/PLL
BD12
SP_PLLVDD
BC12
VID_PLLVDD
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CG922 VGA@
1 1 1 1 1 1
CG49 VGA@
CG50 VGA@
CG51 VGA@
CG52 VGA@
CG53 VGA@
B 2 2 2 2 2 2 B
U42
GPCPLL_AVDD0
AF11
GPCPLL_AVDD1
BB24
XS_PLLVDD
Under GPU
RG86 1 @ 2 10M_0402_5%
1
RG199 VGA@
VGA@ 330_0402_1%
YG1
A 27MHZ_10PF_XRCGB27M000F2P18R0 A
2
XTALIN 1 3
1 3
NC NC
2 2
CG56 VGA@
CG55 VGA@ 2 4 15P_0402_50V8J
15P_0402_50V8J
1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/12/15 Deciphered Date 2017/12/15 Title
N17E-G1(6/8) Strap Pin,ROM
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 30 of 73
5 3 2 1
5 3 2 1
CG63
CG64
CG65
CG66
CG67
CG68
CG69
CG70
CG71
CG72
CG73
CG74
CG75
CG76
CG77
CG78
CG79
CG80
CG81
CG82
CG83
CG84
CG85
CG86
CG87
CG88
CG89
CG90
CG91
CG92
CG93
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
VGA@ 1U_0402_6.3V4Z
BK45
VDD_SENSE BL45 NVVDD1_VCC_SENSE <65>
GND_SENSE NVVDD1_VSS_SENSE <65>
@ N17E-G1_BGA2152~D
+1.35VSDGPU
CG94
CG95
CG96
CG97
CG98
CG99
CG100
CG101
CG102
CG103
CG104
CG105
CG106
1 1 1 1 1 1 1 1 1 1 1 1 1
470uF 22uF 10uF 4.7uF 1uF 0.1uF
A A
2 2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ 1 9 13 24
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 10U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
VGA@ 22U_0603_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
N17E-G1(7/8) Power
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 31 of 73
5 3 2 1
5 3 2 1
1U_0402_6.3V4Z
0.1U_0201_10V6K
0.1U_0201_10V6K
CG108 VGA@
CG109 VGA@
CG110 VGA@
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CG112 VGA@
CG113 VGA@
CG114 VGA@
CG115 VGA@
CG116 VGA@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CG118 VGA@
CG119 VGA@
CG120 VGA@
CG121 VGA@
CG122 VGA@
CG123 VGA@
@ N17E-G1_BGA2152~D @ N17E-G1_BGA2152~D
N17E-G1(8/8) Power,GND
WWW.AliSaler.Com
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 32 of 73
5 3 2 1
5 4 3 2
A A
DQ2 DQ0 FBA_D2 <28> DQ2 DQ0 FBA_D32 <28>
C2 A2 C2 A2
<28> FBA_EDC3 EDC0 EDC3 DQ25 DQ1 FBA_D25 <28> <28> FBA_EDC EDC0 EDC3 DQ25 DQ1 FBA_D33 <28>
C13 B C13 B
<28> FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D26 <28> <28> FBA_EDC5 EDC1 EDC2 DQ26 DQ2 FBA_D3 <28>
R13 B2 R13 B2
<28> FBA_EDC1 EDC2 EDC1 DQ27 DQ3 FBA_D27 <28> <28> FBA_EDC6 EDC2 EDC1 DQ27 DQ3 FBA_D35 <28>
R2 E R2 E
<28> FBA_EDC0 EDC3 EDC0 DQ28 DQ FBA_D28 <28> <28> FBA_EDC7 EDC3 EDC0 DQ28 DQ FBA_D36 <28>
E2 E2
28> FBA_CLK0 DQ29 DQ5 FBA_D29 <28> <28> FBA_CLK1 DQ29 DQ5 FBA_D37 <28>
F F
FBA_D30 <28> FBA_D38 <28>
1
D2 DQ30 DQ6 F2 D2 DQ30 DQ6 F2
<28> FBA_DBI3 DBI0# DBI3# DQ31 DQ7 FBA_D31 <28> <28> FBA_DBI DBI0# DBI3# DQ31 DQ7 FBA_D39 <28>
VGA@ RG99 D13 A11 VGA@ RG98 D13 A11
<28> FBA_DBI2 DBI1# DBI2# DQ16 DQ8 FBA_D16 <28> <28> FBA_DBI5 DBI1# DBI2# DQ16 DQ8 FBA_D 0 <28>
0.2_0 02_1% P13 A13 0.2_0 02_1% P13 A13
D <28> FBA_DBI1 DBI2# DBI1# DQ17 DQ9 FBA_D17 <28> <28> FBA_DBI6 DBI2# DBI1# DQ17 DQ9 FBA_D 1 <28> D
P2 B11 P2 B11
<28> FBA_DBI0 DBI3# DBI0# DQ18 DQ10 FBA_D18 <28> <28> FBA_DBI7 DBI3# DBI0# DQ18 DQ10 FBA_D 2 <28>
B13 B13
FBA_D19 <28> FBA_D 3 <28>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBA_D20 <28> CK DQ20 DQ12 FBA_D <28>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBA_D21 <28> CK# DQ21 DQ13 FBA_D 5 <28>
CG12 0.01U_0 02_16V7K J3 F11 CG125 0.01U_0 02_16V7K J3 F11
<28> FBA_CMD1 FBA_D22 <28> <28> FBA_CMD17 FBA_D 6 <28>
2
CKE# DQ22 DQ1 F13 CKE# DQ22 DQ1 F13
VGA@ DQ23 DQ15 FBA_D23 <28> VGA@ DQ23 DQ15 FBA_D 7 <28>
VGA@ RG100 U11 VGA@ RG101 U11
DQ8 DQ16 FBA_D8 <28> DQ8 DQ16 FBA_D 8 <28>
0.2_0 02_1% H11 U13 0.2_0 02_1% H11 U13
<28> FBA_CMD12 BA0/A2 BA2/A DQ9 DQ17 FBA_D9 <28> <28> FBA_CMD29 BA0/A2 BA2/A DQ9 DQ17 FBA_D 9 <28>
K10 T11 K10 T11
<28> FBA_CMD1 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D10 <28> <28> FBA_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBA_D50 <28>
K11 T13 K11 T13
<28> FBA_CMD13 FBA_D11 <28> <28> FBA_CMD28 FBA_D51 <28>
1
H10 BA2/A BA0/A2 DQ11 DQ19 N11 H10 BA2/A BA0/A2 DQ11 DQ19 N11
28> FBA_CLK0# <28> FBA_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D12 <28> <28> FBA_CLK1# <28> FBA_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBA_D52 <28>
N13 N13
DQ13 DQ21 FBA_D13 <28> DQ13 DQ21 FBA_D53 <28>
M11 M11
DQ1 DQ22 FBA_D1 <28> DQ1 DQ22 FBA_D5 <28>
K M13 K M13
<28> FBA_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBA_D15 <28> <28> FBA_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBA_D55 <28>
H5 U H5 U
<28> FBA_CMD8 A9/A1 A11/A6 DQ0 DQ2 FBA_D0 <28> <28> FBA_CMD20 A9/A1 A11/A6 DQ0 DQ2 FBA_D56 <28>
H U2 H U2
<28> FBA_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBA_D1 <28> <28> FBA_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBA_D57 <28>
K5 T K5 T
<28> FBA_CMD A11/A6 A9/A1 DQ2 DQ26 FBA_D2 <28> <28> FBA_CMD2 A11/A6 A9/A1 DQ2 DQ26 FBA_D58 <28>
J5 T2 J5 T2
<28> FBA_CMD6 A12/RFU/NC DQ3 DQ27 FBA_D3 <28> <28> FBA_CMD22 A12 RFU/NC DQ3 DQ27 FBA_D59 <28>
N N
DQ DQ28 FBA_D <28> DQ DQ28 FBA_D60 <28>
A5 N2 A5 N2
1.35VSDGPU VPP/NC DQ5 DQ29 FBA_D5 <28> VPP/NC DQ5 DQ29 FBA_D61 <28>
U5 M U5 M
VPP/NC DQ6 DQ30 FBA_D6 <28> VPP/NC DQ6 DQ30 FBA_D62 <28>
M2 M2
DQ7 DQ31 FBA_D7 <28> DQ7 DQ31 FBA_D63 <28>
J1 1.35VSDGPU J1 1.35VSDGPU
J10 MF J10 MF
RG106 2 1 121_0 02_1% J13 SEN B1 RG107 2 1 121_0 02_1% J13 SEN B1
VGA@ ZQ VDDQ D1 VGA@ ZQ VDDQ D1
VDDQ F1 VDDQ F1
J VDDQ M1 J VDDQ M1
<28> FBA_CMD7 ABI# VDDQ <28> FBA_CMD23 ABI# VDDQ
G3 P1 G3 P1
<28> FBA_CMD0 RAS# CAS# VDDQ <28> FBA_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
<28> FBA_CMD10 CS# WE# VDDQ <28> FBA_CMD31 CS# WE# VDDQ
L3 G2 L3 G2
<28>
<28>
FBA_CMD3
FBA_CMD15
L12 CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
L2
B3
D3
1.35VSDGPU
Near VRAM <28>
<28>
FBA_CMD16
FBA_CMD26
L12 CAS#
WE#
RAS#
CS#
VDDQ
VDDQ
VDDQ
L2
B3
D3
VDDQ F3 VDDQ F3
D5 VDDQ H3 D5 VDDQ H3
<28> FBA_WCK23# WCK01# WCK23# VDDQ <28> FBA_WCK 5# WCK01# WCK23# VDDQ
D K3 D K3
CG126
CG127
CG128
CG129
CG1 2
CG130
CG178
<28> FBA_WCK23 WCK01 WCK23 VDDQ <28> FBA_WCK 5 WCK01 WCK23 VDDQ
M3 1 1 1 1 1 1 1 M3
P5 VDDQ P3 P5 VDDQ P3
<28> FBA_WCK01# WCK23# WCK01# VDDQ <28> FBA_WCK67# WCK23# WCK01# VDDQ
P T3 P T3
<28> FBA_WCK01 WCK23 WCK01 VDDQ <28> FBA_WCK67 WCK23 WCK01 VDDQ
E5 E5
C VDDQ 2 2 2 2 2 2 2 VDDQ C
N5 N5
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VDDQ VDDQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A10 E10 A10 E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
FBA_VREFC J1 VREFD VDDQ B12 FBA_VREFC J1 VREFD VDDQ B12
1.35VSDGPU VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
1
VGA@ CG152
VGA@ CG153
820P_0 02_25V7
820P_0 02_25V7
1.33K_0 02_1%
CG1 3
CG1 5
CG131
S
3
CG1
VSS VSSQ 1 1 1 1 VSS VSSQ
T10 E1 T10 E1
H1 VSS VSSQ N1 H1 VSS VSSQ N1
1.35VSDGPU K1 VSS VSSQ R1 K1 VSS VSSQ R1
VSS VSSQ U1 2 2 2 2 1.35VSDGPU VSS VSSQ U1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
H2 H2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
G VDD VSSQ C3 G VDD VSSQ C3
L VDD VSSQ E3 L VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
1.35VSDGPU
Near VRAM R5
C10
R10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
R3
U3
C
Under VRAM R5
C10
R10
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
R3
U3
C
D11 VDD VSSQ R D11 VDD VSSQ R
G11 VDD VSSQ F5 G11 VDD VSSQ F5
CG165
CG166
CG176
CG177
CG179
CG180
1.35VSDGPU
CG16
CG1 0
CG1 1
CG1 6
CG1 7
CG1 8
CG1 9
CG150
CG151
CG155
CG156
CG157
CG158
CG159
CG160
CG161
CG162
CG163
B B
CG15
2 2 2 2 2 2 2 VDD VSSQ R11 VDD VSSQ R11
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSSQ
VGA@
VGA@
A12 A12
VGA@
VGA@
VGA@
VGA@
VGA@
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
R12 R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A1 VSSQ A1
VSSQ C1 VSSQ C1
VSSQ E1 VSSQ E1
VSSQ N1 VSSQ N1
VSSQ R1 VSSQ R1
VSSQ U1 VSSQ U1
VSSQ VSSQ
K G80325FB-HC25 FBGA 170P K G80325FB-HC25 FBGA 170P
1.35VSDGPU
Under VRAM @
Under VRAM @
CG167
CG168
CG169
CG170
CG171
CG172
CG173
CG175
CG132
CG133
CG135
CG136
CG137
CG138
CG139
CG182
CG183
CG185
CG17
CG13
CG18
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Near VRAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A A
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-GDDR5 A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ON IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, Feb uary 13, 2018 Sheet 33 of 73
5 4 3 2
5 4 3 2
A A
DQ2 DQ0 FBB_D2 <28> DQ2 DQ0 FBB_D32 <28>
C2 A2 C2 A2
<28> FBB_EDC3 EDC0 EDC3 DQ25 DQ1 FBB_D25 <28> <28> FBB_EDC EDC0 EDC3 DQ25 DQ1 FBB_D33 <28>
C13 B C13 B
<28> FBB_EDC2 EDC1 EDC2 DQ26 DQ2 FBB_D26 <28> <28> FBB_EDC5 EDC1 EDC2 DQ26 DQ2 FBB_D3 <28>
R13 B2 R13 B2
<28> FBB_EDC1 EDC2 EDC1 DQ27 DQ3 FBB_D27 <28> <28> FBB_EDC6 EDC2 EDC1 DQ27 DQ3 FBB_D35 <28>
R2 E R2 E
<28> FBB_EDC0 EDC3 EDC0 DQ28 DQ FBB_D28 <28> <28> FBB_EDC7 EDC3 EDC0 DQ28 DQ FBB_D36 <28>
E2 E2
28> FBB_CLK0 DQ29 DQ5 FBB_D29 <28> <28> FBB_CLK1 DQ29 DQ5 FBB_D37 <28>
F F
FBB_D30 <28> FBB_D38 <28>
1
D2 DQ30 DQ6 F2 D2 DQ30 DQ6 F2
<28> FBB_DBI3 DBI0# DBI3# DQ31 DQ7 FBB_D31 <28> <28> FBB_DBI DBI0# DBI3# DQ31 DQ7 FBB_D39 <28>
VGA@ RG111 D13 A11 VGA@ RG112 D13 A11
<28> FBB_DBI2 DBI1# DBI2# DQ16 DQ8 FBB_D16 <28> <28> FBB_DBI5 DBI1# DBI2# DQ16 DQ8 FBB_D 0 <28>
0.2_0 02_1% P13 A13 0.2_0 02_1% P13 A13
D <28> FBB_DBI1 DBI2# DBI1# DQ17 DQ9 FBB_D17 <28> <28> FBB_DBI6 DBI2# DBI1# DQ17 DQ9 FBB_D 1 <28> D
P2 B11 P2 B11
<28> FBB_DBI0 DBI3# DBI0# DQ18 DQ10 FBB_D18 <28> <28> FBB_DBI7 DBI3# DBI0# DQ18 DQ10 FBB_D 2 <28>
B13 B13
FBB_D19 <28> FBB_D 3 <28>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBB_D20 <28> CK DQ20 DQ12 FBB_D <28>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBB_D21 <28> CK# DQ21 DQ13 FBB_D 5 <28>
CG186 0.01U_0 02_16V7K J3 F11 CG187 0.01U_0 02_16V7K J3 F11
<28> FBB_CMD1 FBB_D22 <28> <28> FBB_CMD17 FBB_D 6 <28>
2
CKE# DQ22 DQ1 F13 CKE# DQ22 DQ1 F13
VGA@ DQ23 DQ15 FBB_D23 <28> VGA@ DQ23 DQ15 FBB_D 7 <28>
VGA@ RG113 U11 VGA@ RG11 U11
DQ8 DQ16 FBB_D8 <28> DQ8 DQ16 FBB_D 8 <28>
0.2_0 02_1% H11 U13 0.2_0 02_1% H11 U13
<28> FBB_CMD12 BA0/A2 BA2/A DQ9 DQ17 FBB_D9 <28> <28> FBB_CMD29 BA0/A2 BA2/A DQ9 DQ17 FBB_D 9 <28>
K10 T11 K10 T11
<28> FBB_CMD1 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D10 <28> <28> FBB_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBB_D50 <28>
K11 T13 K11 T13
<28> FBB_CMD13 FBB_D11 <28> <28> FBB_CMD28 FBB_D51 <28>
1
H10 BA2/A BA0/A2 DQ11 DQ19 N11 H10 BA2/A BA0/A2 DQ11 DQ19 N11
28> FBB_CLK0# <28> FBB_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D12 <28> <28> FBB_CLK1# <28> FBB_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBB_D52 <28>
N13 N13
DQ13 DQ21 FBB_D13 <28> DQ13 DQ21 FBB_D53 <28>
M11 M11
DQ1 DQ22 FBB_D1 <28> DQ1 DQ22 FBB_D5 <28>
K M13 K M13
<28> FBB_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBB_D15 <28> <28> FBB_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBB_D55 <28>
H5 U H5 U
<28> FBB_CMD8 A9/A1 A11/A6 DQ0 DQ2 FBB_D0 <28> <28> FBB_CMD20 A9/A1 A11/A6 DQ0 DQ2 FBB_D56 <28>
H U2 H U2
<28> FBB_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBB_D1 <28> <28> FBB_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBB_D57 <28>
K5 T K5 T
<28> FBB_CMD A11/A6 A9/A1 DQ2 DQ26 FBB_D2 <28> <28> FBB_CMD2 A11/A6 A9/A1 DQ2 DQ26 FBB_D58 <28>
J5 T2 J5 T2
<28> FBB_CMD6 A12/RFU/NC DQ3 DQ27 FBB_D3 <28> <28> FBB_CMD22 A12 RFU/NC DQ3 DQ27 FBB_D59 <28>
N N
DQ DQ28 FBB_D <28> DQ DQ28 FBB_D60 <28>
A5 N2 A5 N2
1.35VSDGPU VPP/NC DQ5 DQ29 FBB_D5 <28> VPP/NC DQ5 DQ29 FBB_D61 <28>
U5 M U5 M
VPP/NC DQ6 DQ30 FBB_D6 <28> VPP/NC DQ6 DQ30 FBB_D62 <28>
M2 M2
DQ7 DQ31 FBB_D7 <28> DQ7 DQ31 FBB_D63 <28>
J1 1.35VSDGPU J1 1.35VSDGPU
J10 MF J10 MF
RG119 2 1 121_0 02_1% J13 SEN B1 RG120 2 1 121_0 02_1% J13 SEN B1
VGA@ ZQ VDDQ D1 VGA@ ZQ VDDQ D1
VDDQ F1 VDDQ F1
J VDDQ M1 J VDDQ M1
<28> FBB_CMD7 ABI# VDDQ <28> FBB_CMD23 ABI# VDDQ
G3 P1 G3 P1
<28>
<28>
<28>
FBB_CMD0
FBB_CMD10
FBB_CMD3
G12
L3
L12
RAS#
CS#
CAS#
CAS#
WE#
RAS#
VDDQ
VDDQ
VDDQ
T1
G2
L2
1.35VSDGPU
Near VRAM <28>
<28>
<28>
FBB_CMD19
FBB_CMD31
FBB_CMD16
G12
L3
L12
RAS#
CS#
CAS#
CAS#
WE#
RAS#
VDDQ
VDDQ
VDDQ
T1
G2
L2
<28> FBB_CMD15 WE# CS# VDDQ <28> FBB_CMD26 WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
CG188
CG189
CG190
CG226
CG192
CG193
CG20
D5 VDDQ H3 D5 VDDQ H3
<28> FBB_WCK23# WCK01# WCK23# VDDQ 1 1 1 1 1 1 1 <28> FBB_WCK 5# WCK01# WCK23# VDDQ
D K3 D K3
<28> FBB_WCK23 WCK01 WCK23 VDDQ <28> FBB_WCK 5 WCK01 WCK23 VDDQ
M3 M3
P5 VDDQ P3 P5 VDDQ P3
<28> FBB_WCK01# WCK23# WCK01# VDDQ 2 2 2 2 2 2 2 <28> FBB_WCK67# WCK23# WCK01# VDDQ
P T3 P T3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0 02_6.3V Z
<28> FBB_WCK01 WCK23 WCK01 VDDQ <28> FBB_WCK67 WCK23 WCK01 VDDQ
VGA@
E5 E5
C VDDQ VDDQ C
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
FBB_VREFC J1 VREFD VDDQ B12 FBB_VREFC J1 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
J2 VDDQ K12 J2 VDDQ K12
1 35VSDGPU <28> FBB_CMD2 RESET# VDDQ <28> FBB_CMD18 RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
1
CG191
CG205
CG206
CG207
1 2 FBB_VREFC W=16mils T5 VSS
VSS
VDDQ
VDDQ
P1 1 1 1 1 T5 VSS
VSS
VDDQ
VDDQ
P1
B10 T1 B10 T1
1
VGA@ CG215
RG122 VGA@
820P_0 02_25V7
820P_0 02_25V7
1.33K_0 02_1%
1 1
VGA@ CG21
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0 02_6.3V Z
1
VGA@
VGA@
VGA@
P10 C1 P10 C1
2 2 VSS VSSQ VSS VSSQ
VGA@
2 QG9 VGA@ T10 E1 T10 E1
< 6,33 35> MEM_VREF
2
CG208
CG209
CG210
CG211
CG212
CG213
CG216
CG217
CG218
CG219
CG220
CG221
CG222
CG223
CG225
CG232
CG233
CG22
G1 VDD VSSQ M10 G1 VDD VSSQ M10
VDD VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD VSSQ
B L1 C11 L1 C11 B
VDD VSSQ R11 VDD VSSQ R11
CG227
CG228
CG238
CG239
CG2 0
CG2 2
CG2 3
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
VSSQ E12 VSSQ E12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
N12 N12
2 2 2 2 2 2 2 VSSQ R12 VSSQ R12
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0 02_6.3V Z
VSSQ VSSQ
VGA@
H13 H13
VGA@
VGA@
VGA@
VGA@
VGA@
CG230
CG231
CG2 1
CG195
CG196
CG197
CG198
CG199
CG200
CG201
CG202
CG203
CG235
CG236
CG237
CG2 5
CG2 6
CG2 7
CG19
CG23
CG2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 x 10uF (0402 X6S) 2 GND/PWR vias for each cap.
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 x 22uF (0603 X6S) 2 GND/PWR vias for each cap
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
10U_0 02_6.3V Z
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A A
N17E-GDDR5 B
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ON IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, Feb uary 13, 2018 Sheet 3 of 73
5 4 3 2
5 4 3 2
A A
DQ2 DQ0 FBC_D2 29> DQ2 DQ0 FBC_D32 <29>
C2 A2 C2 A2
<29> FBC_EDC3 EDC0 EDC3 DQ25 DQ1 FBC_D25 29> <29> FBC_EDC EDC0 EDC3 DQ25 DQ1 FBC_D33 <29>
C13 B C13 B
<29> FBC_EDC2 EDC1 EDC2 DQ26 DQ2 FBC_D26 29> <29> FBC_EDC5 EDC1 EDC2 DQ26 DQ2 FBC_D3 <29>
R13 B2 R13 B2
<29> FBC_EDC1 EDC2 EDC1 DQ27 DQ3 FBC_D27 29> <29> FBC_EDC6 EDC2 EDC1 DQ27 DQ3 FBC_D35 <29>
R2 E R2 E
<29> FBC_EDC0 EDC3 EDC0 DQ28 DQ FBC_D28 29> <29> FBC_EDC7 EDC3 EDC0 DQ28 DQ FBC_D36 <29>
E2 E2
29> FBC_CLK0 DQ29 DQ5 FBC_D29 29> <29> FBC_CLK1 DQ29 DQ5 FBC_D37 <29>
F F
FBC_D30 29> FBC_D38 <29>
1
D2 DQ30 DQ6 F2 D2 DQ30 DQ6 F2
<29> FBC_DB 3 DBI0# DBI3# DQ31 DQ7 FBC_D31 29> <29> FBC_DBI DBI0# DBI3# DQ31 DQ7 FBC_D39 <29>
VGA@ RG126 D13 A11 VGA@ RG127 D13 A11
<29> FBC_DB 2 DBI1# DBI2# DQ16 DQ8 FBC_D16 29> <29> FBC_DBI5 DBI1# DBI2# DQ16 DQ8 FBC_D 0 <29>
0.2_0 02_1% P13 A13 0.2_0 02_1% P13 A13
D <29> FBC_DBI1 DBI2# DBI1# DQ17 DQ9 FBC_D17 29> <29> FBC_DBI6 DBI2# DBI1# DQ17 DQ9 FBC_D 1 <29> D
P2 B11 P2 B11
<29> FBC_DB 0 DBI3# DBI0# DQ18 DQ10 FBC_D18 29> <29> FBC_DBI7 DBI3# DBI0# DQ18 DQ10 FBC_D 2 <29>
B13 B13
FBC_D19 29> FBC_D 3 <29>
2
J12 DQ19 DQ11 E11 J12 DQ19 DQ11 E11
CK DQ20 DQ12 FBC_D20 29> CK DQ20 DQ12 FBC_D <29>
2 1 J11 E13 2 1 J11 E13
CK# DQ21 DQ13 FBC_D21 29> CK# DQ21 DQ13 FBC_D 5 <29>
CG2 8 0.01U_0 02_16V7K J3 F11 CG2 9 0.01U_0 02_16V7K J3 F11
<29> FBC_CMD1 FBC_D22 29> <29> FBC_CMD17 FBC_D 6 <29>
2
CKE# DQ22 DQ1 F13 CKE# DQ22 DQ1 F13
VGA@ DQ23 DQ15 FBC_D23 29> VGA@ DQ23 DQ15 FBC_D 7 <29>
VGA@ RG12 U11 VGA@ RG125 U11
DQ8 DQ16 FBC_D8 <29> DQ8 DQ16 FBC_D 8 <29>
0.2_0 02_1% H11 U13 0.2_0 02_1% H11 U13
<29> FBC_CMD12 BA0/A2 BA2/A DQ9 DQ17 FBC_D9 <29> <29> FBC_CMD29 BA0/A2 BA2/A DQ9 DQ17 FBC_D 9 <29>
K10 T11 K10 T11
<29> FBC_CMD1 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D10 29> <29> FBC_CMD27 BA1/A5 BA3/A3 DQ10 DQ18 FBC_D50 <29>
K11 T13 K11 T13
<29> FBC_CMD13 FBC_D11 29> <29> FBC_CMD28 FBC_D51 <29>
1
H10 BA2/A BA0/A2 DQ11 DQ19 N11 H10 BA2/A BA0/A2 DQ11 DQ19 N11
29> FBC_CLK0# <29> FBC_CMD11 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D12 29> <29> FBC_CLK1# <29> FBC_CMD30 BA3/A3 BA1/A5 DQ12 DQ20 FBC_D52 <29>
N13 N13
DQ13 DQ21 FBC_D13 29> DQ13 DQ21 FBC_D53 <29>
M11 M11
DQ1 DQ22 FBC_D1 29> DQ1 DQ22 FBC_D5 <29>
K M13 K M13
<29> FBC_CMD5 A8/A7 A10/A0 DQ15 DQ23 FBC_D15 29> <29> FBC_CMD25 A8/A7 A10/A0 DQ15 DQ23 FBC_D55 <29>
H5 U H5 U
<29> FBC_CMD8 A9/A1 A11/A6 DQ0 DQ2 FBC_D0 <29> <29> FBC_CMD20 A9/A1 A11/A6 DQ0 DQ2 FBC_D56 <29>
H U2 H U2
<29> FBC_CMD9 A10/A0 A8/A7 DQ1 DQ25 FBC_D1 <29> <29> FBC_CMD21 A10/A0 A8/A7 DQ1 DQ25 FBC_D57 <29>
K5 T K5 T
<29> FBC_CMD A11/A6 A9/A1 DQ2 DQ26 FBC_D2 <29> <29> FBC_CMD2 A11/A6 A9/A1 DQ2 DQ26 FBC_D58 <29>
J5 T2 J5 T2
<29> FBC_CMD6 A12/RFU/NC DQ3 DQ27 FBC_D3 <29> <29> FBC_CMD22 A12 RFU/NC DQ3 DQ27 FBC_D59 <29>
N N
DQ DQ28 FBC_D <29> DQ DQ28 FBC_D60 <29>
A5 N2 A5 N2
1.35VSDGPU VPP/NC DQ5 DQ29 FBC_D5 <29> VPP/NC DQ5 DQ29 FBC_D61 <29>
U5 M U5 M
VPP/NC DQ6 DQ30 FBC_D6 <29> VPP/NC DQ6 DQ30 FBC_D62 <29>
M2 M2
DQ7 DQ31 FBC_D7 <29> DQ7 DQ31 FBC_D63 <29>
J1 1.35VSDGPU J1 1.35VSDGPU
J10 MF J10 MF
RG132 2 1 121_0 02_1% J13 SEN B1 RG133 2 1 121_0 02_1% J13 SEN B1
VGA@ ZQ VDDQ D1 VGA@ ZQ VDDQ D1
VDDQ F1 VDDQ F1
J VDDQ M1 J VDDQ M1
<29> FBC_CMD7 ABI# VDDQ <29> FBC_CMD23 ABI# VDDQ
G3 P1 G3 P1
<29> FBC_CMD0 RAS# CAS# VDDQ <29> FBC_CMD19 RAS# CAS# VDDQ
G12 T1 G12 T1
<29> FBC_CMD10 CS# WE# VDDQ <29> FBC_CMD31 CS# WE# VDDQ
L3 G2 L3 G2
<29> FBC_CMD3 CAS# RAS# VDDQ <29> FBC_CMD16 CAS# RAS# VDDQ
L12 L2 L12 L2
<29> FBC_CMD15 WE# CS# VDDQ <29> FBC_CMD26 WE# CS# VDDQ
B3 B3
D5
VDDQ
VDDQ
VDDQ
D3
F3
H3
1.35VSDGPU
Near VRAM D5
VDDQ
VDDQ
VDDQ
D3
F3
H3
<29> FBC_WCK23# WCK01# WCK23# VDDQ <29> FBC_WCK 5# WCK01# WCK23# VDDQ
D K3 D K3
<29> FBC_WCK23 WCK01 WCK23 VDDQ <29> FBC_WCK 5 WCK01 WCK23 VDDQ
M3 M3
P5 VDDQ P3 P5 VDDQ P3
CG250
CG251
CG252
CG266
CG288
CG253
<29> FBC_WCK01#
CG25
WCK23# WCK01# VDDQ <29> FBC_WCK67# WCK23# WCK01# VDDQ
P T3 1 1 1 1 1 1 1 P T3
<29> FBC_WCK01 WCK23 WCK01 VDDQ <29> FBC_WCK67 WCK23 WCK01 VDDQ
E5 E5
C VDDQ VDDQ C
N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 2 2 2 2 2 2 2 U10 VREFD VDDQ N10
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 35VSDGPU FBC_VREFC VREFD VDDQ FBC_VREFC VREFD VDDQ
VGA@
VGA@
J1 B12 J1 B12
VREFC VDDQ VREFC VDDQ
VGA@
VGA@
VGA@
VGA@
VGA@
D12 D12
VDDQ F12 VDDQ F12
1
VGA@ CG276
VGA@ CG277
RG135 VGA@
820P_0 02_25V7
820P_0 02_25V7
1.33K_0 02_1%
CG255
CG267
CG268
CG269
S
3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSS VSSQ 1.35VSDGPU VSS VSSQ
VGA@
VGA@
VGA@
VGA@
U1 U1
VSSQ H2 VSSQ H2
G1 VSSQ K2 G1 VSSQ K2
L1
G
L
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
A3
C3
E3
Under VRAM L1
G
L
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
A3
C3
E3
CG290
CG300
CG301
CG302
CG291
CG292
CG265
CG270
CG271
CG272
CG273
CG275
CG278
CG279
CG280
CG281
CG282
CG283
CG285
CG286
CG287
CG26
CG27
CG28
L1 VDD VSSQ C11 L1 VDD VSSQ C11
B
VDD VSSQ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD VSSQ B
2 2 2 2 2 2 2 R11 R11
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VSSQ VSSQ
VGA@
VGA@
A12 A12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
C12 C12
VSSQ E12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VSSQ E12
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
VSSQ N12 VSSQ N12
VSSQ VSSQ
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
R12 R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A1 VSSQ A1
VSSQ C1 VSSQ C1
VSSQ E1 VSSQ E1
VSSQ N1 VSSQ N1
VSSQ R1 VSSQ R1
VSSQ U1 VSSQ U1
VSSQ VSSQ
K G80325FB-HC25 FBGA 170P
@ Under VRAM K G80325FB-HC25 FBGA 170P
@
1.35VSDGPU
Under VRAM 18 x 1uF (0402 X6S)
4 x 10uF (0402 X6S)
CG293
CG303
CG305
CG256
CG257
CG258
CG259
CG260
CG261
CG262
CG263
CG295
CG296
CG297
CG298
CG299
CG306
CG307
CG308
CG309
CG30
CG29
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Near VRAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 x 10uF (0402 X6S) 2 GND/PWR vias for each cap.
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
1U_0 02_6.3V Z
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
A A
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-GDDR5 C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ON IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, Feb uary 13, 2018 Sheet 35 of 73
5 4 3 2
A B C D E F G H
+3VSDGPU
1
CG310 VGA@
1.8K_0402_1%
1.8K_0402_1%
VGA@ RG138
VGA@ RG139
0.1U_0201_10V6K
1
2
1 2
<66> CSSN_B+
10U_0603_6.3V6M
VGA@ CG311
RG137 VGA@ 2 UG18 +3VSDGPU
10_0402_1%
2
4 16
VS VPU +1.8VSDGPU_AON
1
RG140 VGA@ 1
10_0402_1% VIN1N 11 13 RG141
1 1 2 VIN1P 12 IN-1 TC 10K_0402_1% 1
<66> CSSP_B+ IN+1 10 VGA@
2
1 2 VIN2N 14 PV
<66> CSSN_NVVDD IN-2
2
10U_0603_6.3V6M
VIN2P 15 9 1 @ 2
G
IN+2 Critical
VGA@ CG312
RG142 VGA@ 2 RG143 0_0402_5%
10_0402_1% VIN3N 1 8 1 3
VIN3P 2 IN-3 Warning OC_WARN# <26>
S
IN+3 5 2 1
RG145 VGA@ 1 6 A0 3
<26> I2CC_SCL SCL GND QG17
665K_0402_1%
665K_0402_1%
665K_0402_1%
VGA@ RG147
VGA@ RG148
VGA@ RG149
10_0402_1% 7 17 RG144
<26> I2CC_SDA SDA ThermalPad
1
1 2 10K_0402_1% MESS138W-G_SOT323-3
<66> CSSP_NVVDD
INA3221AIRGVR_VQFN16_4X4 VGA@ VGA@
1 2 VGA@
<68> CSSN_NVVDDS
10U_0603_6.3V6M
VGA@ CG313
RG146 VGA@ 2
2
10_0402_1%
RG150 VGA@ 1
10_0402_1%
1 2
<68> CSSP_NVVDDS
+3VS
UG104
GPK@
0.1U_0201_10V6K 2 1 CG938 1
VDD PEX_VDD_EN
20
1VSDGPU_EN <26,64> +1.8VALW to +1.8VSDGPU_AON & +1.8VSDGPU_MAIN
2 19
<26,65> NVVDD1_PG NVVDD1_PG FBVDDQ_EN 1.35VSDGPU_EN <26,63>
2 3 18 +1.8VSDGPU_AON 2
<26> OVERT# OVERT# NVVDD1_EN NVVDD1_EN <26,65>
4 DG8
<26,43> GPU_OVERT# GPU_OVERT# 17 DGPU_PWR_EN 3
NVVDD2_EN NVVDD2_EN <26,68> 1V8_AON_EN 1
5 1 @ CG936
<26,68> NVVDD2_PG NVVDD2_PGOOD 2 0.1U_0201_10V6K
6 16 <63> 1.35VSDGPU_PG
<26> GPU_GC6_FB_EN GPU_GC6_FB_EN 1V8_MAIN_EN 1.8VSDGPU_MAIN_EN3V3 <26>
1
BAV70W_SOT323-3 +1.8VALW +1.8VSDGPU_AON 2
7 NGPK@ RG155 NGPK@ UG27
<20,26> GC6_FB_EN3V3 GC6_FB_EN 15 3VSDGPU_EN_R 1 14
100K_0402_5%
8 3V3_SYS_EN 2 VIN1 VOUT1 13
<17,19,26,43,49> PLT_RST# PCH_PLTRST# VIN1 VOUT1
10U_0603_6.3V6M
CG334 VGA@
CG335 220P_0402_50V7K
2
14 1V8_AON_EN 1V8_AON_EN 3 12 1 2
1V8_AON_EN ON1 CT1 1
+5VALW VGA@
9 13 4 11
<20,26> DGPU_HOLD_RST# DGPU_HOLD_RST# GPIO4_1V8_MAIN_EN 1.8VSDGPU_MAIN_EN <26> VBIAS GND CG336 220P_0402_50V7K
12 1.8VSDGPU_MAIN_EN 1 @ 2 1.8VSDGPU_MAIN_EN3V3 5 10 1 2 2
10 DGPU_PWR_EN DGPU_PWR_EN <20,26> ON2 CT2 +1.8VSDGPU_MAIN
RG200 0_0201_5% VGA@
<25,26> DGPU_PEX_RST# DGPU_PEX_RST# +1.8VALW 6 9 +1.8VSDGPU_MAIN
1 VIN2 VOUT2
VGA@ CG337 7 8
VIN2 VOUT2
10U_0603_6.3V6M
@ 11 0.1U_0201_10V6K
GND
22U_0603_6.3V6M
CG338 VGA@
CG939 1 2 0.1U_0201_10V6K OVERT# 15 1 1
2 GPAD
CG339 VGA@
@ @ CG935
1
CG940 1 2 0.1U_0201_10V6K DGPU_PEX_RST# SLG4U41989VTR_STQFN20_3X2 EM5209VF_DFN14_2X3 0.1U_0201_10V6K
@ GPK@ VGA@
CG941 1 2 0.1U_0201_10V6K 1.8VSDGPU_MAIN_EN 2 2
2
Reserve for 1.8V O.D. pin.
3 3
+1.0VSDGPU
RG151
VCC
IN B
1
4 3VSDGPU_EN_1 1 2 3VSDGPU_EN_R 100K_0402_5% +5VS
1.8VSDGPU_MAIN_EN3V3 2 OUT Y NGPK@ +5VS R40 VGA@ RG194 VGA@
GND
IN A
1
20_0402_5% 1_0603_5%
1
1
RG225
2
NL17SZ08DFT2G_SC70-5 CG315 NGPK@ 1M_0402_5% NVVDD2_EN# 2 G
D
QG18B VGA@
3
2
2
NGPK@ 0.22U_0201_6.3V6K VGA@ S PJT138KA_SOT363-6 VGA@ RG196
2
6
PJT138KA_SOT363-6 QG19B VGA@
1
3
3
D 2N7002KDW_SOT363-6 NVVDD1_EN# 2 G
D
NVVDD2_EN 5 G
D
1.35VSDGPU_EN# 5
+3VS/+3VSDGPU
S
1
+1.8V/+3.3V level PJT138KA_SOT363-6
4
+3VS
3
S
4
1
NVVDD1_EN 5 G
D
UG20
RG197 VGA@ VGA@ QG19A S
+3VSDGPU
6
1 2N7002KDW_SOT363-6 D
1_0603_5% +1.8V/+3.3V level
4
2 VIN1 1.35VSDGPU_EN 2
1 VIN2
VGA@ CG314 G
2
1U_0402_6.3V6K 7 6
VIN thermal VOUT +3.3V level S
1
1
2 D
3 1 1
+5VALW VBIAS
10U_0603_6.3V6M
CG316
0.1U_0201_10V6K
CG317
2 QG21 VGA@
3VSDGPU_EN_R 4 5 G
ON GND L2N7002WT1G SC-70-3
S SB00001GE00
3
2 2
1
VGA@ CG319 AOZ1334DI-01_DFN8-7_3X3
VGA@
VGA@
0.1U_0201_10V6K VGA@
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/12/15 Deciphered Date 2017/12/15 Title
GPU power control
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 36 of 73
A B C D E F G H
A B C D E
SM01000EJ00 3000ma
220ohm@100mhz
LCD POWER CIRCUIT DCR 0.04
1U_0402_6.3V6K
CX2
5 1 W=60mils W=60mils
IN OUT LX1 EMI@
1 1 1
2 HCB2012KF-221T30_0805
10U_0603_6.3V6M
1 1
0.1U_0201_10V6K
0.1U_0201_10V6K
GND 1 2 CX7 1 1 1
4 3 CX3 CX4 1 @
2 EN OC 0.1U_0201_10V6K CX6 CX8 CX1
2 2 1
SY6288C20AAC_SOT23-5 @ CX5 1000P_0402_50V7K
10U_0603_6.3V6M 68P_0402_50V8J EMI@ 2 2 2
<18,26> PCH_ENVDD 2
@ESD@
1
2
RX1
100K_0402_5%
2
RX3
0_0402_5%
<17> EDP_HPD 1 @ 2 EDP_HPD_R
EDP_HPD_R <26> LED PANEL Conn.
+3VS
1
+INVPW R_B+ JEDP1
RX4
W=60mils 1
100K_0201_5% 1 DIS@ 2 RG221 EDP_AUXN_C 2 1
100K_0402_5% 2
3
100K_0201_5% 1 DIS@ 2 RG222 EDP_AUXP_C 4 3
2
5 4
100K_0201_5% 1 DIS@ 2 RG223 EDP_AUXN PCH_BKL_PW M 6 5
2 BKOFF# 7 6 2
100K_0201_5% 1 DIS@ 2 RG224 EDP_AUXP +LCDVDD EDP_HPD_R 8 7
9 8
10 9
RX10 1 @ 2 100K_0402_5% 11 10
12 11
@ESD@ 13 12
PCH_BKL_PW M CX9 1 2 220P_0402_50V7K EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
<18,26> PCH_BKL_PW M <7> EDP_AUXN EDP_AUXP CX19 EDP_AUXP_C 14
<7> EDP_AUXP 1 2 0.1U_0201_10V6K 15
@ESD@ 16 15
BKOFF# CX10 1 2 220P_0402_50V7K EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
<43> BKOFF# <7> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
1 2 0.1U_0201_10V6K 18
<7> EDP_TXN0 18
19
RX5 1 @ 2 10K_0402_5% EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20 19
<7> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
1 2 0.1U_0201_10V6K 21
<7> EDP_TXN1 21
22
EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
<7> EDP_TXP2 EDP_TXN2 CX16 EDP_TXN2_C 23
1 2 0.1U_0201_10V6K 24
<7> EDP_TXN2 24
25
EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
<7> EDP_TXP3 EDP_TXN3 CX18 EDP_TXN3_C 26
1 2 0.1U_0201_10V6K 27
<7> EDP_TXN3 27
28
29 28
USB Touch Screen <15> USB20_P6
<15> USB20_N6
30 29
30
31
+TS_PW R 32 31
Touch +TS_PW R 32
+5VS +3VS 33
Screen TS_EN 33
RX6 1 @ 2 0_0603_5% 34
<20,43> TS_EN 34
+3VS 35
3 RX7 1 2 0_0603_5% USB20_N5_CAMERA 36 35 41 3
USB20_P5_CAMERA 37 36 G1 42
For 37 G2
Camera 38 43
DMIC_CLK_R 39 38 G3 44
<42> DMIC_CLK_R DMIC_DATA_R 39 G4
40 45
Camera <42> DMIC_DATA_R 40 G5
ACES_50398-04041-001
CONN@
RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
<15> USB20_N5 DMIC_CLK_R SP010013I00
RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<15> USB20_P5 DMIC_DATA_R
2
DX1
YSLC05CH_SOT23-3
@ESD@
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 37 of 73
A B C D E
A B C D E
RPY2
HDMI_CLKN 1 8 HDMI_GND
CY22 1 2 .1U_0402_16V7K HDMI_CLKP HDMI_CLKP 2 7
<27> GPU_DP3_P3 HDMI_CLKN HDMI_TX_N0
CY24 1 2 .1U_0402_16V7K 3 6
<27> GPU_DP3_N3 HDMI_TX_P0 4 5
1 CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 1
<27> GPU_DP3_P2 HDMI_TX_N0
CY17 1 2 .1U_0402_16V7K 499_0804_8P4R_1%
<27> GPU_DP3_N2
CY18 1 2 .1U_0402_16V7K HDMI_TX_P1 RPY3
<27> GPU_DP3_P1 HDMI_TX_N1 HDMI_TX_N1
CY19 1 2 .1U_0402_16V7K 1 8
<27> GPU_DP3_N1 HDMI_TX_P1 2 7
CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 HDMI_TX_N2 3 6
<27> GPU_DP3_P0 HDMI_TX_N2 HDMI_TX_P2
CY21 1 2 .1U_0402_16V7K 4 5
<27> GPU_DP3_N0
499_0804_8P4R_1%
3
D
+3VS 5 QY2B
G UY2
2N7002KDW _SOT363-6
S 3
4
OUT
1
HDMI_CLKP RY15 1 2 6.04_0402_1% HDMI_R_CLKP 1
IN CY23
2 0.1U_0201_10V6K
GND
2
@EMI@ CY26 2
3.3P_0402_50V8
AP2330W -7_SC59-3
1
2 2
+HDMI_5V_OUT
HDMI_TX_P0 HDMI_R_TX_P0 RPY1
RY16 1 2 6.04_0402_1%
HDMI_CTRL_DAT 8 1
HDMI_TX_N0 RY17 1 2 6.04_0402_1% HDMI_R_TX_N0 HDMI_CTRL_CLK 7 2 +1.8VSDGPU_AON
DY2 GPU_DP3_CTRL_CLK 6 3
HDMI_R_CLKN 1 1 10 9 HDMI_R_CLKN GPU_DP3_CTRL_DAT 5 4
HDMI_R_CLKP 2 2 9 8 HDMI_R_CLKP 2.2K_0804_8P4R_5%
HDMI_TX_P1 RY18 1 2 6.04_0402_1% HDMI_R_TX_P1
HDMI_R_TX_N04 4 7 7 HDMI_R_TX_N0
HDMI_TX_N1 RY19 1 2 6.04_0402_1% HDMI_R_TX_N1
HDMI_R_TX_P05 5 6 6 HDMI_R_TX_P0
3 3
L05ESDL5V0NA-4 SLP2510P8
HDMI_TX_P2 RY20 1 2 6.04_0402_1% HDMI_R_TX_P2 ESD@
HDMI_TX_N2 RY22 1 2 6.04_0402_1% HDMI_R_TX_N2 SC300003Z00 +HDMI_5V_OUT HDMI connector
DY3 JHDMI1
HDMI_R_TX_N11 1 10 9 HDMI_R_TX_N1 HDMI_HPD 19
18 HP_DET
HDMI_R_TX_P12 2 HDMI_R_TX_P1 +5V
9 8 17
+3VS +3VS HDMI_CTRL_DA 16 DDC/CEC_GND
3 HDMI_R_TX_N24 4 HDMI_R_TX_N2 HDMI_CTRL_CLK SDA 3
7 7 15
14 SCL
Reserved
2
HDMI_R_TX_P25 5 6 6 HDMI_R_TX_P2 13
HDMI_R_CLKN 12 CEC
RY24 3 3 11 CK-
CK_shield
2
1M_0402_5% HDMI_R_CLKP 10
G
SC300003Z00 5
HDMI_R_TX_P1 4 D1_shield 20
D1+ GND
2
HDMI_R_TX_N2 3 21
RY11 DY1 2 D2- GND 22
RY11 design guide rev2.0 use 20K pull down. 100K_0402_5% HDMI_HPD 6 3 HDMI_CTRL_CLK HDMI_R_TX_P2 1 D2_shield GND 23
I/O4 I/O2 D2+ GND
CCM_C100042GR019M298ZL
1
CONN@
5 2
VDD GND
+1.8VSDGPU_AON ZZZ2
DC232003500
HDMI_CTRL_DAT 4 1
I/O3 I/O1 +HDMI_5V_OUT
AZC099-04S.R7G_SOT23-6
ESD@
5
QY1A HDMI_ROYALTY
PJT138KA_SOT363-6 ROYALTY HDMI W /LOGO+HDCP
G
4 3 HDMI_CTRL_CLK RO0000003HM
4 <27> GPU_DP3_CTRL_CLK 4
S
45@
2
QY1B
PJT138KA_SOT363-6
G
1 6 HDMI_CTRL_DAT
<27> GPU_DP3_CTRL_DAT Security Classification Compal Secret Data Compal Electronics, Inc.
S
HDMI CONN.
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 38 of 73
A B C D E
5 4 3 2 1
+3VS +3VS_SSD_NGFF
RM1 @
0_0805_5%
1 2
1
10U_0603_6.3V6M
0.1U_0201_10V6K
1 2
+ CM3
CM1 CM2 150U_6.3V_M_D2
2 1 2
SGA00009000
D D
+3VS_SSD_NGFF
M.2 SSD
JSSD1
1 2
3 GND 3P3VAUX 4
5 GND 3P3VAUX 6
<18> PCIE_PRX_DTX_N9 7 PERn3 NC 8
<18> PCIE_PRX_DTX_P9 9 PERp3 NC 10
CM6 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N9 11 GND DAS/DSS# 12
<18> PCIE_PTX_DRX_N9 CM4 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P9 13 PETn3 3P3VAUX 14
<18> PCIE_PTX_DRX_P9 15 PETp3 3P3VAUX 16 ESD@
17 GND 3P3VAUX 18 SSD_RST#_R CM16 2 1 100P_0402_50V8J
<18> PCIE_PRX_DTX_N10 19 PERn2 3P3VAUX 20
<18> PCIE_PRX_DTX_P10 21 PERp2 NC 22
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND NC 24
<18> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 NC 26
Place close to JSSD pin 50
<18> PCIE_PTX_DRX_P10 27 PETp2 NC 28
29 GND NC 30
ESD request to reserve.
<18> PCIE_PRX_DTX_N11 31 PERn1 NC 32
<18> PCIE_PRX_DTX_P11 33 PERp1 NC 34
CM8 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N11 35 GND NC 36
<18> PCIE_PTX_DRX_N11 CM9 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P11 37 PETn1 NC 38 RM2 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <18>
39 40
41 GND NC 42 RM4 1 @ 2 0_0402_5%
<18> PCIE_PRX_DTX_P12 43 PERn0/SATA-B+ NC 44
C <18> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC 46 C
CM10 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N12 47 GND NC 48
<18> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 SSD_RST#_R RM6 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# SSD_CLKREQ#_R PLT_RST_BUF# <17,40,41>
51 52 RM7 1 @ 2 0_0402_5% SSD_CLKREQ# <16>
53 GND CLKREQ# 54
<16> CLK_PCIE_NGFF# REFCLKN PEWake#
<16> CLK_PCIE_NGFF 55 56
57 REFCLKP NC 58
GND NC
RM9 @
SP070018L00
Pull high at PCH side 10K_0402_5%
1
RM10
1 @ 2 SSD_DET#
B <18> SATA_GP1 B
0_0402_5%
1
D
@ QM1 2
BSS138W -7-F_SOT323-3 G SSD_RST#_R 2 @ 1 +3VS
S RM44 10K_0402_5%
3
SSD_CLKREQ#_R 2 @ 1
SSD_DET# RM45 10K_0402_5%
+3VS
SATA Device 0
PCIE Device 1 reserve for Optane Memory
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
mSATA-SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 39 of 73
5 4 3 2 1
A B C D E
LAN-RTL8411B
LDO mode
W=60mil RL1 2 @ 1 0_0603_5% W=60mil +LAN_VDD +3V_LAN
W=60mil
300mA 1.4A
SWR@ IDC 1200mA
+REGOUT LL1 1 2
+3VALW +3V_LAN 2.2UH_HPC252012NF-2R2M_20%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
CL28 SWR@
1U_0402_6.3V6K
CL8
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CL10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1
CL2
RL2 @ 1 Using for Switch mode 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL1
0.1U_0201_10V6K
CL3
0.1U_0201_10V6K
CL4
0.1U_0201_10V6K
CL5
0.1U_0201_10V6K
CL6
0.1U_0201_10V6K
CL7
CL9
CL11
CL12
CL13
0_0805_5%
1 2 The trace length from
SWR@
SWR@
Lx to PIN48 (REGOUT)
2 2 2 2 2 2 2 2 2 2 2 2 2 2
LDO@
60mil 60mil and from C to Lx must
UL1 < 200mils.
5 1
IN OUT
2
GND Using for Switch mode
Place near Pin 3,8,33,46 Place near Pin 20 Place near Pin 11,32,48
4 3 11/27: P/N change to SH00000RT00
EN OC The trace length
2 ( S COIL 2.2UH +-20%
SY6288C20AAC_SOT23-5 from C to
CL14 HPC252012NF-2R2M 1.3A) PIN34,35(VDDREG)
1U_0402_6.3V6K must < 200mils.
1 LAN_PWR_EN
LAN_PWR_EN <43>
PVT modify 01/06
+3V_LAN UL2 R2534, R2537, R2539, R2535, R2536
RL5 1 2 10K_0402_5% Power Manahement/Isolation change to R short
From EC ISOLATEB 31
RL3 2 @ 1 0_0402_5% LAN_PME# 39 ISOLATEBPIN
<17,43> EC_PME# LANWAKEB
High active. Card Reader
15 SD_D0 RL6 1 @ 2 0_0402_5% SD_D0_R
EN threshold voltage min:1.2V reserve EC_PME# pull high 100K to +3VALW_EC SD_D0/MS_D1
PCI Express 14 SD_D1 RL7 1 @ 2 0_0402_5% SD_D1_R
typ:1.6V max:2.0V CLK_PC E_LAN SD_D1 SD_CLK SD_CLK_R
Current limit threshold 1.5~2.8A <16> CLK_PC E_LAN 23 16 RL4 1 2 10_0402_1%
CLK_PC E_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD RL8 1 @ 2 0_0402_5% SD_CMD_R
<16> CLK_PC E_LAN# REFCLK_N SD_CMD/MS_D2 SD_D3 SD_D3_R
+3V_LAN Rising time must >0.5ms and <100ms 18 RL9 1 @ 2 0_0402_5% 2
PLT_RST_BUF# 30 SD_D3/MS_D3 19 SD_D2 RL10 1 @ 2 0_0402_5% SD_D2_R
<17,39,41> PLT_RST_BUF# LAN_CLKREQ# PERSTBPIN SD_D2/MS_CLK SD_WP
29 28 CL16
+3VS <16> LAN_CLKREQ# CLKREQBPIN SD_WP/MS_BS
5P_0402_50V8C
CL15 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P14 25 1
<18> PCIE_PRX_DTX_P14 PCIE_PRX_C_DTX_N14 HSOP @EM @
CL17 1 2 .1U_0402_16V7K 26
<18> PCIE_PRX_DTX_N14 HSON
1
21 42 SD_CD#
<18> PCIE_PTX_C_DRX_P14 HSIP SD_CD# close to pin17
RL15 <18> PCIE_PTX_C_DRX_N14 22 43
2
1K_0402_5% HSIN MS_CD# 2
Transceiver Interface
LAN_MIDI0+ 1
2
LAN_MIDI1- 5 48 +3V_LAN
RL18 LAN_MIDI2+ 6 MDIN1 AVDD33 11 Protect cotact Card contact
LAN_MIDI2- 7 MDIP2 AVDD33 12
15K_0402_5% MDIN2 DVDD33
1400mA
LAN_MIDI3+ 9 32
LAN_MIDI3- 10 MDIP3 DVDD33 Write protect Write Enable
1
MDIN3
RL14 +LAN_VDD
(Lock) (Unlock)
1K_0402_5% XTLI 44 33
XTLO_R 1 2 XTLO 45 CKXTAL1 Clock DVDD10 3 Card Uninsert Open Open Open
+3V_LAN CKXTAL2 AVDD10 8 300mA
SWR mode
AVDD10 Card insert Open Close Close
Regulator and Reference
RL11 1 SWR@2 0_0402_5% +REGOUT 36 20
35 REG_OUT EVDD10
+3V_LAN VDDREG +CARD_3V3
RL13 1 @ 2 0_0402_5% ENSWREG ENSWREG 34 800mA
46 ENSWREG_H 13
+LAN_VDD AVDD10 Card_3V3
LDO mode LAN_RST
2 RL16 1 47
2.49K_0402_1% RSET 27 +VDD33_18
DV33/18
@ T45
0.1U_0201_10V6K
4.7U_0402_6.3V6M
41
1 @ 2 GPO 38 LED0
<19> LAN_GPO LED1/GPO 1 1 1
+3V_LAN
CL20
CL21
RL17 0_0402_5% 37 LEDs
for disable PHY 40 LED3 CL22
@ T46 LED_CR
RL12 1 @ 2 10K_0402_5% GPO reserve 0 ohm 49 @
@ T47 E_Pad 0.1U_0201_10V6K
2 2 2
YL1
25MHZ_20PF_XRCGB25M000F2P18R0
XTLO_R
Place near Pin 27
3 XTLI 3 1 3
3 1 RTL8411B-CGT_QFN48_6X6
NC NC
CL18
1
4 2
1
CL19 +CARD_3V3 Card Reader Connector
15P_0402_50V8J 15P_0402_50V8J
JSD1
2 2
Close to Card Reader CONN
6
SD_CMD_R 3 VDD
P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0) SD_WP# SD_WP SD_CLK_R CMD
4.7U_0402_6.3V6M
0.1U_0201_10V6K
RL22 1 @ 2 0_0402_5% 7
LAN Connector CLK
CL23
CL24
1 1 5
8 VSS1
TL1 JRJ45 +3V_LAN +3VS VSS2
SD_D0_R 9
LAN_TERMAL1 24 12 2 2 SD_D1_R 10 DAT0
TCT1 MCT1 GND DAT1
2
LAN_MIDI0+ 2 23 RJ45_MIDI0+ RJ45_MIDI3- 8 SD_D2_R 1
TD1+ MX1+ PR4- DAT2
2
LAN_MIDI0- 3 22 RJ45_MIDI0- 11 RL21 RL20 SD_D3_R 2
TD1- MX1- RJ45_MIDI3+ 7 GND 100K_0402_5% @ 100K_0402_5% CD/DAT3
4 21 PR4+ SD_WP 12
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1- 6 GND 13
1
LAN_MIDI 6 TD2+ MX2+ 19 RJ45_MIDI1- PR2- SD_WP# 11 GND
1
TD2- MX2- W/P
1
RJ45_MIDI2- 5 D SD_CD# 4
7 18 PR3- SD_WP# 2 QL1 CD
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4 G TAITW_PSDATQ09GLBS1NN4H1
TD3+ MX3+ PR3+ L2N7002WT1G_SC-70-3
LAN_MIDI2- 9 16 RJ45_MIDI2- S SB00001GE00 CONN@
3
TD3- MX3- RJ45_MIDI1+ 3
10 15 PR2+ CL26
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI0- 2
40mil 10P_0402_50V8J
40mil SP011611110
LAN_MIDI3 12 TD4+ MX4+ 13 RJ45_MIDI3- PR1- 10 LANGND 2 1 RJ45_GND
TD4- MX4- RJ45_MIDI0+ 1 GND RL19 @EMI@ CL27 @EMI@
PR1+ 9 0_0402_5% 10P_0402_50V8J
1 GND
3
SD_CLK_R 1 2 1 2
4
3
2
1
MESC5V02BD03_SOT23-3
GST5009-E @
CL25 SP050006B10 RPL1 SINGA_2RJ1660-000111F DL1
0.1U_0201_10V6K 2 75_0804_8P4R_1% CONN@ ESD@ JPL1 Close to JREAD1 for EMI
Place close to TCT pin JUMP_43X118
DC234009H00
5
6
7
8
LANGND
RJ45_GND
1
LAN RTL8411H
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THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 40 of 73
A B C D E
A B C D E
Wireless LAN
+3VALW W=60mils +3VS_W LAN
UM1
1U_0402_6.3V6K
CM15
5 1
IN OUT
1
2
@ GND
1 1
4 3
2 <43> W LAN_ON EN OC
SY6288C20AAC_SOT23-5
IOAC@
JNGFF1
1 2
GND_1 3.3VAUX_2 CNVI@
3 4 1 RM41 2
<15> USB20_P14 USB_D+ 3.3VAUX_4
For BT 5 6 @ T52 75K_0402_1%
<15> USB20_N14 USB_D- LED1#
7 8
2 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 @ 2 0_0201_5% 2
<16> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <19>
<16> CNV_PRX_DTX_P1 11 12
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 @ 2 0_0201_5%
SDIO_DAT0 PCM_IN CLKREQ_CNV# <19>
<16> CNV_PRX_DTX_N0 15 16 @ T53
17 SDIO_DAT1 LED2# 18
<16> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18
19 20
21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 0_0402_5%
<16> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <16>
23
<16> CLK_CNV_PRX_DTX_P SDIO_RST
24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 0_0402_5%
UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX <16>
25 26 RM38 1 @ 2 0_0201_5%
GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <16>
27 28 RM39 1 @ 2 0_0201_5% CNV_BRI_PTX_DRX <16>
<18> PCIE_PTX_C_DRX_P15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM12 2 @ 1 0_0402_5%
<18> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <43>
31 32 RM13 2 @ 1 0_0402_5%
NGFF WL+BT (KEY E) (link to PICE Port 15)
PCIE X1
<18> PCIE_PRX_DTX_P15 33
35
GND_39
PER_TX_P0
CLink_DATA
CLink_CLK
34
36
E51RXD_P80CLK <43>
1
RM19
100K_0402_5%
2 1 W LAN_PME#
+3VS_W LAN
RM16 10K_0402_5%
2
2 1 BT_ON
RM47 10K_0402_5%
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 41 of 73
A B C D E
A B C D E
10U_0402_6.3V6M
CA1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
+5VS_AVDD JPA1 @ 5
RA1 @ 1 2 6 G5
UA1 20mil G6
0_0603_5%
2 2 2 1 2 JUMP_43X39 ACES_50273-0040N-001
CONN@
DA4 256ESD@ GND
1 1 1 1 (output = 300 mA) DMIC_CLK34 1
0.1U_0201_10V6K
CA4
0.1U_0201_10V6K
CA5
10U_0603_6.3V6M
CA6
6 3
+3VS I/O4 I/O2
ALC256-CG MQFN 48P
S IC ALC256-CG MQFN 48P CODEC 2 2 2
256@ SA000080Q00
near Pin41 near Pin46 5 2
VDD GND
GNDA GND
4 1 DMIC_DATA34
CA7 1 2 0.1U_0201_10V6K
near Pin26 +1.8VS I/O3 I/O1
0.1U_0201_10V6K
CA11
10U_0603_6.3V6M
CA12
RA2 0_0402_5%
10U_0603_6.3V6M
CA9
0.1U_0201_10V6K
CA10
40mil JSPK1
SPKR+ EM @ 1 LA2 2 HCB1608KF-121T30_0603 SPK_R+ 1
SPKR- EM @ 1 LA3 2 HCB1608KF-121T30_0603 SPK_R 2 1
2 2 HDA_BIT_CLK_R SPKL+ EM @ 1 LA4 2 HCB1608KF-121T30_0603 SPK_L+ 3 2
near Pin1 Place near Pin40 SPKL- EM @ 1 LA5 2 HCB1608KF-121T30_0603 SPK_L- 4 3
5 4
2
41
46
26
40
6 G1
9
10P_0402_50V8J 2 1 CA27 DMIC_CLK UA1 RA5
G2
0_0402_5%
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
@RF@ ACES_50278-00401-001
Reserved for RF SP02000RR00
1
@EMI@
LINE1_L 22 43 SPKL- GND CONN@
LINE _R LINE1-L(PORT-C-L) SPK-OUT-L- 2
21 42 SPKL+
LINE1-R(PORT-C-R) SPK-OUT-L+ CA13
24 45 SPKR+ 22P_0402_50V8J
2 23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 SPKR- 1 2
+MICBIAS LINE2-R(PORT-E-R) SPK-OUT-R- @EMI@
31
30 LINE1-VREFO-L 32 HP_LEFT
LINE1-VREFO-R HPOUT-L(PORT-I-L) 33 HP_RIGHT
+3VS RING2 17 HPOUT-R(PORT-I-R)
2 1 SENSE_A SLEEVE 18 MIC2-L(PORT-F-L) /RING
RA13 100K_0402_1%
40mil MIC2-R(PORT-F-R) /SLEEVE 10 HDA_SYNC_R
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <19>
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK 5 HDA_SDOUT_R HDA_BIT_CLK_R <19>
GPIO1/DMIC-CLK SDATA-OUT 8 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <19>
<43> EC_MUTE#
47
PDB
SDATA-IN RA10 33_0402_5%
DM C_DATA34
HDA_SD N0 <19>
Digital MIC
48 1 256@ 2 single net
1 255@ 2 RESETB 11 SPDIF-OUT/GPIO2 RA45 0_0402_5%
<19> HDA_RST#_R
RA42 0_0402_5% RESETB 16 1 2 BEEP#_R MIC BOM upload by Audio Team
MONO_IN 12 MONO-OUT 1U_0402_6.3V6K
PCBEEP +MIC2_VREFO 256@ CA28
Close codec
<48> HP_PLUG# RA12 2 1 200K_0402_1% SENSE_A 13 29
14 HP/LINE1 JD(JD1) MIC2-VREFO
RA17 2 @ 1 20K_0402_5% 15 MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3 7 CA14 1 2 10U_0603_6.3V6M
1 LDO3-CAP GND
37 39 CA16 1 2 10U_0603_6.3V6M TO eDP cable
CA15 35 CBP LDO2-CAP 27 CA17 1 2 10U_0402_6.3V6M DM C_DATA 2 1 DMIC_DATA_R
GNDA CBN LDO1-CAP DM C_DATA_R <37>
1U_0402_6.3V6K 10mil RA14 1 2 100K_0402_5% RA7 0_0402_5%
2
3V_1.8V_PVDD 36 CODEC_VREF GNDA PCH_DMIC_DATA0 2
28 CA18 @1 2 10U_0402_6.3V6M <19> PCH_DMIC_DATA0 @ 1
CPVDD VREF RA8 33_0402_5%
CA20 1 2 2.2U_0402_6.3V6M
3V_5V_STB 20 PCH_DMIC_CLK0 2 @ 1
+3VS_DVDD VD33 STB <19> PCH_DMIC_CLK0
CA21 @1 2 0.1U_0201_10V6K RA9 33_0402_5%
1 255@ 2 3V_1.8V_PVDD CA19 1 2 19 34 CPVEE
GNDA MIC CAP CPVEE DMIC_CLK DMIC_CLK_R
1U_0402_6.3V6K
CA22
RA36 0_0402_5% 1 2 1
+1.8VS 10U_0603_6.3V6M LA6 EMI@ BLM15PX221SN1D_2P DM C_CLK_R <37>
GNDA
1 256@ 2
RA37 0_0402_5% RA19 2 @ 1 0_0402_5% 4 25
SM01000Q500
3 49 DC DET AVSS1 38 2 3
+3VALW Thermal PAD AVSS2
1 255@ 2 3V_5V_STB
RA16 0_0402_5% ALC255-CG_MQFN48_6X6
+5VALW
GND SA000082700
1 256@ 2 GNDA
RA35 0_0402_5% 255@
1
256@
2
RA27 RA31 1 @ 2 0_0402_5% RA32 1 @ 2 0_0402_5% RA41 256@ LINE1_L CA23 1 2 4.7U_0402_6.3V6M
1
22K_0402_5% @ESD@ 3.3K_0402_5% RA44
LINE1_R
100P_0402_50V8J
CA26
+MICBIAS DA3
GND GNDA GND GNDA 2 2 RA23 1
RESETB 4.7K_0402_5%
GND 1
3 2 RA28 1
4.7K_0402_5%
BAT54A-7-F_SOT23-3
PN SCSBAT54100
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THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 42 of 73
A B C D E
A B C D E
Board ID
+3VLP_EC
+3VLP_EC +3VLP_ECA
2
+3VLP LB1
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA 100K_0402_1%
1 2 Ra
JUMP_43X39
1
AD_BID
0.1U_0201_10V6K
0.1U_0201_10V6K
@ 1 1 1
CB1
CB2
CB3
2
RB3 32P@ 1
+3VLP_EC @ RB2 0.1U_0201_10V6K RB3 28P@ @ CB4
1 For Power consumption 2 2 2 1
0_0402_5% 20K_0402_1% Rb 0.1U_0201_10V6K
Measurement
RB4 1 @ 2 47K_0402_5% EC_PME# ECAGND 2
ECAGND <53>
1
+3VLP_LPC 240K_0402_1%
SD000001B80
Analog Board ID definition,
111
125
22
33
96
67
Please see page 3.
9
UB1
ESPI Bus Pin : 1~5.7.8.10.12.14
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
1
CB6 1 2 100P_0402_50V8J AC_ N LPC_AD1 8 63 BATT_TEMP D
<18,49> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 BATT_TEMP <53,54> EC_CLR_CMOS
10 LPC & MISC 64 2 QB6
<18,49> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I CHG_CTL1 <46>
65 G L2N7002WT1G_SC-70-3
ADP_I/AD2/GPIO3A ADP_I <53,54>
1
@EMI@ @EMI@ CLK_LPC_R 12 66 AD_BID
AD Input S SB00001GE00
3
2 1 2 1 CLK_LPC_R <18> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 WLAN_PME# RB26
<17,19,26,36,49> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# WLAN_PME# <41> @
CB7 RB6 37 76 10K_0402_5%
<50> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 EC_PME# <17,40>
22P_0402_50V8J 33_0402_5% 20
<20> EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38
<41> WLAN_ON
2
CLKRUN#/GPIO1D
68 LAN_PWR_EN
<49> KSI[0..7] DA0/GPIO3C EC_TP_INT# LAN_PWR_EN <40>
DA Output EN_DFAN1/DA1/GPIO3D 70
VR_PWRGD EC_TP_INT# <17,49>
KSI0 55 71
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN
+3VLP_EC KSI1/GPIO31 DA3/GPIO3F KBL_EN <49>
KSI2 57
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN EC_MUTE# <42> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% KSI4 59 84 1 @ 2 SYS_PWROK <19,51>
2 1 2 2.2K_0402_5% EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_TYPEC_EN# USB_EN <48> 2
RB11 KSI5 60 85 RB7 0_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C EC_TYPEC_EN# <44>
KSI6 61 PS2 Interface 86
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK CHG_EN <46>
KSI7 62 87
<49> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <49>
KSO0 39 88
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <49> +3VS
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL <18,26> GPU_ALERT
KSO4 43 98 RB9 1 VGA@ 2 10K_0402_5%
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_EN TP_PWR_EN <49>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VC N0_PH ME_EN <19> GPU_OVERT# RB12 1 @ 2 10K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <53>
KSO8 47 KSO7/GPIO27
SPOK_3V KSO8/GPIO28 SPI Device Interface SPOK_5V
RB72 1 @ 2 0_0402_5% KSO9 48 119
KSO9/GPIO29 MISO/GPIO5B BT_ON SPOK_5V <55>
KSO10 49 120
KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <41> +3VLP_EC
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
SPOK_5V RB73 1 @ 2 0_0402_5% SPOK_3V5V KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <50> EC Internal PU
KSO13 52
KSO14 53 KSO13/GPIO2D L D_SW# RB13 1 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R GPU_ALERT <26>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89
KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S <54>
90
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 CAPS_LED# BATT_BLUE_LED# <48>
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# CAPS_LED# <49>
77 GPIO 92
SPOK_3V5V EC_RSMRST# <53,54> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <48>
1 2 78 93
<53,54> EC_SMB_DA1 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# <48>
DB2 RB751V-40_SOD323-2 79 95 SYSON
<19,26,44,48> PCH_SML1CLK 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <51,56,58>
<19,26,44,48> PCH_SML1DATA EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON <51,59,60,61>
127
PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <46>
1 2 PU at CPU side SM Bus
DB3 RB751V-40_SOD323-2
PM_SLP_S3# 6 100 EC_RSMRST#
<19,51> PM_SLP_S3# ESPI_RST# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 DGPU_AC_DETECT EC_RSMRST# <19>
14 101
EC_VCCST_PG_R <18> ESPI_RST# SPOK_3V GPIO07 GPXIOA04 VC N1_ADP_PROCHOT DGPU_AC_DETECT <20,26,54>
1 2 15 102
<55,58> SPOK_3V TP_EN GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <53>
DB4 RB751V-40_SOD323-2 16 103
<49> TP_EN TS_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<20,37> TS_EN WL_OFF# GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <50,53,55>
3 18 105 BKOFF# 3
<41> WL_OFF# AC_PRESENT GPIO0C BKOFF#/GPXIOA08 THERMAL_ALERT# BKOFF# <37>
19 GPIO GPO 106 For Thermal Portect Shutdown
<19> AC_PRESENT GPU_OVERT# AC_PRESENT/GPIO0D GPXIOA09 3V_EN_R THERMAL_ALERT# <48>
25 107
<26,36> GPU_OVERT# FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PM_SLP_S0#
28 108 DB1
<50> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 PM_SLP_S0# <19>
29 RB751V-40_SOD323-2
<50> FAN_SPEED2 E51TXD_P80DATA FANFB1/GPIO15 3V_EN
30 MAINPWON 1 2
VCOUT1_PROCHOT <41> E51TXD_P80DATA E51RXD_P80CLK EC_TX/GPIO16 AC_ N 3V_EN <55>
31 110 1
<41> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN <54>
32 112 RB14
<19,51> PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <55>
2
ECAGND 69
LB2 2 1 1 2 VR_HOT#
VR_HOT# <60>
FBMA-L11-160808-800LMT_0603
@ RB18
0_0402_5%
H_PROCHOT# 1 2 SW_PROCHOT#
<11,54> H_PROCHOT#
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
EC ENE-KB9012A4/KB9022
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 43 of 73
A B C D E
5 4 3 2 1
+3.3V_CC +3.3V_CC
2
+5VALW US2 +5V_CC RS103
10K_0402_5% RS105
10K_0402_5%
6 1
2
IN OUT CUR_MODE0
1
1
RS116 1 2 100K_0402_5% 5 2 CUR_MODE1
SET GND CS90
2
+3VALW RS117 1 2 1K_0402_5% 4 3 .1U_0402_16V7K
EN(/EN) FLAG 2 RS106
D D
RS104 10K_0402_5%
1 G527ATP1U_TSOT23-6 10K_0402_5% @
@ @
1
CS101
2.2U_0402_6.3V6M
2
+3VALW +3.3V_CC
H L Default Current
L H Medium current
RS1 1 @ 2 0_0603_5% H H High current
+5V_CC
US3
1 10
GPIO2(INT#) VCONN RSET
2 9 +3.3V_CC CS91 1 2 2.2U_0402_6.3V6M
CUR_DR VDD33
1
8 +1.8V_CC CS92 1 2 1U_0402_6.3V6K RS113 RS109 RS110
179F_SMB_DA2 3 VDD18 6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5%
179F_SMB_CK2 4 SI0(SDA)
+USB3_VCCC SI1(SCL) 11 CC1_VCONN <45>
3 2
VBUS_DC 7 CC1 12
CUR_MODE0 VBUS_DC CC2 CC2_VCONN <45>
C 14 D C
CUR_MODE0
1
CUR_MODE1 15 5
CUR_MODE1 TYPEC_3A <19>
RS101 16 G
39K_0402_1% CC_EN 5
CC_SEL 13 VBUS_EN_179 S QS2B
4
TYPC_CONN_DET 2N7002KDW _SOT363-6
2
6
6 17 D
GND EPAD
1
VBUS_DC 2 TYPEC_1P5A <17>
RS118 G
1
EJ179F_QFN16_4X4 10K_0402_5%
RS102 S QS2A
1
3.01K_0402_1% 2N7002KDW _SOT363-6
2
check bios
1050 is use PCH output
2
150U_D2_6.3VM_R17M
1
.1U_0402_16V7K
1
CS95
CS96
0.1U_0402_25V6
22U_0805_25V6M
22U_0805_25V6M
+
1 1 1
CS97 @
CS98 @
CS99 @
+3.3V_CC
2 2
US11 2 2 2
6 1
IN OUT
1
@ RS108 RS107 @
+3.3V_CC +5VALW
4.7K_0402_5% 4.7K_0402_5% RSET 5 2
SET GND
1
2
VBUS_EN_179 4 3 1 @ 2
EN FLAG USB_OC0# <15>
RS111 @ Initial Current mode selection
5
G518B1TP1U_TSOT23-6 RS112
G
100K_0402_5% 1
QS1B @ 0_0402_5% VBUS_EN_179 EC_TYPEC_EN# V BUS
2
<19,26,43,48> PCH_SML1CLK
D
6
1 @ 2 D H H 0
RS114 0_0402_5% 2 QS3A @
A A
G H L
2N7002KDW _SOT363-6 1
2
S
G
QS1A @
2N7002KDW _SOT363-6
<19,26,43,48> PCH_SML1DATA
D
1 @ 2 CC+USB TYPE C
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS115 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 44 of 73
5 4 3 2 1
5 4 3 2 1
D
USB3.0 (Port 2) D
2 8 TBTA_SBU2 2 8 TBTA_SBU2
Change to 0201 for placement. Follow intel #575549. USB3_PTX_L_DRX_N3 4 USB3_PTX_L_DRX_N3 USB3_PRX_L_DTX_N2 4 USB3_PRX_L_DTX_N2
7 7
USB3_PTX_L_DRX_P3 5 6 USB3_PTX_L_DRX_P3 USB3_PRX_L_DTX_P2 5 6 USB3_PRX_L_DTX_P2
C C
LS10 EMI@ 3 3
USB20_P2 2 1 USB20_P2_L
<15> USB20_P2 2 1 TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9
USB20_N2 3 4 USB20_N2_L SC300003Z00 SC300003Z00
<15> USB20_N2 3 4
DLM0NSN900HY2D_4P
SM070005U00
+USB3_VCCC +USB3_VCCC
0.1U_0402_25V6 2 1 CS84
B RS119 RS120 A4 B9 CS87 1 2 0.1U_0402_25V6 B
220K_0402_5% VBUS VBUS
220K_0402_5%
A5 B8 TBTA_SBU2
<44> CC1_VCONN CC1 SBU2
1
CS13
2
2
DN1 DP2
3
TBTA_SBU1 A8 B5
SBU1 CC2 CC2_VCONN <44>
0.1U_0402_25V6
DS19 ESD@ 2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
MESC5V02BD03_SOT23-3 VBUS VBUS
USB3_PRX_C_DTX_N3 A10 B3 USB3_PTX_C_DRX_N3
USB3_PRX_L_DTX_P3 CS104 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_P3 USB3_PRX_C_DTX_P3 A11 SSRXN2 SSTXN2 B2 USB3_PTX_C_DRX_P3
SSRXP2 SSTXP2
USB3_PRX_L_DTX_N3 CS105 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_N3 A12 B1
GND GND
1
1
1 5
RS121 RS122 2 GND GND 6
220K_0402_5% 3 GND GND 7
220K_0402_5% GND GND
4 8
GND GND
2
LOTES_AUSB0249-P001A
CONN@
Security Classification
2017/07/20
Compal Secret Data
2018/07/20 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CC+USB TYPE C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 45 of 73
5 4 3 2 1
A B C D E
USB3_PTX_L_DRX_N1 2
1
ESD@
9
8
USB3_PTX_L_DRX_P1
USB3_PTX_L_DRX_N1
1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1
<18> USB3_PTX_DRX_P1 USB3_PRX_L_DTX_P1 USB3_PRX_L_DTX_P1
CS2 .1U_0402_16V7K 4 7
1 3 1
TVWDF1004AD0_DFN9
SC300003Z00
USB3_PRX_DTX_P1 RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1
<18> USB3_PRX_DTX_P1
LS1 EMI@
USB3_PRX_DTX_N1 RS91 1 @ 2 0_0402_5% USB3_PRX_L_DTX_N1 U2DP1 3 4 U2DP1_L
<18> USB3_PRX_DTX_N1 3 4
U2DN1 2 1 U2DN1_L
2 1
DLM0NSN900HY2D_4P
SM070005U00
DS2 ESD@
6 3 U2DP1_L
I/O4 I/O2
+USB3_VCCA
5 2
VDD GND
U2DN1_L 4 1
0904 vendor recommend I/O3 I/O1
+5VALW AZC099-04S.R7G_SOT23-6
2 2
RS8 1 @ 2 0_1206 5%
22U_0603_6.3V6M
.1U_0402_16V7K
1 1
CS9
CS7
+USB3_VCCA
2@ 2 US12
+5VALW_CHG 1 12 +USB3VCCA_CHG RS10 1 @ 2 0_1206_5%
VIN VOUT
2
<15> USB20_N1 3 DM_OUT
RS11
<15> USB20_P1 DP_OUT 10 U2DP1
0_0402_5%
2 @ 1 13 DP_IN 11 U2DN1
<15> USB_OC1# FAULT# DM_IN
1 4
<43> CHG_ILMSEL ILIM_SEL
CS8 5 15
0.1U_0201_10V6K
<43> CHG_EN EN ILIM_L 16
0831 Reserve ILIM_L R as vendor recommend
@ 2 ILIM_HI
1
6
<43> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
7 9
CTL2 NC
RS12
RS13
8 14
<43> CHG_CTL3 CTL3 GND 17
Thermal Pad @
2
+5VALW SLGC55544CVTR_TQFN16_3X3
+USB3_VCCA
USB3_PTX_L_DRX_N1
6
7
8
SSRX-
SSRX+
GND
GND
GND
10
11
12
CTL1 CTL2 CTL3 ILIM SEL MODE Current Limit Note USB3_PTX_L_DRX_P1 SSTX- GND
Setting 9 13
SSTX+ GND
1 1 0 1 SDP1 ILIM H Data Lines Connected ACON_TARB5-9V1391
CONN@
1 1 1 0 SDP2 ILIM L Data Lines Connected DC23300NH00
1 1 1 1 CDP ILIM H Data Lines Connected
0 1 1 1 DCP ILIM H Data Lines Disconnected
Aut o
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 46 of 73
A B C D E
A B C D E
+3VS +5VS_HDD
1 2 +5VS_HDD
RO4 0_0805_5% 100mils
UO2 @
SATA_PRX_DTX_P4_R
10U_0603_6.3V6M
CO12
1 SATARD@
2 5 1 1 1
<18> SATA_PRX_DTX_P4 IN OUT
1
RO21 1 SATARD@
20_0201_5% SATA_PRX_DTX_N4_R
<18> SATA_PRX_DTX_N4 2
RO22 0_0201_5% CO11 CO13
1 SATARD@
2 SATA_PTX_DRX_N4_R GND 0.1U_0201_10V6K 0.1U_0201_10V6K
<18> SATA_PTX_DRX_N4
2
RO23 1 SATARD@
20_0201_5% SATA_PTX_DRX_P4_R 4 3 2 @ 2 @
1 <18> SATA_PTX_DRX_P4 <17> HDD_PWRGT EN OC 1
RO24 0_0201_5%
SY6288C20AAC_SOT23-5
B_EQ1
A_EQ2
A_EQ1
DEW
+3VS JHDD3
CO1 14
2 1 13 GND
SATARD@ GND
0.01U_0402_16V7K UO1 +5VS_HDD 12
20
19
18
17
16
SATARD@ PS8527CTQFN20GTR2A_TQFN20_4X4 11 12
10 11
DEW
VDD2
B_EQ1
A_EQ2
A_EQ1
G_INT2_R 9 10
8 9
SATA_PTX_DRX_P4_RSATARD@ CO4 2 1 SATA_PTX_C_DRX_P4 0.01U_0402_16V7K 1 15 RDSATA_PTX_DRX_P4 7 8
SATA_PTX_DRX_N4_RSATARD@ CO5 2 1 SATA_PTX_C_DRX_N4 0.01U_0402_16V7K 2 A_INP A_OUTP 14 RDSATA_PTX_DRX_N4 SATA_PRX_DTX_P4 NORD@ CO14 2 1 0.01U_0201_6.3V7K SATA_PRX_DTX_P4_C 6 7
3 A_INN A_OUTN 13 B_EQ2 SATA_PRX_DTX_N4NORD@ CO15 2 1 0.01U_0201_6.3V7K SATA_PRX_DTX_N4_C 5 6
SATA_PRX_DTX_N4_RSATARD@ CO8 2 1 SATA_PRX_C_DTX_N4 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_PRX_DTX_N4 4 5
SATA_PRX_DTX_P4_RSATARD@ CO9 2 1 SATA_PRX_C_DTX_P4 0.01U_0402_16V7K 5 B_OUTN B_INN 11 RDSATA_PRX_DTX_P4 SATA_PTX_DRX_N4NORD@ CO16 2 1 0.01U_0201_6.3V7K SATA_PTX_DRX_N4_C 3 4
21 B_OUTP B_INP SATA_PTX_DRX_P4 NORD@ CO17 2 1 0.01U_0201_6.3V7K SATA_PTX_DRX_P4_C 2 3
GND2 2
VDD1
REXT
1
B_DE
A_DE
1
EN
ACES_51625-01201-001
CONN@
6
7
8
9
10
+3VS
SP010028W00
SATARD@
RO6 1 @ 2 4.7K_0402_5% A_DE RO7 2 1
+3VS +3VS
0.1U_0201_10V6K
SATARD@ CO10
4.99K_0402_1%
B_DE
A_DE
B_DE 1
RO8 1 @ 2 4.7K_0402_5%
2 1 RO9 @ 2 2
RO10 1 @ 2 4.7K_0402_5% B_EQ1 4.7K_0402_5%
2
RO11 1 @ 2 4.7K_0402_5% A_EQ1
A_EQ2
Cable Type
RO12 1 SATARD@
2 4.7K_0402_5%
JHDD2
RO13 1 @ 2 4.7K_0402_5% B_EQ2 1
USE 8527 re-driver 1
2
RO14 1 @ 2 4.7K_0402_5% DEW SA00007JU10 FFC Type +3VS 3
4
2
3
JHDD1
14 5 4
13 GND 6 5
GND 7 6
RO15 1 @ 2 4.7K_0402_5% A_DE +5VS_HDD 12 8 7
11 12 +5VS_HDD 9 8
RO16 1 @ 2 4.7K_0402_5% B_DE 10 11 10 9
G_INT2_R 9 10 11 10
RO17 1 @ 2 4.7K_0402_5% B_EQ1 JHDD_P8 8 9 G_INT2 1 @ 2 G_INT2_R 12 11
7 8 RO5 0_0402_5% JHDD_P8 13 12
RO18 1 @ 2 4.7K_0402_5% A_EQ1 RDSATA_PRX_C_DTX_P4 6 7 14 13
RDSATA_PRX_C_DTX_N4 5 6 RDSATA_PRX_DTX_P4 SATARD@ CO7 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P4 15 14
RO19 1 @ 2 4.7K_0402_5% A_EQ2 4 5 RDSATA_PRX_DTX_N4 SATARD@ CO6 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N4 16 15
RDSATA_PTX_C_DRX_N4 3 4 17 16
RO20 1 SATARD@
2 4.7K_0402_5% B_EQ2 RDSATA_PTX_C_DRX_P4 2 3 RDSATA_PTX_DRX_N4 SATARD@ CO3 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N4 18 17
1 2 RDSATA_PTX_DRX_P4 SATARD@ CO2 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P4 19 18
1 20 19
ACES_51625-01201-001 21 20
CONN@ 22 G1
23 G2
SP010028W00 24 G3
G4
3 ACES_50406-02071-001 3
CONN@
SP010016L00
+3VS
G-Sensor
1
RZ1
10K_0402_5% +3VS
GSEN@
UZ1 GSEN@
2
1 CZ1 1 2 10U_0603_6.3V6M
8 Vdd_IO
4 CS 14 1 2 GSEN@
<19,23,24> D_CK_SCLK 6 SCLSPC Vdd CZ2 0.1U_0201_10V6K
<19,23,24> D_CK_SDATA 1 2 10K_0402_5% 7 SDA/SDI/SDO
+3VS RZ2 @
RZ3 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT
16 INT1 9 G_INT2 G_INT <20>
15 ADC1 INT2
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
HDD/ Re-Driver/ G-sensor
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 47 of 73
A B C D E
A B C D E
LS11 EMI@
SLEEVE
RING2
HP_PLUG#
3
4
5
2
3
4
<42>
<42>
RING2
HP_PLUG#
RING2
HP_PLUG#
4
5
6
3
4
5
To Hall sensor/B
USB20_P3_L 5 GNDA SUB_PIN7 6
3 4 GNDA 6 7
<15> USB20_P3 3 4 SUB_PIN7 6 7 +3VLP
7 8
8 7 USB20_P3_L 9 8
2 1 USB20_N3_L USB20_P3_L 9 8 USB20_N3_L 10 9 JHS1
1 <15> USB20_N3 1
2 1 USB20_N3_L 10 9 11 10 1
DLM0NSN900HY2D_4P 11 10 USB20_P4_L 12 11 LID_SW # 2 1
USB20_P4_L 11 USB20_N4_L 12 <43> LID_SW# 2
SM070005U00 12 13 3
USB20_N4_L 13 12 14 13 4 3
14 13 BATT_AMB_LED# 15 14 4
BATT_AMB_LED# 14 <43> BATT_AMB_LED# BATT_BLUE_LED# 15
15 <43> BATT_BLUE_LED# 16 5
BATT_BLUE_LED# 16 15 PWR_SUSP_LED# 17 16 6 GND
PWR_SUSP_LED# 16 <43> PW R_SUSP_LED# PW R_LED# 17 GND
17 <43> PW R_LED# 18
PW R_LED# 18 17 19 18 ACES_51524-0040N-001
LS12 EMI@ 19 18 20 19 CONN@
USB20_P4_L USB_EN 19 <43> USB_EN 20
3 4 20 +5VALW 21 SP010022M00
<15> USB20_P4 3 4 20 21
+5VALW 21 22
22 21 23 22
2 1 USB20_N4_L 23 22 24 23
<15> USB20_N4 2 1 23 24
24 25
DLM0NSN900HY2D_4P 25 24 26 25
26 25 27 26
SM070005U00 27 26 28 27
28 GND 29 28
GND <18> USB3_PRX_DTX_N4 29
<18> USB3_PRX_DTX_P4 30
ACES_51522-02601-001 31 30
CONN@ 32 31
<18> USB3_PTX_DRX_N4 32
SP01001AO00 <18> USB3_PTX_DRX_P4 33
34 33
35 34
<18> USB3_PRX_DTX_N5 35
<18> USB3_PRX_DTX_P5 36 41
37 36 G1 42
38 37 G2 43
<18> USB3_PTX_DRX_N5 38 G3
2
<18> USB3_PTX_DRX_P5 39 44 2
40 39 G4 45
For USB3.0 DB. 40 G5
Pop R227, de-pop R228. ACES_50398-04041-001
R227 1 @ 2 0_0402_5% SUB_PIN7 CONN@
+3VALW
SP010013I00
R228 1 2 0_0402_5%
+3VS
Thermal sensor SMBus address
1
1
2.2K_0402_5%
RF9
2.2K_0402_5%
RF10 TMS@
-->100-1_100xb : 0x4C
(x=0)Write Address(0x98h)
0.1U_0201_10V6K
1
+3VS
TMS@
CF4
(x=1)Read Address(0x99h)
TMS@
2
2
5
G
1
TMS@ QF1B 2
2N7002KDW _SOT363-6 UF1 SA000067P00 RF8 TMS@
1 8 TMS_SMB_CLK 10K_0402_5%
3 4 TMS_SMB_CLK VDD SCLK
<19,26,43,44> PCH_SML1CLK
S
H_THERMDA 2 7 TMS_SMB_DATA
D
2
D+ SDATA
2
G
NCT7718W _MSOP8
TMS@
4 4
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 48 of 73
A B C D E
A B C D E
KSI[0..7]
KSI[0..7] <43>
<43> CAPS_LED#
+5VS
RK1
RK3
1
1 @
2
2
1K_0402_5%
0_0402_5%
1
2
JKB1
1
30
29 GND2
JKB2
KB
<43> NUM_LED#
RK4
RK2
1
1
@ 2
2
0_0402_5%
1K_0402_5%
3
4
5
2
3
4
5
28
ON/OFFBTN# 27
KSO0 26
GND1
28
27
26
BackLight
R17 PVT modify ON/OFFBTN# 6 KSO1 25
+3VLP 100K_0402_5% KSO0 7 6 KSO2 24 25
2 1 KSO1 8 7 KSO3 23 24
KSO2 9 8 KSO4 22 23
KSO3 10 9 KSO5 21 22 +5VS JBL1
1 10 21 1
<43> ON/OFFBTN# ON/OFFBTN# KSO4 11 KSO6 20 U4 1
KSO5 12 11 KSO7 19 20 5 1 +5VS_BL 2 1
KSO6 13 12 KSO8 18 19 IN OUT 3 2
KSO7 14 13 KSO9 17 18 2 4 3
SW1 @ KSO8 15 14 KSO10 16 17 GND 4
EVQPLDA15_4P KSO9 16 15 KSO11 15 16 1 @ 2 4 3 5
Test Only 1 3 KSO10 17 16 KSO12 14 15 <43> KBL_EN EN OC 6 GND
R18 0_0402_5% 1
KSO11 18 17 KSO13 13 14 SY6288C20AAC_SOT23-5 GND
BOT 2 4 KSO12 19 18 KSO14 12 13 C32 @ ACES_51524-0040N-001
KSO13 20 19 KSO15 11 12 0.1U_0201_10V6K CONN@
KSO14 21 20 KSO16 10 11 2
SP010022M00
6
5
KSO15 22 21 KSO17 9 10
KSO16 23 22 KSI0 8 9
KSO17 24 23 KSI1 7 8
KS 0 25 24 KSI2 6 7
KSI1 26 25 KSI3 5 6
KSI2 27 26 33 KSI4 4 5
KSI3 28 27 GND 34 KSI5 3 4
KSI4 29 28 GND KSI6 2 3
KS 5 30 29 KSI7 1 2
KS 6 31 30 1
KSI7 32 31
32 ACES_85201-2805
CONN@
ACES_50596-03201-P01
CONN@ SP01000GO00
+3V_PTP +3VALW 2 @ 1
+3VALW
0_0402_5% RK5
+3VS
2 @ 1
0_0402_5% RK6
UK1
+3VALW +3VALW_TPM +3VS +3VS_TPM +3V_PTP
4.7U_0402_6.3V6M
R19 R20 1 5 @ CK1
0_0603_5% 0_0603_5% OUT IN 0.1U_0201_10V6K JTP1
1
CK2
1 @ 2 1 @ 2 2 2 2 1 1
GND 1
2
TP_CLK 2
TP_DATA 2
10U_0603_6.3V6M
0.1U_0201_10V6K
10U_0603_6.3V6M
0.1U_0201_10V6K
C36
0.1U_0201_10V6K
C37
0.1U_0201_10V6K
C38
3 4 CK3 3
1 1 1 1 1 1 2 OC EN EC PS2 3
C33
C34
C35
1U_0402_6.3V6K RK7 4
SY6288C20AAC_SOT23-5 1 10K_0402_5% I2C_1_SDA_R 5 4
I2C_1_SCL_R 6 5
near PCH I2C
1
2 TPM@ 2 TPM@ 2 TPM@ 2 2
TPM@ 2
TPM@ TPM@ EC_TP_INT# EC_TP_ NT# 7 6
pin1 <17,43> EC_TP_INT# TP_EN 8 7
<43> TP_PWR_EN <43> TP_EN 8
9
10 GND
GND
TP_PWR_EN follow SYSON behavior
near ACES_51524-00801-001
CONN@
pin8,14,22
SP01001A910
BADD SELECTION +3V_PTP +3V_PTP
* 1 AEh(write),
AFh(read)
1
+3V_PTP
1
2
RK8 RK9
G
QK1A 2.2K_0402_5% 2.2K_0402_5%
1
U5 TPM@ +3VALW_TPM 2N7002KDW_SOT363-6
2
1 RK10 RK11
2
29 VSB +3VS_TPM 6 1 I2C_1_SCL_R 4.7K_0402_5% 4.7K_0402_5%
S
XOR_OUT/SDA/GPIO0 <20> I2C_1_SCL
3 30 8
D
3
3 SCL/GPIO1 VDD1 14 1 @ 2
2
0_0402_5% 1 @ 2 R21 TPM_BADD 6 GPX/GPIO2 VDD2 22 RK12 0_0402_5%
GPIO3/BADD VDD3
5
G
LPC_AD0 24 2 QK1B TP_CLK
<18,43> LPC_AD0 LPC_AD1 LAD0/MISO NC1 TP_DATA TP_CLK <43>
21 7 2N7002KDW_SOT363-6
<18,43> LPC_AD1 LPC_AD2 LAD1/MOSI NC2 TP_DATA <43>
18 10
<18,43> LPC_AD2 LPC_AD3 LAD2/SPI_IRQ# NC3 I2C_1_SDA_R
15 11 <20> I2C_1_SDA 3 4
S
<18,43> LPC_AD3 LAD3 NC4 25
D
CLK_LPC_TPM_R 19 NC5 26 1 2
<18> CLK_LPC_TPM_R LPC_FRAME# 20 LCLK/SCLK NC6 31 @ 0_0402_5%
RK13
<18,43> LPC_FRAME# PLT_RST# LFRAME#/SCS# NC7
17
<17,19,26,36,43> PLT_RST# TPM_SERIRQ LRESET#/SPI_RST#/SRESET#
27 9
<18,43> TPM_SERIRQ PM_CLKRUN# 13 SERIRQ GND1 16
<19> PM_CLKRUN# CLKRUN#/GPIO4/SINT# GND2
28 23
LPCPD# GND3 32
4 GND4 33
5 PP PGND 12
TEST Reserved
NPCT650LA0YX_QFN32_5X5
SERIRQ PH 10K to +3VS at PCH side P/N:SA00008ELC0 (S IC NPCT650ABBYX QFN 32P TPM2.0 FW 1.3.1.0)
CLKRUN# PH 10K to +3VS at PCH side
LPCPD# had internal PH @EMI@ @EMI@
CLK_LPC_TPM_R R22 1 2 33_0402_5% C39 1 2 22P_0402_50V8J
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
KB & TP & TPM Connector
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 49 of 73
A B C D E
+5VS
1 @ 2 +VCC_FAN1
40mil +5VS
1 @ 2
40mil
+VCC_FAN2
Screw
RF4 0_0603_5%
1 1
RF6 0_0603_5%
1 1
Hole
CF5 CF6 CF8 CF9
4.7U_0603_10V6K 1000P_0402_50V7K 4.7U_0603_10V6K 1000P_0402_50V7K
@EMI@ @EMI@ @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14
2 2 2 2 H_6P4 H_4P0 H_3P8 H_3P8 H_3P8 H_4P0 H_3P8 H_3P8 H_3P8 H_4P0 H_2P0N H_3P0 H_3P0 H_3P0
FD1 FD2
1
@ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ H15 @ H17 @ H18 @ H20 @ H21 @ H22 @ H23 @ H24
H_3P8 H_3P0 H_2P5 H_2P7x2P0N H_6P0 H_2P7x2P0N H_3P2 H_3P2 FD3 FD4
+3VS @ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
RF3
10K_0402_5%
FAN Conn
JFAN1
2
+VCC_FAN1 1
2 1
<43> FAN_SPEED1 FAN_PWM1 3 2
<43> FAN_PWM1 4 3
1
CF7 5 4
1000P_0402_50V7K 6 G1
@EMI@ G2
2 ACES_50278-00401-001
CONN@
SP02000RR00
+3VS
1
DK1 FPESD@
6 3 USB20_N8_L
I/O4 I/O2
R24 0_0402_5%
R25 USB20_P8_L 4 1
I/O3 I/O1
10K_0402_5%
AZC099-04S.R7G_SOT23-6
1
Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
2N7002KDW_SOT363-6
side S +FP_VCC
1
1
JFP1
PIN ETU801 FA577E-1200
3
Q1B D C40 8
BI_GATE 5 0.1U_0201_10V6K USB20_P8_L 7 8 10
<53> BI_GATE G 2 USB20_N8_L 6 7 G2 9 1 +FP_VCC(5V) +FP_VCC(3V)
5 6 G1
2N7002KDW_SOT363-6 USBP D+
S 4 5 2
4
3 4
2 3 3 USBN D-
1 2
1 4 GND GND
ACES_51522-00801-001
CONN@ 5 NC NC
6 NC NC
BI SW SP01001AE00
Reset Button @ 7 NC
3 SW2 1
8 NC
SW3
BI_GATE 1 2 BI_GATE
BI_S <53>
4 2
3 4 ATE-2-V-TR_4P
H : 3.8mm
SKRPABE010_4P
Release : Battery Off
Push : Battery ON
SN10000CV00
THIS SHEET OF ENG NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
FAN & FP & Screw Hole
Size Document Number R ev
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AND TRADE SECRET INFORMAT ON. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRON CS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 50 of 73
A B C D E
2
2 13
G
VIN1 VOUT1
1
JUMP_43X118 Q10A
SUSP# RQ1 1 2 0_0402_5% 3VS_ON 3 12 1 2 R37 2N7002KDW_SOT363-6
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5%
4 11 1 6
S
+5VALW VBIAS GND EC_VCCST_PG_R <11,43>
D
2
1 5VS_ON 1
RQ2 2 @ 1 0_0402_5% 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion
5
@ 6 9 @ PQ2
G
+5VALW VIN2 VOUT2 +5VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +5VS
Q10B
15 JUMP_43X118 Q11A 2N7002KDW_SOT363-6
GPAD 2N7002KDW_SOT363-6 4 3
S
VR_ON <43,59,60,61>
D
EM5209VF_DFN14_2X3 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<19,43> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
G
2 2 2 2
S
1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
Place CQ7 close UQ1 pin 1&2
G
Q12A @
Place CQ8 close UQ1 pin 6&7 2N7002KDW_SOT363-6
1 6
S
SYS_PWROK <19,43>
D
5
G
+3VALW Q12B @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ 2N7002KDW_SOT363-6
1
4 3
S
PCH_PWROK <19,43>
2
D
R38
2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @
2
2
Q13A PM_SLP_S4 2
1
1
2N7002KDW_SOT363-6
5
SUSP +0.6VS_VTT_R SYSON# +1.2V_VDDQ_R D
G
2 Q13B
<19,43> PM_SLP_S4# G 2N7002KDW_SOT363-6
S 4 3 SYSON
S
1
D
@ Q7A Q7B @ @ Q8B Q8A @ MOW14, For tPLT15 200us(max)
6
6
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 SLP_S4# to VDDQ ramp down
2 5SUSP SYSON 5 2 SYSON#
<43,54,56,59> SUSP# G G <43,56,58> SYSON G G
1
R32 S S S S
1
1
10K_0402_5%
@
2
@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1 05V_VCCST_OUT RQ5 1 @ 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0402_6.3V6K
VIN1 VOUT1 1 UC4
SYSON RQ4 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1 +1.05VS_VCCSTG
4 11 VIN2
+5VALW VBIAS GND +1.05VS_VCCSTG_OUT
7 6 RQ6 1 @ 2 0_0603_5%
SUSP# RQ8 1 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1 8VS_OUT VBIAS 2
+1.8VALW
6 9 RQ9 1 @ 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2
+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
DC Interface
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 51 of 73
A B C D E
A B C D E
1 1 2
1 2 EMI@ PL102
2
EMI@ PC104
3
1000P_0402_50V7K
FBMA-L11-201209-800LMA50T
3
1
EMI@ PC102
4 PR103
100P_0402_50V8J
4 5 1 2 PR102
5
1
6 4.7_1206_5% EMI@ PL103
6
1
7 FBMA-L11-201209-800LMA50T 4.7_1206_5%
2
7 8
2
8 1 2
2
1
PJP101
1
PC101 EMI@ EMI@ PC105
99.9
0.1U_0603_25V7K 0.1U_0603_25V7K
2
2 2
3 3
@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
4 4
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 52 of 73
A B C D E
WWW.AliSaler.Com
A B C D E
+3VLP
1
1 1
PC205 @
1
0.1U_0603_25V7K
2
@
PR207 100_0402_1% @ PR215 PR214
100K_0402_1%
1 2 26.7K_0402_1% 21.5K_0402_1%
EC_SMB_DA1 <43,54>
PR213
PR205 100_0402_1%
2
1
1 2
EC_SMB_CK1 <43,54>
PU201 @
1 8
VCC TMSNS1
(Common Part)
PR202 2 7 2 1
Battery Bot Side <45,47> SL200002H00
2
200K_0402_1% GND RHYST1
@
1
1 2 MAINPWON 3 6 @ PR216
+3VLP <43,50,55> MAINPWON OT1 TMSNS2
100K_0402_1%_NCP15WF104F03RC
@ PJP201 10K_0402_1% @
PIN1 GND 1 4 5 2 1
1 2 OT2 RHYST2
PIN2 GND 2 3
1 2
BATT TEMP <43,54>
1
EC_SMB_DA1-1
PH202
G718TM1U_SOT23-8 @ PR218
PIN3 SMD
2
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% 14K_0402_1%
4 5 BATT_TS
100K_0402_1%_NCP15WF104F03RC
PIN4 SMC 5 6 BATT_B/I
6 7
PIN5 TEMP
PH203
(Common Part)
2
7 8
PIN6 BI 8 9 +RTCVCC SL200002H00
GND 10
PIN7 Batt+ GND 2016/09/26 @
PIN8 Batt+ PH3 Near VGA.
CVILU_CI9908M2HR0-NH Change thePQ201 from
1
PR212 SB00000QO00 to SB00001GD00,
100K_0402_5%
1
2 D 2
2 PQ201
<50> BI_GATE G LBSS139LT1G 1N SOT-23-3
S
3
+12.6V BATT+
EMI@ PL201 2016/11/22 update
FBMA-L11-201209-800LMA50T
1 2 For KB9022
+12.6V BATT BI_S <50>
sense 5mΩ Active Recovery When PR204=16.9K
EMI@ PL202
1
FBMA-L11-201209-800LMA50T
1 2 PR217 For KB9022
0_0402_5% OTP Active Recovery
2
design reserve VCIN0_PH(V) 89'C, 1V 56'C, 2V
1
1000P_0402_50V7K 0.01U_0402_25V7K
2
1
3 3
PR204
18.7K_0402_1%
VCIN1 ADP PROCHOT <43>
2
VCIN0 PH <43>
1
PC203 must close to EC pin
1
PR208
10K_0402_1% PH201
2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2
0.1U_0402_25V6
1
T202@ PH201 is Common Part SL200002H00
T201@
ECAGND <43>
T202 T201 must close to PH201
ADP_I=20*I(adapter)*0.01
I(adapter)=adapter(W)*130%/19
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS NC. AND CONTAINS CONF DENTIAL
BATTERY CONN/OTP
AND TRADE SECRET NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTA NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 53 of 73
A B C D E
5 3 2 1
Vgs = 20V
Vds = 60V
Id = 250mA
1
D D D
2 PQ301 max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W
G L2N7002WT1G_SC70-3 PR339 @
S 0.01_1206_1%
CSR rating: 1W +19VB
3
VCSIP-VCSIN spec < 81mV
1 2 1 2 1
PR301 PR302 2 3
1M_0 02_1% 3M_0 02_5%
PQ311
PQ310 +19V_P1 AON7380_DFN3X3-8-5
Need check the SOA for inrush TPCA8057 1N DFN5X6-8
+19V_P2
PR303
+19VB_CHG
1 1 0 005_1206_1% EMI@ PL70
2 2 FBMA-L11-201209-800LMA50T
5 3 3 5 1 1 2
+19V_VIN
EMI@
EMI@
EMI@
2200P_0 02_25V7K
2 3 Isat: 10A
10U_0805_25V6K
10U_0805_25V6K
0.1U_0 02_25V6
0.1U_0 02_25V6
CSIP_CHG_R
DCR: 14mohm
1
CSIN_CHG_R
PC302
PC303
PC305
PC30
PC32
@ PC322 @ PJP1
2
1 2 1 2
1 2
1000P_0 02_25V JUMP_ 3X118
1
2_0 02_5%
Co-lay jump and ISN choke.
PR305
@
PR30
1 0_0 02_5%
PR306
2
99K_0 02_1%
2
PC306
PQ312
2
.02K_0 02_1%
.02K_0 02_1%
1 2 AON7380_DFN3X3-8-5
1
L >H 0.1U_0 02_25V6 2
2.04 vin min w/o 2M =17.41 5 3
C H >L PR309 C
PC307 0.22U_0603_25V7K
2.02 vin min w 2M =17.77 100_0 02_1%
2
PR307
PR308
1 2 +12.6V BATT
1
CMSRC_CHG
2200P_0 02_50V7K
66.5K_0 02_1%
@ PC308
1
PR310
PC301
1
ASGATE_CHG 1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0 02_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
0x3CH <BIT9> PSYS current gain
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 1 Ω
m
1 VDD_CHG
AON7506_DFN33-8-5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20m Ω
100K_0 02_1%
32
31
30
29
28
27
26
25
BIT0 = 2.28uA/W no support Turbo boost 0 1u PU301
BIT1 = 0.57uA/W Choke 4.7uH SH00000YC00 (Common Part) Power loss: 0.245W
PR311
CSIP
ASGATE
QPCP
BGATE
CSIN
CMSRC
OPCN
VBAT
PC309 (Size:6.6 x 7.3 x 3 mm) CSR rating: 1W
Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBA
T ) PR312 0. 7U_0 02_16V Z (DCR:28m~33m) VCSPP-VCSON spec < 81mV
ACIN_CHG 1 2 BST_CHG 1 2 BST_CHG_R
1 2
R Psys = 1 2V / Ipsys
2
3
2
1
<43> AC_IN @ PR31 0_0 02_5% ACOK UGATE .7UH_PCMB063T- R7MS_8A_20% +12.6V BATT
Battery wattage = 40Wh
1
1 2 22 1 2
Ipsys = 1 14 x (45+40) = 96 9uA <43,53> EC_SMB_DA1 SDA PHASE
PR313
.7_1206_5%
1 2 21 2 3
<43,53> EC_SMB_CK1 SCL LGATE
1
=====================================
EM @ PR320
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PR317 0_0 02_5% PQ306
5
adapter wattage = 65W 1 2 5 20 VDDP_CHG
2
AON7506_DFN33-8-5
1
2 1K_0 02_1%AMON_ISL95520 6 VDD_CHG
PC310
PC311
PC312
Ipsys = 1 14 x (65+40) = 119 7uA PR318 1 19 1 2
R Psys = 1 2V / 96 9uA = 10K ohm <43,53> ADP_I AMON VDD
2
PR321 1 2 1K_0 02_1%BMON_ISL95520 7 ISL88739AHRZ-T_QFN32_ X 18 PR319 7_0 02_5%
2
BMON DCIN
680P_0 02_50V7K
**Design Notes**
BATGONE
Close to EC. 8 17 PC313 PC31
For 45W/65W /90W system, 2S/3S/4S battery NC NTC
1U_0201_6.3V6K 1U_0201_6.3V6K
CCLIM
2
ACLIM
COMP
1
B Maximum Charging current 3.5A
PROG
B
AGND
CSON
CSOP
EMI@ PC315
FSET
PR323
1
Maximum Battery discharge power 55W 100K_0 02_1%
3
2
1
1
2
0.1U_0 02_25V6 0.1U_0 02_25V6 PR322 PD1
33
10
11
12
13
15
16
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function Follow adapter and 0_0 02_5% 1 PR32 10_1206_5% 3
+19V_VIN
2
2
#Circuit Design Close to Vsys current source. 2
2
2
FSET_CHG
PC318
1U_0603_25V6
EC
1. ACLIM and CCLIM are devider voltage control. Base on CPU Core VR design@ VF = 0.38V For 4S per cell 4.35V battery
The resistor is pop on CPU VR schematic. S SCH DIO BAS 0CW SOT-323
1
1
Charge current 3A PR325 0_0603_5%
AC N_CHG
10K_0 02_1% 1 2
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) VDD_CHG +12.6V_BATT
Power density : 0.61 (23X16) VDD=5V
2
#Protect function
1
CCLIM_CHG
1. ACOVP : VCC voltage > 24V
200K_0 02_1%
S_BATT@ PR3 2
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
1
PR329
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
4. CHGOCP : based on charge current setting 200K_0 02_1%
2
5. BATOVP : 4.6V/Cell +3VS Pull high on HW side COMP_CHG PR330 2_0 02_5%
2
1
6. BATLOWV : No.
@ PR331 PR333=0 ohm, Fs=500KHZ ~ +/ 15%
7. TSHUT : 150C PC319 S_BATT@ PQ308
1
1
100_0 02_1%
2
PR332
1 2 LTC015EUBFS8TL_UMT3F
1
CSON_CHG CSON_CHG_R
150K_0 02_1%
560P_0 02_50V7K
@ 1 2
1
1
PR335
1
PR336 180W@
PC320
2
1
D
110K_0 02_1%
AC_IN
0.015U_0 02_25V7K
PC321
S 1 2 2
3
3
1
PQ315 D
6
D 2
2 < 3 51,56,59> SUSP# G
A A
G
@VGA@ @VGA@ @VGA@ 2N7002KW_SOT323-3 S
3
PQ31 PQ313B S PQ313A
1
1
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs1 = 20mΩ and Rs2 = 10mΩ) .
CC LIM = VccLIM / 64 x Rs2 Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
============================================================= PWR_CHARGER
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs1 = 20mΩ and Rs2 = 20mΩ) . THIS SHEET OF ENG NEERING DRAW NG S THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D S ze Document Number Rev
CC LIM = VccLIM / 32 x Rs2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, NC. NEITHER THIS SHEET NOR THE NFORMATION IT CONTAINS 1.A
WWW.AliSaler.Com
============================================================= MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, NC.
AC LIM = Vac LIM / 32 x Rs1 Date: Tuesday, February 13, 2018 Sheet 5 of 73
5 3 2 1
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 1 2
+19VB
1
150K_0402_1%
PR404
EN1 and EN2 dont't floating
2
@EMI@ PL401
HCB2012KF-121T50_0805
1 2 PU401
1 +19VB SY8286BRAC_QFN20_3X3 PC401 1
PR401
@ PJ403 0.1U_0603_25V7K
+19VB_3V BST_3V
2200P_0402_50V7K
1 2 1 2 1 2 Choke 1.5uH SH000016800 (Common Part)
1 2
(Size:4.9 x 5.2 x 3 mm)
10U_0805_25V6K
EMI@ PC431
@EMI@ PC403
EMI@ PC404
0.1U_0402_25V6
0.1U_0402_25V6
JUMP_43X79
0_0603_5%
1
(DCR:20m~25m)
PC405
BS
IN
IN
IN
IN
PL402
2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP
7 19 1.5UH_PCMB053T-1R5MS_6A_20%
GND LX
@EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR405
1
1
680P_0402_50V7K 4.7_1206_5%
8 18
+3VALWP GND GND
PC407
PC408
PC409
PC410
@ PC429
@ PC430
9 17
+3VLP
2
PG LDO
1
1 3V_SN
10 16
2
NC NC
1
Check pull up resistor of SPOK at HW side PC411
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
PR406 GND 2
100K_0402_5%
11
12
13
14
15
@EMI@
PC412
2
2
3.3V LDO 150mA~300mA Vout is 3.234V~3.366V
<43,58> SPOK_3V
ENLDO_3V5V PC402 PR403
Ipeak=4.65A
3V_FB
1000P_0402_25V8J K_0402_5% Imax=3.25A
1 2 1 2
<43> 3V_EN Iocp=10A
@EMI@ PL403
2 HCB2012KF-121T50_0805 2
+19VB 1 2 +19VB 5V
PU402 PC418
PR408
@ PJ404 SY8288CRAC_QFN20_3X3 0.1U_0603_25V7K
1 2 +19VB_5V BST_5V 1 2 1 2
1 2
Choke 1.5uH SH000016700 (Common Part)
1
JUMP_43X79 0_0603_5% (Size:7.3 x 6.6 x 3 mm)
BS
IN
IN
IN
IN
(DCR:14m~15m)
EMI@ PC432
0.1U_0402_25V6
1
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
20
LX LX PL404
7 19 LX_5V 1 2 +5VALWP
2
GND LX
1
1
PC414
PC415
EMI@ PC416
@EMI@ PC417
8 18 1.5UH_9A_20%_7X7X3_M
GND GND PC419
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
1
9 17 1 2
PG VCC
1
PR409
PC420
PC421
PC422
PC423
@ PC424
@ PC425
4.7_1206_5%
+3VLP
@EMI@
10 16 4.7U_0402_6.3V6M
2
NC NC
OUT
LDO
EN2
EN1
21
FF
GND
1
2
11
12
13
14
15
PR413
VL
1 5V_SN
100K_0402_5% 1
5V LDO 150mA~300mA
2
680P_0402_50V7K
PC427
<43> SPOK_5V ENLDO_3V5V 2
4.7U_0402_6.3V6M Vout is 4.998V~5.202V
PC426
@EMI@
Ipeak=9A
2
5V_EN
Imax=6.6A
3 Iocp=10A 3
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
PR410
2.2K_0402_5%
1 2
<43> EC_ON @ PR411
0_0402_5% @ PJ401
1 2 +3VALWP 1 2 +3VALW
<43,50,53> MAINPWON 1 2
JUMP_43X118
5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
@ PJ402
1
PR412
PC428
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
2
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, NC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 55 of 73
A B C D E
A B C D E
1 1
@ PJ503
JUMP_43X79 Pin19 need pull separate from +1.35VP.
1 2
1 2 +19VB 1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
1 2 +19VB_1.2VP PR502 Peak Current 1A
+19VB @EMI@ PL501 2.2_0603_5%
HCB2012KF-121T50_0805 BST_1.2VP_R 1 2 BST_1.2VP
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
+1.2VP
1
1
EMI@ PC526
@EMI@ PC502
EMI@ PC503
PC504
PC505
change PL501 from UG_1.2VP +0.6VSP
2
2
SM01000C000 to comm
part SM01000P200 LX_1.2VP
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC506
1
PC507
PC508
0.1U_0603_25V7K
16
17
18
19
20
2
PU501
2
2 2
VLDOIN
PHASE
UGATE
BOOT
VTT
Choke 1uH SH00000YE00 (Common 4 21
PAD
Part) LG_1.2VP 15 1
(Size:6.86 x 6.47 x 3 mm) LGATE VTTGND
(DCR:6.2m~7.2m Ohm) PQ503 IOCP
1
2
3
AON7408L 1N DFN 14 2
PL502 PR503 PGND VTTSNS
1UH_PCMC063T-1R0MN_11A_20% 17.4K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PQ502
PC509 CS RT8207PGQW _W QFN20_3X3 GND
1
5 1U_0201_6.3V6K
AON7506_DFN3X3-8-5 1 2 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505 VDDP VTTREF
4.7_1206_5% 5.1_0603_5% 35.4
1 2 VDD_1.2VP 11 5
PC523
PC522
PC521
PC524
PC525
PC520
1 2
1
PGOOD
PC516
1 1 1 1 1 1 4
TON
1
1
@EMI@ PC518 PC517 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K
2
1U_0201_6.3V6K PR511
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10
6
2 2 2 2 2 2 2.2_0402_1%
35.4
1
2
3
FB_1.2VP
TON_1.2VP
EN_1.2VP
Frequency PR506
+5VALW
EN_0.6VSP
6.19K_0402_1%
PR507 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
3 3
Vout=0.75V* (1+Rup/Rdown)
1
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A =0.75*(1+(6.19/10))
PR501 PR508
0_0402_5% 10K_0402_1% =1.214V 1.2%
L/S SI7716 Rds(on) :typ:13.5m Ohm, max:16.5m Ohm 1 2
2
Idsm(TA=25)=16A, Idsm(TA=70)=9.5A <43,51,58> SYSON
Vout=0.75V* (1+Rup/Rdown)
1
@ PC501
Choke: 7x7x3 0.1U_0402_10V7K
=0.75*(1+(8.2/10))
Rdc=6.2mohm(Typ), 7.2mohm(Max) =1.365V 1.1%
2
Switching Frequency: 530kHz @ PR509
Imax=A, Iocp=A 0_0402_5%
Iocp=10.63~12.76A 1 2
<43,51,54,59> SUSP#
OVP: 110%~120% @ PJ501
VFB=0.607V, Vout=1.214V PR510 JUMP_43X118
0_0402_5% +1.2VP 1 2 +1.2V VDDQ
1 2 1 2
<11> SM PG CTRL
1
@ PC519 @ PJ502
JUMP_43X39
0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS VTT
2
1 2
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 56 of 73
A B C D E
A B C D E
10U_0805_25V6K
0.1U_0 02_25V6
@ PJ602 3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL602
EMI@ PC616
0.1U_0603_25V7K
2200P_0 02_50V7K
IN BS
1
JUMP_ 3X79 1UH_11A_20%_7X7X3_M
@EMI@ PC605
PC606
LDO_3V
EMI@ PC60
LX_1VALW
4
IN LX
6 1 2
+1.05VALWP
220U_B2_ VM_R35M
2
2
5 19 Choke 1uH SH00000YE00 (Common Part) 1
330P_0 02_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
IN LX
(Size:6.86 x 6.47 x 3 mm)
1
PR607 @ 7 20 +
PR608
PC608
PC609
PC610
PC611
PC612
@ PC615
GND LX (DCR:6.2m~7.2m Ohm)
0_0 02_5%
8 14 FB_1VALW Rup
2
GND FB 2
2
2
ILMT_1VALW 18 17 LDO_3V
GND VCC
1
1
EN_1VALW 11 10
@ PR609 EN NC PC613
change PL601 FB = 0.6V
1
ILMT_1VALW 13 12 2.2U_0 02_6.3V6M
2
SM01000C000 to comm ILMT NC PR610
0_0 02_5%
15 16
part SM01000P200 +3VALW Rdown
2
2
PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC61
is pull low, floating or pull high 1U_0 02_6 3V6K
2
Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(15.4/20))
Vout=1.062V
2 2
PR611
10K_0 02_1%
1 2
1.8_PG <58>
PR603
10K_0 02_1%
EN_1VALW 1 2
+3VALW
@
1
@ PC601
PR601
0.22U_0 02_10V6K
2
1M_0 02_1%
2
3 3
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
1V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTA NS C 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 57 of 73
A B C D E
A B C D E
PR7123
0_0 02_5%
EN_1.8V 1 2
SPOK_3V < 3,55>
1
Current limit = 4.7A(min) PR712 @ PC7118
0.1U_0 02_16V7K
2
PR7126 1M_0 02_5%
100K_0 02_5%
2
2 1
+3VALW
1 1
20.5K_0 02_1%
68P_0 02_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
PGND NC
@EMI@ PR7125
.7_0603_5%
1
1
PC7127
PR7122
PC7123
1
SY8003ADFC_DFN8_2X2
PC7119
PC7125
@ PC7126
22U_0603_6.3V6M
Rup
2
2
2
2
FB_1.8V
680P_0 02_50V7K
1
1
FB=0.6V PR7121
@EMI@ PC712
Note:Iload(max)=3A
10K_0 02_1%
Rdown
2
+3VALW
2 2
+5VALW
2
PJ7105
2
JUMP_ 3X79
@
1
1
1
PC7210
2
1
PC7108
FB=0.8V
22U_0603_6.3V6M Note:Iload(max)=4A
2
PU7102 G9661MF11U_SO8
PR7110 4 5
0_0 02_5% VIN_2.5V 3 VDD NC 6
< 3,51,56> SYSON 1 2 EN_2.5 2 VN VOUT 7 +2.5VP
GND
1 EN ADJ 8
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0 02_25V7K
PGOOD GND
1
0.1U_0 02_16V7K
1
PR7115
PC7109
9
1
1
PR7113
PC7107
PC7110
@ PC7111
21.5K_0 02_1%
Rup
2
1M_0 02_5%
2
2
@ FB_2.5V
1
PR7116
10K_0 02_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
2
3 3
@ PJ7103
JUMP_ 3X79
1 2
+2.5VP 1 2 +2.5V
@ PJ7107
JUMP_ 3X79
1 2
+1.8VALWP 1 2 +1.8VALW
+1.5VSP:
Imax=0.5A Ipeak=0.75A
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc
Issued Date Deciphered Date
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
1.5VS/2.5V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTA NS C 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 58 of 73
A B C D E
5 3 2 1
10U_0805_25V6K
0.1U_0 02_25V6
2200P_0 02_50V7K
1
1
1
IN BS 0.68UH_7.9A_20%_5X5X3_M
PC7207
@EMI@ PC7217
PC7208
VCCIOP_LX
4
IN LX
6 1 2
+1.0VS_VCCIOP
2
2
1
5 19
PC7219
330P_0 02_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
1
7 20
EMI@
PC7205
PC7206
PC7211
PC7212
Note:Iload(max)=5.5A
10_0 02_1%
2
PC720
PC721
GND LX @
PR7212
8 14 VCCIOP_FB
IOCP=7A~8A(typ)
2
2
2
GND FB
2
1K_0 02_1%
PR721
18 17 VCCIOP_LDO_3V @
2
GND VCC
1
VCCIOP_EN 11 10 PC7218 @
EN NC 2.2U_0 02_6.3V6M
Vout=0.6V* (1+Rup/Rdown)
1
VCCIOP_ILMT 13 12 FB = 0.6V Rup
2
ILMT NC 1 2 =0.6*(1+(12k/20.5k))
15 16
+3VALW BYP NC PR7218 OVP=0.95V*115%=1.0925V
1
21 12K_0 02_1%
Vout=0.951 V 2%
1U_0 02_6.3V6K
PAD
PC7209
20.5K_0 02_1%
1
SY8288RAC_QFN20_3X3
Rdown
2
PR7215
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
2
PR7209 @ 0_0 02_5%
VCCIO_SENSE_R 1 2 VCCIO_SENSE
+VCCIOP_LDO_3V VCCIO_SENSE <13>
@ PR7207 1 2 VSSIO_SENSE
VSSIO_SENSE <13>
C 0_0 02_5% C
@ PR7213 VR_ON 1 2
0_0 02_5% < 3,51,60,61> VR_ON
2
VCCIOP_ILMT PR7208
1K_0 02_5%
1
SUSP# 1 2 VCCIOP_EN
@ < 3,51 5 ,56> SUSP#
0.1U_0 02_25V6
PR7217
1M_0 02_5%
1
1
PC7201
check delay time with HW
PR7201
0_0 02_5%
2
2
2
B B
A A
19VB_CPU 19VB_CPU
90A for ICCMAX=2.2V 76A for ICCMAX=2.2V EMI@ 8 02
BMA- -20 209-800 MA50
VREF +VRE 2
19VB
C8 04 C8 05 C8 06 C8 07 EMI@ 8 03
confirm w th power sequence, EMI@ EM @ BMA- -20 209-800 MA50
00U_25V_NC_6 3X6
0 U_0402_25V6
2200 _0402_50V7K
t need behind 5VS. 2
0U_0805_25V6K
0U_0805_25V6K
+
C8 08
R8 02 R8 03
2
30 _0402_ %
8 45K_0402_ % 2
7 5K_0402_ %
4 02K_0402_ %
19VB_CPU 19VB_CPU
2
N C N CG
R8 04
R8 05
R8 06 R8 0 C8 0 Ta=70=>Id=17 5A
H8 02 H8 0 00_0402_ % 2 2_0603_ % 0 U_0603_25V7K
Rdson=8 2~10 5 mohm
2
2 BOOS _VCC 2BOOS _VCC _R 2 Choke 0.15uH SH00000X700
00K_0402_ %_B25 50 4250K 0K_0402_ %_B25 50 3370K
8 66K_0402_ %
8 66K_0402_ %
Q8 0 (Size:6.59 x 6.6 x 3.0 mm)
2 2_0402_ %
2 2_0402_ %
2
U8 02
2
C8 09 C8 0 N C N N CG N (DCR:0.9m + 7%)
R8 07
R8 08
R8 09
R8 0
2 VCC_CORE
VSSG _SENSE < 2> VCC_UG
D
Fs=400k LL=1 8m for Core 0 22U_0402_25V6K 0 22U_0402_25V6K 4 3 8 0
2
@ R8 0_0402_5% BOO UGA E 0 5UH_MMD06CZER 5MG_37A_20%
2 R C U_ SEN_R 2
2 R C U_ SENA_R 2
5 2 VCC_ HASE 7 VCC_ HASE 4
Fs=400k LL=2 1m for GT WM HASE D2 S
R8 5
8K_0402_ %
5 76K_0402_ %
D SET1 ICCMAX=128A OCP=120% DVIDT=35 7mV 00_0402_ % R8 2 EN 6 2 3 D
EN GND
1 05V_VCCS 2 5 _0402_ %
G2
R8 3
R8 4
S2
S2
S2
57 6K_0402_ %
2 8 7 VCC_ G
SET2 Ramp=133% DVIDW=9us QRT=25mV QRW=44%
57 6K_0402_ %
5VALW VCC GA E 9
R8 9
402K_0402_ %
442K_0402_ %
0 47U_0402_ 6V4Z
3
GND ON6962_D N5X6D-8-7 @EM @
SET3 Zero LL disable VR address Core=0 GT=1
R8 8
2
220K_0402_5%_B25 50 4700K
220K_0402_5%_B25 50 4700K
C8 2 R8 2
R8 6
R8 7
2 R 96 0CGQW_WD N8_2X2 4 7_ 206_5%
SETA1 ICCMAX=32A OCP=120% DVIDT=60mV VSSSENSE < 2>
2
@ R8 22 U_020 _6 3V6K
2
SETA2 Ramp=133% DVIDW=9us QRT=25mV QRW=44% @ R8 20 0_0402_5%
H8 03
H8 04
C8
200_0402_ %
2
2
K_0402_ %
R8 23
SNUB_VC
Core offset function disable GT offset R8 26
2
R C U_ ONSE A R C U_ ONSE
00_0402_ % C8 3
R C U_ S N
00K_0402_ %
function disable PSYS disable 2 0 47U_0402_6 3V6K
VR_HOT# < 3>
2
R C U_ SENA
VREF @EMI@ 2 2
R8 24
_0402_ %
SC K_C U R8 29
C8 4
R8 27
SD O_C U R C U_ S4
2
2 EN 680 _0603_50V8 R8 25 @ R8 3
2
A ER _C U
R8 30 200_0402_ % 0_0402_5%
R8 28
0_0402_5%
19VB_CPU
R C U_ BIAS 2
0_0402_5% 2
2
R C U_EN 2 0_0402_5%
VSSG _SENSE_R VR_ON <43 5 59 6 >
@
0K_0402_ %
3 0 K_0402_ %
3 3K_0402_ %
3 3K_0402_ %
VSSSENSE_R
@ Ta=70=>Id=30A AIS AVco e
5 K_0402_ %
VREF
R 3607CEGQW _W Q N56_6X6 C8 9 C8 20 C8 2 C8 7
Rdson=2 8~3 5 mohm
R8 32
R8 33
R8 34
R8 35
R8 36
EMI@ EM @
U8 0
0 U_0402_25V6
2200 _0402_50V7K
C8 5
57
42
20
22
23
26
25
24
27
32
0U_0805_25V6K
0U_0805_25V6K
2
3
U_020 _6 3V6K
VDIO
GND
SEN
IMON
NC
EN
RGND
SENA
IMONA
IB AS
VC K
RGNDA
2
VR_HO
A ER
VRE
0_0402_5%
2K_0402_ %
24 9_0402_ %
8 2K_0402_ %
26 7K_0402_ %
@ R8 39 0_0402_5%
R8 37
R8 43
R8 38
R8 40
2 56
R C U_ W M
R8 4
@ R8 42 0_0402_5% NC 52
2 44 WM R8 44 C8 22
2
NC 5 R C U_ W M2
@ 2 2_0603_ % 0 U_0603_25V7K Ta=70=>Id=17 5A
R C U_ ONSE 55 WM2 BOOS _VCC2 2BOOS _VCC2_R 2
R C U_SE ONSE 53 R C U_ W M3 Rdson=8 2~10 5 mohm
R C U_SE 2 R C U_ ONSE A 43 WM3
R C U_SE 3 ONSE A 50 R C U_ W M4 Q8 02
R C U_SE A R C U_ S4 WM4 U8 03
2
49
R C U_SE A2 S4 30
R C U_SE NC VCC_UG2
D
4 4 3 8306
SE 5 R8 50 BOO UGA E 0 5UH_MMD06CZER 5MG_37A_20%
768_0402_ %
402_0402_ %
3 4K_0402_ %
02K_0402_ %
300_0402_ % 3 6K_0402_ %
R8 46
R8 47
R8 48
R8 49
SE 3 5 _0402_ % EN GND
G2
S2
S2
S2
R C U_SE A 8 6 2 8 7 VCC_ 2
R8 52
GND AIS 2 5VALW
2
3
7 R C U_ISEN2N 2 GND ON6962_D N5X6D-8-7 @EM @
4 2_0402_ %
R8 54
R8 55
R8 56
R8 57
0_0402_5%
0_0402_5%
0_0402_5%
2 R8 59 U_020 _6 3V6K
AIS 3
2
SEN3 680_0402_ %
200_0402_ %
2
R C U_VSENA 33 3 R C U_ISEN3N 2 R8 6
R8 60
R C U_VSENA AVco e3
2
C RT3607CE 9
AIS 4 R8 62
C8 24
0 47U_0402_6 3V6K C
2
SEN4 680_0402_ % @EMI@ 2 2
R C U_VSEN 2 8 R C U_ISEN4N 2 R8 63
R C U_VSEN AVco e4 C8 25
VSEN SEN4N R C U_ S4 2 EN2 680 _0603_50V8 @ R8 64
2
0_0402_5%
47 R C U_ W MA 2
R C U_VSEN R C U_COM WMA 0_0402_5%
@ R8 65 R8 66 R8 67 COM 46 @
0_0402_5% 0K_0402_ % 23 2K_0402_ % 0 WMA2
Ta=70=>Id=30A AIS 2 AVco e2
ISENA3N
ISENA2N
ISENA N
B
GOOD
COM A
ISENA3
ISENA2
2 2 2 48
< 2> VCCSENSE Rdson=2 8~3 5 mohm
ISENA
WMA3
DVD
VCC
BA
R C U_ B 19VB_CPU
NC
R8 68 C8 26 C8 27
00_0402_ % 330 _0402_50V8 82 _0402_50V8
2 2 2 + 9VB_C U
VCC_CORE
45
28
R C U_COM A 34
35
54
29
40
36
37
R C U_ISENA N 39
38
4
AS G
C8 30 C8 3 C8 32 C8 33
5 0K_0402_ %
R C U_VCC
R C U_DVD
R C U_ BA
0 U_0402_25V6
2200 _0402_50V7K
0U_0805_25V6K
0U_0805_25V6K
R8 7
R8 69
@ R8 70 680_0402_ %
2
0_0402_5% 2
AVG
2
R CPU_VCC
00K_0402_ %
R CPU_VCC
2
R8 74 C8 35 Ta=70=>Id=17 5A
C8 34 2 2_0603_ % 0 U_0603_25V7K
R8 72
0_0603_ %
C8 36
BOOS _VCC3 2BOOS _VCC3_R 2 Rdson=8 2~10 5 mohm
R8 73
0 U_0402_25V6
2
2
2 2U_0402_6 3V6M Q8 03
U8 04
2
2
@ R8 75 R C U_VSENA
2
0_0402_5% R8 77 R8 76
VCC_UG3
D
0K_0402_ % 6 9K_0402_ % 4 3 8305
2 2 2 BOO UGA E 0 5UH_MMD06CZER 5MG_37A_20%
< 2> VCCG _SENSE VCC_ HASE3 VCC_ HASE3
5 2 7 4
R8 78 C8 37 C8 38 WM HASE D2 S
5VALW
00_0402_ % 330 _0402_50V8 68 _0402_50V8 R8 79 EN3 6 2 3
2 2 2 5 _0402_ % EN GND
G2
S2
S2
S2
VCC_G VCCCORE_VR_PWRGD < 3> 2 8 7 VCC_ G3
5VALW VCC GA E 9
3
GND AON6962_D N5X6D-8-7 @EM @
00K_0402_ %
C8 39 R8 8
R 96 0CGQW_WD N8_2X2 4 7_ 206_5%
U_020 _6 3V6K
R8 80
200_0402_ %
2
R8 82
2
SNUB_VC 3
Reserved for RF Team Request
R8 83 C8 40
200_0402_ 0% 7U_0402_6 3V6K
2
1 05V_VCCS confirm with power sequence, R8 84
@EMI@ 2 2
it need behind 5VS. C8 4
R C U_ S4 2
@R @ C8 42 3VALW EN3 680 _0603_50V8 @ R8 85
2
2 2 _0402_50V8C PR96and PR98 pull high resistor are pop at the end of VR 0_0402_5%
2 SVID 2
0_0402_5%
Other VR is unpop @
B B
R8 86 @ R8 87 R8 88 C8 43 Ta=70=>Id=30A AIS 3 AVco e3
19VB_CPU
Rdson=2 8~3 5 mohm
0 U_0402_25V6
00_0402_ %
00_0402_ %
45 3_0402_ %
ENABLE @
Upper Threshold > 0 8V
2
EMI@ EMI@
0 U_0402_25V6
2200 _0402_50V7K
0U_0805_25V6K
0U_0805_25V6K
SC K_C U 2 49 9_0402_ %
R8 89
CPU_SVID_CLK_R <11,61>
2
A ER _C U 2 0_0402_5%
@ R8 90
CPU_SVID_ALERT#_R <11,61>
SDIO_C U 2
R8 9 0_0402_ % CPU_SVID_DAT_R <11 61> R8 92 C8 50 Ta=70=>Id=17 5A
2 2_0603_ % 0 U_0603_25V7K
BOOS _VCC4 2BOOS _VCC4_R 2 Rdson=8 2~10 5 mohm
Ta=70=>Id=30A
Rdson=2 8~3 5 mohm Q8 04
U8 05
2
19VB_CPU
VCC_UG4
D
4 3 8 06
H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm BOO UGA E 0 5UH_MMD06CZER 5MG_37A_20%
VCC_ HASE4 VCC_ HASE4
Idsm(TA=25)=22A, Idsm(TA=70)=17.5A 5
WM HASE
2 7
D2 S
4
C8 5 C8 52 C8 53 C8 54 C8 55 C8 56 R8 93 EN4 6 2 3
EMI@ EMI@ 5 _0402_ % EN GND
G2
S2
S2
S2
VCC_ G4
0 U_0402_25V6
2200 _0402_50V7K
2 8 7
L/S AON6314 Rds(on) :typ:2.8mOhm, max:3.5mOhm
0U_0805_25V6K
0U_0805_25V6K
0U_0805_25V6K
0U_0805_25V6K
5VALW VCC GA E 9
3
Idsm(TA=25)=37A, Idsm(TA=70)=30A GND AON6962_D N5X6D-8-7 @EM @
2
C8 57 R8 94
R 96 0CGQW_WD N8_2X2 4 7_ 206_5%
U_020 _6 3V6K
200_0402_ %
2
R8 96 C8 58 Ta=70=>Id=17 5A
R8 95
SNUB_VCC4
2 2_0603_ % 0 U_0603_25V7K
BOOS _VCCG 2BOOS _VCCG R2 Rdson=8 2~10 5 mohm R8 97 C8 59
200_0402_ 0% 7U_0402_6 3V6K
2
Q8 05 @EMI@ 2 2
U8 06 R8 98
2
VCC_G C8 60
R C U_ S4 2 EN4 680 _0603_50V8 @ R8 99
2
VCCG _UG
G
4 3 8 07 0_0402_5%
BOO UGA E 0 5UH_MMD06CZER 5MG_37A_20% 2
R C U_ W MA 5 2 VCCG _ HASE 7 VCCG _ HASE 4 0_0402_5%
WM HASE D2 S @
R8200 EN5 6 2 3 Ta=70=>Id=30A AIS 4 AVco e4
5 _0402_ % EN GND
G2
S2
S2
S2
82_0402_ %
A A
2
R8202
SNUB_VC G
R8203 C8 63
82_0402_ 0% 7U_0402_6 3V6K
2
@EMI@ 2 2
R8204
C8 62
R C U_ S4 2 EN5 680 _0603_50V8 @ R8205
2
0_0402_5%
2
0_0402_5%
@
AS G AVG
HIS SHEE O ENGINEERING DRAW NG IS HE RO R E AR RO ER O COM A E EC RONICS INC AND CON A NS CON IDEN IA
RT3607CE
Size Document Numbe ev
WWW.AliSaler.Com
AND RADE SECRE IN ORMA ON HIS SHEE MA NO BE RANS ERED ROM HE CUS OD O HE COM E EN DIVISION O R&D
DE AR MEN EXCE AS AU HORIZED B COM A E EC RON CS NC NEI HER H S SHEE NOR HE N ORMA ION I CON AINS Cus m A
MA BE USED B OR D SC OSED O AN HIRD AR WI HOU RIOR WRI EN CONSEN O COM A E EC RONICS INC
Da e uesday eb ua y 3 20 8 Sheet 60 o 73
5 4 3 2
5 4 3 2
PR902 and PR904 pull high resistor are pop at the end of VR SVID.
+1.05V_VCCST Other VR is unpop.
SVID_ALERT# pull high resistor is at HW side.
1
Confirm HW side
Don't double pull high @ PR8302 +1.05V_VCCST confirm with power sequence,
D
it need behind +5VS. D
1K_0 02_5%
2
< 3> VR2_HOT#
100_0 02_1%
0.1U_0 02_25V6
0. 7U_0 02_6.3V6K
1
PC8303
PR8303
PR830
VREF_VCCSA
1
PC8302
5.3_0 02_1%
2
1 K_0 02_1% 30.9K_0 02_1%
2
1
VR_HOT# 90 degreeC PR8306
PR8305
9 9_0 02_1%
ALERT# 87.3 degreeC
1
1 2
CPU_SVID_CLK_R <11,60>
PR8307
PH8302 @ PR8308
2
100K_0 02_1%_B25/50 250K 1_0 02_1% 0_0 02_5%
1 2 1 2
CPU_SVID_ALERT#_R <11,60>
2
1
PR8309
59K_0 02_1%
PR8311
1
10_0 02_1% Choke 7x7x4 7x7x3
1 2
PR8310
PR8313 CPU_SVID_DAT_R <11,60> Size and DCR 0.67m +-5%0.9m +-5%
1
10K_0 02_1%
8.7K_0 02_1%
2
TSEN_VCCSA_R
2 1 2 1 +19VB_CPU
PR8312
7.32K_0 02_1%
2
1
PR831 PR813 68 1K 73 2K
PR8315
Vboot=0V 200_0 02_1% IMON
1
VREF_VCCSA
2200P_0 02_50V7K
PR841 0 1 1K
2. K_0 02_1%
PR8316
EMI@ PC8308
10U_0805_25V6K
10U_0805_25V6K
0.1U_0 02_25V6
1
@EMI@ PC8307
2
1
ALERT#_VCCSA
PC8305
PR832 10K
PC830
TSEN_VCCSA
VREF_VCCSA
VCLK_VCCSA
IMON_VCCSA
SDIO_VCCSA
22K_0 02_1%
3.6K_0 02_1%
COMP
22.6K_0 02_1%
2
1
1
2K_0 02_1%
@ PC8306 PR833 40.2K 37.4K
2
1
1
+19VB_CPU
PR8318
PR8317
PR8319
PR8320
0.1U_0 02_25V6 PR8321 EN: high > 0.7V, Low < 0.3V
2
0_0 02_5% PR828 604 665
VCCSA_VR_EN 1 2
VR_ON < 3,51,59,60>
2
PR8322 ISEN PR830 243 549
2
1
SET1 connect to 5V is into test mode. 2.2_0805_1%
16
18
17
2
0_0 02_5%
120_0 02_1%
1
PR8326
300_0 02_1%
VRHOT#
VCLK
VD O
ALERT#
TSEN
IMON
VREF
EN
UG_VCCSA
PR8325
PC8309 PR8301
PR832
C C
0.22U_0 02_25V6K 2.2_0603_5% PH802 10K(3370K) 1K(3650K)
2
1 2 13 BOOST_VCCSA 1 2BOOST_VCCSA_R
@ VIN
2
PSYS_VCCSA 19 PU8301
0.22U_0 02_16V7K
PSYS
3
SET1_VCCSA
PC8301
RT3601EAGQW_WQFN28_ X
SE 2_ CCSA PL8301 +VCC_SA
G1
D1
D1
D1
SET3_VCCSA 0.2 UH_22A_20%_ 7X7X3_M
7.68K_0 02_1%
2
28
PR8329
100_0 02_1% 1.78K_0 02_1%
1
27 D2/S1 D1
PR8327
PR8328
SET2 1 A SP1_R 2 3
26 PWM PQ8301
Local sense, for debug only.
G2
S2
S2
S2
1
SET3 AONH3633 _DFN3X3A8-10
.7_1206_5%
Trace is form output cap that is near choke.
1 2
1 2
1 2
1
11 LG_VCCSA
@EMI@ PR8330
PR8331
5
LGATE
2.2K_0 02_1%
10 LX_VCCSA
PR8332
PR8333
576_0603_1% PC8310
PR833
2
100_0 02_1% VSEN_VCCSA 25 9 UG_VCCSA 1 2
1 SNUB_VCCSA 2
2 1 VSEN UGATE PR8336 PR8337
+VCC_SA
2
@ PR83 0
AVcore1_VCCSA
0_0201_5%
2 1 1 2AVcore1_NTC_R
1 2
680P_0 02_50V7K
<13> VCCSA_SENSE
AISP1_VCCSA
COMP_VCCSA 23
COMP
PC8311
@ PR8339 @ PR83 1 @ PR83 2 PR83 3 PR83 PR83 5
0_0 02_5% 0_0 02_5% 10K_0 02_1% 300_0 02_1% 7 5K_0 02_1% FB_VCCSA 2 PH8301
0_0 02_5% 2 1 2 1 2 1 2 1 2 1 FB 10K_0 02_1%_B25/50 3370K
2
29
GND
1
RGND_VCCSA
@EMI@
PC8312 PC831 22
@ PC8313 330P_0 02_50V8J 100P_0 02_50V8J RGND
For NTC trace routing only.
0.1U_0 02_25V6 2 1 1 2
VR_READY
2
ISEN1N
ISEN1P
DRVEN
1
PVCC
VCC
@ PC8315
0.1U_0 02_25V6
2
VCC_VCCSA1
12
15
21
20
B B
2 1
<13> VSSSA_SENSE
@ PR83 6
+5VALW
1U_0201_6.3V6K
1
AISP1_VCCSA
PC8317
100_0 02_1%
0.1U_0 02_25V6
2
2
1
AVcore1_VCCSA
PR83 8
0.1U_0 02_25V6
2
1
22_0 02_1%
1
PR83 9
PC8319
2.2U_0603_10V6K
2
2
2
+5VALW
VCCSENSE and VSSSENSE need have
a 100ohm at HW Side
A A
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT3601EA VCC SA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ON IT CONTAINS Cust m 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, Feb uary 13, 2018 Sheet 61 of 73
5 4 3 2
A
B
C
D
2 1 2 1 2 1 2 1 2 1 2 1 2 1 +VCC_CORE
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1
5
5
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
WWW.AliSaler.Com
@ PC9147 PC9132 PC9122 PC9075 PC9047 PC9017 PC9155
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
24 X 1uF_0201
2 1 2 1 2 1 2 1
+VCC_GT
2 1 2 1 2 1 2 1
23 +10 X 22uF_0603_X5R
2 1 2 1 2 1 2 1
2
1
+
2 1 2 1 2 1 2 1 PC9007
220U_D2_2V_Y
@ PC9102 PC9081 PC9053 PC9023
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
3
3
2 1 2 1 2 1 2 1
2 1 2 1 2 1 2 1
2 X 330uF
Issued Date
2 1 2 1 2 1 2 1
Security Classification
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
5+13 X 22uF_0603_X5R
2 1 2 1 2 1 2 1
NA
2
2
2 1 2 1
@
PC9108 PC9087
22U_0603_6.3V6M 22U_0603_6.3V6M
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 2 1 2 1
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D
1 X 1uF_0201
2 1 2 1 2 1
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
@
2 1 2 1 2 1
2 1 2 1 2 1
Custom
2 1 2 1 2 1
Sheet
62
of
Compal Electronics, Inc.
73
R ev
1.A
A
B
C
D
A B C D E
@ PJ1701 +19VB_GPU
JUMP_43X79
+19VB_1.35VSDGPUP 1 2
+5VALW 1 2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
EMI@ PC1703
0.1U_0402_25V6
1
1
EMI@ PC1702
PC1704
PC1705
2
PR1701
AON6962 2N DFN5X6D
1 1
2
2.2_0603_5%
1
RT8812_PVCC
PQ1701
Choke 1uH SH00000YE00 (Common Part)
PC1701
(Size:7.6 x 6.6 x 3 mm)
1
2.2U_0603_16V6K
2
PC1706 (DCR:6.7m~7.4m)
D1
G1
1 1.35VSDGPUP_TON_R
2 PL1701
+1.35VSDGPU
18
Frequency PU1701 1UH_11A_20%_7X7X3_M
0.1U_0402_25V6 7 1 2
PVCC
PR1702 PR1703 D2/S1
1
+19VB_1.35VSDGPUP 2.2_0402_1% 383K_0402_1%
2 1 2 1 1.35VSDGPUP_TON 9 2 HGATE1_1.35VSDGPUP
G2
S2
S2
S2
TON UGATE1
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
PC1707 PR1704 EMI@
PR1705 PR1706 2.2_0603_1% 0.22U_0603_25V7K 4.7_1206_5% 1 1 1
6
2 1 13 1 BST1_1.35VSDGPUP 2 1 BST1_1.35VSDGPUP_R 2 1
+3VS
1 2
PGOOD BOOT1
PC1709
PC1710
PC1722
+ + +
10K_0402_5% PC1708 EMI@
<36> 1.35VSDGPU_PG 1.35VSDGPU_EN_R 3 20 LX1_1.35VSDGPUP 680P_0402_50V7K
EN PHASE1 2 2 2
2
@ PR1707 @
1 2 4 19 LGATE1_1.35VSDGPUP
+3VS PSI LGATE1
1
PR1709
10U_0805_25V6K
10U_0805_25V6K
@ PR1708 PC1711 2 1
0_0402_5% 100K_0402_5% 8.25K_0402_1%
2
<26,36> 1.35VSDGPU_EN
1
PC1712
PC1713
1 2 0.1U_0402_25V6 IOCP Common part
PR1710 5 14 HGATE2_1.35VSDGPUP
AON6962 2N DFN5X6D
SGA0000BT00
1K_0402_1% 1 VID UGATE2 PC1714
2
PR1711 2.2_0603_1% 0.22U_0603_25V7K
1.35VSDGPUP_VREF BST2_1.35VSDGPUP 1 BST2_1.35VSDGPUP_R
2 8
VREF BOOT2
15 2 2 1
2
1
@ PR1721 7 16 LX2_1.35VSDGPUP
R1 REFIN PHASE2
PQ1702
49.9_0402_1% Choke 1uH SH00000YE00 (Common Part)
PR1712
(Size:7.6 x 6.6 x 3 mm)
1
6 17 LGATE2_1.35VSDGPUP
10K_0402_1%
1 2
D1
G1
2
D2/S1
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
1
21 10
GND RGND
G2
R2
S2
S2
S2
1
1
PC1715
PC1718
PR1714 EMI@
PC1716
1
@ 4.7_1206_5%
6
P5@ PR1722 PR1715 PC1717 RT8812AGQW-GP PR1716
2
1 2
0_0402_5%
30.9K_0402_1% 35.7K_0402_1% 47P_0402_50V8J 0_0402_5%
OPS
2
PR1717
P55@ PC1719 EMI@
2
680P_0402_50V7K
2
1
52.3K 0402_1%
2
1
68.1K_0402_1%
P5@ PR1723
PR1718
PC1015.2的GND
單單 單 vi a 下下 <31> FB_VDDQ_SENSE
+1.35VSDGPUP
Vout = 1.35V
3 TDC = 16.9A 3
Peak Current = 24.2A
R1 R2 R3 Vout OCP=36.3A
3
Hynix@ Samsung@
PQ1703B
FSW=400kHz
DMN53D0LDW-7 2N SOT363-6
PR1719
2 1 5 10 35.7 NA 1.55 0.8% DaulMOS AON6992 TYP MAX
+3VALW
10 35.7 52.3 1.352 0.7% H/S Rds(on) = 6.8mohm ,8.6mohm
10K_0402_5%
4
6
PR1720 Micron@
<26> MEM_VDD_CTL
2 1 2 10 30.9 NA 1.5 0.7%
10 30.9 68.1 1.36 0.74%
1
0_0402_5%
1
0.1U_0402_25V6
PC1720
4 4
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENG NEER NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 63 of 73
A B C D E
@ PJ1802
JUMP_ 3X79
1 2
+1.0VSDGPUP 1 2 +1.0VSDGPU
1 1
PC1802
68P_0 02_50V8J
PR1801 6 1 EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
1 2 FB EN PR1802
+3VALW
1
10K_0 02_5% .7_0603_5%
PC1803
@ PC1805
VFB=0.6V
PC180
PR180 PR1803
2
0_0 02_5% 13.7K_0 02_1% Vout=0.6V* (1+Rup/Rdown)
2
2 1 1VSDGPU_EN_R
<26,36> 1VSDGPU_EN =0.6V* (1+13.7/20)
2
SNUB_1.0VSDGPUP
Vout=1.011V
1
FB_1.0VSDGPUP
PR1805 PC1806
1M_0 02_1% 0.1U_0 02_16V7K
Rdown
1
2
PR1806
1
EMI@ 20K_0 02_1%
PC1807
2
680P_0 02_50V7K
2
Note:
When design Vin=5V, please stuff snubber
2 2
to prevent Vin damage
3 3
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc
Issued Date Deciphered Date
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
1.05VSDGPU
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTA NS C 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 6 of 73
A B C D E
5 4 3 2 1
1
1 2
0_0402_5%
PR1202
PR1203
PR1204
20K_0402_1%
20K_0402_1%
20K_0402_1%
2
0.1U_0402_25V6
PR1205
PC1202
2
layout
l 上 :
2
1
91K_0402_1%
請 將 Tota l DC R sensin
in g 的 compon
o en t
PR1206
@ @
1
PR1201 放 靠 近 Control
on le r .
22.1K_0402_1%
PR1207 for OCP setting
1
NTC_La NTC_Lb
2
D D
PR1207
10K_0402_5% @PR1208 @PR1209
2 1 1 2 1 2 2 1 NVVDD_ISUMN1 <66>
PR1210 1_0402_1%
0_0402_5% 0_0402_5%
2 1
2
NVVDD_ISUMN2 <66>
PC1203 PC1217 1 2 PR1211 1_0402_1%
0.01U_0402_16V7K @ 0.1U_0402_25V6 @ PR1212 0_0402_5% 2 1 NVVDD_ISUMN3 <67>
1 2 1 2 PR1213 1_0402_1%
1 2
For N17E-G1, TDP 60.2W
2 1 2 1
@ PC1204 0.1U_0402_25V6
PR1214 PR1215 1 2 NVVDD1
0_0402_5% 0_0402_5%
TDC = 60A
2
1 2 2 1 @ PC1205 0.1U_0402_25V6 NTC_La NTC_Lb
PC1206 PR1216 PR1217 1 2 Peak Current = 127A
GPU_PROG5
GPU_PROG1
GPU_PROG2
PR1218 PH1201
0.015U_0402_16V7K 2.4K_0402_1% 0_0402_5% @ OCP = 165A
1 2 1 2 PC1207 0.1U_0402_10V6K 1 2
Close to PU1201
EAP 1
VINMON
@ PC1208 2 1 470K_0402_5%_B25/50 4700K
COMP
0_0402_5% 0_0402_5% 0.1U_0402_25V6 PR1219 1K_0402_1%
PR1220
2
<31> NVVDD1_VCC_SENSE
0_0402_5%
PR1221
SS
Close to PL1301
1
1 2
CSNSUM
CSPSUM
PC1209
0.1U_0402_10V6K
2
+NVVDD1
2 1 @
1
PR1222
layout
a 上 : 請 將 RSE
R N1N ~4
100_0402_5% PR1262 放 靠 近 C o n t r o l l e r..
@ 0_0402_5% @ PC1212
24
23
22
21
20
19
18
17
33
1 2 1 2
0.1U_0402_25V6
PC1211
C C
LDO_VIN
MUX_CTRL
FBA
LDO_OUT
S5_OUT
VSEN_NB_IN
VDDIO
SVT
EPAD
2
0.1U_0402_25V6
2 1 25 16
PR1223 BOOT SVD
1
PR1224 @ 1K_0402_1% 26 15
GPU_PROG6
<31> NVVDD1_VSS_SENSE 0_0402_5% FBRTN UGATE SVC
1 2 27 14 PR1225 2.2K_0402_1%
GPU_PROG3 PHASE PW ROK ISEN1 2 1 GPU_PH1
2 1 28 PU1201 13 PR1226 2.2K_0402_1%
PR1228 GPU_PROG4 PVCC UP9511QQKI_WQFN32_4X4 VCC ISEN2 2 1 GPU_PH2
100_0402_5% 29 12 PR1227 2K_0402_1%
FBRTN GPU_LPC LGATE VREF_PINSET ISEN3 2 1 GPU_PH3
Fsw=300kHz
30 11 PR1264 100K_0402_5%
1 2 NVVDD1_ENP NC IMON ISEN4 2 1
+3VALW 5VCC
PR1263 31 10
PGOOD SET1
1
GPU_PSI 5VCC
30K_0402_5%
10K_0402_5%
PR1230
32 9
VRHOT_L
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
ISEN1N
ISEN1P
COMP
RGND
請 教 A U TO
VSEN
5VCC 2 1
6
2
VIN
33K_0402_5%
FB
PWM1
PHASE的
H 的 設 定
2
PHASE
1U_0402_6.3V6K
PQ1201A
PQ1201B
PR1234
1
PC1214
<26,36> NVVDD1 EN
8
2 5
1
@ PR1232 GPU_VID
1
PWM2
+3VS REFADJ
1
6.19K_0402_1%
PR1236
B R1 B
REFIN
@ PR1233 0_0402_5%
GPU_PROG6
2
43K_0402_5%
36K_0402_5%
100K_0402_5%
100K_0402_5%
51K_0402_5%
10K_0402_5%
2 1 PR1245 0_0402_5%
+1.8VS R3 GPU_PWM2 <66>
PR1242
PR1246
PR1243
PR1247
PR1244
PR1248
2 1
PWM3
2
PR1241
NVVDD1_PSI <26,68> @ PR1235 0_0402_5% 2 1
2 1 PR1250 0_0402_5%
1
1
2 1 GPU_PWM3 <67>
309_0402_1% 16.5K_0402_1%
4.32K_0402_1% @
PR1249
GPU_PROG1
GPU_PROG2
GPU_PROG3
GPU_PROG4
GPU_PROG5
1 2
R4
GPU_LPC
@
PR1237 0_0402_5%
2
PR1238
100K_0402_5%
1
+3VS 1 2
PR1256
R5
0_0402_5%
8.2K_0402_5%
8.2K_0402_5%
0_0402_5%
PR1251
PR1252
PR1255
PR1257
<26,36> NVVDD1_PG R2PR1258
2
2 1
1
4700P_0402_50V7K
20.5K_0402_1% @
1
1
PC1215
@
0.01U_0402_16V
@
PR1240 C
2
2
PC1216
1 2
<26> NVVDD1_VID
1
0_0402_5%
FBRTN
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR VGA UP9511P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 65 of 73
5 4 3 2 1
1 2 3 4 5
+19VB +19VB_GPU
EMI@ PL1303
PR1301 PR1302
FBMA-L11-201209-800LMA50T
1 2 1 4 1 4 +19VB_NVVDD
EMI@ PL1304 2 3 2 3
FBMA-L11-201209-800LMA50T
NVVDD (NVVDD1)
1 2
0.005_1206_1% 0.005_1206_1%
Vboot=0.8V
TDC=60A
Peak Current=127A
A
OCP=165A A
+5VS
FSW=300kHz
Dr.MOS SIC632 TYP MAX
0_0402_5%
@ PR1303
<36> CSSP_B+ <36> CSSN_B+ CSSP_NVVDD <36><36> CSSN_NVVDD H/S Rds(on) = 4.8mohm ,5.76mohm
+5VS L/S Rds(on) = 1.3mohm ,1.56mohm
1
PR1304
10K_0402_1%
PR1305 PU1301 1 2
1K_0402_1% 1 28
<65> GPU_PWM1 2 1 2 PW M CGND 27
+5VS 3 ZCD_EN# GL 26 PR1307
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1306
5 24 2 1
6 BOOT VDRV 23
PR1308 NC PGND Choke 0.22uH SH00000QZ00
1
1U_0603_16V7
PC1302
7 22
PHASE GL
1
1U_0603_16V7
PC1304
1 2 8 21
1
9 VIN SW 20 GPU_PH1
2
2
0_0402_5% 1 2 11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 12 SW SW 17 GPU_PH1 1 4
0.1U_0603_25V7K 13 SW SW 16
14 SW SW 15 2 3
SW SW
SIC632CDT1GE3_POWERPAK31_5X5
PC1306
PC1307
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
1
1
PC1308
PC1309
PC1310
PC1311
B EMI@ B
1
PC1327
PC1326
PR1309
4.7_1206_5%
2
2
@EMI@
EMI@
2
<65> NVVDD_ISUMP1
2
@
GPU_SNB1
<65> NVVDD_ISUMN1
1
EMI@
PC1312
680P_0402_50V7K
2
+5VS
2
0_0402_5%
@ PR1310
+5VS
1
PR1311
PR1312 PU1302 1 2
C C
1K_0402_1% 1 28
<65> GPU_PWM2 2 1 2 PW M CGND 27 10K_0402_1%
+5VS 3 ZCD_EN# GL 26 PR1314
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1313
5 24 2 1
PR1315 BOOT VDRV
6 23 Choke 0.36uH SH00000R500
NC PGND
1
1U_0603_16V7
PC1313
1 2 7 22
PHASE GL (Size:13.5 x 12.5 x 2.8 mm)
1
1U_0603_16V7
PC1315
8 21
1
2
11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 0.1U_0603_25V7K 12 SW SW 17 GPU_PH2 1 4
13 SW SW 16
14 SW SW 15 2 3
SW SW
1
SIC632CDT1GE3_POWERPAK31_5X5 EMI@
PC1318
PC1319
2200P_0402_50V7K
PR1316
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
4.7_1206_5%
1
1
PC1322
PC1323
<65> NVVDD_ISUMP2
2
2
GPU_SNB2
@EMI@
EMI@
1
EMI@
PC1324
680P_0402_50V7K
2
<65> NVVDD_ISUMN2
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +NVVDD1
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 66 of 73
1 2 3 4 5
5 4 3 2 1
+5VS
D D
0_0402_5%
@ PR1351
1 +5VS
PR1352
10K_0402_1%
PR1353 PU1351 1 2
1K_0402_1% 1 28
<65> GPU_PWM3 2 1 2 PW M CGND 27
+5VS 3 ZCD_EN# GL 26 PR1355
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
CGND THW n
@ PR1354
5 24 2 1
PR1356 BOOT VDRV
6 23
NC PGND
1
1U_0603_16V7
PC1352
1 2 7 22
PHASE GL
1
1U_0603_16V7
PC1354
8 21
1
2
11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +NVVDD1
+19VB_NVVDD 0.1U_0603_25V7K 12 SW SW 17 GPU_PH3 1 4
13 SW SW 16
14 SW SW 15 2 3
SW SW
SIC632CDT1GE3_POWERPAK31_5X5
PC1356
PC1357
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
1
EMI@
1
1
PC1358
PC1359
PC1360
PC1361
PR1357
4.7_1206_5%
C C
2
2
@EMI@
EMI@
2
@ @ <65> NVVDD_ISUMP3
GPU_SNB3
1
EMI@ <65> NVVDD_ISUMN3
PC1362
680P_0402_50V7K
2
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +NVVDD1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 67 of 73
5 4 3 2 1
1 2 3 5
A A
1 2
3VS 5VS
.7U_0 02_6.3V6M
PR1 01 1
2.2_0603_1%
PC1 01
2
@ PR1 30 2 19VB_GPU
2
30K_0 02_5%
@ PR1 31
NVVDDS_LG1 PR1 02
30K_0 02_1%
1
1 4 19VB_NVVDDS
PR1 0 NVVDDS_SW1
1
100K_0 02_1% 2 3
2 1 PC1 08
1
0 22U_0603_25V7K PU1 01 RT@
RT8816AGQW_WQFN20_3X3 0.005_1206_1%
2 2
3VS
21
20
19
18
17
16
UPI@
PR1 05 PU1 01
PHASE1
LGATE1
LGATE2
PHASE2
TPAD
PVCC
2.2_0603_1% UP1666QQKF_WQFN20_3X3
<26,36> NVVDD2_EN
2
1.8VS <36> CSSP_NVVDDS <36> CSSN_NVVDDS
PR1 07
1
NVVDDS_BST1 1 15
BOOT1 BOOT2 10K_0 02_5%
1
0.1U_0 02_25V6
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
2200P_0 02_50V7K
PR1 06 NVVDDS_HG1 2 14
EMI@ PC1 05
1
@EMI@ PC1 0
1
20K_0 02_1% UGATE1 UGATE2
PC1 06
PC1 07
PC1 16
PC1 17
GND
NVVDD2_EN 3 13 NVVDD2_PG <26,36>
PR1 09 EN PGOOD UPI@ PR1 10 UPI@ PC1 09
2
2
1 2 NVVDD2_PSI_R 4 12 NVVDDS_COMP
2 1 2 1
PR1 11 PSI COMP
,65> NVVDD1_PSI
2
NVVDDS_HG1
REFADJ
OCS/CB
2 1 1 2
FBRTN
<26> NVVDD2_VID
REFIN
0_0 02_5%
VREF
Avoid high dV/dt RT@ PR1 32 93.1K_0 02_1%
1
0_0603_5% @
PIN12
2
B PQ1 01 PQ1 02 B
10
RT:93.1K OCP=37A
G1
D1
G1
D1
NVVDD2
OCP=[[(10uA*93.1k)/12/2.5m]+(12A/2)]*1phase=37A
AON6962_DFN5X6D-8-7
AON6962_DFN5X6D-8-7
NVVDDS_VREF
NVVDDS_SW1 7 7
D2/S1 D2/S1
2
NVVDDS_VIDBUF
PR1 13 @ Choke 0.22uH SH000011H00
9.9_0603_1%
G2
G2
S2
S2
S2
S2
S2
S2
(Size:7*7*4 mm)
2
@
PR1 1 DCR 0.97
2 1
3
0_0 02_5%
PL1 01
R1 R3 R4
1
PC1 12 @ 1 2
1500P_0 02_50V7K
1
PR1 15
PR1 17
7P_0 02_50V8J
6.19K_0 02_1%
.32K_0 02_1%
16.5K_0 02_1%
1
1
1 2 NVVDDS_LG1
PR1 16
2
UPI@ PR1 18
2
1
100K_0 02_5% EMI@
1
1
@ @ RT@ @ PR1 08
RT@ PR1 20 PR1 21 PR1 33
R5 .7_1206_5%
1
PR1 3 0_0 02_5% 0_0 02_5% 2.2_0805_5%
1
32K_0 02_1%
309_0 02_1%
2
PR1 22
2
NVVDDS_SNB1
RT@ PC1 18
1
1
1U_0603_25V6K PR1 23 100_0 02_5% EMI@
2
2 1 NVVDD2 PC1 11
R2 680P_0 02_50V7K
2
2
OCP & FS setting
2 1 NVVDD2_VCC_SENSE <31>
PR1 2 20.5K_0 02_1% Avoid high dV/dt
C
700P_0 02_50V7K
NVVDD2_VSS_SENSE <31>
1
0.01U_0 02_16V 2 1
2
C
Vboot=0.8V C
TDC=18A
Close to PU1201 Peak Current=30.7A
PIN9 OCP=37A
UPI:OCP & FS setting FSW=350kHz
RT:Switching frequency setting:(Ton pin) DaulMOS AON6962 TYP MAX
Fsw=(Vin-0.5)/(2*Vin*432K*3.2p) H/S Rds(on) = 6.8mohm ,8.6mohm
=352Khz L/S Rds(on) = 2.0mohm ,2.5mohm
D D
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONFIDENTIAL
PWR +NVVDD2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTA NS 1.A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date: Tuesday, February 13, 2018 Sheet 68 of 73
1 2 3 5
D
1.A
22uF_0603 X 2 (unpop 2)
22uF_0603 X 4 (unpop 2)
Rev
4.7uF_0603 X 2
47uF_0805 X 1
22uF_0603 X 2
10uF_0603 X 4
1uF_0402 X 16
73
220uF X 2
560uF X 1
of
Compal Electronics, Inc.
+NVVDD2
69
47uF_0805 X 1
10uF_0603 X 4
1uF_0402 X 16
10uF_0603 X 4
1uF_0402 X 16
220uF X 2
560uF X 1
560uF X 1
1
1
+NVVDD2
+NVVDD2
PC1609
1U_0402_6.3V6K
Tuesday February 13 2018
1 2 PC1629
PC1608 22U_0603_6.3V6M
1U_0402_6.3V6K
1 2
Document Number
1 2 PC1625
PC1607 PC1616 22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K
1 2
1 2 1 2
PC1606 PC1615 PC1624
1U_0402_6.3V6K 1U_0402_6.3V6K 22U_0603_6.3V6M
@
1 2 1 2 1 2
Title
Date
Size
1 2 1 2 1 2
PC1604 PC1613 PC1622
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
220U_D2 SX_2VY_R9M 1 2 1 2 1 2
PC1626
PC1603 PC1612 PC1621
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1 2 1 2 1 2
2017/01/06
220U_D2 SX_2VY_R9M
PC1602 PC1611 PC1620
PC1627
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
+
1
2
SGA0000BT00
Common part
1 2 1 2 1 2
220U_D2 SX_2VY_R9M
PC1601 PC1610 PC1619
PC1628
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2
+NVVDD2
+NVVDD2
Deciphered Date
Compal Secret Data
10uF_0603X 11(unpop 5)
10uF_0603X 11(unpop 5)
4.7uF_0603 X 9
47uF_0805 X 2
22uF_0603 X 4
10uF_0603X 23
1uF_0402 X 49
47uF_0805 X 2
22uF_0603 X 4
1uF_0402 X 49
22uF_0603 X 8
1uF_0402 X 49
2016/11/03
220uF X 4
560uF X 3
220uF X 4
560uF X 3
220uF X 4
330uF X 2
560uF X 1
+NVVDD1
+NVVDD1
+NVVDD1
3
3
Security Classification
Issued Date
PC1515 PC1530 PC1543 PC1575
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2 1 2 22U_0603_6.3V6M 1 2
PC1557
PC1514 PC1529 PC1545 PC1574
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
2 1
1 2 1 2 1 2 22U_0603_6.3V6M 1 2
PC1556
PC1513 PC1528 PC1544 PC1573
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1 2
1 2 1 2 1 2 1 2
PC1512 PC1527 PC1542 PC1572
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1547
1 2 1 2 1 2 1 2
PC1511 PC1526 PC1541 2 1 PC1571
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
PC1555
1 2 1 2 1 2 1 2
PC1510 PC1525 PC1540 2 1 PC1570
220U_D2 SX_2VY_R9M
SF-OS CON Cap Common
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
4
4
PC1592 PC1554
1 2 1 2 1 2 1 2
+
1
PC1593
1 2 1 2 1 2 1 2
PC1507 PC1522 PC1537 2 1 PC1567
+
1
22U_0603_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
330U_2.5V_ESR17M_6.3X4.5 PC1546
PC1594 1 2 1 2 1 2 1 2
PC1506 PC1521 PC1536 1 2 PC1566
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2 1 2
PC1505 PC1520 PC1535 PC1565 PC1580
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1504 PC1519 PC1534 PC1551 PC1579
PC1591
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1503 PC1518 PC1533 PC1550 PC1578
SGA0000BT00
Common part
PC1590
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
+
1
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1502 PC1517 PC1532 PC1549 PC1577
PC1589
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
5
5
+
1
2
1 2 1 2 1 2 1 2 1 2
@
220U_D2 SX_2VY_R9M
PC1501 PC1516 PC1531 PC1548 PC1576
PC1588
+ 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M
1
2
1 2 1 2 1 2 1 2 1 2
@
+NVVDD1
+NVVDD1
D
A
5 3 2 1
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
PR1301,PR1302,PR1402: 0.005_2512_1%SD000016U00->0.005_1206_1%SD000017R00
PC1410: 0.1U_0603_16VSE026104K80->Del
PR1432: Add->93.1K_0402_1%SD034931280
02 PR1410: 51.1K_0402_1%SD034511280->un pop
PC1409: 1000P_0402_25V8JSE068102J80->un pop
Down Size & NVVDDS IC COLAY 0.1 PU1401: UP1666QQKF_WQFN20_3X3SA00009SX00 -> RT8816AGQW_WQFN20_3X3 SA00009WE00
PR1414: 10K_0402_5%SD028100280->0_0402_5%SD028000080 10/26 A
PR1418: 45.3K_0402_1%SD034453280->un pop
PR1419: 84.5K_0402_1%SD034845280->Del
PR1433: Add->2.2_0805_5%SD002220B80
PC1418: Add->1U_0603_25V6KSE000006900
PR1434: Add->432K_0402_1%SD034432380
C PC8134: 0.1U 0402 50V7KSE074104K80->0.1U 0402 25V6SE00000G880 C
PR8331 _470_0603_1%_SD014470080_->_576_0603_1%_SD014576080
PR8336 _42.2_0402_1%_SD00000ZN00_->_255_0402_1% _SD034255080
PC9110 PC9108 _22U_0603_6.3V6M_SE00000M000_->_unpop
PC9112 PC9113_unpop _->_22U_0603_6.3V6M_SE00000M000
PC8126,PC8137 _330P_0402_25V8J_SE00000FD80_->_330P_0402_50V8J_SE000006I80
PR8134 _121K_0402_1%_SD034121380_->_13.3K_0402_1%_SD034133280
PR8138 _49.9K_0402_1%_SD034499280_->_26.7K_0402_1%_SD034267280
PR8147 _3.32K_0402_1%_SD034332180_->_768_0402_1% _SD00000TT80
PR8173 _0_0603_5%_SD013000080_->_10_0603_1%_SD014100A80
PU1201 _UP9511PQGJ_VQFN40_5X5_SA00009SW00_->_UPI9511QQKI WQFN 32P _SA0000BK300
down size &CHANGE VGA IC PC8317,PC509,PC517_1U_0402_10V6K_SE00000QL10_->_1U 6.3V K X5R 0201_SE00000YB00 11/08 A
04 0.2
PC8112,PC8115,PC8123,PC8139,PC8157,PC8161_1U_0402_25V6K_SE000010V00_->_1U 6 3V K X5R 0201_SE00000YB00
PQ307_ LMUN5113T1G PNP SOT323-3_SB000013X00_->_Unpop
Unpop reduce charger IC loss extra circuit. PQ308 _ LMUN5236T1G NPN SOT323-3_SB000011K00_->_Unpop
Unpop GPIO12& PROCHOT synchronous 0.2 PQ313 _2N7002KDW 2N SOT-363-6_SB00000EO00_->_Unpop
05 11/15 A
circuit. PQ314_RUM001L02 1N VMT3_SB000012900_->_Unpop
PR340 _10K_0402_1%_SD034100280_->_Unpop
A
PR327 _0_0603_5%_SD013000080_->_Unpop A
PR326 _0_0603_5%_SD013000080_->_SMT
PR310 _51.1K_0402_1%_SD034511280_->_52.3K_0402_1%_SD034523280
PC1709 _220U_D2 SX_2VY_R9M _SGA0000BT00_->_Unpop
PC8147 _10U 0805 25V6K SE00000QK00 -> Unpop
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
PIR
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS INC. AND CONTA NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON CS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 70 of 73
5 3 2 1
5 3 2 1
PQ307 _LMUN5113T1G_SOT323-3_SB000013X00_->del
03 PR327unpop_0_0603_5%_SD013000080_->del
1.0 PR342Add _->_2M_0402_1%_SD034200480 12/20 A.2
For 4S per cell 4.35V battery
PR343Add _100K_0402_1%_SD034100380
PQ315Add _2N7002KW_SOT323-3_SB00000ST00
B B
A A
Security Classification
2016/11/03
Compal Secret Data
2017/06/14 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS INC. AND CONTA NS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON CS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 71 of 73
5 3 2 1
A B C D E
Item Page Title Date Issue Description Solution Description Phase Rev.
1 46 USB 10/18 Correct USB charger connection. 1.Change RS15 connection to CHG_ILMSEL. DVT 0.2
1.Remove RPH10, add RH197,RH198.
1
2 19,36 Placement 10/18 Placement 2.UG27 source change to +1.8VALW for +1.8VSDGPU_AON/+1.8VSDGPU_MAIN. DVT 0.2 1
3 41 CNVI 10/18 For CNVI power rail. 1.Co-lay RM46 for CNVI +3VALW power rail. DVT 0.2
4 42 Material 10/18 X1 code issue. 1.LA1 change to SM01000NS00. DVT 0.2
5 48 USB 10/18 redriver verify. 1.Add one USB3.0 port to JIO3. DVT 0.2
1. Change RM36,RM37,RM42,RM43 to 0402 size.
2. Change RH186,RH47,RH98~RH100,RH103,RH105,RD2,RD3,RD6,RD13,RD15,RD17,RM34,RM35
6 Placement 10/21 Placement ,RM38,RM39,RS1,R19,R20,RQ5,RQ6,RQ9 to R-short. DVT 0.2
3. Change RS8,RS10 to 1206 R-short.
4. Change RH97 to 0805 R-short.
7 11 ESD cap. 10/21 Sourcer request. 1.Change CC66,CC68 to SE074102K80. DVT 0.2
8 43 EC 10/21 EC board ID. 1.Change RB3 to 12kohm/28P@ and 160kohm/32P@ DVT 0.2
2 1. Change CA6,CA8,CA9,CA12,CA14,CA16,CA19,CC71~CC81,CC88~CC90,CG130,CG131 2
10 50 Screw hole 10/25 Screw hole 1.Change H21 footprint to H_6P0. DVT 0.2
11 48 USB EMI 10/25 EMI issue. 1.Add LS11,LS12. DVT 0.2
12 41,43 CNVI 10/26 For CNVI power rail detect. 1.Add net CNVI_DET#,RB78,RB79. DVT 0.2
13 46 USB 10/26 Correct USB charger connection. 1.Correct USB2.0 connection for US12. DVT 0.2
14 42 DMIC 10/26 Acer request. 1.Change JDMIC1 from 8pin to 4pin. DVT 0.2
15 47 SATA 11/03 Co-layout. 1.Co-lay JHDD3,CO14~CO17,RO21~EO24. DVT 0.2
16 44 SMBus 11/08 Co-layout. 1.Co-lay RS114,RS115. DVT 0.2
3 3
17 49 SW 11/14 Remove debug SW. 1.De-pop SW1. DVT 0.2
18 44 Type-C 11/14 CC logic control by EC SMBus. 1.De-pop QS1,QS3,RS107,RS108,RS111. Pop RS114,RS115. DVT 0.2
19 16 Cap. 11/14 by crystal vendor test result. 1.Change CH7,CH8 to 10pF. DVT 0.2
20 45 Cap. 11/16 For shortage. 1.Change CS84~CS87 to SE00000G880. DVT 0.2
21 43 CNVI 11/16 CNVI detect by SW. 1.De-pop RB78. Pop RB79. DVT 0.2
22 43 CNVI 12/15 Remove CNVI detect. 1.Remove RB78, RB79 and netname CNVI_DET#. PVT 1.0
23 18 PECI 12/15 For PECI issue. 1.De-pop RH41. PVT 1.0
24 50 BI SW 12/15 By customer request. 1.De-pop SW2. PVT 1.0
25 43 EC 12/15 Update EC board ID. 1.Change RB3 to 15kohm/28P@ and 200kohm/32P@ PVT 1.0
26 42 Inductor 12/15 Change source. 1.Change LA1 to SM01000EE00. PVT 1.0
27 NPI 12/15 For NPI test. 1.Change RB19,RC17,RG143,RG200,RG202,RH101,RH102,RH5,RH6,RH92,RH93,RH94,RH96 PVT 1.0
,RM2,RS114,RS115,RB72,RB76,RL1,RL13,RQ2 to R-short.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2016/07/18 Deciphered Date 2016/11/10 T tle
PIR-HW1
WWW.AliSaler.Com
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 72 of 73
A B C D E
A B C D E
Item Page Title Date Issue Description Solution Description Phase Rev.
28 44 Type-C 12/18 Change current limit solution 1.Change US2 to SA00006Y700. PVT 1.0
2.Add RS116,RS117,RS118. Reserve CS101.
1 29 43 EC 12/20 For PWR BATT_4S 1.Add net BATT_4S to EC pin89. PVT 1.0 1
33 36 GPU 12/21 Fine tune GPU sequence 1.Change CG315 to 0.22uF, RG190 to 16.9k ohm, add RG225. PVT 1.0
34 20 12/28 For MB ID 1.De-pop RH86. Pop RH85,RH87. PVT 1.0
35 7,15 CPU,PCH 12/28 Update intel chip to QS PN 1.SA0000BPJ10 for i5@, SA0000BPI10 for i7@, SA0000BPF10 for PCH@. PVT 1.0
36 7 DAZ 12/28 Update MB DAZ PN. 1.DAZ29000100 for PCB@. PVT 1.0
37 37 eDP 12/28 For eDP sequence 1.Pop RX1. PVT 1.0
2 2
38 18,39 PCIE 01/11 For IRST support issue. 1.Change PCIE port17~20 to port 9~12 for PCIE SSD. PVT 1.C
2.Change SATA port0A to port4 for SATA HDD.
3.Change SSD_DEVSLP4 to SSD_DEVSLP1.
4.Change SATA_GP4 to SATA_GP1.
39 45 Type-C 01/11 For intel new topology 1.Place CS58~CS61 close to connector and change net name. PVT 1.C
40 43 EC 01/11 Update EC board ID. 1.Change RB3 to 20kohm/28P@ and 240kohm/32P@ PVT 1.C
41 21 PCH 01/12 For layout routing. 1.Change RH93 to 0ohm footprint. PVT 1.C
42 45 Type-C 01/16 For intel new topology 1.Change CS58~CS61 to 0.22uF. PVT 1.C
43 7 CPU,DAZ 01/27 Update CPU,DAZ PN 1.SA0000BPZ10 for i7@, DAZ29000103 for PCB@. PVT 1.C
44 7,15 CPU,PCH 02/13 Update CPU,PCH PN to MP PN. 1.SA0000BPJ40 for i5@,SA0000BPZ40 for i7@,SA0000BVP10 for PCH@. Pre-MP 1.C
3 3
THIS SHEET OF ENG NEERING DRAW NG IS THE PROPR ETARY PROPERTY OF COMPAL ELECTRONICS, NC. AND CONTAINS CONF DENTIAL
PIR-HW2
AND TRADE SECRET INFORMATION. TH S SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIV SION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.A
MAY BE USED BY OR D SCLOSED TO ANY TH RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH53F M/B LA-F991P
Date Tuesday February 13 2018 Sheet 73 of 73
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