Slide JNT

Junctionless Nanowire Transistors
Performance: Static and Dynamic

Modeling
Marcelo Antonio Pavanello
pavanello@fei.edu.br
Department of Electrical Engineering

Centro Universitario FEI
Av. Humberto de Alencar Castelo Branco, 3972
09850-901 – São Bernardo do Campo, Brazil
MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br 1

Outline
Introduction & Motivation
The Junctionless Nanowire Transistor
Compact Modeling
Static Drain Current Model
Dynamic Model
Conclusion
MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

Outline
Compact Modeling
Dynamic Model
Conclusion

Moore’s Law: The number of devices per chip double each
two years

Reduction on cost/function
Performance improvement
Scaling
Active Area
Gate Field
Spacers
Ge/IIIV
ArF + RET FinFET
metal gate
ArF immersion HfO2
25 nm high -k
NiSi
NiSi
L=35nm
FUSI
SiGe
strain
hyper NA
immersion
USJ
silicide EUVL
time
Courtesy of Prof. Cor Claeys

Evolution of Transistors
“Gate-all-Around”
“3 Gates”
“2 Gates”
Gate Source
“1 Gate”
Drain
ID
Buried oxide
Gate Polysilicon Gate
Source Drain Silicon

Fin
Gate
Gate
BOX
20 nm Buried Oxide
Gate
Tri-Gate with 800C 600Torr 5min H2Anneal
Source
Buried oxide
Drain
Courtesy Dr. Jean-Pierre Colinge
Fins are 45x78nm, Nice corner rounding by H2 anneal
MOS-AK Workshop, ESSDERC, Leuven, 2017

Back gate (substrate) www.fei.edu.br |
Outline
Compact Modeling
Dynamic Model
Conclusion

• The Junctionless Nanowire Transistor (JNT)
 Developed in 2009 by J.P. Colinge et al.[1].
➢ Absence of doping gradients;
➢ Avoids impurity diffusion into
the channel region;
➢ Presents doping concentration in
the order of 1019 cm-3;
Junctionless IM Trigate
[1] J. P Colinge et al., in: SOI Conference (2009).

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 9
SBMicro 2014 - 29th Symposium on Microelectronics Technology and Devices

Introduction
• The Junctionless Nanowire Transistor
With respect to inversion mode devices:

Advantages Drawbacks
➢ Reduced electric field; ➢Strong dependence of VTH on the
➢ Smaller mobility degradation; fin dimensions;
➢ Better analog properties;
➢ Higher Series Resistance;
➢ Better DIBL;
➢ Reduced low frequency noise. ➢ Smaller low field mobility.

Junctionless nanowire transistor - (3 parallel nanowires)
A
C
5 nm
B
Courtesy Dr. Jean-Pierre Colinge
Performance Comparison: Inversion-Mode and Junctionless nanowire transistors
- Common parameters in JNT and IM:

✓EOT=1.3 nm
✓tSi = 10 nm
✓ Wfin > 10 nm
✓ L = down to 10 nm
- JNT Characteristics:
✓ND = 1.1019 cm-3
- IM Characteristics:
✓ NA = 1.1015 cm-3

Comparison between IM and Junctionless nanowire transistors of similar dimensions
Drain current vs. VGT - L down to 10 nm

-4
10 Junctionless Transistors
3
IDS/(W/L) [A]
IDS/(W/L) [A]
Experimental Data
-7 L = 100 nm Better
10 2
L = 30 nm Subthreshold
L = 10 nm
-10
1 Swing
10
10
-13 0
-4
10
Nanowire Transistors 9
IDS/(W/L) [A]
IDS [A]/(W/L)
L = 100 nm
-7 L = 30 nm
10 6
L = 10 nm
Hfin = 10 nm
-10
10 W fin = 10 nm 3 Higher IDS
VDS = 50 mV
-13
10 0
-0.50 -0.25 0.00 0.25 0.50
VGS-VTH [V]
R. T. Doria et at., IEEE S3S Conference, 2017
VTH and Subthrehsold Swing (SS) vs. L
0.44 Junctionless Transistors
SS [mV/dec]
64
VTH [V]
VTH Nearly ideal

0.42
62 Subthreshold
SS Swing
0.40
60
0.38
0.50 240
SS [mV/dec]
0.00 Nanowire Transistors 180
VTH [V]
-0.50 Smaller
Wfin = 10 nm threshold
-1.00 120
VDS = 50 mV voltage roll-off
-1.50
60
-2.00 10 100
L [nm]
Drain Induced Barrier Lowering (DIBL) vs. L
1
Wfin = 10 nm
Junctionless
Nanowires
DIBL [mV/V]
VDS1 = 50 mV
0.1
VDS2 = 1.0 V
0.01 10 100
L [m]

ION and IOFF vs. L

-4
10
Closed Symbols - JNTs Smaller ION
Open Symbols - NWs
ION [A]
-5
10 Lower carrier mobility
ION @ VGS - VTH = 0.5 V
-6
10
-7
10 VDS = 1 V IOFF @ VGS - VTH = -0.3 V
IOFF [A]
-9 Wfin = 10 nm Smaller IOFF

10
Hfin = 10 nm
-11
10
Better electrostatic control
-13
10 10 100 Longer L in subthreshold
L [nm] R. T. Doria et at., IEEE S3S Conference, 2017
ION/IOFF vs. L
7
10
Larger ION/IOFF at all L
5
10
ION/IOFF
Wfin = 10 nm Open Symbols - NWs

Hfin = 10 nm Closed Symbols - JNTs Smaller IOFF
3
10
, VDS = 50 mV
, VDS = 1 V
1
10 10 100
L [nm]

gmmax and RS vs. L

Smaller gmmax at all L
15
-5
10
gmmax , R Lower carrier mobility
S
, Nanowires 10
gmmax [ ]

RS [k]
Junctionless
5 Larger RS
Wfin = 10 nm
-6
VDS = 50 mV Not optimized S/D extensions
10 0
0 50 100 150 200
L [nm]

ION,IOFF and ION/IOFF vs. WFin

8 Smaller ION
10
-4
10
ION @ VGS - VTH = 0.5 V 7
Lower carrier mobility
Open Symbols - NWs 10
Closed Symbols - JNTs
-6
10
ION, IOFF [A]
L = 100 nm Smaller IOFF
ION/IOFF
6
Hfin = 10 nm 10
-8
10
IOFF @ VGS - VTH = -0.3 V Better electrostatic control
5
VDS = 1 V 10
-10
Longer L in subthreshold
10
4
10
0 20 40 60 80 100 120 Larger ION/IOFF at all WFin
Wfin [nm]

SS and DIBL vs. WFin

68 60
Open Symbols - NWs
Closed Symbols - JNTs
66 50 Better Subthreshold
Swing at all WFin
DIBL [mV/V]
SS [mV/dec]
40
64
30
62
L = 100 nm 20 Better DIBL for Wfin<60 nm
Hfin = 10 nm
60
10
0 20 40 60 80 100 120
Wfin [nm]

Outline
Compact Modeling
Dynamic Model
Conclusion

Long Channel Drain Current Model
Bulk conduction
▪ 2D Poisson equation (considering only the depletion charge):
d 2Φ d 2Φ q ND
  
dx 2 dz 2 ε Si
2
dΦ dΦ  dΦ  q ND
▪ Using the approximation:  2d    2 dΦ
dx dz  dx   Si
and considering the center potential as zero at the source side
Poisson equation can be
integrated, leading to:
E S ,depl  q N D Φ S ,depl / ε Si
TREVISOLI, R.. D ; DORIA, R. T. ; DE SOUZA, M. ; DAS, S. ; FERAIN, I. ; PAVANELLO, M. A. . Surface
Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE
Transactions on Electron Devices, v. 59, p. 3510-3518, 2012.
dΦ dΦ 5
ERight surface =4.16 x10 V/cm
▪ Approximation:  4
5
ETop surface =4.04 x10 V/cm
Electric field [x10 V/cm]

dx dz 5
3 ELeft surface =4.16 x10 V/cm
5
Exz
2
Ezx
0.00 1
zx
0
-0.04
Potential [V]
-6 -4 -2 0 2 4 6
-0.08 xz x,z [nm]

Right surface =-0.11 V
-0.12 Top surface =-0.12 V

Left surface =-0.11 V
-6 -4 -2 0 2 4 6
x,z [nm]
Bulk conduction
▪ Relation between depletion charge and electric field:
QDepl  ε Si ES (2 H Fin  WFin )
ES  q N D Φ S ,depl / ε Si 2
a  a 
 S ,depl  VG  V FB      a (VG  VFB )
2 2  2
2C ox  ox
2C  C ox
MOS capacitor:
(Φ S ,depl  VG  VFB )Cox  QDepl a = Si q ND (2HFin + WFin)2

Accumulation conduction
▪ 2D Poisson equation:
d 2Φ d 2Φ q N D  / t
 2  e
dx 2
dz ε Si
Poisson equation can be
integrated, leading to: E S ,acc  q N Dt (exp( Φ S ,acc / t )  1) / ε Si
 (VG  V FB  Φ S ,acc ) 2 C ox 2 
Φ S ,acc  t ln 1  
 a  t 
An exact solution for ΦS,acc can be obtained by the use of the Lambert function.
However, in order to obtain a simplified solution, as ΦS,acc values a few ϕt in strong
accumulation, ΦS,acc can be neglected for VG >> VFB inside the logarithm term.

▪ Transition between bulk and accumulation conduction
to have a continuous transition between both conduction regimes (bulk conduction and both
accumulation layer and bulk conductions), a smooth function has been used to VG [24]:
 ln[1  exp( A1 (1  (VG  Vy) / VFB ))] 

VG 2  VFB 1  
 ln(1  exp( A1 )) 
where A1 controls the smoothness and has been set to 12 and Vy is the voltage at the point y of the channel, i.e.
Vy = 0 at source and Vy = VD at drain for the calculation of the source and drain surface potentials, respectively.
This equation is used to limit the maximum gate voltage in VFB. This
function is used inside the square root term of Φs,depl instead of VG, so that
the depletion charge smoothly tends to zero at the flatband condition.

▪ Transition between subthreshold and above threshold regimes
This equation limits the minimum gate voltage in the threshold voltage,
such that the conduction charge reduces exponentially.
 ln[1  exp( A2 (1  VG 2 / VT ))] 

VG 3  VT 1  
 ln(1  exp( A2 )) 
where A2 is related to the subthreshold slope, calculated as A2 = VT/(2.n.ϕt),

where n is the body factor which is close to the unity for these devices.

▪ General solution
 S   S ,depl   S ,acc
2
a  a 
 S ,depl  VG 2  VFB  Vy      a (VG 3  VFB )
2 2  2
2C ox  ox
2C  C ox
 (VG  VG 2 ) 2 Cox 2 
Φ S ,acc  t ln 1  
 a t 

▪ The drain current can be obtained by:
dVy μn  (Q
2
 Q
2
n,D )

I D  μ n Qn ID  
n,S

dy L  2C ox 
Qn  Q f  Q  q N D W H  (V FB VG  Φ S )C ox

Saturation voltage I Dsat  Qsat v sat
The drain current IDsat is obtained by considering Qn,D = Qsat. Therefore, Qsat can be
isolated, reaching:
2
L C ox  L C ox 
Qsat   v sat   v sat   Qn ,S 2
μn  μn 
 Q Q 1 
2
 1 
2

 a           V FB  VG
sat f
V Dsat
 2a 2a C ox   C ox  
 ln[1  exp( A3 (1  VD / VDsat ))] 

VD  VDsat 1  
 ln(1  exp( A3 )) 

• Three-dimensional simulations were performed in Sentaurus

▪ channel length = 1 m
▪ N+ polysilicon gate
▪ tSi = 10 nm
• Device characteristics
▪ ND = 1 x 1019 cm-3
▪ tox = 2 nm
▪ W = 10 nm
• Low Field Mobility was considered as 100 cm2/V.s

0.8 19 -3
Surface potential at drain
ND = 1 x 10 cm
Effective Surface Potential [V]
for VD = 0.1, 0.2 and 0.5V > VD

H = 10 nm Good Agreement
0.4 W = 10 nm between simulated
tox = 2 nm
and modeled data
L = 1 m
for various VDS
0.0
Surface potential at source

-0.4
lines - model
-0.8 symbols - simulation
0.0 0.4 0.8 1.2 1.6

Gate voltage [V]

19 -3
-12
ND = 1 x 10 cm
10
Charge density [C/cm]
H = 10 nm
W = 10 nm
-14 tox = 2 nm > VD Good Agreement
10
L = 1 m between simulated
-16
Charge density Charge denstiy at drain
and modeled data
10 at source for VD = 0.1, 0.2 and 0.5V for various VDS
-18
10 lines - model
symbols - simulation
0.0 0.4 0.8 1.2 1.6
Gate voltage [V]

-5
-2.4 10
(A) VD = -0.05 and -1 V
▪ Comparison of the curves
Absolute drain current [A]

-7
-2.0 10
Drain current [A]

ID x VG and gm x VG : -1.6
-9
10
-11
-1.2 10
VD = -0.05, -0.1 -13
10
-0.8 -0.2, -0.5 and -1 V
-15
4 (B) symbols - simulation 10
lines - model -0.4

Transconductance [S]
-17
10
3 0.0
-19
VD = -0.05, -0.1 10
-0.2, -0.5 and -1 V 0.0 -0.4 -0.8 -1.2 -1.6
2
Gate voltage [V]
L = 1 m
W = H = 10 nm
1 tox = 2 nm
19
NA = 1 x 10 cm
-3
▪ ID and gm are correctly
0
predicted by the model in
0.0 -0.4 -0.8 -1.2 -1.6 both subthreshold and
Gate voltage [V] above threshold regions.
(A)
▪ Comparison of the curves -2.0
VGT = -0.2, -0.4,
ID x VD and gD x VD :

-0.6, -0.8 and -1 V
-1.5
-1.0
-5
10
(B) symbols - simulation -0.5
lines - model
Drain conductance [S]
-6
VGT = -0.2, -0.4, 0.0
10
-0.6, -0.8 and -1 V
0.0 -0.4 -0.8 -1.2 -1.6
-7
10
Drain voltage [V]
-8
10
L = 1 m
-9
tox = 2 nm ▪ The dependence on
10 W = H = 10 nm
19
NA = 1 x 10 cm
-3 VD is also adequately
0.0 -0.4 -0.8 -1.2 -1.6 modeled
Drain voltage [V]

Short Channel Effects
▪ To obtain an analytical expression for SCE, the 3D Poisson

equation must be solved:
d 2Φ d 2Φ d 2Φ q N A
 2  2 
dx 2
dz dy ε Si
▪ Using the superposition principle, the solution of the 2D Poisson

equation can be added to the solution of the 3D Laplace equation for
the minimum potential: d 2 Φ d 2 Φ d 2 Φ
  0
dx 2 dz 2 dy 2
V sinh( ymin /  )  U sinh(( L  ymin ) /  )

which is given by: Φ min 
sinh( L /  )
  U exp(L /  )  V 

ymin is point of the minimum potential given by: min 2 ln V  U exp( L /  ) 
y
 
 is the characteristic length
▪ The minimum potential in the channel is obtained by:

Φ min 
sinh( L /  )
  U exp(L /  )  V 
ymin 
2 V  U exp( L /  ) 
ln 
2
  W t ox   W 
1   Si 1  ox 
where: 1
 2   4  Si ox 
t
 2
1  1 
2  ox
  and
          H t ox   H 
2

  1   22  
2   Si 1  ox 
 4  ox  2  Si ox 
t
▪ To calculate the drain current with the short channel effects correction:
VG  VG   min

▪ min represents the variation of the minimum potential in the channel:
0.6 L = 20 nm VG = 1.2 V
L = 1 m
0.5
Channel potential [V]
0.4
0.3 VG = 0.4 V
0.2
0.1
0.0 variation of the
minimum potential VG = 0 V
-0.1
-0.2
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
y/L
-12
▪ Comparison of the curves (A) VD = -0.05 and -0.5 V
-5
10

2
-10 -7
ID x VG and gm x VG for a 10

-8 -9 1
10
device with L = 40 nm:
-6 -11
10
VD = -0.05, -0.1 1
-4 -0.2 and -0.5 V -13
10
(B) symbols - simulation -2 -15
10
20
lines - model
-17
0 10
15 VD = -0.05, -0.1 -19
2 10
1
-0.2 and -0.5 V 0.0 -0.4 -0.8 -1.2
10 Gate voltage [V]
3 L = 40 nm
W = H = 10 nm
5 5 tox = 2 nm
19
NA = 1 x 10 cm
-3 ▪ ID and gm are correctly
7
0 predicted by the model in
9
0.0 -0.4 -0.8 -1.2

both subthreshold and
Gate voltage [V] above threshold regions.
▪ Comparison of the curves -12 (A) VGT = -0.2, -0.4,

-10
ID x VD and gD x VD for a and -0.6 V

device with L = 40 nm: -8
-6
-4
-4
10 (B) symbols - simulation
lines - model
-2
Drain conductance [S]
-5 0
10 VGT = -0.2, -0.4,
and -0.6 V 0.0 -0.4 -0.8 -1.2
-6
10 Drain voltage [V]
L = 40 nm
-7
10
W = H = 10 nm
tox = 2 nm
▪ The dependence on
19
NA = 1 x 10 cm
-3
VD is also adequately
0.0 -0.4 -0.8 -1.2 modeled
Drain voltage [V]
▪ Comparison of the curve gm/ID x |ID|:
-40
-30 W = H = 10 nm
L = 40 nm
tox = 2 nm
gm/ID [V ]
▪ The plateau in the

-1
NA = 1 x 10 cm
19 -3 VD = -0.05
-20 and -0.5 V weak inversion regime is
L = 1 m
inversely proportional to
-10 VD = -0.05 the subthreshoold slope
and -0.5 V
lines - model
0 symbols - simulation
-12 -11 -10 -9 -8 -7 -6 -5
10 10 10 10 10 10 10 10

Drain Current Model – Devices with L=30 nm
100
Transconductance [ S] Drain current [ A]
symbols - experimental
Drain current [A]

-6
75 lines - model 10
T = 300, 360
50 and 420 K -10
10
T = 300, 360
25 and 420 K -14
10
0 -18
10
19 -3
120 ND = 1 x 10 cm
EOT = 1.5 nm
80 W = 20 nm
H = 12 nm
T = 300, 360
L = 30 nm
40 VD = 40 mV
and 420 K
50 fins
0
-1.2 -0.8 -0.4 0.0 0.4 0.8
Gate voltage [V]

Drain Current Model – Devices with L=30 nm
800
, T = 300 K VGT = 0.6 V
, T = 420 K
600 symbols - experimental
lines - model
VGT = 0.4 V
400
VGT = 0.2 V
200
L = 30 nm
H = 10 nm EOT = 1.5 nm
0 19 -3
W = 20 nm ND = 1 x 10 cm
0.0 0.2 0.4 0.6 0.8 1.0
Drain voltage [V]
TREVISOLI, R.. D ; DORIA, R. T. ; DE SOUZA, M. ; DAS, S. ; FERAIN, I. ; PAVANELLO, M. A. . Surface

Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors. IEEE
Transactions on Electron Devices, v. 59, p. 3510-3518, 2012.
Substrate Bias Influence
▪ Relation between depletion charge and electric field:
  ε Si t Box 
2 
 ε Si t Box 2ε Si 
H eff  H Fin        (VFBs  VBS )  This approximation neglects the
 ε ox  ε ox  q N D  cross-dependence between the gate
 
and the substrate biases on the
QSi  q N D WFin H Fin  C Box (VFBs  VBS ) channel potential.
2
a  a 
ES  q N D Φ S ,depl / ε Si
 S ,depl  VG  V FB      a (VG  VFB )
2 2  2
2C ox  ox
2C  C ox
MOS capacitor:
(Φ S ,depl  VG  VFB )Cox  QDepl a = Si q ND (2Heff + WFin)2

-5
0.3 10
Drain current [A] Drain current [A]
Drain current [A]

VBS = -40, -20,
0, 20 e 40 V -8
0.2 10
tox = 2 nm
-11
0.1
H = 10 nm 10
W = 10 nm
19 -3 -14
ND = 1 x 10 cm 10
0.0 L = 1 m
5 VBS = -40, -20, -6

10
Drain current [A]

4 0, 20 e 40 V
-9
3 10
-12
2 Symbols - Simulations 10
Lines - Model
1 -15
L = 30 nm 10
0
-0.5 0.0 0.5 1.0 1.5
Gate Voltage [V]
TREVISOLI, Renan Doria ; DORIA, Rodrigo Trevisoli ; DE SOUZA, Michelly ; PAVANELLO, Marcelo
A. . Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors. IEEE Transactions on
Electron Devices, v. 61, p. 1575-1582, 2014.
Outline
Compact Modeling
Dynamic Model
Conclusion

TREVISOLI, RENAN ; Doria, Rodrigo Trevisoli ; DE SOUZA, Michelly ; BARRAUD, SYLVAIN ; VINET, MAUD ;
Pavanello, Marcelo Antonio . Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire
Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, p. 856-863, 2016.

Dynamic Model - Formulation
▪ Conduction charge density per unit of length:
Gate
N+ Si
Substrate
QC  qN DWFin H Fin  (VFBs  VB  Φ SB )C Box  (VFB  VG  Φ S (VG , Vy ) )Cox

Fixed Substrate induced Gate induced
Charges Charges Charges

▪ Total Conduction charge at the channel:
▪ Integrating the conduction charge density:

L VD
Qt   QC dy   QC dVy
2
0
ID VS Charges
density at
drain-side
 
QC , D
Qt    QC dQC  (QC , S  QC , D )
2 3 3
C ox I D 3C ox I D Charges
QC , S
density at
source-side
▪ Total charge at the gate:
  (QC ,S  QC , D ) 
2 2
QG = Qt – L(qNDWH – CBox(VFBs – VB + SB))) ID   
L  2C ox 
▪ Total charge at drain node:
▪ Following Ward–Dutton scheme:

L y LQ f  2
VD
LQ f
Q D    QC dy    QC (QC ,S  QC ) dVy 
2 2 2
0 L 2  2C ox L I D 2 VS
2
2  QC , S 2 (QC , S 3  QC , D 3 ) (QC , S 5  QC , D 5 )  LQ f
QD    
2 L (C ox I D ) 2  3 5  2
▪ Total charge at source node:

QS = –QG –QD
▪ Substituting the drain current into the charges equation:
2 L (QC , S  QC , S QC , D  QC , D )
2 2
QG   LQ f
3 (QC , S  QC , D )
2 L(2QC , S  4QC , S QC , D  6QC , S QC , D  3QC , D )

3 2 2 3
LQ f
QD   
15(QC , S  2QC , S QC , D  QC , D )
2 2
2
QS = –QG –QD
All charges are written in terms of the charge densities at

source- and drain-side of the channel

▪ Transcapacitances:
The transcapacitances are obtained by the node Cjk = – ∂Qj/∂Vk
charges derivatives:
QG 2 L QC , S  2QC , S  QC , D QC , S 2  QC , S QC , D  QC , D 2  2 L QC , D  2QC , D  QC , S QC , S 2  QC , S QC , D  QC , D 2 
      
Vk 3 Vk  QC , S  QC , D (Q  Q ) 2  3 Vk  QC , S  QC , D (Q  Q ) 2 
 C ,S C ,D   C ,S C ,D 
QD 4 L QC , S  QC , S  3QC , D QC , S  QC , S QC , D

3 2 2
 2 L QC , D  3QC , D 3  8QC , D QC , S 2  9QC , S QC , D 2 
    
Vk 15 Vk  Q 3  3Q Q 2  3Q Q 2  Q 3  15 Vk  Q 3  3Q Q 2  3Q Q 2  Q 3 
 C ,S C ,D C ,S C ,S C ,D C ,D   C ,S C ,D C ,S C ,S C ,D C ,D 
QS Q QD
 G 
Vk Vk Vk
All the transcapacitances are

written in terms of QC As the surface potentials are
QC  VG Φ S (VG ,Vy)   V Φ SB  obtained analytically, their
   Cox   B  C Box
Vk  Vk Vk   Vk Vk  derivatives are also analytical
▪ Transconductances:
The transconductances are also written in terms of QC:
I D   QC , S QC , D 
  C ,S
2Q  2Q 
Vk Vk Vk 
C ,D
2C ox L 
▪ Quantization:
QM effects are considered by the addition of QM to S
h2 h2   Si 
1/ 3 Accounts for electrical
ΦQM     ( N D 
) 4qkT  (ES ) 0.63
  (N D ) and structural
8 m x W 2 8m y H 2  
confinements
ΦQM
1/ 3
   0.63 E S
  ( N D ) Si 
Vk  4qkT  ES
0.37
Vk

Model Derivation
▪ Short-Channel Effects:
SCE effects are considered by the addition of the minimum
potential variation to VG

Φ min 
sinh( L /  ) U and V are the
surface potential at
drain- and source-
  U exp(L /  )  V  sides of the channel
y min  ln  
2 V  U exp( L /  ) 

Dynamic Model – Comparison against 3D simulations
W = 10 nm L = 1 m
1.0 H = 10 nm VDS = 1 V
Charge [fC]
EOT = 2 nm
0.5 tBox = 100 nm
QG
19 -3
ND = 10 cm
QS
0.0 QD
Lines - Model
-0.5 Symbols - Simulation
0 1 2 3
Gate voltage [V]
Conductances [S]
6
W = 10 nm L = 1 m gDG = dID/dVG
3 H = 10 nm VDS = 1 V
EOT = 2 nm
0
tBox = 100 nm gDD = dID/dVD
-3 19
ND = 10 cm
-3
gDS = dID/dVS
-6
-0.5 0.0 0.5 1.0 1.5 2.0

Gate voltage [V]

Capacitances [fF]
0.6 C , C ,C ,C
GG GD DS SD
19 -3
CGG
0.4 ND = 1 x 10 cm
W = 10 nm CGD CSD
CDS
0.2 H = 10 nm
tox = 2 nm
0.0
0.4
Capacitances [fF]
CGS,CSG, CDG CGS
CSG
L = 1 m
0.2 V = 1 V
DS
tBox = 10 nm CDG
0.0
0.06
Capacitances [fF]
CGB, CSB, CDB

0.04 CGB
Lines - Model
Symbols - Simulation
0.02 CSB
CDB
0.00
0.0 0.5 1.0 1.5 2.0 2.5

Gate voltage [V]

0.7 Symbols - Simulation VDS = 1 V

Lines - Model
CGG
0.6 N = 1019 cm-3 L = 1 m
Capacitances [fF]
0.5 tBox = 10 nm
W = 15 nm
0.4 H = 10 nm
tox = 2 nm CGS
0.3
VBS = 2, 0 CGD
0.2 and -2 V
0.1
0.0
0 1 2
Gate voltage [V]

Dashed lines - Model neglecting SCEs
Capacitances [fF]
0.02 Solid lines - Model including SCEs CGG
Symbols - Simulations
0.01 CGS
CGD W = 10 nm
0.00
19 -3
ND = 1 x 10 cm
Capacitances [fF]
0.02 tBox = 100 nm

CGG
H = 10 nm
tox = 2 nm
L = 30 nm CGS
0.01 VDS = 0.5 V
CGD
W = 20 nm
0.00
0 1 2
Gate voltage [V]

0.5
, Neglecting QM - tox = 2 nm CGG
Capacitances [fF]
, Including QM - tox = 2 nm
0.4
Neglecting QM - tox = 2.4 nm
0.3 19
ND = 1 x 10 cm
-3
W = 10 nm
CGS
0.2 H = 5 nm
L = 1 m
VDS = 1 V
0.1 tBox = 100 nm CGD
0.0
0.5 Symbols - Simulation

CGG
Capacitances [fF]
Lines - Model
0.4 19 -3
ND = 1 x 10 cm
CGS
0.3 H = 10 nm
W = 5 nm
0.2 L = 1 m
VDS = 1 V
0.1 tBox = 100 nm CGD
0.0
0 1 2 3
Gate voltage [V]
Capacitances [fF]
1.2 CGG tox = 2 nm W = 5, 20 and 50 nm
CGS
(A)
1.0 H = 10 nm
L = 1 m
0.8 CGD
19 -3
VDS = 1 V
0.6 ND = 1 x 10 cm
0.4 Lines - Model
0.2
0.0
2.0
Capacitances [fF] Capacitances [fF]

CGG
1.6 CGS
tox = 2 nm
W = 10 nm
(B) H = 5, 20 and 50 nm
CGD L = 1 m
1.2 VDS = 1 V
19 -3
ND = 1 x 10 cm
0.8
0.4 Lines - Model
0.0
1.2
Opened symbols - tox = 1 nm L = 1 m
1.0
Closed symbols - tox = 3 nm
(C) VDS = 1 V
0.8
CGG 19
ND = 1 x 10 cm
-3
0.6 CGS W = 10 nm
0.4 CGD
H = 10 nm
0.2
0.0
0.6
Capacitances [fF]
19 -3
CGG tox = 2 nm ND = 0.5, 2 and 3 x10 cm
0.5 CGS W = 10 nm
(D)
H = 10 nm
0.4 CGD
L = 1 m
0.3 Symbols - Simulation
Lines - Model
0.2 VDS = 1 V
0.1
0.0
0 1 2
MOS-AK Workshop, ESSDERC, Leuven, 2017
Gate voltage [V] www.fei.edu.br |
Dynamic Model – Comparison against Experimental data
Capacitances [pF] Capacitances [pF]

Opened Symbols, dashed lines - W mask= 40 nm L = 10 m
0.6 Closed Symbols, solid lines - W mask= 20 nm
EOT = 1.5 nm
0.4 H = 9 nm C GG
tBox = 145 nm
0.2 VDS = 0 V
VBS = 0 V CGS
0.0
0.8
Symbols - Experimental
0.6 Lines - Model CGG
L = 10 m tBox = 145 nm
0.4 VBS = -10,0, 10, VDS = 0 V
0.2 20 and 30 V EOT = 1.5 nm
W mask = 40 nm
0.0 H = 9 nm
-0.8 -0.4 0.0 0.4 0.8 1.2

Gate voltage [V]
TREVISOLI, RENAN ; Doria, Rodrigo Trevisoli ; DE SOUZA, Michelly ; BARRAUD, SYLVAIN ; VINET, MAUD ;
Pavanello, Marcelo Antonio . Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire
Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, p. 856-863, 2016.

Outline
Compact Modeling
Dynamic Model
Conclusion

Conclusion
•The Junctionless Nanowire Transistor is an interesting alternative for MOSFET

downscaling with respect to IM nanowires.
• Smaller IOFF and higher ION/IOFF at similar L (down to 10 nm).
•The analytical models presented show good agreement with experimental and
simulated data.
• Accounted for terminal voltages variations;
• Symmetric in the vicinity of VDS=0 V;
• Transconductances and transcapacitances.

Tasks Ongoing
• Transfer the models to VERILOG-A
• Compact modeling of Low Frequency Noise

Acknowledgements
Michelly de Souza Antonio Cerdeira

Rodrigo Doria
Renan Trevisoli
Genaro Mariniello Jean-Pierre Colinge
Bruna Cardoso Paz Olivier Faynot
Flávio Bergamaschi Maud Vinet
Claudio Vilela Moreira Sylvain Barraud

Acknowledgements

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Junctionless Nanowire Transistors

Performance: Static and Dynamic

Department of Electrical Engineering

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br 1

Introduction & Motivation

The Junctionless Nanowire Transistor

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

Introduction & Motivation

The Junctionless Nanowire Transistor

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

ArF + RET FinFET

Courtesy of Prof. Cor Claeys

Source Drain Silicon

MOS-AK Workshop, ESSDERC, Leuven, 2017

Introduction & Motivation

The Junctionless Nanowire Transistor

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

[1] J. P Colinge et al., in: SOI Conference (2009).

SBMicro 2014 - 29th Symposium on Microelectronics Technology and Devices

• The Junctionless Nanowire Transistor

With respect to inversion mode devices:

SBMicro 2014 - 29th Symposium on Microelectronics Technology and Devices

- Common parameters in JNT and IM:

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

Drain current vs. VGT - L down to 10 nm

VTH and Subthrehsold Swing (SS) vs. L

0.44 Junctionless Transistors

VTH Nearly ideal

Drain Induced Barrier Lowering (DIBL) vs. L

R. T. Doria et at., IEEE S3S Conference, 2017

ION and IOFF vs. L

-9 Wfin = 10 nm Smaller IOFF

Wfin = 10 nm Open Symbols - NWs

R. T. Doria et at., IEEE S3S Conference, 2017

gmmax and RS vs. L

R. T. Doria et at., IEEE S3S Conference, 2017

ION,IOFF and ION/IOFF vs. WFin

L = 100 nm Smaller IOFF

R. T. Doria et at., IEEE S3S Conference, 2017

SS and DIBL vs. WFin

R. T. Doria et at., IEEE S3S Conference, 2017

Introduction & Motivation

The Junctionless Nanowire Transistor

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br |

Electric field [x10 V/cm]

-0.08 xz x,z [nm]

-0.12 Top surface =-0.12 V

QDepl  ε Si ES (2 H Fin  WFin )

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 24

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 25

 ln[1  exp( A1 (1  (VG  Vy) / VFB ))] 

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 26

 ln[1  exp( A2 (1  VG 2 / VT ))] 

where A2 is related to the subthreshold slope, calculated as A2 = VT/(2.n.ϕt),

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 27

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 28

▪ The drain current can be obtained by:

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 29

Saturation voltage I Dsat  Qsat v sat

 ln[1  exp( A3 (1  VD / VDsat ))] 

MOS-AK Workshop, ESSDERC, Leuven, 2017 www.fei.edu.br | 30