PD - 95440B

IRLR7843PbF
IRLU7843PbF
Applications HEXFET® Power MOSFET
l High Frequency Synchronous Buck
Converters for Computer Processor Power VDSS RDS(on) max Qg
l High Frequency Isolated DC-DC 30V 3.3m: 34nC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free

Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
D-Pak I-Pak
l Fully Characterized Avalanche Voltage
IRLR7843PbF IRLU7843PbF
and Current

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 161 f
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 113 f A
IDM Pulsed Drain Current c 620
PD @TC = 25°C Maximum Power Dissipation g 140 W
PD @TC = 100°C Maximum Power Dissipation g 71
Linear Derating Factor 0.95 W/°C
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.05
RθJA Junction-to-Ambient (PCB Mount) g ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110

Notes  through … are on page 11

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IRLR/U7843PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 19 ––– mV/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 2.6 3.3 mΩ VGS = 10V, ID = 15A e
––– 3.2 4.0 VGS = 4.5V, ID = 12A e
VGS(th) Gate Threshold Voltage 1.4 ––– 2.3 V VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -5.4 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 24V, VGS = 0V
––– ––– 150 VDS = 24V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 37 ––– ––– S VDS = 15V, ID = 12A
Qg Total Gate Charge ––– 34 50
Qgs1 Pre-Vth Gate-to-Source Charge ––– 9.1 ––– VDS = 15V
Qgs2 Post-Vth Gate-to-Source Charge ––– 2.5 ––– nC VGS = 4.5V
Qgd Gate-to-Drain Charge ––– 12 ––– ID = 12A
Qgodr Gate Charge Overdrive ––– 10 ––– See Fig. 16
Qsw Switch Charge (Qgs2 + Qgd) ––– 15 –––
Qoss Output Charge ––– 21 ––– nC VDS = 15V, VGS = 0V
td(on) Turn-On Delay Time ––– 25 ––– VDD = 15V, VGS = 4.5V e
tr Rise Time ––– 42 ––– ID = 12A
td(off) Turn-Off Delay Time ––– 34 ––– ns Clamped Inductive Load
tf Fall Time ––– 19 –––
Ciss Input Capacitance ––– 4380 ––– VGS = 0V
Coss Output Capacitance ––– 940 ––– pF VDS = 15V
Crss Reverse Transfer Capacitance ––– 430 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy d ––– 1440 mJ
IAR Avalanche Current c ––– 12 A
EAR Repetitive Avalanche Energy c ––– 14 mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 161 f MOSFET symbol
(Body Diode) A showing the
ISM Pulsed Source Current ––– ––– 620 integral reverse
(Body Diode)c p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 12A, VGS = 0V e
trr Reverse Recovery Time ––– 39 59 ns TJ = 25°C, IF = 12A, VDD = 15V
Qrr Reverse Recovery Charge ––– 36 54 nC di/dt = 100A/µs e
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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1000 1000
VGS VGS
TOP 10V TOP 10V
4.5V 4.5V
3.7V 3.7V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

3.5V 3.5V
100 3.3V 3.3V
3.0V 3.0V
2.7V 100 2.7V
BOTTOM 2.5V BOTTOM 2.5V

10

2.5V
10
2.5V
1

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
0.1 1
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
ID = 30A
RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (Α)

100 1.5
T J = 175°C
(Normalized)

T J = 25°C
10 1.0

VDS = 15V
20µs PULSE WIDTH
1 0.5
2.0 3.0 4.0 5.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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100000 12
VGS = 0V, f = 1 MHZ ID= 12A
Ciss = C gs + Cgd, C ds SHORTED VDS= 24V

VGS, Gate-to-Source Voltage (V)

Crss = C gd 10 VDS= 15V
Coss = Cds + Cgd
C, Capacitance (pF)

10000 8

Ciss
6

Coss 4
1000

Crss 2

0
100
0 20 40 60 80
1 10 100
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.0 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.0 1000
T J = 175°C

10.0 100
100µsec

1.0 10
T J = 25°C 1msec
Tc = 25°C
VGS = 0V Tj = 175°C
Single Pulse 10msec
0.1 1
0.0 0.5 1.0 1.5 0.1 1.0 10.0 100.0 1000.0
VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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160 2.5
LIMITED BY PACKAGE

VGS(th) Gate threshold Voltage (V)

2.0
120
ID = 250µA
ID , Drain Current (A)

1.5
80

1.0

40
0.5

0
0.0
25 50 75 100 125 150 175
-75 -50 -25 0 25 50 75 100 125 150 175
T C , Case Temperature (°C)
T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Case Temperature

10
Thermal Response ( Z thJC )

1
D = 0.50

0.20
R1 R2
0.1 0.10 R1 R2 Ri (°C/W) τi (sec)
τJ τC
0.05 τJ τ 0.5084 0.000392
τ1 τ2
0.02 τ1 τ2 0.5423 0.011108
0.01 Ci= τi/Ri
0.01 Ci i/Ri
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U7843PbF
15V
6000

EAS, Single Pulse Avalanche Energy (mJ)

ID
TOP 8.6A
L DRIVER 5000
VDS 9.6A
BOTTOM 12A

RG D.U.T 4000
+
V
- DD
IAS A
20V
VGS 3000
tp 0.01Ω

Fig 12a. Unclamped Inductive Test Circuit 2000

1000
V(BR)DSS
tp
0
25 50 75 100 125 150 175

Starting T J, Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
I AS LD
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD -

Current Regulator D.U.T

Same Type as D.U.T. VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ

12V .2µF
.3µF
Fig 14a. Switching Time Test Circuit
+
V
D.U.T. - DS VDS
90%
VGS

3mA

10%
IG ID
Current Sampling Resistors
VGS

td(on) tr td(off) tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
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 IRLR/U7843PbF

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRLR/U7843PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛ Qgd ⎞ ⎛ Qgs 2
+⎜I × × Vin × f⎟ + ⎜ I × × Vin × f ⎟
⎝ ig ⎠ ⎝ ig
+ (Qg × Vg × f )
⎛ Qoss
+ × Vin × f ⎞
⎝ 2 ⎠ are transfered to Q1 and increase the dissipation in
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
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Synchronous FET
The power loss equation for Q2 is approximated
by;
Ploss = Pconduction + Pdrive + Poutput
*
( 2
Ploss = Irms × Rds(on) )
+ (Qg × Vg × f )
⎛Q ⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2 ⎠
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
⎞ portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
⎠ it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
 IRLR/U7843PbF
D-Pak (TO-252AA) Package Outline

D-Pak (TO-252AA) Part Marking Information

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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRLR/U7843PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

(;$03/( 7+,6,6$1,5)8 3$57180%(5
:,7+$66(0%/< ,17(51$7,21$/
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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 IRLR/U7843PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 20mH, RG = 25Ω,
IAS = 12A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
… When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/2008
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