BRIVO CT315/325 Schematic Diagrams: GE Healthcare

GE Healthcare
BRIVO CT315/325
SCHEMATIC DIAGRAMS
Operating Documentation
5306515-1EN
Rev 5
© 2009-2011, General Electric Company,
All Rights Reserved.
Brivo CT315
Brivo CT325
GE HEALTHCARE SCHEMATIC DIAGRAMS
REV 5 5306515-1EN
警告 • 本维修手册仅提供英文版本。
(ZH-CN) • 如果维修服务提供商需要非英文版本，客户需自行提供翻译服务。
• 未详细阅读和完全理解本维修手册之前，不得进行维修。
• 忽略本警告可能对维修人员，操作员或患者造成触电、机械伤害或其他形式的
伤害。
• THIS SERVICE MANUAL IS AVAILABLE IN ENGLISH ONLY.

WARNING
• IF A CUSTOMER’S SERVICE PROVIDER REQUIRES A LANGUAGE
(EN) OTHER THAN ENGLISH, IT IS THE CUSTOMER’S RESPONSIBILITY TO
PROVIDE TRANSLATION SERVICES.
Attention
• DO NOT ATTEMPT TO SERVICE THE EQUIPMENT UNLESS THIS
SERVICE MANUAL HAS BEEN CONSULTED AND IS UNDERSTOOD.
• FAILURE TO HEED THIS WARNING MAY RESULT IN INJURY TO THE
SERVICE PROVIDER, OPERATOR OR PATIENT FROM ELECTRIC
SHOCK, MECHANICAL OR OTHER HAZARDS.
ATTENTION • Ce manuel de service n'est disponible qu'en anglais.

• Si le technicien du client a besoin de ce manuel dans une autre langue
(FR) que l'anglais, c'est au client qu'il incombe de le faire traduire.
• Ne pas tenter d'intervenir sur les équipements tant que le manuel service
n'a pas été consulté et compris
• Le non-respect de cet avertissement peut entraîner chez le technicien,
l'opérateur ou le patient des blessures dues à des dangers électriques,
mécaniques ou autres.
警告 • このサービスマニュアルには英語版しかありません。
(JA) • サービスを担当される業者が英語以外の言語を要求される場合、翻訳作業は
その業者の責任で行うものとさせていただきます。
• このサービスマニュアルを熟読し理解せずに、装置のサービスを行わないで
ください。
• この警告に従わない場合、サービスを担当される方、操作員あるいは患者さ
んが、感電や機械的又はその他の危険により負傷する可能性があります。
ATENÇÃO • Este manual de assistência técnica só se encontra disponível em inglês.

• Se qualquer outro serviço de assistência técnica, que não a gems,
(PT-BR) solicitar estes manuais noutro idioma, é da responsabilidade do cliente
fornecer os serviços de tradução.
• Não tente reparar o equipamento sem ter consultado ecompreendido este
manual de assistência técnica.
• O não cumprimento deste aviso pode por em perigo a segurança do
técnico, operador ou paciente devido a choques elétricos, mecânicos ou
outros.
ATTENTION
Brivo CT315
Brivo CT325
ОСТОРОЖНО! • Данное руководство по обслуживанию предлагается только на

английском языке.
(RU) • Если сервисному персоналу клиента необходимо руководство не на
английском, а на каком-то другом языке, клиенту следует
самостоятельно обеспечить перевод.
• Перед обслуживанием оборудования обязательно обратитесь к
данному руководству и поймите изложенные в нем сведения.
• Несоблюдение требований данного предупреждения может привести
к тому, что специалист по обслуживанию, оператор или пациент
получат удар электрическим током, механическую травму или другое
повреждение.
ATENCION • Este manual de servicio sólo existe en inglés.

• Si el encargado de mantenimiento de un cliente necesita un idioma que
(ES) no sea el inglés, el cliente deberá encargarse de la traducción del
manual.
• No se deberá dar servicio técnico al equipo, sin haber consultado y
comprendido este manual de servicio.
• La no observancia del presente aviso puede dar lugar a que el proveedor
de servicios, el operador o el paciente sufran lesiones provocadas por
causas eléctricas, mecánicas o de otra naturaleza.
DIKKAT • Bu servis kilavuzunun sadece ingilizcesi mevcuttur.

• Eğer müşteri teknisyeni bu kilavuzu ingilizce dişinda bir başka lisandan
(TR) talep ederse, bunu tercüme ettirmek müşteriye düşer.
• Servis kilavuzunu okuyup anlamadan ekipmanlara müdahale etmeyiniz.
• Bu uyariya uyulmamasi, elektrik, mekanik veya diğer tehlikelerden dolayi
teknisyen, operatör veya hastanin yaralanmasina yol açabilir.
경고 • 본 서비스 지침서는 영어로만 이용하실 수 있습니다 .

(KO) • 고객의 서비스 제공자가 영어 이외의 언어를 요구할 경우 , 번역 서비스를 제공
하는 것은 고객의 책임입니다 .
• 본 서비스 지침서를 참고했고 이해하지 않는 한은 해당 장비를 수리하려고 시
도하지 마십시오 .
• 이 경고에 유의하지 않으면 전기 쇼크 , 기계상의 혹은 다른 위험으로부터 서비
스 제공자 , 운영자 혹은 환자에게 위해를 가할 수 있습니다 .
ATENŢIE • Acest manual de service este disponibil numai în limba engleză.

• Dacă un furnizor de servicii pentru clienţi necesită o altă limbă decât cea
(RO) engleză, este de datoria clientului să furnizeze o traducere.
• Nu încercaţi să reparaţi echipamentul decât ulterior consultării şi
înţelegerii acestui manual de service.
• Ignorarea acestui avertisment ar putea duce la rănirea depanatorului,
operatorului sau pacientului în urma pericolelor de electrocutare,
mecanice sau de altă natură.
ATTENTION
Brivo CT315
Brivo CT325
DAMAGE IN TRANSPORTATION
All packages should be closely examined at time of delivery. If damage is apparent write “Damage In Shipment” on ALL
copies of the freight or express bill BEFORE delivery is accepted or “signed for” by a GE representative or hospital receiving
agent. Whether noted or concealed, damage MUST be reported to the carrier immediately upon discovery, or in any event,
within 14 days after receipt, and the contents and containers held for inspection by the carrier. A transportation company
will not pay a claim for damage if an inspection is not requested within this 14 day period.
To file a report:
Fill out a report on http://egems.med.ge.com/edq/home.jsp
Contact the local service coordinator.
Attention
CERTIFIED ELECTRICAL CONTRACTOR STATEMENT
All electrical Installations that are preliminary to positioning of the equipment at the site prepared for the equipment shall be
performed by licensed electrical contractors. In addition, electrical feeds into the Power Distribution Unit shall be performed
by licensed electrical contractors. Other connections between pieces of electrical equipment, calibrations and testing shall
be performed by qualified GE Medical personnel. The products involved (and the accompanying electrical installations) are
highly sophisticated, and special engineering competence is required. In performing all electrical work on these products,
GE will use its own specially trained field engineers. All of GE’s electrical work on these products will comply with the
requirements of the applicable electrical codes.
The purchaser of GE equipment shall only utilize qualified personnel (i.e., GE’s field engineers, personnel of third-party
service companies with equivalent training, or licensed electricians) to perform electrical servicing on the equipment.
IMPORTANT! . . . X-RAY PROTECTION

X-ray equipment if not properly used may cause injury. Accordingly, the instructions herein contained should be thoroughly
read and understood by everyone who will use the equipment before you attempt to place this equipment in operation. The
General Electric Company, Medical Systems Group, will be glad to assist and cooperate in placing this equipment in use.
Although this apparatus incorporates a high degree of protection against x-radiation other than the useful beam, no practical
design of equipment can provide complete protection. Nor can any practical design compel the operator to take adequate
precautions to prevent the possibility of any persons carelessly exposing themselves or others to radiation.
It is important that anyone having anything to do with x-radiation be properly trained and fully acquainted with the
recommendations of the National Council on Radiation Protection and Measurements as published in NCRP Reports
available from NCRP Publications, 7910 Woodmont Avenue, Room 1016, Bethesda, Maryland 20814, and of the
International Commission on Radiation Protection, and take adequate steps to protect against injury.
The equipment is sold with the understanding that the General Electric Company, Medical Systems Group, its agents, and
representatives have no responsibility for injury or damage which may result from improper use of the equipment.
Various protective materials and devices are available. It is urged that such materials or devices be used.
ATTENTION
Brivo CT315
Brivo CT325
LITHIUM BATTERY CAUTIONARY STATEMENTS
CAUTION
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent
type recommended by the manufacturer. Discard used batteries according to the manufacturer’s
instructions.
OMISSIONS & ERRORS

Customers, please contact your GE Sales or Service representatives.
GE personnel, please use the GEMS CQA Process to report all omissions, errors, and defects in this publication.
ATTENTION
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
REVISION HISTORY
REV Date Primary Reason for Change
5 05/09/2011 Added Multi-language warning for Korean and Romanian.
PDU Added new section for Adapter. (Sec. 3)
4 01/17/2011 Gantry Updated DTB BD Assy SCH figure. (Sec. 4)
3 07/13/2010 Added Multi-language warnings for French, Japanese, Portuguese-Brazil, Russian, Spanish and Turkish.
Revision History
OC Updated SCB SCH figure. (Sec. 2)
Added new Gantry Assy SCH figure for EMC. (Sec. 1)

Gantry Updated TGP BD Assy SCH figure. (Sec. 2)
Added new DTB BD Assy SCH figure for EMC. (Sec. 4)
DAS Updated GDAS Convertor PWA from 2364354 to 5955032. (Sec. 2)
PDU Added RMT Control Loop figure. (Sec. 1)
2 11/06/2009 Gantry Updated TGP Board SCH figure. (Sec. 2)

Udpated S-DISP Board SCH figure. (Sec. 6)
DAS Updated DAS PS figure. (Sec. 3)
1 07/22/2009 Initial release.
REVISION HISTORY
Brivo CT315
Brivo CT325
REVISION HISTORY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SYSTEM
TABLE OF CONTENTS
SECTION PAGE
SECTION 1 - SYSTEM ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Table of Content
SYSTEM i
Brivo CT315
Brivo CT325
ii SYSTEM
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 1 - SYSTEM ASSY
1-1 SYSTEM POWER & GROUND CABLING
SYSTEM
TABLE
State: RELEASE - Document is released and under formal Change Control. Changes are subject to the ECR/ECO Process.
24VDC
Gantry PE line
See the GEHC Myworkshop System to determine the status of this document.
220VAC+PE OC
Neutral line
PDU
PE line
3-phase 380VAC
5328739SCH
Approved Document - 5328739SCH_r1.pdf Page 2 of 3
SYSTEM 1-1
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1-2 SYSTEM SIGNAL CABLING

TABLE
5321396
TGP.CN11 5321396
Comm Line Table.RL2
Gantry 5321623
OC.NIC
5321623
DTB.J3 DAS Data (CAT5)
Comm Line OC
Safety loop
5321390 5321390
TGP.CN5 OC.RL1
PDU
5328739SCH
1-2 SYSTEM
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REV 5 5306515-1EN
OC
TABLE OF CONTENTS
SECTION PAGE
SECTION 1 - OC ASSY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SECTION 2 - SCAN CONTROL BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table of Content
OC i
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Brivo CT325
ii OC
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Brivo CT325
REV 5 5306515-1EN
SECTION 1 - OC ASSY
J1 (To TGP)
Scan Control Box

Host Computer (5311762) (5337068)
OC
SCB CON
Standard Keyboard
PS/2
(5328718)
DVI PS/2
Mouse (5132092)
To Monitor
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'HVLJQHU 5325157 SCH
7,7/( '2&1R
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ᡍ‫ޚ‬ *(+:0(',&$/6<67(06 ݅ 1 义㄀1 义 Sheet 1 Of 1
$SSURYDO
OC 1-1
Brivo CT315
Brivo CT325
blank
1-2 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 2 - SCAN CONTROL BOX

1 2 3 4 5 6 7 8
NOTES:
1. THE VARIATION AND VERSION FOR THIS
REVISION ECR/ECO DATE SIGN OFF
A PWA IS 5337819 REV1. A
--- ------ DD-MMM-YY --- 2. THIS COVER SHEET CONTROLS THE RE-
B ------ 12-SEP-08 --- VISION STATUS OF THE ENTIRE DOCUMENT.

THE REVISION OF ALL SHEETS OF THIS
C ------ 13-NOV-08 --- DOCUMENT WILL BE AT THE SAME LEVEL.
1 ------ 14-APR-09 --- 3. THIS SCHEMATIC MEETS THE SPECIFICA-
2 ------ 14-APR-09 --- TIONS OF THE GLOBAL SCHEMATIC STANDARD
GUIDELINES 2299773GSP.
3 ------ 20-NOV-09 ---
4. ELECTRONIC SIGNATURES FOR BOTH THE
SCHEMATIC REVIEWER(S) AND APPROVER(S)
CAN BE FOUND WITHIN MY WORKSHOP.
OC
5. UNLESS OTHERWISE SPECIFIED:
RESISTORS ARE IN OHMS.
CAPACITORS ARE IN FARADS.
ADD MOUNT PROPERTY TO RESERVED AND DEBUG COMPONENT INDUCTORS ARE IN HENRIES
VALUE:RSV=RESERVED NOT INSTALL.
DEBUG=DEBUG--SOLDER ON ES ONLY
B B
C C
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Block Path Block Sheet Dwg No Rev Sheet
Mon Apr 27 13:28:53 2009 scancontrolbox 1 of 16 5337819SCH 3 1 of 16
1 2 3 4 5 6 7 8
A dD t 5337819SCH 3 df P 2 f 17
OC 2-1
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Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
CONNECTOR
OC MIC OC SPEAKER
J1 J3 J4
A A
1 1 2 2 4C5> OCMIC_P 1 1 17C7> OCSPEAK_P 1 1
4A1> OGCOM_H 3 3 4 4 OGCOM_L 4A1> 4C5> OCMIC_N 2 2 17C7> OCSPEAK_N 2 2

4A1< GOCOM_H 5 5 6 6 GOCOM_L 4A1< 3 3 3 3
4B1> RESET_H 7 7 8 8 RESET_L 4B1>
4B1< OCXLED_H 9 9 10 10 OCXLED_L 4B1<
11 11 12 12 RAW_VCC PIN PIN
13 14 A A
13 14 STRAIGHT STRAIGHT
4D1< SC1_RXD 15 15 16 16 USB_+5V WIRE_TO_BOARD WIRE_TO_BOARD
4C1> SC1_TXD 17 17 18 18 USB_DATA- 4C1<
19 19 20 20 USB_DATA+ 4C1<
PATMIC_P2 21 21 22 22
4A3> SAFETY_A 23 23 24 24 SAFETY_B 4A3>
4B3> ERESET_A 25 25 26 26 ERESET_B 4B3> E-STOP E-RESET
4B3> ESTOP_A 27 27 28 28 ESTOP_B 4B3> J2 4B5< ERESET_A_F
4D1< HOSTAUDP 29 29 30 30 HOSTIN_R
4D1> HOSTIN_L 31 31 32 32 S8
4C3< PATMIC_P 33 33 34 34 PATMIC_N 4C3< 4B5< ESTOP_A_F 1 1 GB25AP-XA AVCC_5V
RAW_+12V 35 35 36 36 RAW_+12V 4B5< ESTOP_B_F 2 2
37 37 38 38 8B1< FPGA_ESTOP 3 3
17B7> PATSPEAK_N 39 39 40 40 PATSPEAK_P 17B7> AVCC_5V R13 4 4 NC1 3
R66
4B5< ERESET_B_F 2 COM1
10K
10K 1
NO1
10K
0.1U
PIN PIN
STRAIGHT RIGHT_ANGLE NC2 6
B B
R31
RIBBON_CABLE_LOW_PROFILE WIRE_TO_BOARD 8B1< FPGA_ERESET 5 COM2
C12
HDR_STR_PLU_2MM_40 NO2 4
R32
C13
10K
0.1U
A
OC MIC VOLUME J7
R89 J5
4D3< OCVOL_A 1 1
0 PATVOL_A 1 OCVOL_C 2
4C3< 1 4D3> 2
RSV 4C3> PATVOL_C 2 2 2C6< 16B7> OCVOL_B_F OCVOL_B_F_T 4D5> 4D3< OCVOL_B 3 3
2C4< 14B6> PATVOL_B_F PATVOL_B 3 3 R109
FL8 100
R106
BLM31P601SG 100
4D3< 4D5> PIN
C 1 2 AVCC_5V PIN AVCC_5V STRAIGHT
C
WIRE_TO_BOARD
600 OHM PATVOL_B_F_T
A
U14
R105
R108
ADG802 U13 ADG802
10K
10K
JD1 JD2
JUMPER JUMPER
6 VDD GBLC05C 6 VDD
1 2 1 2
4 INPT D 1 CR24 4 INPT D 1 CR22
14B6> PATVOL_B_F 2 S 5 16B7> OCVOL_B_F 2 S 5

2C4< NC1 5V_STAND_OFF 2C6< NC1 5V_STAND_OFF
GND 3 GND 3
LOGIC 0 LOGIC 0
A A
LOGIC 0 CONNECT
D D
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GE Healthcare
Company Restricted
B Size
Wed Apr 22 13:35:54 2009 scancontrolbox 2 of 16 5337819SCH 3 2 of 16
1 2 3 4 5 6 7 8
2-2 OC
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SERVICE AND DEBUG

3V3 3V3 1K
R146
DS17
A 3V3 TP12 VCC TP13 AVCC_12V TP14 AVCC_5V TP7 AVCC_2.5V R23 8D5> PATVOICE_LED A
8D5> FPGAST_LED1 1 2
2
TIN TIN TIN TIN 1K
GREEN
GREEN
R139
3V3
DS18
1K
DS4
1 2 R69
8D5> FPGAST_LED
1K
R20
1
1K
R141
R30
10K GREEN
2
GREEN
1K
1K
R201
R12
100
DS6
2 DS19 3V3
2
DS8
R19
2
GREEN
HSMG-C190
1V2 SAFETY_LOOP_BACK
1 2
DS7
11B2> 8B1>
GREEN
GREEN
GREEN
GREEN
1
TP11
DS16
C 1K
R140 GREEN
B
DS1
DS2
1
1
Q1
TIN
1
1K MMBT3904
E
TP2 3V3
0
TIN R301
OC
R28 R29
JD8
B 3V3 10K 10K B
0.1W 0.1W
7B6> USB_AD0 1 2 OG_TXD 8D5>
12D1< 3C7> AS MODE J9 1% 1%
USB_+5V VCC
RSV JD7 2 1 FPGA_DCLK
JUMPER F3 JUMPER 2 1 8B1< 8B5<
RESETTABLE 4 4 3 3 FPGA_CONF_DONE 8C1>
0 1 2 FPGA_CE_N 6 5 FPGA_CONFIG_N
R302 8A1< 6 5 8A1< 8C1<
8A5< 8B1> FPGA_CS_N 8 8 7 7 FPGA_DATA0 8A8> 8B1<
1.1A RSV 10 9 FPGA_ASD

10 9 8B1> 8B5<
JD9 6V
7C6> USB_AD1 1 2 GO_RXD 8D1> 12C2< S1 R38 AS CONFIGRATION

KSC121G 10K
0.1W
RSV
JUMPER R144 1%
1 1 3 3 MRESET 5B5<
JD10 2 2 4 4 1K
12C6> 4A3< OGCOM_H_F 1 2 GOCOM_H_F 4A3> 12A1< RSV GND

0
R303 RSV
C JUMPER
C
JD13
JD11 OG_TXD_T 1 2 OG_TXD

12C5> 3B3> 8D5>
12D1<
VCC JD3
12C6> 4A3< OGCOM_L_F 1 2 GOCOM_L_F 4A3> 12A1< R135 RSV
1 2 JUMPER
3V3
1K
JUMPER
0.1W TALKON_DO
JUMPER 10B4<
1%
R143
10K
JD12 0.1W JD4
1%
1 2 TALK_SET 8D1< 10B3> TALKON_DI 1 2
JUMPER JUMPER
JD5
3
JD6 1 2
JUMPER
2 3
D 11C4< RELAY_DO 2 D
JUMPER
1
REV 2 01July04
1
11C4> RELAY_DI
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
OC 2-3
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FILTER
VCC
A RAW_VCC A
F1 FL2
FL15 FL22 RESETTABLE BLM31P601SG
NFA31CC222R1E4 NFA31CC222R1E4 1 2
1.1A 600 OHM
GOCOM_H 3 7 GOCOM_H_F 3 7 6V
2A1< A1 B1 3C3> 12A1< A1 B1
SM6T6V8CA
2A3< GOCOM_L 4 A2 B2 8 GOCOM_L_F 3C3> 12A1< 4 A2 B2 8
C10
0.1U
+80%-20%
2A1> OGCOM_H 5 A3 B3 9 OGCOM_H_F 3C1<
12C6> 2B1> SAFETY_A 5 A3 B3 9 SAFETY_A_F 11B5>
OGCOM_L 6 10 OGCOM_L_F SAFETY_B 6 10 SAFETY_B_F
6.8V
2A3> A4 B4 3C1<
12C6> 2B3> A4 B4 11B5>
25V
0.1U
C8
CR6
GND1 1 GND1 1
GND2 2 GND2 2
2200PF 2200PF
+5V POWER
FL16 FL26
NFA31CC222R1E4 NFA31CC222R1E4
RAW_+12V F2
OCXLED_H 3 7 OCXLED_H_F ERESET_A 3 7 ERESET_A_F FL4 600 OHM AVCC_12V
2A1< A1 B1 11A1< 2B1> A1 B1 2B6< RESETTABLE
2A3< OCXLED_L 4 A2 B2 8 OCXLED_L_F 11A1< 2B3> ERESET_B 4 A2 B2 8 ERESET_B_F 2B6< 1 2
B 2A1> RESET_H 5 A3 B3 9 RESET_H_F 12D6> 2B1> ESTOP_A 5 A3 B3 9 ESTOP_A_F 2B5<
1.5A
B
RESET_L 6 10 RESET_L_F ESTOP_B 6 10 ESTOP_B_F
15.15V
2A3> A4 B4 12D6> 2B3> A4 B4 2B5<
15V
GND1 1 GND1 1
C15
0.1U
GND2 2 GND2 2
C16
0.1U
CR18
FL28 600 OHM
2200PF 2200PF
1 2
A
+12V POWER
FL27
PATMIC_P2 1 2 PATMIC_P2_F 14A1<
FL1 BLM18PG221SN1 FL34
2A3< USB_DATA- 1 2 USB_DATA-_F 7B2< 2B1< PATMIC_P 1 2 PATMIC_P_F 14B1<
FL35
FL3 BLM18PG221SN1 2B3< PATMIC_N 1 2 PATMIC_N_F 14B1<
2A3< USB_DATA+ 1 2 USB_DATA+_F 7B2<
C FL17 C
16B1< OCMIC_P 1 2 OCMIC_P_F 2A5<
FL18
16B1< OCMIC_N 1 2 OCMIC_N_F 2A5<

2A1> SC1_TXD 1 2 SC1_TXD_F 12C2< 2C4< PATVOL_A 1 2 PATVOL_A_F 14B6>
FL25
FL6 BLM18PG221SN1 2C4> PATVOL_C 1 2 PATVOL_C_F 14B6<
2A1< SC1_RXD 1 2 SC1_RXD_F 12C5>
FL24
2C5< PATVOL_B 1 2 PATVOL_B_F_T 2C5>
FL7 BLM18PG221SN1
2B1< HOSTIN_L 1 2 HOSTIN_L_F 16C8>
FL19
2C6< OCVOL_A 1 2 OCVOL_A_F 16B7>

2B1> HOSTAUDP 1 2 HOSTAUDP_F 15B1<
2C6> OCVOL_C 1 2 OCVOL_C_F 16B7<
FL21
D D
2C8< OCVOL_B 1 2 OCVOL_B_F_T 2C7>
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Thu Mar 26 19:53:58 2009 scancontrolbox 4 of 16 5337819SCH 3 4 of 16
1 2 3 4 5 6 7 8
2-4 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
DIGITAL POWER& RESET
A A
VR1 U17
VCC LT1117-3V3 LT3021-1.2 1V2
3V3 VCC
3 VIN VOUT1 2 8 VIN VOUT 2

VOUT2 4
+80%-20%
C49 C69 5 SHDN_N SENSE 3
10U ADJ_GND 1 C64 0.1U
10V
10U
C52
10U 1 NC1 AGND 4
7 NC2 PGND 6 C66 C70
3.3V 10U 0.1U
1.2V
OC
VCC
B B
U33
1V2_PLLA VCC 10K ADM811
R33
1V2 L1 22N 1A 0.1W
1% R34
4 VCC RESET_N 2 RESET_N 8B1<
17B3<
C76 C80 C84 C88 C154 C155 C156
3 1 10K
1U 10U 10N 10N 0.1U 0.1U 0.1U MR_N GND
10V 25V 25V 25V 3C5> MRESET C11 C17 C19 C18
R35
0.1W
0.1U 10N 10N 10N
10K
1%
3.3V 25V
C9
0.1U
25V
A
1V2
3V3
C C
C48 C50 C53 C56 C58 C60 C62 C65
10V
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U

10U
C46
25V 25V 25V 25V 25V 25V 25V 25V

C158 C160 C161 C165 C166 C167 C162
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
25V 25V 25V 25V 25V 25V 25V
DECOUPLING CAPACITORS FOR FPGA
3V3
C47 C51 C57 C59 C61 C63 C67 C68 C71 C72 C73
C45 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
10U 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Fri Jan 16 09:59:26 2009 scancontrolbox 5 of 16 5337819SCH 3 5 of 16
1 2 3 4 5 6 7 8
OC 2-5
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
ANALOG POWER
A A
0 TP8
R67
AR2 AVCC_5V AVCC_2.5V
AVCC_12V LM2937IMP-5.0 AVCC_5V TIN
0.1W
1 VIN VOUT 3 U3
LM431
R200
0.25W
GND1 2
1%
49
C112 C29 C74 GND2 4 C75 C77 C137 R37
10U 0.1U 10N 0.1U 10N 10U 8 REF NC1 4
NC2 5
2 100
5V A1
3 A2 C 1
2
6 A3
GREEN
A 7
DS9
A4
A
C27
100U
10U
C28
A
2.5V TO 36V
1
B A
B
A
AVCC_5V
C79 C81 C82 C83 C85 C86 C89 C90 C91 C149 C14
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V
C C
MH2 MH4 MH6 MH10 MH13 MH17 MH20 MH23 MH24 MH25
MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00
MH3 MH5 MH9 MH12 MH16 MH19 MH26

MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00 MH3_05RD4_00
MH32 MH33 MH34 MH41 MH40

MH7 MH11 MH14 MH18 MH21 MH30 MH31 MH3_20 MH3_20 MH3_20 MH3_20 MH3_20
MH3_20 MH3_20 MH3_20 MH3_20 MH3_20 MH3_20 MH3_20
MH1 MH8 MH15 MH28 MH27 MH22 MH29 MH35

MH8_20RD9_70 MH9_00RD9_70 MH9_00RD9_70 MH9_00-8_20RD9_70 MH9_00RD9_70 MH9_00RD9_70 MH9_00RD9_70 MH9_00RD9_70
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Thu Apr 02 00:08:03 2009 scancontrolbox 6 of 16 5337819SCH 3 6 of 16
1 2 3 4 5 6 7 8
2-6 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
USB AND UART INTERFACE

VCC
60 OHM AT 100MHZ
C43
0.1U
2
A A
BLM21PG600SN1
FL9
C36
1
10N
R64
0.25W
1%
267
C37
0.47U
C38
C35
0.1U
0.1U
3V3
OC
B B
U11
+80%-20%
4C3< USB_DATA-_F
C40
C42
25V
0.1U
0.1U
FT2232D
14
46
42
31
4C3< USB_DATA+_F
VCCIOA
VCCIOB
VCC_2
C34
33N
VCC_1
AVCC
R62
33.2
AD0 24 USB_AD0 3B1<

AD1 23 USB_AD1 3C1>
R59
6 3V3OUT AD2 22
33.2
CR7 AD3 21
CR8 8 USBDM AD4 20
GBLC05C AD5 19
5V_STAND_OFF 7 USBDP AD6 17
AD7 16
R60 AC0 15
5 RSTOUT AC1 13
AC2 12
1.5K 11
AC3
C C31 27P C
43 XTIN SI/WUA 10
R58
2
1% 40 USB_D0
6MHZ
VCC BD0 8D5<

Y2
BD1 39 USB_D1 8D5<

10K 38 USB_D2
BD2 8D5<
C32 27P BD3 37 USB_D3 8D5<
1
44 XTOUT BD4 36 USB_D4 8D5<

BD5 35 USB_D5 8C5<
1% 33 USB_D6
BD6 8D5<
U12 BD7 32 USB_D7 8C5<
93C46 4 RESET
BC0 30 USB_RXF_N 8C5<
48 EECS BC1 29 USB_TXE_N 8C5<
8 VCC BC2 28 USB_RD_N 8C5>
1 EESK BC3 27 USB_WR_N 8C5>
6 ORG
1 CS SI/WUB 26 3V3
2 SK 2 EEDATA
R63
3 DI DO 4 47 TEST PWREN 41
7 5 1K
GND_D2
GND_D3
GND_D4
NC GND
GND_D1
AGND
D R61 D
9
18
45
25
34
10K
REV 2 01July04
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
OC 2-7
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
FPGA & CONFIGRATION &OCSILLATOR

U4 U4
EP2C5T144C8N 3V3 EP2C5T144C8N
A 3V3 BANK 1 BANK 2 1V2 1V2_PLLA 1V2 A

VCCIO1<2..0> VCCIO2<2..0> VCCINT<3..0> GND<16..0>
7 IO_7_VREFB1N0 IO_120_VREFB2N0 120 VCCA_PLL<1..0> GNDA_PLL<1..0>
28 IO_28_VREFB1N1 IO_132_VREFB2N1 132 VCCD_PLL<1..0> GND_PLL1<1..0>

GND_PLL2<1..0>
17 CLK0_LVDSCLK0P
18 CLK1_LVDSCLK0N SYM 1 OF 3
21 CLK2_LVDSCLK1P
8C8> C32M 22 CLK3_LVDSCLK1N U5
EPCS4
3B5< FPGA_CE_N 16 CE_N
8C1< 3B8> FPGA_CONFIG_N 20 CONFIG_N
3B5< 8B1> FPGA_CS_N 1 CS_N DATA 2 FPGA_DATA0 3B8> 8B1<
8B8> FPGA_TDO 10 TDO IO_143_LVDS13P 143 3V3
8C8> FPGA_TMS 11 TMS IO_144_LVDS13N 144 8B1< 3B8> FPGA_DCLK 6 DCLK
8C8> FPGA_TDI 13 TDI IO_141_LVDS14P 141
1K
8B8> FPGA_TCK 12 TCK IO_142_LVDS14N_NDEV_CLR 142 8B1> 3B8> FPGA_ASD 5 ASDI
IO_139_LVDS15P 139
R133
8A8> 3B8> FPGA_DATA0 14 DATA0 IO_137_LVDS15N 137 U30
8B5< 3B8> FPGA_DCLK 15 DCLK IO_136_LVDS16P 136 VCC=3V3;GND=GND
IO_135_LVDS16N 135
8B5< 3B8> FPGA_ASD 1 IO_1_ASDO IO_134_LVDS18P 134 2 IO GND 1 CONFIGRATION CHIP
8A5< 3B5< FPGA_CS_N 2 IO_2_NCSO IO_133_LVDS18N 133
31 IO_31_PLL1_OUTP IO_129 129
32 IO_32_PLL1_OUTN IO_126_LVDS22P 126 STOPMOVE 9C6> DS2431 3V3
17B3< 5B8> RESET_N 30 IO_30 IO_125_LVDS22N 125 STOPMOVE_LED 9D6 B
27 IO_27_LVDS3N IO_121_LVDS24N 121 STARTSCAN_LED 9B6<
12D1< TGP_RST3V3_N 24 IO_24_LVDS4P IO_119_LVDS25P 119 PAUSE 9A6> 3V3
11C1< SAFETY_LOOP_N 25 IO_25_LVDS4N IO_118_LVDS25N 118 PAUSE_LED 9B6< R25 R26 R27
2B6> FPGA_ERESET 8 IO_8_LVDS5P IO_115_LVDS27P 115 STOPSCAN 9A6> 10K 10K 10K
11B2>
3B5< SAFETY_LOOP_BACK 9 IO_9_LVDS5N IO_114_LVDS27N 114 STOPSCAN_LED 9B6< 0.1W 0.1W 0.1W
2B5> FPGA_ESTOP 3 IO_3_LVDS9P_CRC_ERROR IO_113_LVDS28P 113 MOVETOSCAN 9C6> JTAG J8 1% 1% 1%
11A5> XLEDON 4 IO_4_LVDS9N_CLKUSR IO_112_LVDS28N 112 MOVETOSCAN_LED 9D6< R22
10K
SYM 2 OF 3 0.1W 2 2 1 1 FPGA_TCK 8B1<

1% 4 4 3 3 FPGA_TDO 8B1>
6 6 5 5 FPGA_TMS 8B1<
8 8 7 7
10 10 9 9 FPGA_TDI 8B1<
U4 JTAG CONFIGRATION
EP2C5T144C8N
3V3 BANK 3 BANK 4 3V3

VCCIO3<2..0> VCCIO4<2..0>
99 IO_99_VREFB3N0 IO_63_VREFB4N0 63
79 IO_79_VREFB3N1 IO_51_VREFB4N1 51
C C
91 CLK4_LVDSCLK2P
R24 90 CLK5_LVDSCLK2N
10K 89 CLK6_LVDSCLK3P
0.1W 88 CLK7_LVDSCLK3N 3V3
1% Y1
82 STATUS_N
IO_71_LVDS43P 71 USB_RD_N 7D6< FL50 R36
3B8> FPGA_CONF_DONE 83 CONF_DONE IO_72_LVDS43N 72 USB_WR_N 7D6< 1 2 4 VCC VOUT 3 C32M 8A1<
85 MSEL0 IO_69_LVDS44P 69 USB_RXF_N 7C6<
84 70 USB_TXE_N 1 2 33.2
MSEL1 IO_70_LVDS44N 7D6<
67 USB_D7 ENABLE GND
IO_67_LVDS45N 7C6<
C151
47P
8A1< 3B8> FPGA_CONFIG_N 103 IO_103_PLL2_OUTP IO_64_LVDS46P 64 USB_D5 7C6< C78
104 IO_104_PLL2_OUTN IO_65_LVDS46N 65 USB_D6 7C6< 0.1U 32MHZ
12A6> V_C3V3_1 101 IO_101_LVDS30P IO_59_LVDS51P 59 USB_D2 7C6<
12A6> V_C3V3_2 100 IO_100_LVDS30N IO_60_LVDS51N 60 USB_D3 7C6<
12B6> V_C3V3_3 97 IO_97_LVDS33N IO_57_LVDS52P 57 USB_D0 7C6<
12B6> V_C3V3_4 96 IO_96_LVDS34P IO_58_LVDS52N 58 USB_D1 7C6<
10B6> TALKON3_3 94 IO_94_LVDS34N IO_53_LVDS53P 53 USB_D4 7C6< 3V3
10C5< 14D7> PAT_VOICE 93 IO_93_LVDS35P IO_55_LVDS53N 55 GREEN R11
TALKON 92 52 DS5 1 2 100
16B6< IO_92_LVDS35N IO_52_LVDS54P
14B4< TALKON_N 87 IO_87_LVDS36P IO_47_LVDS55P 47
10B6<
10C5< TALKON_LED 86 IO_86_LVDS36N IO_48_LVDS55N 48 FPGAST_LED1 3A5<
12C2< 3C3< GO_RXD 81 IO_81_LVDS37P IO_44_LVDS56P 44 R300
TALK_SET 80 45 1K OG_TXD
3D3> IO_80_LVDS37N IO_45_LVDS56N 3B3> 3C7> 12D1<
TP3 DEBUG1 76 IO_76_LVDS41P_NCEO IO_42_LVDS57P 42 PATVOICE_LED 3A7<
D TP4 DEBUG2 75 IO_75_LVDS41N_INIT_DONE IO_43_LVDS57N 43 D
TP5 DEBUG3 74 IO_74_LVDS42P IO_41_LVDS58P 41 XRAYON_LED 11A6<
15B5< AUTOVOICE_CTRL 73 IO_73_LVDS42N IO_40_LVDS58N_DEV_OE 40 FPGAST_LED 3A5<
REV 2 01July04
SYM 3 OF 3
10C4<
GE Healthcare
Company Restricted
B Size
Tue Mar 31 15:40:57 2009 scancontrolbox 8 of 16 5337819SCH 3 8 of 16
1 2 3 4 5 6 7 8
2-8 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
BUTTONS & LEDS

VCC
U1
74LVTH244
R6
R7
R8
1K
1K
1K
A A
19 OE_N RSV
J25
STARTSCAN_KEY 1K 11 9 STARTSCAN J17 RSV

R14 A1 Y1 8B5<
PAUSE_KEY 1K 13 7 PAUSE 1 2 PAUSE_KEY
R16 A2 Y2 8B5< 10C5<
2 1 STOPSCAN_KEY 1K 15 5 STOPSCAN 1 2 STARTSCAN_KEY
R17 A3 Y3 8B5< 10C4<
17 A4 Y4 3
GREEN
J26 RSV
RSV
0.1U
0.1U
0.1U
C4
C5
C1
DS13 J18
VCC=3V3;GND=GND
START SCAN 1 2
4
1 2
5V_STAND_OFF
J27 RSV
J19 RSV
1 2
2 1 1 2
SRV05_4
CR3
GREEN RSV
J28
3
DS14 1 J20 RSV
U1
PAUSE 74LVTH244 1 2
1 2
OC
OE_N 1
B 100
B
R1 18 Y1 A1 2 STARTSCAN_LED 8B5>
100 16 4 PAUSE_LED
R2 Y2 A2 8B5>
2 1 100 14 6 STOPSCAN_LED
R3 Y3 A3 8B5>
12 8 J21 RSV
Y4 A4
GREEN
6
DS15 4 1 2 STOPSCAN_KEY 10C4<

VCC=3V3;GND=GND
STOP SCAN
5V_STAND_OFF J22 RSV
VCC 1 2
SRV05_4
CR2
J23 RSV
U2
74LVTH244
2
3
1
R10
R9
1 2
1K
1K
1 OE_N
R15
MOVETOSCAN_KEY 1K 2 18 MOVETOSCAN J24 RSV
A1 Y1 8B5<
C 4 A2 Y2 16 C
2 1 R18 6 A3 Y3 14 1 2
STOPMOVE_KEY 1K 8 12 STOPMOVE
A4 Y4 8B5<
GREEN
6
DS12
VCC=3V3;GND=GND
0.1U
0.1U
C2
C3
5V_STAND_OFF
J13 RSV J29 RSV

MOVE TO SCAN
1 2 MOVETOSCAN_KEY 10C5< 1 2 STOPMOVE_KEY 10C4<
U2
SRV05_4
74LVTH244
J14 RSV J30
CR1
RSV
OE_N 19
1 2 1 2
2
3
1
100 9 11 MOVETOSCAN_LED
R4 Y1 A1 8B5>
2 1 100 7 13 STOPMOVE_LED
R5 Y2 A2 8B5>
5 Y3 A3 15
3 17 J15 RSV J31
GREEN Y4 A4 RSV
DS11 1 2 1 2
VCC=3V3;GND=GND
STOP MOVE
J16 RSV J32 RSV
D D
1 2 1 2
REV 2 01July04
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
OC 2-9
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A TALK ON A
VCC
R137
AVCC_5V
1K
GREEN
2
R121
U6
DS10
1K
74VHC_AHC14 U27
J33
RSV 74AHC1G14
R131
1 2 TALK_KEY TALKON_DI 3D3< 3C5> TALKON_DO 13 A B 12 TALKON3_3 8D1< 8D1>
10C5< TALKON_LED 2 4
1
A Y
1K
VCC=3V3;GND=GND VCC=VCC
J34 RSV
C145 GND=GND
10N
B 1 2 B
CR20
GBLC05C
A 5V_STAND_OFF
TALK ON CONTROL
J10
VCC
C 2 2 1 1 TALKON_LED 8D1> 10B6<

C
9A7< STARTSCAN_KEY 4 4 3 3 PAUSE_KEY 9A8<
9B7< STOPSCAN_KEY 6 6 5 5 MOVETOSCAN_KEY 9C7<
9C8< STOPMOVE_KEY 8 8 7 7 PAT_VOICE 14D7> 8D1<
8D1< DEBUG1 10 10 9 9
AS CONFIGRATION
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
2-10 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
TGP SIGNALS (1)

XRAY_ON VCC
A A
AVCC_5V
R41
0.1W
1%
332
R39 U7
4B3> OCXLED_H_F HCPL0631
R21
VCC
MMSD4148
1K
33.2 DS3
U6 U31
8
100V
VCC 74VHC_AHC14 74AHC1G14 RED
D4 1 VO R42 8D5> XRAYON_LED 2

A Y
4 1 2
R40 7 1 A B 2 XLEDON 8B1<
4B3> OCXLED_L_F 2
GND 5 100 HLMP-1700
VCC=AVCC_5V
33.2 0.1W
VCC=3V3;GND=GND GND=GND_ANALOG
1%
10%
C20
50V
10N
SAFETY_A_F 4A5<
OC
K1 SAFETY_B_F 4A5
3B5< SAFETY_LOOP_BACK 6
5 1K
VCC 1
8
MMSD4148
100V
D3
RELAY_DO 3D1>
VCC
RELAY_DI 3D1<
C C
R68
0.1W
1%
1K
U29
74AHC1G14 D
R129 R53
SAFETY_LOOP_N 2 4 G Q5
8B1> A Y 2N7002
100 100
S
VCC=VCC
10%
C148
GND=GND
50V
10N
0.1U
C7
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
OC 2-11
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
TGP SIGNALS(2)
A A
VCC U6
U9 74VHC_AHC14
HCPL0631 VCC
R45
0.1W
U6
1%
332
9 8 V_C3V3_1
10%
R43 8D1<
50V
10N
C21
74VHC_AHC14 A B
GOCOM_H_F 33.2 8
4A3> 3C3> VCC
R50
GOCOM_L_F 1% 0.1W 1 3 4
4A3> 3C3> VO<1> A B VCC=3V3;GND=GND
7 V_C3V3_2 8D1<
2 100
R44
33.2 0.1W
VCC=3V3;GND=GND
4 1% V_C3V3_3
VO<0> U6 8D1<
1% 0.1W 6 R49 74VHC_AHC14
3
5 U6
100 5 6
GND A B 74VHC_AHC14
0.1W
R46
10%
0.1W
50V
C22
10N
1%
332
1%
VCC=3V3;GND=GND 11 A B 10 V_C3V3_4 8D1<
VCC
VCC VCC=3V3;GND=GND
C26
B 0.1U
B
C24
U10
0.1U MAX232A
VCC
16 VCC
2 VP
C25 6 VN
C23 1 C1P
0.1U 3 C1M
4 C2P
0.1U 5 C2M
FPGA 3C3< 8D1> GO_RXD 11 T1IN T1OUT 14 SC1_RXD_F 4D3>

10 T2IN T2OUT 7
TGP CONTROL SERIAL PORT TX 4C3< SC1_TXD_F 13 R1IN R1OUT 12 OG_TXD_T 3C5<
8 R2IN R2OUT 9
C TO TGP C
WITH HOST GND 15
U8
DS26C31T
OG_TXDH 33.2
R47
VCC 12 EN_N OGCOM_H_F 3C1<
4A3<
4 OG_TXDL 33.2 OGCOM_L_F
EN R48 4A3<
3C1<
RESET_H_F 4B3<
OG_TXD 1 2 TGP_RESET_H 33.2 RESET_L_F
3B3>
8D5>
3C7> I<3> OUTP<3> R51 4B3<
OUTN_N<3> 3
TGP_RST3V3_N 7 6 TGP_RESET_L 33.2
8B1< I<2> OUTP<2> R52
OUTN_N<2> 5
9 I<1> OUTP<1> 10
OUTN_N<1> 11
6
15 I<0> OUTP<0> 14
OUTN_N<0> 13
5V_STAND_OFF
VCC=VCC;GND=GND
D D
SRV05_4
REV 2 01July04
CR5
3
1
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
2-12 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
AVCC_2.5V
R111
2.21K
C6 0
R114
4C5> PATMIC_P2_F 47N
PATIENT MIC IN
A AVCC_2.5V A
AVCC_2.5V CR23 AVCC_5V C300
470PF
R107 AVCC_2.5V AVCC_5V TP18
U25
2.21K
10K
10K
A
MAX4502 TIN
TP16
2
VREF
VN
6 VDD 4
5
VSP 7
TIN VOUT
R115
R117
AR1 C136 R128 R136 1 OCSPEAK 17B1<
0 TALKON_N 4 INPT D 1 PATVOL_A_F PATVOL_C_F 3
R112 LT1167 8D1> 4C5> 4C5<
PATMIC_P_F C55 47N 2 TLV2461
VP
4C5>
3 6 2 S 5 0.1U 100K 200K U28
5
PATMIC_N_F C125 47N 1 VOUT NC1 0.1W
4C5> R1
R134
1%
220PF
8 3 AVCC_2.5V
C139
200K
0.1W
R113 GND
27P
10K
1%
R2
4 VSN
0 1K AVCC_5V
R96
TP17 LOGIC 0 A PATVOL_B_F 2C4< 2C4<
TIN
R119
R142
C144
LOGIC 0 CONNECT
OC
2.21K
R123
0.1W CW
B A
B
R215
CR16 CR17
CW
AVCC_2.5V
20K A
39.2K
USE INA AND HIGH ACCURACY RESISTOR CR19
20K
TO IMPROVE CMR
TP1 CR21
GBLC05C
R147
5V_STAND_OFF
C127
0.1U
TIN
A
A
R110
AVCC_2.5V AVCC_5V AVCC_5V

10K
ASUME INPUT PSOUND=50~70DB
PV_IN=PSOUND-94-44=-88~-68DBV
1K
REF LMV1012 DATASHEET P10
R149 10K
C128
U21
0.1U
R130
SSM2167
R148
10K
10 VDD OUTPUT 9
10K C132
R99
C 5 INPUT
C
C142 GATE_THRS 7
0.1U 2 VCAIN
C41 RSV 8
COMPRESSION_RATIO
10U 4 BUF_OUT AVG_CAP 6
AVCC_2.5V 1N RSV 3 1
R82 R95 R98 SHUTDOWN_N GND
10V
C143 10U
39.2K
R56 R57
150 49.9K 100K 2 BAV99 1
39.2K AVCC_5V 0.1W K A
AK
1%
R65
U26
10K
AVCC_2.5V D1 A
U26 TLV2464
4
VP
TLV2464 10 R122
4
VP
12 C126 8
14 9 VOUT
100K
VN
13 VOUT U26
VN
0.1U
C134
4
0.1U
11
VP
1K
R90
3
100K
TLV2464 R126
11
AVCC_5V 1 PAT_VOICE 8D1< 10C5<

2 VOUT
VN
A
R124 AVCC_2.5V R125

11
R127
39.2K
AVCC_2.5V
1K
R116
100K
147K
R210
D U26 D
4
VP
5 CW A
TLV2464
7
6 VOUT 20K
REV 2 01July04
VN
10%
C131
16V
2.2U
11
GE Healthcare
Company Restricted
B Size
AVCC_2.5V Block Path Block Sheet Dwg No Rev Sheet
Fri Apr 24 16:58:07 2009 scancontrolbox 13 of 16 5337819SCH 3 13 of 16
1 2 3 4 5 6 7 8
OC 2-13
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A
HOST AUDIO OUT A
AVCC_2.5V
C133 27P 50V

1%
AVCC_5V
AVCC_5V AVCC_2.5V 1K 1%
R97 R102
0.1W
10K
10K
R86
4.7K
0.0625W
0.1%
R85
ADG802 U24
A
2
0 0
VN
C140 R83 6 VDD 4 R132
5
VOUT
VP
4D3> HOSTAUDP_F 3 C141 1 HOSTAUD 16C1<
1 AUTOVOICE_CTRL 4 INPT D 1 3
8D1>
22N 4 VOUT TLV2461 0.1W
VP
R138 10K
B 25V
B
VN
2 S 5 22N U32
5
10% U18 NC1 25V
27P
2
TLV2461 10%
GND 3 AVCC_5V
R92 10K
GBLC05C A LOGIC 0
CR13
C129
5V_STAND_OFF A
LOGIC 0 CONNECT
AVCC_2.5V
A
ABOUT VPP=0.75V
A
INPUT FROM HOST VPP 0~1.5V
C C
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
1 2 3 4 5 6 7 8
Approved Document - 5337819SCH r3 pdf Page 15 of 17
2-14 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
OC MIC IN
A
A A
AVCC_5V
GBLC05C
C130 27P RSV

AVCC_5V CR14
AVCC_2.5V 100K R100 5V_STAND_OFF

R91 R94
10K U22
AVCC_2.5V
10K
MAX4502 POTENTIOMETER
RSV
AVCC_5V 6 VDD
10K
10K
R79 A 0
U19 R120
2.21K SSM2167 8D1> TALKON 4 INPT D 1 OCVOL_A_F 4D5> 4D5< OCVOL_C_F OCMIC 16C1<
2
R87
R88
VN
4 VOUT
C30 1 2 S 5 OCVOL_B_F 0.1W
2C6< 2C6<
C122 0 10 9 3 NC1
R80 VDD OUTPUT
TLV2461 3
VP
GND
4C3< OCMIC_P_F 5 INPUT 22N U20
5
1U 0.1W C33 7 25V LOGIC 0
GATE_THRS
10K
OCMIC_N_F 2 10% AVCC_5V GBLC05C
4C3<
R84 100K
VCAIN
8 A
COMPRESSION_RATIO LOGIC 0 CONNECT
R93
10U 4 BUF_OUT AVG_CAP 6 CR15
OC
3 SHUTDOWN_N GND 1 5V_STAND_OFF
R77 AVCC_2.5V
10V
10U
C44
B 0 B
0.1W CR12 AVCC_2.5V
GBLC05C A
5V_STAND_OFF
A
C135 27P RSV
R54
TP15 10K
TIN
A
C39 R103
2
10K
VN
4 VOUT R104
C123 1N 1 HOSTIN_L_F 4D3<
C 0.1U 25V 3 C
TLV2461 1K
VP
R101 10K
100K AVCC_2.5V U23
R75 R81
5
15B8> HOSTAUD AVCC_5V
200K
100K 0.1W
R76
1%
TO HOST IN
16B8> OCMIC
A
2
AVCC_2.5V
VN
4 VOUT
1K 1 PATSPEAK
R78 17B1<
AVCC_2.5V 3
TLV2461
VP
U16
5
AVCC_5V
C124
0.1U
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Mon Mar 30 13:33:55 2009 scancontrolbox 15 of 16 5337819SCH 3 15 of 16
1 2 3 4 5 6 7 8
OC 2-15
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
POWER AMPLIFIER
A A
AVCC_12V
C120 C121
TP21 L8 22U 1.9A FL12 10U 0.1U
C106 1 2 PATSPEAK_P 2B3> 25V 25V
TIN
C110
SMAJ12A
U15 0.47U 16V 0.68U
10%
TPA3005D2 C113
14V
CR11
A
0.68U
16V 50V
OCSPEAK C92 0.47U 10% 3 14 AVCC_12V
14B8> RINP PVCCL0 RSV
2 RINN PVCCL1 15 C107 A
C93 0.47U PGNDL0 18 A
A
LOUTP0 20
B 16C3> PATSPEAK C94 0.47U 5 LINP LOUTP1 21 0.47U C116 C118 B
6 LINN BSLP 24 FL13
C95 0.47U 1 2 PATSPEAK_N 2B1> 10U 0.1U
A
L9 22U
SMAJ12A
8B1< 5B8> RESET_N 1 SHUTDOWN_N PVCCL2 22 1.9A C111
C96 0.47U 4 V2P5 PVCCL3 23
14V
CR10
A
25 VCLAMPL PGNDL1 19
36 16 A
VCLAMPR LOUTN0
C97 1U 29 AVDD LOUTN1 17
28 COSC BSLN 13
27 ROSC AVCC_12V
C98 1U A
PVCCR0 38
7 AVDDREF PVCCR1 39 C117 C119
C99 1U 9 GAIN0 PGNDR0 42 10U 0.1U
10 GAIN1 ROUTP0 40 FL10 25V 25V
R71 R73 26 41 1 2 OCSPEAK_P 10% +80%-20%
AGND0 ROUTP1 2A6>
C100 220P 10K 10K AVCC_12V BSRP 37 L6 22U
0.1W 33 AVCC 1.9A C108
SMAJ12A
R70 1% C104 0.68U
121K 8 46 0.47U 50V
RSV NC1 PVCCR2 C138
14V
11 47 A
CR9
C102 C103 NC2 PVCCR3 0.68U
10U 0.1U 12 NC3 PGNDR1 43 50V
C 25V 25V 31 44 AVCC_12V C
470U
20%
C101
NC4 ROUTN0 RSV

25V
R72 R74 10% +80%-20% 32 45 A

NC5 ROUTN1
34 48 A
10K 10K NC6 BSRN
RSV 35 NC7
C105
30 AGND1 PPAD 49 0.47U FL11 C114 C115
1 2 OCSPEAK_N 2A6> 10U 0.1U
L7 22U
SMAJ12A
A A
1.9A
C109
14V
CR4
A
0.68U
REFENRENCE SLOA119A AND SLOA103A FOR MORE INFORMATION

ABOUT THE FILTER.
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Fri Apr 24 17:04:35 2009 scancontrolbox 16 of 16 5337819SCH 3 16 of 16
1 2 3 4 5 6 7 8
2-16 OC
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
GANTRY
TABLE OF CONTENTS
SECTION PAGE
SECTION 1 - GANTRY ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1-1 GANTRY ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1-2 GANTRY ASSY FOR EMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
SECTION 2 - TGP BD ASSY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table of Content
SECTION 3 - OGP BD ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SECTION 4 - DTB BD ASSY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4-1 DTB DB ASSY (5270966) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 DTB DB ASSY (5270966-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
SECTION 5 - TEMP CONT ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
SECTION 6 - S-DISP ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
SECTION 7 - X-DISP ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
GANTRY i
Brivo CT315
Brivo CT325
ii GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 1 - GANTRY ASSY

1-1 GANTRY ASSY

㪝㪠㪙㪜㪩
㪌㪊㪉㪈㪍㪉㪊㪈㪇㪆㪈㪇㪇㩷㪹㪸㫊㪼㩷㪫㪌㪊㪉㪈㪍㪉㪉
㪈
# 㪫㪦㩷㪦㪚㩷㪥㪠㪚
#
㪡㪊
DTB BD ASSY
㪡㪉
㪜㫋㪿㪼㫉㫅㪼㫋㩷㪺㪸㪹㫃㪼㪉
㪡㪈
㪌㪊㪊㪐㪈㪏㪌㩺㪈㪋㩷㪞㪩㪥㪆㪰㪜㪣㪡㪈
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪞㪸㫅㫋㫉㫐㩷㪝㫉㪸㫄㪼㪌㪉㪎㪇㪐㪍㪍㪄㪯
RF
㪌㪊㪉㪈㪋㪏㪋
㪈㪉
㩺㪉㪉㪦㪩㪥㩷㪈 FAN FAN
㪌㪊㪉㪐㪎㪍㪌㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼㩺㪉㪉㪮㪟㪫㪊
RCV
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪞㪸㫅㫋㫉㫐㩷㪝㫉㪸㫄㪼㪡㪉
㪬㪇㪌㪈㪌㪘㪤
㪚㪌㪊㪉㪈㪍㪉㪏㩺㪋㩷㪙㪣㪢㩷㪈㪈㪣㪼㪽㫋㩷㪫㫆㫇㩷㪝㪘㪥㩷㪘㪪㪪㪰
㪉
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪟㪭㩷㪧㪮㪩㪙㪌㪊㪉㪈㪍㪉㪎㩺㪋㩷㪙㪣㪢㩷㪉
㪘㪌㪊㪉㪈㪍㪉㪍㩺㪋㩷㪙㪣㪢㩷㪊
FAN FAN
㪡㪎㪄㪉㩺㪈㪋㪣㪄㪙㪣㪬㪋
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪈㪈㪌㪭㫋㫆㩷㪪㪣㪠㪧㩷㪩㪠㪥㪞
㪡㪎㪄㪈㪌㪊㪉㪈㪍㪊㪇㩺㪈㪋㪙㪩㪥㪌
㪌㪊㪇㪌㪍㪎㪋㪄㪯
㪌㪊㪉㪈㪍㪉㪐㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪍
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪈
㪉
㪡㪌㪄㪈㩺㪈㪍㪙㪩㪥㪣
㪌㪊㪉㪈㪊㪏㪏
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㪡㪌㪄㪉㪌㪊㪉㪈㪍㪉㪋㩺㪈㪍㪣㪄㪙㪣㪬㪥
㩺㪉㪉㪦㪩㪥㩷㪌㪊㪉㪈㪌㪊㪋㪈 FAN FAN
$ 㩺㪉㪉㪮㪟㪫㪊
$
㩺㪈㪏㩷㪞㪘㪩㪰㩷
㩺㪈㪏㩷㪩㪜㪛㩷
PS 㪉㪋㪭 M Signal
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㪡㪊㪌㪊㪊㪉㪎㪌㪐㪫㪦㩷㪦㪚㩷㪸㫅㪻㩷㪣㪚㪛 U
Brush 㪬㪇㪌㪈㪌㪘㪤
㪌㪈㪌㪐㪇㪐㪎 X 㪈
㪞㪘㪥㪫㪩㪰㩷㪘㪥㪛㩷㪉
㪩㫀㪾㪿㫋㩷㪫㫆㫇㩷㪝㪘㪥㩷㪘㪪㪪㪰
GANTRY
㩺㪈㪏㩷㪞㪩㪘㪰
㪌㪊㪉㪋㪎㪋㪇㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪫㪘㪙㪣㪜㩷㪞㪥㪛
㩺㪈㪏㩷㪩㪜㪛
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛
FAN FAN
㪡㪍㪄㪈㩺㪈㪍㪩㪜㪛㩺㪈㪏㪩㪜㪛㪈
㪌㪊㪉㪏㪐㪏㪍
㪡㪍㪄㪉㪌㪊㪉㪋㪈㪌㪎㩺㪈㪍㪞㪩㪘㪰㩺㪈㪏㪞㪩㪘㪰
㪫㪦㩷㪧㪛㪬㩷㪛㪚㩷㪉㪋㪭㪉
㩺㪈㪏㪩㪜㪛㪈
㩺㪈㪏㪞㪩㪘㪰
㪉
㪡㪉㪄㪈㪌㪊㪉㪈㪊㪏㪍㪩㪜㪛㩺㪈㪏㩺㪈㪏㩷㪩㪜㪛㩷㩺㪈㪏㩷㪩㪜㪛㩷㪌㪊㪉㪈㪌㪊㪎
㪈
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪛㪚㩷㪉㪋㪭㪡㪉㪄㪉㪞㪩㪘㪰㩺㪈㪏㩺㪈㪏㩷㪞㪘㪩㪰㩷㩺㪈㪏㩷㪞㪩㪰㩷㪉
㪉
㪈
㪚㪥㪈
㪉
㪈
㩺㪈㪏㩷㪞㪩㪰
㪉㩺㪉㪉㪌㪊㪉㪈㪊㪐㪌㪌㪊㪉㪈㪍㪈㪏㪈

㩺㪈㪋㩷㪞㪩㪥㪆㪰㪜㪣㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪚㪥㪈㪚㪥㪎㪚㪥㪈㪇㪈 XDISP BD ASSY
㪈㩺㪉㪉
㪉㪉
㪌㪊㪈㪌㪉㪐㪈
㪪㪫㪜㪧㩷㪤㪦㪫㪦㪩㩷
㪈㪉
㪘㪪㪪㪰㪧㪜
㪚㪥㪊㪦㪝㪞㪈㩺㪉㪉㪮㪟㪫㪈㪇
% %
㪈㩺㪈㪏㪦㪩㪥㪉㩺㪉㪉㪙㪣㪢㪉㪇
㪉㩺㪈㪏㪩㪜㪛㪈㪊㩺㪉㪉㪙㪩㪥㪈㪈㪌㪊㪉㪈㪊㪐㪉
STEP
㪊㩺㪈㪏㪙㪣㪬㪉㪋㩺㪉㪉㪰㪜㪣㪈㪐
㪈
㪉
㪙㪩㪥
㪙㪣㪢㪦㪧㪫
㪞㪄㪧㪬㪣㪪㪜㪈
MOTOR 㪚㪥㪉 DRIVE BOARD 㪌㩺㪉㪉㪮㪟㪫㪉㪉㪌㪊㪉㪈㪊㪐㪍㪚㪥㪏㪬㪇㪇㪇㪉㪧㪙
㪋㩺㪈㪏㪰㪜㪣㪊㪊㪙㪣㪬㪪㪮
ASSY 㪋㪚㪥㪈㪍㩺㪉㪉㪞㪩㪥㪐
㪎㩺㪉㪉㪭㪠㪦㪣㪜㪫㪈㪉
㪦㪝㪞㪏㩺㪉㪉㪞㪩㪘㪰㪉㪈
㩺㪈㪋㩷㪞㪩㪥㪆㪰㪜㪣
㪚㪥㪈㪈㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪪㪮
㪌㪊㪉㪈㪊㪏㪐
㪚㪩㪘㪛㪣㪜㩷 CRADLE 㪈㩺㪉㪉㪩㪜㪛㪍㪚㪥㪊
㪈
㪉
㪩㪜㪛
㪙㪣㪢㪙㪣㪢
㪧㪦㪫㩷 POT 㪉㩺㪉㪉
㩺㪉㪉
㪰㪜㪣
㪙㪣㪢
㪎
㪏
㪉㪊㪏㪏㪉㪊㪇㩺㪈㪏㪉㪊㪏㪏㪉㪊㪇
㪊㩺㪈㪏
㪘㪪㪪㪰 ASSY
TGPL BD ASSY 㪝㪩㪦㪥㪫㩷㪣㪜㪝㪫㪝㪩㪦㪥㪫㩷㪩㪠㪞㪟㪫
㪪㪟㪠㪜㪣㪛
㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪪㪮
㪌㪊㪉㪈㪍㪉㪈
㪌㪊㪉㪈㪊㪐㪈㪌㪊㪉㪈㪍㪇㪎㪩㪜㪛
㪉㪈
㪜㪥㪚㪦㪛㪜㪩㩷㪌㪊㪈㪇㪐㪐㪇㪄㪯 DISP/ 㪙㪣㪢㪙㪣㪢
㪡㪈
㪈㩺㪉㪉㪮㪟㪫㪈㪚㪥㪍
㪡㪉
㪈㪙㪩㪥㪉㪌㪊㪉㪉㪏㪈㪉㩺㪈㪏㪌㪊㪉㪉㪏㪈㪉
㪉㩺㪉㪉
㪘㪪㪪㪰㪊
㪉
㩺㪉㪉㪩㪜㪛㪊 CONTROL 㩺㪈㪏
ENCODER
ASSY 㪋
㪊
㪋㩺㪉㪉㪙㪣㪢㪋 PANEL 㪝㪩㪦㪥㪫㩷㪚㪦㪭㪜㪩㩷㪣㪜㪝㪫㪝㪩㪦㪥㪫㩷㪚㪦㪭㪜㪩㪩㪠㪞㪟㪫
㪌
㪍㪌㪊㪈㪌㪊㪏㪈
㩺㪉㪉㪙㪣㪢㪈㪍
㪣㪘㪫㪚㪟㩷㪪㪮㩿㪩㪀㪰㪜㪣㩺㪉㪉㪰㪜㪣㪈㪎㪈㪤㫀㪺㪂㪮㪟㪫㩺㪉㪋㪌㪊㪉㪈㪊㪐㪐㪌㪊㪉㪈㪍㪉㪇㪮㪟㪫㩺㪉㪋
㪈㪉㪌㪉㪤㫀㪺㪄㪩㪜㪛㩺㪉㪋㪈
㪉
㪩㪜㪛㩺㪉㪋㪤㪠㪚㪝㫉㫆㫅㫋㩷㪤㪠㪚㪩㪦㪧㪟㪦㪥㪜
㪉㪍㪚㪥㪌㪚㪥㪈㪏㪊㪪㪿㫀㫃㪼㪻㩺㪉㪋㪉㪈㪈㪈㪐㪌㪌
㪉㪈㪊
㪙㪣㪢㪈㩺㪉㪉㪙㪣㪢
㪰㪜㪣㪉㩺㪉㪉㪮㪟㪫㪤㫀㪺㪂㩺㪉㪋㪌㪊㪉㪈㪊㪐㪏㪌㪊㪉㪈㪍㪈㪐㪮㪟㪫㩺㪉㪋
㪈㪮㪟㪫
& &
㪉
㪈㪉㪤㫀㪺㪄㪩㪜㪛㩺㪉㪋㪈
㪉
㪩㪜㪛㩺㪉㪋㪤㪠㪚㪩㪼㪸㫉㩷㪤㪠㪚㪩㪦㪧㪟㪦㪥㪜
㪚㪥㪈㪉
㪉㪪㪧㪜㪘㪢㪜㪩㪊㪪㪿㫀㫃㪼㪻㩺㪉㪋㪉㪈㪈㪈㪐㪌㪌
㪚㪥㪋
㪚㪥㪐㪊
㪚㪥㪉
㪙㪣㪢
㪣㪘㪫㪚㪟㩷㪪㪮㩿㪣㪀
㪈㪉
㪈㪐
㪈㪏
㪉㪋
㪌
㪈㪍
㪈㪇
㪉㪇
㪍
㪈㪋
㪈㪌
㪈
㪐
㪉㪈
㪉㪊
㪏
㪉㪉
㪉
㪋
㪈
㪉
㪊
㪋
㪌
㪍
㪍
㪈
㪌
㪊
㪋
㪉
㪪㫆㫃㫀㪻㩷㪪㫋㪸㫋㪼㩷㪩㪼㫃㪸㫐
㪮㪟㪫
㪩㪜㪛
㪙㪣㪬
㪟㫆㫄㪼㩷㪝㫃㪸㪾
㪜㪩㪩㪦㪩㪶㪧㪈
㪚㪟㩷㪙㩷㪥
㪛㫉㫀㫍㪼㫉㪶㪜㪥
㪙㪣㪢
㪜㪩㪩㪦㪩㪶㪧㪉
㪚㪟㩷㪙㩷㪧
㪚㪟㩷㪘㩷㪥
㪚㪟㩷㪘㩷㪧
㪝㪘㪬㪣㪫㪶㪩㪜㪪㪜㪫㩺㪉㪋
㪛㪠㪥㪧㩷㪚㪦㪤
㪙㪩㪘㪢㪜㪂
㪙㪩㪘㪢㪜㪄
㪚㪟㩷㪱㩷㪥
㪚㪟㩷㪱㩷㪧
㪚㪘㪥㪄㪟
㪭㪄
㪙㪣㪢
㪚㪘㪥㪄㪣
㪭㪂
㪪㪟㪠㪜㪣㪛
㪰㪜㪣
㪌㪊㪉㪈㪊㪐㪇
㪝㪩㪦㪤㩷㪦㪚㩷㪪㪚㪙
㩺㪉㪉㪮㪟㪫
㩺㪉㪉㪙㪩㪥
㩺㪉㪉㪩㪜㪛
㩺㪉㪉㪙㪣㪢
㩺㪉㪉㪙㪣㪬
㩺㪉㪉㪰㪜㪣
㪝㫌㫊㪼
㩺㪈㪏㪙㪣㪢
㩺㪈㪏
㩺㪈㪏
㩺㪈㪏㪩㪜㪛
㩺㪈㪏
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㪤㪦㪣㪛㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪌㪊㪉㪈㪍㪇㪌㪪㪘㪝㪜㪫㪰㩷㪣㪦㪦㪧
㪩㪜㪛
㪩㪜㪛
㪙㪣㪢
㪙㪣㪢
㪩㪜㪛
㪙㪣㪢
㪙㪣㪢
㪩㪜㪛
㪩㪜㪛
㪩㪜㪛
㪩㪜㪛
㪙㪣㪢
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪪㪘㪝㪜㪫㪰㩷㪫㪼㫉㫄㫀㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫀㫆㫅
㪣㪦㪦㪧㩷㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪡㪈㪌㪊㪉㪈㪍㪇㪏
㪝㪼㫉㫉㫀㫋㪼㩷㪺㫆㫉㪼
㩺㪈㪏㪩㪜㪛
㪧㫉㫆㫋㪼㪺㫋㩷㪼㪸㫉㫋㪿㪆㪽㫃㫆㪸㫋㩷㪼㪸㫉㫋㪿
㪚㪟㩷㪙㩷㪦㪬㪫㩷㪥
㪚㪟㩷㪙㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪘㩷㪦㪬㪫㩷㪥
㪚㪟㩷㪘㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪱㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪱㩷㪦㪬㪫㩷㪥
㪛㪦㪬㪫㪈㩷㪧
㪛㪦㪬㪫㪈㩷㪥
㩺㪈㪏㪞㪘㪩㪰
㪛㪠㪥㪧㩷㪚㪦㪤㪈
㪛㪠㪥㪧㩷㪉
㪛㪠㪥㪧㩷㪊㪋
㪛㪠㪥㪧㩷㪈㪉
㩺㪈㪏㪮㪟㪫㫏㫏㫏㫏㫏㪧㪸㫉㫋㩷㫅㫌㫄㪹㪼㫉
㪈㪌㪊㪉㪈㪊㪐㪋
㩺㪈㪏㪙㪣㪢㪈㪉㪈㫆㪿㫄㪃㩷㪂㪆㪄㪈㩼㪃㩷㪇㪅㪈㪉㪌㪮㪸㫋㫋
㪉
' 㩺㪈㪏㪩㪜㪛
'
㪉㪍
㪉㪉
㪉㪈
㪉㪇
㪈㪐
㪈㪏
㪈㪎
㪊
㪎
㪍
㪊㪪㪫㪘㪫㪠㪚㩷㪙㪼㪸㪻
㩺㪈㪏㪰㪜㪣㪋㪙㪩㪘㪢㪜
300 watt
㩺㪈㪏㪙㪩㪥
㪌 25 ohm
㪡㪋
㪌㪭㪂㪙㪩㪦㪮㪥㩺㪉㪋㪪㪜㪩㪭㪦㪈㪉
㩺㪈㪏㪙㪣㪬㪌㪊㪉㪊㪋㪎㪌
㪍
Regen Resistor
㪈㪋㪚㪘㪥㪄㪟㪩㪜㪛㩺㪉㪋㪤㪦㪫㪦㪩㪫㫎㫀㫊㫋㩷㫎㫀㫉㪼
㪌㪊㪉㪈㪍㪇㪍㪌㪊㪊㪍㪉㪋㪉㩺㪈㪋㩷㪣㪄㪙㪣㪬㪩㪜㪞㪜㪥㪉㪰㪜㪣㪣㪦㪮㩺㪉㪋
㪈㪋㪊㪪㪟㪠㪜㪣㪛
㪂㪚㪦㪤㪊㪡㪈㪈
㪍㪅㪉㪌㪘㪮㪟㪠㪫㪜
㪩㪜㪣㪘㪰㪈㪐㪌㪊㪊㪍㪉㪋㪇㩺㪈㪋㩷㪙㪩㪥㪙㪬㪪㪂㪋
㪡㪈
DRIVER 㪉㪚㪘㪥㪄㪣㩺㪉㪋
㪮㫀㫉㪼㩷㪫㪼㫉㫄㫀㫅㪸㫃㪇㪅㪌㪘㩺㪈㪋㪙㪩㪥㪚㪉㪌㪙㪣㪘㪚㪢㩺㪉㪋
㪛㪚㪉㪋㪭
㪌㪊㪉㪋㪇㪈㪏㪈㪭㪄㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪠㪥㪧㪬㪫㪈㩿㪛㪦㪦㪩㩷㪪㪮㪠㪫㪚㪟㪄㪛㫆㫆㫉㩷㪺㫃㫆㫊㪼㪀㪌㪊㪉㪋㪇㪉㪇
㪌㪈
㩺㪈㪋㪣㪄㪙㪣㪬㪚㪈
㪣㪊
㪍
㪎
S20660
AKM52G
㩺㪈㪏㩷㪩㪜㪛㩺㪈㪏㪩㪜㪛㪌㪊㪉㪈㪍㪊㪉㪌㪊㪊㪍㪉㪋㪈
㪈㪇㪘㩺㪈㪋㪙㪩㪥㪣㪉㪏㪌㪊㪉㪊㪐㪏㪈
㩺㪈㪏㩷㪙㪣㪢㩺㪈㪏㪙㪣㪬㪈㪊㪥㪅㪦㪅㩺㪈㪋㪣㪄㪙㪣㪬㪐㪌㪊㪉㪊㪐㪏㪉
㪄㪣㪈㪜㪥㪚㪦㪛㪜㪩㪌㪊㪉㪈㪍㪈㪎㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪫㪈㪄㪈㪫㪈㪄㪉㩺㪈㪏㩷㪞㪩㪥
㪦㪬㪫㪧㪬㪫㪈㩿㪙㪘㪰㩷㪣㪘㪤㪧㪀㩺㪈㪏㩷㪩㪜㪛㩺㪈㪏㩷㪞㪩㪥㪡㪈㪊
㪫㪉㪄㪈㪫㪉㪄㪉㪧㪜㪜㪥㪚㪦㪛㪜㪩
㪈㪉㪇㪭㪘㪚㩷㪣㩺㪈㪏㩷㪙㪣㪢㪚㪦㪤㪉㪋㪪㫆㪺㫂㪼㫋㪧㫀㫅
㩺㪈㪏㩷㪙㪣㪢㪈㪊㪄㩺㪈㪋㪙㪩㪥㪡㪉
㪫㪊㪄㪈㪫㪊㪄㪉㪈㪠㫅㫋㪼㫉㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪈㪉㪇㪭㪘㪚㩷㪥㪩㪜㪣㪘㪰㪉㪐㪉
㪛㪚㪉㪋㪭
㪫㪋㪄㪈㪫㪋㪄㪉㪌㪊㪉㪋㪇㪈㪏㪈㪊

㩺㪈㪋㪣㪄㪙㪣㪬㪧㪦㪮㪜㪩
㪫㪼㫉㫄㫀㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫀㫆㫅
㪦㪬㪫㪧㪬㪫㪉㩿㪩㪼㪸㪻㫐㩷㪪㫋㪸㫋㫌㫊㩷㪣㪘㪤㪧㪀㪫㪌㪄㪈㩺㪈㪏㩷㪮㪟㪫㪈㪌
㪥㪝
㪧㪦㪮㪜㪩
㪌㪊㪉㪈㪍㪊㪌
㩺㪈㪏㩷㪩㪜㪛㪫㪌㪄㪉㪧㪩㪦㪫㪜㪚㪫㩷㪜㪘㪩㪫㪟㩿㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼㪀

㪌㪊㪉㪋㪈㪌㪍㪌㪊㪉㪉㪎㪊㪉
㪉㪉㪇㪭㪘㪚㩷㪣
㩺㪈㪏㩷㪙㪣㪢㪫㪍㪄㪈㪫㪍㪄㪉㪥㪅㪦㪅㪈㪋㪂㪌㪊㪉㪈㪍㪈㪍㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㫇㫆㫀㫅㫋
㪉㪉㪇㪭㪘㪚㩷㪥㪫㪎㪄㪈㪫㪎㪄㪉
㩺㪈㪏㩷㪙㪩㪥㪚㪦㪤
㪫㪏㪄㪈㪫㪏㪄㪉㪈㪊㪄
㪐㪧㪜
㪩㪜㪣㪘㪰㪊
㪛㪚㪉㪋㪭
( (
㪌㪊㪉㪋㪇㪈㪏
㩺㪈㪏㩷㪰㪜㪣㩷㪈㪌
㪥㪅㪦㪅㪈㪋㪂
&4 Wang, donghua 2009.06.25 LingLong Single Gantry SCHEMATIC
㪌㪊㪉㪈㪍㪊㪈㪙㪩㪥
(STAY-W FRONT/REAR COVER)
㩺㪈㪋
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㩷㪡㪋㩺㪈㪋㪣㪄㪙㪣㪬 %*
2#)'
#22 㪌㪊㪉㪊㪐㪉㪊㩷㪪㪚㪟 1/2
4'8<10'&#6' 4'8$; Yang, lingfeng 2009.06.25
5+<'
#Approved Document - 5323923SCH_r3.pdf Page
/+%41
2 of 3

GEHW Medical Systems
GANTRY 1-1
Brivo CT315
Brivo CT325
REV 5 5306515-1EN

㪪㫃㫀㫇㩷㪩㫀㫅㪾
㪰㪜㪣
# #
㪧㪐㪈㪋㪇㪪㪘
㪝㫌㫊㪼
㪬㪙㪇㪇㪉㪐㪜㪢
㩺㪈㪋㩷㪙㪩㪥㪉㪉㪋㪈㪉㪉㪇㪉㪉㪉㪌㪋㪊㪊㩺㪈㪋㩷㪙㪩㪥

㪡㪌
㪘㪚㩷㪈㪈㪌㪭㩺㪈㪋㩷㪣㪄㪙㪣㪬㪈㪉㩺㪈㪋㩷㪣㪄㪙㪣㪬
㪡㪋
㪋㪊㪩㪜㪣㪘㪰
㪉㪉㪇㪊㪊㪏㪎
HV Control Board
㩺㪋㩷㪙㪣㪢㪉㪈㪎㪍㪈㪋㪋
㪈㪉㪉㪉㪎㪎㪉㪇
㩺㪋㩷㪙㪣㪢㪉㪈㪎㪍㪈㪋㪌
㪟㪭㩷㪧㪮㪩㪉
㪉㪈㪎㪍㪈㪋㪍
㩺㪋㩷㪙㪣㪢
㪊
㪧㪣㪈
㪉㪈㪇㪌㪍㪈㪎㪄㪯㪧㪣㪉
㪉㪈㪇㪌㪍㪈㪎㪄㪯
$ 㪘㪚㩷㪈㪈㪌㪭
㪡㪌㩺㪈㪋㩷㪙㪩㪥
㩺㪈㪋㪣㪄㪙㪣㪬㪚㪥㪍㪇㪄㪪㪚㪥㪍㪈㪄㪪
$
㪡㪋
㪉㪈㪉㪈
㪚㪥㪍㪇㪄㪧㪚㪥㪍㪈㪄㪧
㪌㪊㪉㪍㪐㪍㪎㩺㪉㪉㩷㪩㪜㪛㩺㪉㪉㩷㪩㪜㪛㩷
㪈㪌㪊㪉㪈㪎㪌㪇㩺㪉㪉㩷㪩㪜㪛㩷㪂㪌㪭㪈
㩺㪉㪉㩷㪙㪣㪢㪚㪥㪈㪇㪈㩺㪉㪉㩷㪩㪜㪛㩷
㪉㪈
㩺㪋㩷㪰㪜㪣㪆㪞㪩㪥㪌㪊㪊㪉㪎㪍㪇㪞㪧㪣㪪㪉㪉㩺㪉㪉㩷㪙㪣㪢㩷㪂㪌㪭㩷㪩㪫㪥㪉
㩺㪉㪉㩷㪙㪣㪢㩷
㪞㪥㪛㪬㪇㪇㪇㪉㪧㪙
㩷㪚㪥㪌㪊
㪉㩺㪉㪉㩷㪙㪣㪢㩷㪘㪥㪦㪛㪜㪂
㪋㪉㪉㪇㪈㪈㪏㪋㪄㪉
㪌㪊㪉㪍㪐㪍㪌
㪦㪧㪫
㩺㪉㪉㩷㪙㪩㪥
㩺㪉㪉㩷㪙㪣㪢
㪈 HV Generator 㪚㪘㪫㪟㪦㪛㪜㪄
X-RAY TUBE
㪉㪚㪥㪋
㪪㪮㩺㪉㪉㩷㪙㪣㪬㪊㪉㪉㪋㪈㪉㪉㪍㪪㪟㪠㪜㪣㪛㩷㪚㪘㪙㪣㪜㩷㪬㪣㪉㪋㪍㪋㩷㪫㪮㪠㪪㪫㩷㪧㪘㪠㪩㪉㪉㪉㪎㪎㪉㪇
㪉㪉㪇㪈㪈㪏㪌㪄㪉
㪛㪊㪈㪍㪈㪫
㩷㪚㪥㪐
㪞㩷㪧㪬㪣㪪㪜㪉
㪩㪦㪫㪘㪫㪜㩷
㪝㪩㪘㪤㪜
㪉㪉㪋㪈㪉㪉㪎㪄㪉㪉㪋㪭㩷㩺㪉㪉㩷㪩㪜㪛
㪉㪉㪋㪈㪉㪉㪌㪚㪥㪎㪤㪦㪫㪦㪩㩷㪛㪩㪠㪭㪜㪩㪉㪋㪭㩷㪩㪫㪥㩷㩺㪉㪉㩷㪙㪣㪢㪈㪣㪄㪤㩽㪈㪣㪄㪞
㪛㪄㪪㪬㪙㩷㪈㪌㩷㪧㪠㪥㪚㪥㪍㪌㪊㪉㪋㪈㪌㪏㩿㪤㪦㪫㪦㪩㪀㩺㪉㪉㪚㪥㪈㪚㪥㪉㪤㪦㪫㪦㪩
OGPL BD ASSY 㪚㪥㪈
MOTOR 㪉㪉㪌㪐㪎㪏㪌㪄㪋㩷㪪㫀㫅㪾㫃㪼
㪪㪆㪩 DRIVER
㪤㪦㪫㪦㪩
MUX 㪌㪊㪉㪐㪈㪍㪏㪄㪯㪌㪊㪉㪋㪈㪌㪐㩺㪉㪉㪚㪥㪌㪈
㪉㪉㪇㪈㪈㪎㪐㩷
㪜㪥㪚㪦㪛㪜㪩
㪚㪥㪌㪊 COLLIMATOR ASSY
㪚㪥㪊㪉㪊㪉㪇㪎㪏㪊㪄㪉㩷㪛㫌㪸㫃
㪤㪦㪣㪜㪯㩷㪌㪊㪊㪉㪎㪍㪈㪈
㪋㩷㪧㪠㪥㪉
㪊㪜㪥㪚㩽㪧㪟㪦㪫㪦
㪧㪟㪦㪫㪦
㪊
㪉
㪈
㪋
㪋
% %
㪚㪥㪉
㪌
㪍㪚㪥㪌㪉
㪧㪦㪮㪜㪩
㪚㪥㪈㪚㪥㪈㪱㪄㪤㫆㫋㫆㫉
㪚㪥㪉
㪚㪥㪏 MOTOR
DRIVER
㪉㪉㪋㪈㪊㪉㪎
㪌㪊㪉㪎㪎㪊㪐㪈㪈㪌㪭㪘㪚
㩺㪈㪍㩷㪩㪜㪛㩷㪉㪈㪎㪍㪈㪋㪊㪄㪉
㩺㪈㪍㩷㪙㪣㪢㩷
㪈
㪉
㪡㪌㪊
㪋
& 㪫㪜㪤㪧㩷㪚㪦㪥㪫㩷㪘㪪㪪㪰
㪈㩺㪉㪋㩷㪰㪜㪣
&
㪉㪋㪭㪌㪈㪋㪏㪎㪈㪊㪉㩺㪉㪋㩷㪙㪣㪢
㪈㩺㪈㪋㩷㪩㪜㪛㩷㪈㪬㪥㪠㪭㩷㪬㪥㪠㪭㩷
㪉㪉㪌㪈㪏㪈㪋㪊㩺㪉㪋㩷㪩㪜㪛
㪡㪊㪉㪉㪋㪭㩷㪩㪠㪥㩺㪈㪋㩷㪙㪣㪢㩷㪉㩷㪧㪠㪥㪋㩷㪧㪠㪥
㪋㩺㪉㪋㩷㪙㪣㪢
㪉
㩺㪉㪉㩷㪰㪜㪣㪌㪭㪈
㩺㪉㪉㩷㪩㪜㪛㪌㪭㩷㪩㪫㪥㪉㪈㪪㫆㫃㫀㪻㩷㪪㫋㪸㫋㪼㩷㪩㪼㫃㪸㫐
㩺㪉㪉㩷㪙㪣㪬㪉㪋㪭㪊㪬㪥㪠㪭㩷㪉
㩺㪉㪉㩷㪙㪣㪢㪉㪋㪭㩷㪩㪫㪥㪋
㪡㪈
㪉㪉㪋㪌㪈㪌㪈㩷㪪㫀㫅㪾㫃㪼 DETECTOR ASSY 㪉㪊㪉㪈㪇㪋㪊㩷㪛㫌㪸㫃
㪋㩷㪧㪠㪥
㪊
㪋
㩺㪉㪉㩷㪮㪟㪠㪫㪜㪉㪋㪭㪌
㩺㪉㪉㩷㪦㪩㪞㪉㪋㪭㩷㪩㪫㪥㪍㪝㫌㫊㪼

㪎㪈㪉㪋㪭
㪏
㪐
㪡㪇㪉㪉㪋㪭㩷㪩㪠㪥
㪈㪇㪝㪣㪜㪯㩷㪘㪪㪪㪰
㪈㪈
㪈㪉
PS ASSY
㪌㪊㪉㪊㪐㪎㪇㪛㪶㪪㪬㪙㩷
㪉㪌㩷㪧㪠㪥㪧㫉㫆㫋㪼㪺㫋㩷㪼㪸㫉㫋㪿㪆㪚㪿㪸㫊㫀㫊㩷㪼㪸㫉㫋㪿
㫏㫏㫏㫏㫏㪧㪸㫉㫋㩷㫅㫌㫄㪹㪼㫉
㪈
㪤㪦㪣㪜㪯㩷㪉
㪋㩷㪧㪠㪥㪊㪙㪼㪸㪻
' 㪋
'
㪌㪊㪉㪎㪎㪋㪈㪈
㩺㪉㪉㩷㪩㪜㪛㪉㪋㪭㪫㫎㫀㫊㫋㩷㫎㫀㫉㪼
㩺㪉㪉㩷㪙㪣㪢㪉㪌㪈㪋㪉㪇㪉㪎㪄㪉㩷㪪㫀㫅㪾㫃㪼
㪉㪋㪭㩷㪩㪫㪥
㩺㪉㪉㩷㪩㪜㪛㪉㪋㪭㪊㪡㪉
RF XMT 㩺㪉㪉㩷㪙㪣㪢㪉㪋㪭㩷㪩㪫㪥㪋
㪈
㪂㪌㪭㪘㩺㪈㪋㩷㪩㪜㪛㩷㪊 DAS ASSY 㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪉㪘㪞㪥㪛㩺㪈㪋㩷㪮㪟㪫㪋
㪊㪄㪌㪭㪘㩺㪈㪋㩷㪞㪩㪥㪌㪌㪈㪋㪉㪇㪉㪎㩷㪛㫌㪸㫃
㪎
㪝㪠㪙㪜㪩
㪡㪋㪋
㪏㪬㪥㪠㪭㩷㪈㪉㩷㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪌
㪦㪧㪫㪍
㪂㪌㪭㪣㩺㪈㪋㩷㪩㪜㪛㩷
㪐㪧㪠㪥
㪩㪝ห䕈㪎㪈
㪪㪤㪙㪪㪤㪙㪛㪞㪥㪛㩺㪈㪋㩷㪙㪣㪢㩷㪉㪪㫆㪺㫂㪼㫋㪧㫀㫅
㪏
㩺㪈㪋㩷㪰㪜㪣㪍㪈㪠㫅㫋㪼㫉㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪐
㪉
㪦㪧㪫㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㫇㫆㫀㫅㫋
( (
&4 Wang, donghua 2009.06.25 LingLong Dual/Single Gantry SCHEMATIC
%*
2#)'
#22
Yang, lingfeng 2009.06.25
㪌㪊㪉㪊㪐㪉㪊㩷㪪㪚㪟 2/2
5+<' 4'8<10'&#6' 4'8$;
#Approved
/+%41
Document - 5323923SCH_r3.pdf Page 3 of 3

1-2 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1-2 GANTRY ASSY FOR EMC

㪌㪊㪉㪈㪋㪇㪇㪄㪉
㪝㪩㪦㪤㪘㪯㪠㪘㪣㩷㪛㪩㪠㪭㪜㩷㪘㪪㪪㪰㪌㪊㪐㪉㪍㪋㪈㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼
㪡㪋
㪤㫆㫋㫆㫉㩷㪝㫉㪸㫄㪼
㪝㪠㪙㪜㪩
㪌㪊㪉㪈㪍㪉㪊㪄㪉㪈㪇㪆㪈㪇㪇㩷㪹㪸㫊㪼㩷㪫 DTB BD ASSY 㪈
# 㪫㪦㩷㪦㪚㩷㪥㪠㪚
#
㪡㪊
㪡㪉
㪌㪊㪉㪈㪍㪉㪉㪄㪉㪉
㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼㪜㫋㪿㪼㫉㫅㪼㫋㩷㪺㪸㪹㫃㪼㪡㪈
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪌㪊㪊㪐㪈㪏㪌㪄㪉
㪞㪸㫅㫋㫉㫐㩷㪝㫉㪸㫄㪼㪌㪉㪎㪇㪐㪍㪍㪄㪯㪡㪈
RF
㪌㪊㪉㪐㪎㪍㪌㪄㪉㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼
㪈㪉
㪞㪸㫅㫋㫉㫐㩷㪝㫉㪸㫄㪼㩺㪉㪉㪦㪩㪥㩷㪌㪊㪉㪈㪋㪏㪋㪄㪉㪈 FAN FAN
㩺㪉㪉㪮㪟㪫㪊
RCV
㪌㪊㪏㪇㪋㪏㪐㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼㪡㪉
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪤㫆㫋㫆㫉㩷㩷㪝㫉㪸㫄㪼
㪬㪇㪌㪈㪌㪘㪤
㪚㪌㪊㪉㪈㪍㪉㪏㪄㪉㩺㪋㩷㪙㪣㪢㩷㪈㪈㪣㪼㪽㫋㩷㪫㫆㫇㩷㪝㪘㪥㩷㪘㪪㪪㪰
㪉
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪟㪭㩷㪧㪮㪩㪙㪌㪊㪉㪈㪍㪉㪎㪄㪉㩺㪋㩷㪙㪣㪢㩷㪉
㪘㪌㪊㪉㪈㪍㪉㪍㪄㪉㩺㪋㩷㪙㪣㪢㩷㪊
FAN FAN
㪡㪎㪄㪉㩺㪈㪋㪣㪄㪙㪣㪬㪋
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪈㪈㪌㪭㫋㫆㩷㪪㪣㪠㪧㩷㪩㪠㪥㪞
㪡㪎㪄㪈㪌㪊㪉㪈㪍㪊㪇㩺㪈㪋㪙㪩㪥㪌
㪌㪊㪇㪌㪍㪎㪋㪄㪯
㪌㪊㪉㪈㪍㪉㪐㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪍
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪞㪥㪛㪈
㪉
㪡㪌㪄㪈㩺㪈㪍㪙㪩㪥㩺㪈㪍㪙㪩㪥
㪉㪋㪣
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㪡㪌㪄㪉㪌㪊㪉㪈㪍㪉㪋㪄㪉㩺㪈㪍㪣㪄㪙㪣㪬㩺㪈㪍㪣㪄㪙㪣㪬
㪥
㪈㪊㩺㪉㪉㪌㪊㪉㪈㪌㪊㪋㪄㪉
㪌㪊㪏㪇㪋㪏㪏㪦㪩㪥㩷㪈 FAN FAN
$ 㩺㪉㪉㪮㪟㪫㪊
$
㩺㪈㪏㩷㪞㪘㪩㪰㩷
㩺㪈㪏㩷㪩㪜㪛㩷
㪥㪝 PS 㪉㪋㪭 M Signal
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㪡㪊㪌㪊㪊㪉㪎㪌㪐㪄㪉㪫㪦㩷㪦㪚㩷㪸㫅㪻㩷㪣㪚㪛㪌㪊㪐㪉㪍㪋㪇
U
Brush 㪬㪇㪌㪈㪌㪘㪤
㪌㪈㪌㪐㪇㪐㪎 X 㪈
㪞㪘㪥㪫㪩㪰㩷㪘㪥㪛㩷㪉
㪩㫀㪾㪿㫋㩷㪫㫆㫇㩷㪝㪘㪥㩷㪘㪪㪪㪰
㪌㪊㪉㪋㪎㪋㪇㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪫㪘㪙㪣㪜㩷㪞㪥㪛
FAN FAN
㪡㪍㪄㪈㩺㪈㪍㪩㪜㪛
㪌㪊㪉㪏㪐㪏㪍㪄㪉
㪡㪍㪄㪉㪌㪊㪉㪋㪈㪌㪎㪄㪉㩺㪈㪍㪞㪩㪘㪰㩺㪈㪏㪞㪩㪘㪰
㪫㪦㩷㪧㪛㪬㩷㪛㪚㩷㪉㪋㪭㪉
㩺㪈㪏㪞㪩㪘㪰
㪉
㪡㪉㪄㪈㪌㪊㪉㪈㪊㪏㪍㪄㪉㪩㪜㪛㩺㪈㪏㩺㪈㪏㩷㪩㪜㪛㩷㩺㪈㪏㩷㪩㪜㪛㩷㪌㪊㪉㪈㪌㪊㪎
㪈
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪛㪚㩷㪉㪋㪭
GANTRY
㪡㪉㪄㪉㪞㪩㪘㪰㩺㪈㪏㩺㪈㪏㩷㪞㪘㪩㪰㩷㩺㪈㪏㩷㪞㪩㪰㩷㪉
㪈
㪉
㪚㪥㪈
㪉
㪈
㩺㪈㪏㩷㪞㪩㪰
㪚㪥㪈㪎㪉㩺㪉㪉㪌㪊㪉㪈㪊㪐㪌㪌㪊㪉㪈㪍㪈㪏㪈

㩺㪈㪋㩷㪞㪩㪥㪆㪰㪜㪣㩺㪋㩷㪞㪩㪥㪆㪰㪜㪣㪚㪥㪈㪚㪥㪎㪚㪥㪈㪇㪈 XDISP BD ASSY
㪈㩺㪉㪉
㪉㪉
㪌㪊㪈㪌㪉㪐㪈
㪪㪫㪜㪧㩷㪤㪦㪫㪦㪩㩷
㪈㪉
㪘㪪㪪㪰㪧㪜
㪚㪥㪊㪦㪝㪞㪈㩺㪉㪉㪮㪟㪫㪈㪇
% %
㪈㩺㪈㪏㪦㪩㪥㪉㩺㪉㪉㪙㪣㪢㪉㪇
㪉㩺㪈㪏㪩㪜㪛㪈㪊㩺㪉㪉㪙㪩㪥㪈㪈㪌㪊㪉㪈㪊㪐㪉㪄㪉
STEP
㪊㩺㪈㪏㪙㪣㪬㪉㪋㩺㪉㪉㪰㪜㪣㪈㪐
㪈
㪉
㪙㪩㪥
㪙㪣㪢㪦㪧㪫
㪞㪄㪧㪬㪣㪪㪜㪈
MOTOR 㪚㪥㪉 DRIVE BOARD 㪌㩺㪉㪉㪮㪟㪫㪉㪉㪌㪊㪉㪈㪊㪐㪍㪄㪊㪚㪥㪏㪬㪇㪇㪇㪉㪧㪙
㪋㩺㪈㪏㪰㪜㪣㪊㪊㪙㪣㪬㪪㪮
ASSY 㪋㪚㪥㪈㪍㩺㪉㪉㪞㪩㪥㪐
㪎㩺㪉㪉㪭㪠㪦㪣㪜㪫㪈㪉
㪦㪝㪞㪏㩺㪉㪉㪞㪩㪘㪰㪉㪈
㩺㪈㪋㩷㪞㪩㪥㪆㪰㪜㪣
㪚㪥㪈㪈㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪪㪮
㪌㪊㪉㪈㪊㪏㪐
㪚㪩㪘㪛㪣㪜㩷 CRADLE 㪈㩺㪉㪉㪩㪜㪛㪍㪚㪥㪊
㪈
㪉
㪩㪜㪛
㪙㪣㪢㪙㪣㪢
㪧㪦㪫㩷 POT 㪉㩺㪉㪉
㩺㪉㪉
㪰㪜㪣
㪙㪣㪢
㪎
㪏㪉㪊㪏㪏㪉㪊㪇㩺㪈㪏㪉㪊㪏㪏㪉㪊㪇
㪊㩺㪈㪏
㪘㪪㪪㪰 ASSY
TGPL BD ASSY 㪝㪩㪦㪥㪫㩷㪣㪜㪝㪫㪝㪩㪦㪥㪫㩷㪩㪠㪞㪟㪫
㪪㪟㪠㪜㪣㪛
㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪪㪮
㪌㪊㪉㪈㪍㪉㪈
㪌㪊㪉㪈㪊㪐㪈㪄㪉㪌㪊㪉㪈㪍㪇㪎㪄㪉㪩㪜㪛
㪉㪈
㪜㪥㪚㪦㪛㪜㪩㩷㩺㪉㪉㪮㪟㪫㪈㪌㪊㪈㪇㪐㪐㪇㪄㪯 DISP/ 㪙㪣㪢㪙㪣㪢
㪡㪈
㪈㪚㪥㪍
㪡㪉
㪈㩺㪉㪉㪙㪩㪥㪉㪌㪊㪉㪉㪏㪈㪉㩺㪈㪏㪌㪊㪉㪉㪏㪈㪉
㪘㪪㪪㪰㪉
㪉㪊 CONTROL 㩺㪈㪏
㪊㩺㪉㪉㪩㪜㪛
ENCODER
ASSY 㪋
㪊
㪋㩺㪉㪉㪙㪣㪢㪋 PANEL 㪝㪩㪦㪥㪫㩷㪚㪦㪭㪜㪩㩷㪣㪜㪝㪫㪝㪩㪦㪥㪫㩷㪚㪦㪭㪜㪩㪩㪠㪞㪟㪫
㪌
㪌㪊㪈㪌㪊㪏㪈
㪍
㩺㪉㪉㪙㪣㪢㪈㪍
㪣㪘㪫㪚㪟㩷㪪㪮㩿㪩㪀㪰㪜㪣㩺㪉㪉㪰㪜㪣㪈㪎㪈㪤㫀㪺㪂㪮㪟㪫㩺㪉㪋㪌㪊㪉㪈㪊㪐㪐
㪈
㪌㪊㪉㪈㪍㪉㪇㪮㪟㪫㩺㪉㪋
㪈㪉㪌㪉㪤㫀㪺㪄㪩㪜㪛㩺㪉㪋㪉
㪩㪜㪛㩺㪉㪋㪤㪠㪚㪝㫉㫆㫅㫋㩷㪤㪠㪚㪩㪦㪧㪟㪦㪥㪜
㪉㪍㪚㪥㪌㪚㪥㪈㪏㪊㪪㪿㫀㫃㪼㪻㩺㪉㪋㪉㪈㪈㪈㪐㪌㪌
㪉㪈㪊
㪙㪣㪢㩺㪉㪉㪙㪣㪢
㪈
㪉㩺㪉㪉㪮㪟㪫㪤㫀㪺㪂㩺㪉㪋㪌㪊㪉㪈㪊㪐㪏㪌㪊㪉㪈㪍㪈㪐㪮㪟㪫㩺㪉㪋
㪰㪜㪣㪈㪮㪟㪫
& &
㪉㪈
㪈㪉㪤㫀㪺㪄㪩㪜㪛㩺㪉㪋㪉
㪩㪜㪛㩺㪉㪋㪤㪠㪚㪩㪼㪸㫉㩷㪤㪠㪚㪩㪦㪧㪟㪦㪥㪜
㪚㪥㪈㪉
㪉㪪㪧㪜㪘㪢㪜㪩㪊㪪㪿㫀㫃㪼㪻㩺㪉㪋㪉㪈㪈㪈㪐㪌㪌
㪚㪥㪋
㪚㪥㪐㪊
㪚㪥㪉
㪙㪣㪢
㪣㪘㪫㪚㪟㩷㪪㪮㩿㪣㪀
㪈㪉
㪈㪐
㪈㪏
㪉㪋
㪌
㪈㪍
㪈㪇
㪈㪋
㪉㪇
㪍
㪈
㪈㪌
㪉㪈
㪉㪊
㪐
㪏
㪉㪉
㪉
㪋
㪈
㪉
㪊
㪋
㪌
㪍
㪈
㪌
㪊
㪍
㪋
㪉
㪪㫆㫃㫀㪻㩷㪪㫋㪸㫋㪼㩷㪩㪼㫃㪸㫐
㪮㪟㪫
㪩㪜㪛
㪙㪣㪬
㪟㫆㫄㪼㩷㪝㫃㪸㪾
㪜㪩㪩㪦㪩㪶㪧㪈
㪜㪩㪩㪦㪩㪶㪧㪉
㪚㪟㩷㪙㩷㪥
㪚㪟㩷㪙㩷㪧
㪚㪟㩷㪘㩷㪧
㪛㫉㫀㫍㪼㫉㪶㪜㪥
㪛㪠㪥㪧㩷㪚㪦㪤
㪙㪩㪘㪢㪜㪂
㪙㪩㪘㪢㪜㪄
㪙㪣㪢
㪚㪟㩷㪘㩷㪥
㪚㪟㩷㪱㩷㪧
㪝㪘㪬㪣㪫㪶㪩㪜㪪㪜㪫㩺㪉㪋
㪭㪄
㪙㪣㪢
㪚㪟㩷㪱㩷㪥
㪚㪘㪥㪄㪟
㪚㪘㪥㪄㪣
㪭㪂
㪪㪟㪠㪜㪣㪛
㪰㪜㪣
㪌㪊㪉㪈㪊㪐㪇
㪝㪩㪦㪤㩷㪦㪚㩷㪪㪚㪙
㩺㪉㪉㪮㪟㪫
㩺㪉㪉㪙㪩㪥
㩺㪉㪉㪩㪜㪛
㩺㪉㪉㪙㪣㪢
㩺㪉㪉㪙㪣㪬
㩺㪉㪉㪰㪜㪣
㪝㫌㫊㪼
㩺㪈㪏㪙㪣㪢
㩺㪈㪏
㩺㪈㪏
㩺㪈㪏㪩㪜㪛
㩺㪈㪏
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㩺㪉㪋
㪤㪦㪣㪛㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪌㪊㪉㪈㪍㪇㪌㪄㪉㪪㪘㪝㪜㪫㪰㩷㪣㪦㪦㪧
㪩㪜㪛
㪩㪜㪛
㪙㪣㪢
㪙㪣㪢
㪩㪜㪛
㪙㪣㪢
㪙㪣㪢
㪩㪜㪛
㪩㪜㪛
㪩㪜㪛
㪩㪜㪛
㪙㪣㪢
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪪㪘㪝㪜㪫㪰㩷㪫㪼㫉㫄㫀㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫀㫆㫅
㪣㪦㪦㪧㩷㪜㪤㪜㪩㪞㪜㪥㪚㪰㩷㪡㪈㪌㪊㪉㪈㪍㪇㪏㪄㪉
㪪㪫㪘㪫㪠㪚㩷
㪙㪩㪘㪢㪜
㩺㪈㪏㪩㪜㪛
㪧㫉㫆㫋㪼㪺㫋㩷㪼㪸㫉㫋㪿㪆㪽㫃㫆㪸㫋㩷㪼㪸㫉㫋㪿
㪚㪟㩷㪙㩷㪦㪬㪫㩷㪥
㪚㪟㩷㪙㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪘㩷㪦㪬㪫㩷㪥
㪚㪟㩷㪘㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪱㩷㪦㪬㪫㩷㪧
㪚㪟㩷㪱㩷㪦㪬㪫㩷㪥
㪛㪦㪬㪫㪈㩷㪧
㪛㪦㪬㪫㪈㩷㪥
㩺㪈㪏㪞㪘㪩㪰
㪛㪠㪥㪧㩷㪚㪦㪤㪈
㪛㪠㪥㪧㩷㪉
㪛㪠㪥㪧㩷㪊㪋
㪛㪠㪥㪧㩷㪈㪉
㩺㪈㪏㪮㪟㪫㫏㫏㫏㫏㫏㪧㪸㫉㫋㩷㫅㫌㫄㪹㪼㫉
㪈
㩺㪈㪏㪙㪣㪢㪌㪊㪉㪈㪊㪐㪋㪄㪉㪈㪉㪈㫆㪿㫄㪃㩷㪂㪆㪄㪈㩼㪃㩷㪇㪅㪈㪉㪌㪮㪸㫋㫋
㪉
' 㩺㪈㪏㪩㪜㪛
㪉㪍 '
㪉㪉
㪈㪐
㪈㪏
㪈㪎
㪉㪈
㪉㪇
㪊
㪎
㪍
㪊㪙㪼㪸㪻
㩺㪈㪏㪰㪜㪣㪋
300 watt
㩺㪈㪏㪙㪩㪥
㪌 25 ohm
㪡㪋
㪌㪭㪂㪙㪩㪦㪮㪥㩺㪉㪋㪪㪜㪩㪭㪦
㩺㪈㪏㪙㪣㪬㪌㪊㪉㪊㪋㪎㪌
㪍
Regen Resistor
㪈㪋㪚㪘㪥㪄㪟㪩㪜㪛㩺㪉㪋㪤㪦㪫㪦㪩㪫㫎㫀㫊㫋㩷㫎㫀㫉㪼
㪌㪊㪉㪈㪍㪇㪍㪄㪉㪌㪊㪊㪍㪉㪋㪉㩺㪈㪋㩷㪣㪄㪙㪣㪬㪩㪜㪞㪜㪥㪉㪰㪜㪣㪣㪦㪮㩺㪉㪋
㪈㪋㪊㪪㪟㪠㪜㪣㪛
㪂㪚㪦㪤㪊㪡㪈㪈
㪍㪅㪉㪌㪘㪮㪟㪠㪫㪜㩺㪉㪋
㪩㪜㪣㪘㪰㪈㪐㪌㪊㪊㪍㪉㪋㪇㩺㪈㪋㩷㪙㪩㪥㪙㪬㪪㪂㪋
㪡㪈
DRIVER 㪉㪚㪘㪥㪄㪣
㪮㫀㫉㪼㩷㪫㪼㫉㫄㫀㫅㪸㫃㪇㪅㪌㪘㩺㪈㪋㪙㪩㪥㪚㪉㪌㪙㪣㪘㪚㪢㩺㪉㪋
㪛㪚㪉㪋㪭
㪌㪊㪉㪋㪇㪈㪏㪈㪭㪄㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪠㪥㪧㪬㪫㪈㩿㪛㫆㫆㫉㩷㫊㫎㫀㫋㪺㪿㪄㪛㫆㫆㫉㩷㪺㫃㫆㫊㪼㪀㪌㪊㪉㪋㪇㪉㪇
㪌㪈
㩺㪈㪋㪣㪄㪙㪣㪬㪚㪈
㪣㪊
㪍
㪎
S20660
AKM52G
㪘㪮㪞㪉㪉㪄㪘㪮㪞㪈㪉㩺㪈㪏㪩㪜㪛㪌㪊㪉㪈㪍㪊㪉㪄㪉㪌㪊㪊㪍㪉㪋㪈㪙㪩㪥
㪈㪇㪘㩺㪈㪋㪣㪉㪏㪌㪊㪉㪊㪐㪏㪈
㩺㪈㪏㪙㪣㪬㪈㪊㪥㪅㪦㪅㩺㪈㪋㪣㪄㪙㪣㪬㪣㪈㪐㪌㪊㪉㪊㪐㪏㪉
㪄㪜㪥㪚㪦㪛㪜㪩㪌㪊㪎㪈㪊㪊㪋㪄㪉㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪫㪈㪄㪈㪫㪈㪄㪉㩺㪈㪏㩷㪞㪩㪥
㩺㪈㪏㩷㪞㪩㪥㪡㪈㪊
㪫㪉㪄㪈㪧㪜㪧㪦㪮㪜㪩
㪦㪬㪫㪧㪬㪫㪈㩿㪙㪘㪰㩷㪣㪘㪤㪧㪀㪫㪉㪄㪉㩺㪈㪏㩷㪙㪣㪢㪚㪦㪤㪉㪋㪡㪉
㪪㫆㪺㫂㪼㫋㪧㫀㫅
㪘㪮㪞㪉㪉㪄㪘㪮㪞㪈㪉㪫㪊㪄㪈㪫㪊㪄㪉㪈㪊㪄㩺㪈㪋㪙㪩㪥㪈㪠㫅㫋㪼㫉㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪩㪜㪣㪘㪰㪉㪐㪉
㪛㪚㪉㪋㪭
㪫㪋㪄㪈㪫㪋㪄㪉㪌㪊㪉㪋㪇㪈㪏㪈㪊

㪉㪌㪇㪭㪘㪚㩷㪤㪸㫏㪃㩷㪌㪘㩷㪤㪸㫏㩺㪈㪋㪣㪄㪙㪣㪬㪧㪦㪮㪜㪩
㪌㪊㪉㪈㪍㪊㪌㪄㪉
㩺㪈㪏㩷㪮㪟㪫㪈㪌
㪫㪌㪄㪈㪫㪌㪄㪉㪥㪝㪧㪩㪦㪫㪜㪚㪫㩷㪜㪘㪩㪫㪟㩿㪙㫉㪸㫀㪻㩷㪚㪸㪹㫃㪼㪀
㪌㪊㪉㪋㪈㪌㪍㪄㪉㪌㪊㪉㪉㪎㪊㪉㪄㪊㪌㪊㪎㪈㪊㪊㪌㪄㪉
㪫㪍㪄㪈㪫㪍㪄㪉㪥㪅㪦㪅㪈㪋㪂㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㫇㫆㫀㫅㫋
㪦㪬㪫㪧㪬㪫㪉㩿㪩㪼㪸㪻㫐㩷㪪㫋㪸㫋㫌㫊㩷㪣㪘㪤㪧㪀㪫㪎㪄㪈㪫㪎㪄㪉
㪘㪮㪞㪉㪉㪄㪘㪮㪞㪈㪉㩺㪈㪏㩷㪙㪩㪥㪚㪦㪤
㪫㪏㪄㪈㪫㪏㪄㪉㪈㪊㪄
㪐㪧㪜
㪉㪌㪇㪭㪘㪚㩷㪤㪸㫏㪃㩷㪌㪘㩷㪤㪸㫏㪩㪜㪣㪘㪰㪊
㪛㪚㪉㪋㪭
( (
㪌㪊㪉㪋㪇㪈㪏
㩺㪈㪏㩷㪰㪜㪣㩷㪈㪌
㪥㪅㪦㪅㪈㪋㪂
&4 Wang, donghua 2010.05.30 LingLong Single Gantry SCHEMATIC
㪌㪊㪉㪈㪍㪊㪈㪄㪉㪙㪩㪥
㩺㪈㪋
㪝㪩㪦㪤㩷㪧㪛㪬㩷㪘㪚㩷㪉㪉㪇㪭㩷㪡㪋㩺㪈㪋㪣㪄㪙㪣㪬 %*
2#)'
#22 2010.05.30
㪌㪊㪉㪊㪐㪉㪊㩷㪪㪚㪟 1/2
5+<' 4'8<10'&#6' 4'8$; Yang, lingfeng
# /+%41
GANTRY 1-3
Brivo CT315
Brivo CT325
REV 5 5306515-1EN

㪪㫃㫀㫇㩷㪩㫀㫅㪾
㪰㪜㪣
# #
㪧㪐㪈㪋㪇㪪㪘
㪝㫌㫊㪼
㪬㪇㪇㪉㪐㪜㪢
㩺㪈㪋㩷㪙㪩㪥㪉㪉㪋㪈㪉㪉㪇㪉㪉㪉㪌㪋㪊㪊㩺㪈㪋㩷㪙㪩㪥

㪡㪌
㪘㪚㩷㪈㪈㪌㪭㪡㪋
㩺㪈㪋㩷㪣㪄㪙㪣㪬㪈㪉㩺㪈㪋㩷㪣㪄㪙㪣㪬
㪋㪊㪩㪜㪣㪘㪰
㪉㪉㪇㪊㪊㪏㪎
HV Control Board
㩺㪋㩷㪙㪣㪢㪉㪈㪎㪍㪈㪋㪋
㪈㪉㪉㪉㪎㪎㪉㪇
㩺㪋㩷㪙㪣㪢㪉㪈㪎㪍㪈㪋㪌
㪟㪭㩷㪧㪮㪩㪉
㪉㪈㪎㪍㪈㪋㪍
㩺㪋㩷㪙㪣㪢
㪊
㪧㪣㪈
㪉㪈㪇㪌㪍㪈㪎㪄㪯㪧㪣㪉
㪉㪈㪇㪌㪍㪈㪎㪄㪯
$ 㪘㪚㩷㪈㪈㪌㪭
㪡㪌㩺㪈㪋㩷㪙㪩㪥
㩺㪈㪋㪣㪄㪙㪣㪬㪚㪥㪍㪇㪄㪪㪚㪥㪍㪈㪄㪪
$
㪡㪋
㪉㪈㪉㪈
㪚㪥㪍㪇㪄㪧㪚㪥㪍㪈㪄㪧
㪌㪊㪉㪍㪐㪍㪎㩺㪉㪉㩷㪩㪜㪛㩺㪉㪉㩷㪩㪜㪛㩷
㪈㪌㪊㪉㪈㪎㪌㪇㩺㪉㪉㩷㪩㪜㪛㩷㪂㪌㪭㪈
㩺㪉㪉㩷㪙㪣㪢㪚㪥㪈㪇㪈㩺㪉㪉㩷㪩㪜㪛㩷
㪉㪈
㩺㪋㩷㪰㪜㪣㪆㪞㪩㪥㪌㪊㪊㪉㪎㪍㪇㪞㪧㪣㪪㪉㪉㩺㪉㪉㩷㪙㪣㪢㩷㪂㪌㪭㩷㪩㪫㪥㪉
㩺㪉㪉㩷㪙㪣㪢㩷
㪞㪥㪛㩷㪚㪥㪌㪊
㪉
㩺㪉㪉㩷㪙㪣㪢㩷㪘㪥㪦㪛㪜㪂
㪬㪇㪇㪇㪉㪧㪙
㪋㪉㪉㪇㪈㪈㪏㪋㪄㪉
㪌㪊㪉㪍㪐㪍㪌㪄㪉㩺㪉㪉㩷㪙㪩㪥
㪦㪧㪫㩺㪉㪉㩷㪙㪣㪢
㪈 HV Generator 㪚㪘㪫㪟㪦㪛㪜㪄
X-RAY TUBE
㪉㪚㪥㪋
㪪㪮㩺㪉㪉㩷㪙㪣㪬㪊㪉㪉㪋㪈㪉㪉㪍㪪㪟㪠㪜㪣㪛㩷㪚㪘㪙㪣㪜㩷㪬㪣㪉㪋㪍㪋㩷㪫㪮㪠㪪㪫㩷㪧㪘㪠㪩㪉㪉㪉㪎㪎㪉㪇
㪉㪉㪇㪈㪈㪏㪌㪄㪉
㪛㪊㪈㪍㪈㪫
㩷㪚㪥㪐
㪞㩷㪧㪬㪣㪪㪜㪉
㪩㪦㪫㪘㪫㪜㩷
㪝㪩㪘㪤㪜
㪉㪉㪋㪈㪉㪉㪎㪄㪉㪉㪋㪭㩷㩺㪉㪉㩷㪩㪜㪛
㪉㪉㪋㪈㪉㪉㪌㪚㪥㪎㪤㪦㪫㪦㪩㩷㪛㪩㪠㪭㪜㪩㪉㪋㪭㩷㪩㪫㪥㩷㩺㪉㪉㩷㪙㪣㪢㪈㪣㪄㪤㩽㪈㪣㪄㪞
㪛㪄㪪㪬㪙㩷㪈㪌㩷㪧㪠㪥㪚㪥㪍㪌㪊㪉㪋㪈㪌㪏㩿㪤㪦㪫㪦㪩㪀㩺㪉㪉㪚㪥㪈㪚㪥㪉㪤㪦㪫㪦㪩
OGPL BD ASSY 㪚㪥㪈
MOTOR 㪉㪉㪌㪐㪎㪏㪌㪄㪋㩷㪪㫀㫅㪾㫃㪼
㪪㪆㪩 DRIVER
㪤㪦㪫㪦㪩
MUX 㪌㪊㪉㪐㪈㪍㪏㪄㪯㪌㪊㪉㪋㪈㪌㪐㩺㪉㪉㪚㪥㪌㪈
㪉㪉㪇㪈㪈㪎㪐㩷
㪚㪥㪌㪊 COLLIMATOR ASSY
㪉㪊㪉㪇㪎㪏㪊㪄㪉㩷㪛㫌㪸㫃
㪌㪊㪊㪉㪎㪍㪈㪈㪚㪥㪊
㪤㪦㪣㪜㪯㩷
㪋㩷㪧㪠㪥㪉
㪊㪜㪥㪚㩽㪧㪟㪦㪫㪦
㪧㪟㪦㪫㪦
㪊
㪉
㪈
㪋
㪋
% %
㪚㪥㪉
㪌
㪍㪚㪥㪌㪉
㪧㪦㪮㪜㪩
㪚㪥㪈㪚㪥㪈㪱㪄㪤㫆㫋㫆㫉
㪚㪥㪉
㪚㪥㪏 MOTOR
DRIVER
㪉㪉㪋㪈㪊㪉㪎
㪌㪊㪉㪎㪎㪊㪐㪈㪈㪌㪭㪘㪚
㩺㪈㪍㩷㪩㪜㪛㩷㪉㪈㪎㪍㪈㪋㪊㪄㪉
㩺㪈㪍㩷㪙㪣㪢㩷
㪈
㪉
㪡㪌㪊
㪋
& 㪫㪜㪤㪧㩷㪚㪦㪥㪫㩷㪘㪪㪪㪰
㪈㩺㪉㪋㩷㪰㪜㪣
&
㪉㪋㪭㪌㪈㪋㪏㪎㪈㪊㪉㩺㪉㪋㩷㪙㪣㪢
㪈㩺㪈㪋㩷㪩㪜㪛㩷㪈㪬㪥㪠㪭㩷㪬㪥㪠㪭㩷
㪉㪉㪌㪈㪏㪈㪋㪊㩺㪉㪋㩷㪩㪜㪛
㪡㪊㪉㪉㪋㪭㩷㪩㪫㪥㩺㪈㪋㩷㪙㪣㪢㩷㪉㩷㪧㪠㪥㪋㩷㪧㪠㪥
㪋㩺㪉㪋㩷㪙㪣㪢
㪉
㩺㪉㪉㩷㪰㪜㪣㪌㪭㪈
㩺㪉㪉㩷㪩㪜㪛㪌㪭㩷㪩㪫㪥㪉㪈㪪㫆㫃㫀㪻㩷㪪㫋㪸㫋㪼㩷㪩㪼㫃㪸㫐
㩺㪉㪉㩷㪙㪣㪬㪉㪋㪭㪊㪬㪥㪠㪭㩷㪉
㩺㪉㪉㩷㪙㪣㪢㪉㪋㪭㩷㪩㪫㪥㪋
㪡㪈
㪉㪉㪋㪌㪈㪌㪈㩷㪪㫀㫅㪾㫃㪼 DETECTOR ASSY 㪉㪊㪉㪈㪇㪋㪊㩷㪛㫌㪸㫃
㪋㩷㪧㪠㪥
㪊
㪋
㩺㪉㪉㩷㪮㪟㪠㪫㪜㪉㪋㪭㪌
㩺㪉㪉㩷㪦㪩㪞㪉㪋㪭㩷㪩㪫㪥㪍㪝㫌㫊㪼
㪎㪈㪉㪋㪭
㪏
㪐
㪡㪇㪉㪉㪋㪭㩷㪩㪫㪥
㪈㪇㪝㪣㪜㪯㩷㪘㪪㪪㪰
㪈㪈
㪈㪉
PS ASSY
㪌㪊㪉㪊㪐㪎㪇㪛㪶㪪㪬㪙㩷
㪉㪌㩷㪧㪠㪥㪧㫉㫆㫋㪼㪺㫋㩷㪼㪸㫉㫋㪿㪆㪚㪿㪸㫊㫀㫊㩷㪼㪸㫉㫋㪿
㫏㫏㫏㫏㫏㪧㪸㫉㫋㩷㫅㫌㫄㪹㪼㫉
㪈
㪤㪦㪣㪜㪯㩷㪉
㪋㩷㪧㪠㪥㪊㪙㪼㪸㪻
' 㪋
'
㪌㪊㪉㪎㪎㪋㪈㪈
㩺㪉㪉㩷㪩㪜㪛㪉㪋㪭㪫㫎㫀㫊㫋㩷㫎㫀㫉㪼
㩺㪉㪉㩷㪙㪣㪢㪉㪌㪈㪋㪉㪇㪉㪎㪄㪉㩷㪪㫀㫅㪾㫃㪼
㪉㪋㪭㩷㪩㪫㪥
㩺㪉㪉㩷㪩㪜㪛㪉㪋㪭㪊㪡㪉
RF XMT 㩺㪉㪉㩷㪙㪣㪢㪉㪋㪭㩷㪩㪫㪥㪋
㪈
㪂㪌㪭㪘㩺㪈㪋㩷㪩㪜㪛㩷㪊 DAS ASSY 㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪉㪘㪞㪥㪛㩺㪈㪋㩷㪮㪟㪫㪋
㪊㪄㪌㪭㪘㩺㪈㪋㩷㪞㪩㪥㪌㪌㪈㪋㪉㪇㪉㪎㩷㪛㫌㪸㫃
㪎
㪝㪠㪙㪜㪩㪡㪋㪋
㪏㪬㪥㪠㪭㩷㪈㪉㩷㪪㪿㫀㪼㫃㪻㩷㫎㫀㫉㪼
㪌
㪦㪧㪫㪍
㪂㪌㪭㪣㩺㪈㪋㩷㪩㪜㪛㩷
㪐㪧㪠㪥
㪩㪝ห䕈㪎㪈
㪪㪤㪙㪪㪤㪙㪛㪞㪥㪛㩺㪈㪋㩷㪙㪣㪢㩷㪉㪪㫆㪺㫂㪼㫋㪧㫀㫅
㪏
㩺㪈㪋㩷㪰㪜㪣㪍㪈㪠㫅㫋㪼㫉㫅㪸㫃㩷㪺㫆㫅㫅㪼㪺㫋㫆㫉
㪐
㪉
㪦㪧㪫㪚㫆㫅㫅㪼㪺㫋㪼㪻㩷㫇㫆㫀㫅㫋
( (
&4 Wang, donghua 2010.05.30 LingLong Dual/Single Gantry SCHEMATIC
%*
2#)'
#22 㪌㪊㪉㪊㪐㪉㪊㩷㪪㪚㪟 2/2
5+<' 4'8<10'&#6' 4'8$; Yang, lingfeng 2010.05.30
# /+%41
1-4 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 2 - TGP BD ASSY

1 2 3 4 5 6 7 8
A A
GANTRY
1 ------ 10-07-08 LIU LINA
2 2079407 03-20-09 LIU LINA
3 2083382 07-02-09 LIU LINA
4 2100389 05-31-10 LIU LINA
PART NAME SHEET NUMBER
TGPL 1-2
B CONNECTOR_POWER 3-7 B
GNT 8-12
NOTES:
OC 13
1. THE VARIATION AND VERSION FOR THIS
PWA IS 5310990 REV5. TBL 14-16
2. THIS COVER SHEET CONTROLS THE RE-

CPU 17-24
VISION STATUS OF THE ENTIRE DOCUMENT.
THE REVISION OF ALL SHEETS OF THIS MISC 25-29
DOCUMENT WILL BE AT THE SAME LEVEL.
3. THIS SCHEMATIC MEETS THE SPECIFICA-
TIONS OF THE GLOBAL SCHEMATIC STANDARD
GUIDELINES 2299773GSP.
SCHEMATIC REVIEWER(S) AND APPROVER(S)
C CAN BE FOUND WITHIN MY WORKSHOP. C
INDUCTORS ARE IN HENRIES.
6. THIS PWA IS ESSENTIAL TO FUNCTION AND
THE ACCEPTANCE CRITERIA REFERS TO DOC0580909
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Mon May 31 11:49:52 2010 tgpl 1 of 2 5310990SCH 4 1 of 29

1 2 3 4 5 6 7 8
GANTRY 2-1
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
GPLS1_N
SILP_RING[5..0]
DTB[9..0]
GANTRY_DRIVER[13..0]
GANTRY_COVER[18..0] I48
RELAY_INF[1..0]
A OCXLED_N_F CONNECTOR_POWER A
I44
I40
GPLS1_N
CPU SLIP_RING<5..0>
GNT DTB<9..0>
OCXLED GANTRY_DRIVER<13..0>
RELAY_INF<1..0> RELAY_BUS<1..0> RELAY_BUS[1..0] RELAY_BUS<1..0> GANTRY_COVER<18..0>
GANTRY_COVER<18..0> DRIVER_BUS[10..0] RELAY_INF<1..0>
DRIVER_BUS<10..0> DRIVER_BUS<10..0>
GANTRY_DRIVER<13..0> COVER_BUS<13..0> COVER_BUS[13..0] COVER_BUS<13..0> I42
DTB<9..0> SLIP_R<2..0> SLIP_R[2..0] SLIP_R<2..0> OC
SLIP_RING<5..0> OCCOM[5..0]
DTB_BUS<4..0> DTB_BUS[4..0] DTB_BUS<4..0> OCCOM<5..0>
GPLS1_N OCXLED OCXLED EMRG-L EMRG-L
RST_N RST_N RST_N OCCOM<5..0>
OC_BUS<1..0> OC_BUS[1..0] EMRG_OC_L EMRG_OC_L
OC_BUS<1..0> EMRG-L
SAFE-L SAFE-L
GMT_SAFE GMT_SAFE GMT_SAFE EMRG_OC_L
SAFE-L SAFE_OC_L
RLIN_N_F RLIN_N_F RLIN_N_F
SAFE_OC_L RLIN_N
EMRG_LOOP_OPEN EMRG_LOOP_OPEN EMRG_LOOP_OPEN SAFE_OC_L
TABLE_BUS<12..0> RLIN_N RLIN_N
B B
JTAG_TCK
SWITCH_BUS<18..0>
JTAG_TCK JTAG_TCK
JTAG_TMS
ETHERNET<19..0>
CPLD_RESET_N
JTAG_TMS JTAG_TMS FPGA_TDI
LED_BUS<18..0>
CPLD_TDO
FPGA_TDI FPGA_TDI
DEBUG<19..0>
CPLD_TDO CPLD_TDO
DEBUG<19..0> DEBUG[19..0]
I46
TBL
ERST_L
TGCOM<3..0> TABLE_BUS<12..0> TABLE_BUS[12..0] ERST_OC_L
TABLE_CONTROL<6..0>
SWITCH_BUS[18..0]
CPLDE_RESET_N
ETHERNET[19..0]
LED_BUS[18..0]
C PHY_TDI C
CRADLE_POT<2..0> ETHERNET_INF<5..0>
PHY_TDO
I47 RESET_INF<1..0>
TRST_N
CRADLE_POT<2..0>
CPLD_RESET_N
TABLE_CONTROL<6..0>
SWITCH_BUS<18..0>
ERST_L ERST_L TGCOM<3..0>
ETHERNET<19..0>
LED_BUS<18..0>
RST_N ERST_OC_L ERST_OC_L
PHY_TDI PHY_TDI
ETHERNET_INF<5..0> ETHERNET_INF[5..0]
PHY_TDO PHY_TDO
RESET_INF<1..0> RESET_INF[1..0]
TRST_N
MISC_PART TRST_N
JTAG_TCK
JTAG_TMS
D D
CRADLE_POT[2..0]
TABLE_CONTROL[6..0]
REV 2 01July04
TGCOM[3..0]
GE Healthcare
Company Restricted
B Size
Fri Mar 27 11:24:46 2009 tgpl 2 of 2 5310990SCH 4 2 of 29

1 2 3 4 5 6 7 8
2-2 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
CONNECTOR
POWER SUPPLY
CN18 MIC1
A CN1
CN2 PDU
CN5 OC
A
MIC1+ 1
EMRG-H 3 1 SAFE-H 3B6< 1

24V_IN 2 1 GND_IN 3B4< 3 2 1 3A6< 3C6< MIC- 2 1
6A1< 4B1< 2 1 6A1< 2 ERST_H 3B8> 2 1
4 3 3B6< 3C6< 3B5< 3 OGCOM_H 2 14 OGCOM_L
4 3 EMRG-L 6 4 SAFE-L 3 5C3> 2 14 5C3>
2B7^ IN 6 5 4 IN 2B7^ GOCOM_H 3 15 GOCOM_L
5 ERST_L 5D3< 3 15 5D3<
OUT 2C7^ 24V 5C7> RESET_H 4 4 16 16 RESET_L 5C7<
PIN PIN 5D3< OCXLED_H 5 5 17 17 OCXLED_L 5D3<
PIN 6 18
STRAIGHT GND STRAIGHT 6 18
STRAIGHT 7 19
MATE_N_LOK WIRE_TO_BOARD 7 19
MATE_N_LOK EMRG_OC_H 8 20 EMRG_OC_L
4A5< 3C6< 8 20 OUT 3C8> 2B7^
3C6< 3A4< SAFE-H 9 9 21 21 SAFE_OC_L 3C8>
2B7^
IN
3C6< 3A4< ERST_H 10 22 ERST_OC_L GND
10 22 OUT 3C8> 2C7^
3A5> MIC1+ 11 11 23 23
3B5> MIC2+ 12 12 24 24 MIC- 3A5< 3B5<
3C3> SPK+ 13 13 25 25 SPK- 3C3>
CN8 GPLS1
VCC CN7 SLIP RING CN12 MIC2
G1 G1
G2 G2
1 1
5C3< GSCOM-H 1 1 2 2 GSCOM-L 5C3< 3B6< MIC2+ 1 1
2A7^ GPLS1_N 2 2
OUT SGCOM-H 3 4 SGCOM-L MIC- 2
GANTRY
3 5C3> 3 4 5C3> 3A5< 3B8> 2
3 GDTRIG-H 5 6 GDTRIG-L 3
4 5C3< 5 6 5C3< 3 PIN
4 7 8 GND
7 8 RIGHT_ANGLE
9 9 10 10 STD_DENSITY
GND PIN
PIN
STRAIGHT
B STRAIGHT
PIN
GND
WIRE_TO_BOARD
B
WIRE_TO_BOARD
STRAIGHT
RIBBON_CABLE_STANDARD
CN3 EMRG SW
S2
VCC CN11 TABLE VCC EMRG-H 1 CHS_04TB

3A3< 1
4A4> EMRG2 2 2
1 1 10 10 4A5< 3A6< EMRG_OC_H 1 I1 O1 8 EMRG_OC_L 3A8> 2B7^
5A3> CRDLPLS_B 2 2 11 11
CRDLPLS_A 3 12 PIN SAFE-H 2 7 SAFE_OC_L
5A3> 3 12 3A6< 3A4< I2 O2 3A8<
2B7^
4 13 24V STRAIGHT
4 13
5 14 TGCOM_P MATE_N_LOK ERST_H 3 6 ERST_OC_L
5 14 5B3> 3B6< 3A4< I3 O3 3B8>
2C7^
5B3< CPPOT_H 6 6 15 15 TGCOM_N 5B3>
5B3> CPPOT_M 7 7 16 16 R57 10K 4 I4 O4 5
5B3< CPPOT_L 8 8 17 17 LATCH 5A3>
9 9 18 18 R73 10K NOT MOUNT
R78 10K 24V CN19 RESERVED FOR SBRK
C 19 19 CINPLS 5A3<
USED TO SHORTEN EMRG, ERST AND SAFETY LOOP OF OC
C
20 20 COUTPLS 5A3<
GND 21 21 EX_OFF 5A3< 1 1
22 22 STEPSEL 5A3< 5C5> SBRK_N 2 2
23 23 GTCOM_P 5B3<
24 24 GTCOM_N 5B3<
25 25 SPK+ 3B6< PIN
26 26 SPK- 3B8> STRAIGHT
WIRE_TO_BOARD
G1 G1
G2 G2
SOCKET
RIGHT_ANGLE GND
SUBD HIGH_DENSITY CN14 UART1 24V CN10 X-DIS
CONNECTION BETWEEN UART AND PC
5C5< UART1_TX 1 1 1 1
24V 5C5> UART1_RX 2 2 SERIALCN14 PC COM
5B5< XLEDON_N 2 2
CN4 RELAY 3 3
1 2
2 3
RLIN_N 1 3 5 PIN
2B7^ OUT 1 PIN
2 STRAIGHT
2 STRAIGHT
3 GND WIRE_TO_BOARD
3 WIRE_TO_BOARD
5C7> XRAY_ON_N 4 4
D 5 5
D
5C7< SYS_READY_N 6 6
REV 2 01July04
GND PIN
STRAIGHT
WIRE_TO_BOARD GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:42 2010 connector_power 1 of 5 5310990SCH 4 3 of 29

1 2 3 4 5 6 7 8
GANTRY 2-3
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
R294 DON'T MOUNT

FL1
NFM55PC155F1H4
0
1 3 1W
S5
+0.05
1.5UF GND CHS_04TB
2
4
2B7^ CPLD_TDO 1 I1 O1 8 JTAG_TDO 4B5<

GND IN
CN9 AXIAL PIN 18 IS THE SHIELD FOR CAN OPEN CN6 COVER
A 2C7^ IN
PHY_TDO 2 I2 O2 7 A
GND
1 EMRG2 1 2 EMRG_OC_H 3 6 PHY_TDI
1 3C4> 1 2 3A6<
3C6< I3 O3 OUT 2C7^
VCC 5B5< DRIVER_EN 2 2 14 14 FAULT_RESET 5B5< 12V 5A5> CN_INR 3 3 4 4 CN_OUTR 5A5>
5B5< DV_NC 3 3 15 15 HOME_FLAG 5B5< 5A5> CN_FAST 5 5 6 6 CN_EXLMR 5A5> 4 I4 O4 5
4 4 16 16 ERROR_RTN 5B5< 5A5> CN_PLSW 7 7 8 8 CN_DGND 5B5<
5 5 17 17 5B5< CN_5V 9 9 10 10 A0 5A5<
5B5<> CAN_H 6 6 18 18 5A5< CN_XLEDON_N
11 11 12 12 B1 5A5<
7 7 19 19 CAN_L 5B5<> 5A5< B0 13 13 14 14 B3 5A5< WHEN 1 ON, 2, 3 OFF: FPGA + CPLD ONLY
5B5> AXPLSA_H 8 8 20 20 5A5< B2 15 15 16 16 SL0 5A5< WHEN 1 OFF, 2, 3 ON: FPGA + CPLD + PHY
ISOGND
5B5> AXPLSB_H 9 9 21 21 AXPLSA_L 5B5> 5A5< SL1 17 17 18 18 SL2 5B5<
5B5> AXPLSZ_H 10 10 22 22 AXPLSB_L 5B5> GND 5B5< CN_24V 19 19 20 20 CN_24V_GND 5B5<
11 11 23 23 AXPLSZ_L 5C5>
6A1< 3A1< 24V_IN 12 12 24 24
13 13 25 25 PIN
STRAIGHT
G1 G1 RIBBON_CABLE_STANDARD
GND GND 3V3
G2 G2
PIN12 AND PIN24 NOTE:
WHEN TGPL POWER ON
IT MAKES SBRK OFF SOCKET GND
RIGHT_ANGLE
0.1W
0.1W
0.1W
0.1W
STD_DENSITY 3V3
10K
10K
10K
10K
GND
GND
DIR2
0.1W
5D5 JTAG_TDO 3 3 4 4
74LVC-LCX245 74LVC-LCX245 JTAG_TMS 5 6
2B7^ 5 6
1%
OUT
R228
1%
TRST_N 7 8
R233
2C7^ OUT 7 8
2B7^ FPGA_TDI 9 9 10 10
19 OE_N CN15 TEST 19 OE_N OUT
5D5< DIR1 1 DIR 1 DIR
0 2 18 1 2 2 18 8 PIN
A<7> B<7> 1 2 A<7> B<7>
1 3 17 3 4 3 17 9 STRAIGHT GND
A<6> B<6> 3 4 A<6> B<6>
2 4 16 5 6 4 16 10 DUAL_ROW_HEADER_BREAK
A<5> B<5> 5 6 A<5> B<5>
3 5 A<4> B<4> 15 7 7 8 8 5 A<4> B<4> 15 11
4 6 A<3> B<3> 14 9 9 10 10 6 A<3> B<3> 14 12
5 7 A<2> B<2> 13 11 11 12 12 7 A<2> B<2> 13 13
6 8 A<1> B<1> 12 13 13 14 14 8 A<1> B<1> 12 14
7 9 A<0> B<0> 11 15 15 16 16 9 A<0> B<0> 11 15 3V3 CN16 ETHERNET
17 17 18 18
19 19 20 20 3V3
3V3 3V3
VCC=3V3;GND=GND VCC=3V3;GND=GND R15
C NOT MOUNT 3V3 332 R290 10K C
PIN 0.1W
GND 1% 0.125W 1% R292
STRAIGHT
2
GND 332
0.1W
TEST<15..0> 5D6<> R291 10K 1%
FL2 0.125W 1%
FPGA WILL WRITE DIR1 AND DIR2 TO CONTROL THE DATA DIRECTION BLM21BD471SN1
WHEN LOW: B IS INPUT, A = B 470 OHM LED 1
8 7 LED_CFG1 5B7>
WHEN HIGH: A IS INPUT, B = A
LED_CFG2 R14 332 10 9
5B7>
1
0.1W 1%
LED 2
1 1
5B7< TPOP 2 2
5B7< TPON 3 3
CN17 DTB 5B7> TPIP 4 4
5B7> TPIN 5 5 G1 G1
6 6 G2 G2
5A7> DTB_OUTA_P 1 1 2 2 DTB_OUTA_N 5A7<
5A7< DTB_OUTB_P 3 3 4 4 DTB_OUTB_N 5A7< C86
5A7< DTB_SA_OP_P 5 5 6 6 DTB_SA_OP_N 5A7< 10N SOCKET GND
5A7< RESET_DTB_P 7 7 8 8 RESET_DTB_N 5A7> 50V RIGHT_ANGLE
5A7> XRAY_DTB_P 9 9 10 10 XRAY_DTB_N 5A7> 10% JACK_LED1_YEL_LED2_GRN-OR
D PIN
D
STRAIGHT GND
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-4 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
TABLE INTERFACE
GANTRY INTERFACE
DTB INTERFACE
2A7^ GANTRY_COVER<18..0>
2C7^ TABLE_CONTROL<6..0> IO
IO
A 6 LATCH 3C3>
18 CN_INR 4A4>
2A7^ IO
DTB[9..0] A
17 CN_OUTR 4A5>
5 CINPLS 3C3< 16 CN_FAST 4A4>
4 COUTPLS 9 DTB_OUTA_P
3C3< 15 CN_EXLMR 4D2>

3 EX_OFF 4A5> 8 DTB_OUTA_N
3C3< 14 CN_PLSW 4D3>
2 STEPSEL 4A4> 7 DTB_OUTB_P
3C3< 13 A0 4D2>
1 CRDLPLS_B 4A5< 6 DTB_OUTB_N
3C1< 12 CN_XLEDON_N 4D3>
0 CRDLPLS_A 4A4< 5 DTB_SA_OP_P
3C1< 11 B0 4D2>
4A4< 4 DTB_SA_OP_N
10 B1 4D3>
4A5< 3 RESET_DTB_P
9 B2 4D2<
4A4< 2 RESET_DTB_N
8 B3 4D3<
4A5< 1 XRAY_DTB_P
7 SL0 4D2<
TGCOM<3..0> 4A5< 0 XRAY_DTB_N
2C7^ IO 6 SL1 4D3<
4A4<
5 SL2 4A5<
3 TGCOM_P 3C3> 4 XLEDON_N 3D6<
2 TGCOM_N 3C3> 3 CN_5V 4A4<
1 GTCOM_P 3C3< 2 CN_DGND 4A5>
0 GTCOM_N 3C3< 1 CN_24V 4A4<
0 CN_24V_GND 4A5>
CRADLE_POT<2..0>
GANTRY
2C7^ IO ETHERNET INTERFACE
2 CPPOT_H 3C1>
1 CPPOT_M 3C1<
2A7^ GANTRY_DRIVER<13..0>
0 CPPOT_L 3C1> IO
13 DRIVER_EN 4A1< 2C7^ ETHERNET_INF[5..0]
B 12 FAULT_RESET 4A3<
IO B
11 DV_NC 4A1< 5 LED_CFG1 4C8<
10 HOME_FLAG 4A3< 4 LED_CFG2 4C5<
9 ERROR_RTN 4A3> 3 TPOP 4D5<
8 CAN_H 4A1< 2 TPON 4D5<
SLIP RING 7 CAN_L 1 TPIP
4A3> 4D5>
6 AXPLSA_H 4A1> 0 TPIN 4D5>
5 AXPLSA_L 4A3<
4 AXPLSB_H 4A1>
3 AXPLSB_L 4A3<
2A7^ SLIP_RING<5..0>
IO 2 AXPLSZ_H 4A1>
1 AXPLSZ_L 4B3<
5 GSCOM-H 3B3< 0 SBRK_N 3C4>
4 GSCOM-L 3B4<
3 SGCOM-H 3B3>
2 SGCOM-L 3B4>
1 GDTRIG-H 3B3<
0 GDTRIG-L 3B4<
DEBUG INTERFACE 2A7^ RELAY_INF[1..0]
IO
1 XRAY_ON_N 3D1<
C 0 SYS_READY_N 3D1< C
2B7^ DEBUG[19..0]
IO
19 UART1_TX 3D3<
OC INTERFACE 18 UART1_RX 3D3>
17 15
2C7^ RESET_INF[1..0]
16 14 OUT
15 13
14 12
2B7^ OCCOM<5..0> 1 RESET_H 3A6>
IO 13 11
0 RESET_L 3A8>
12 10
5 OGCOM_H 3A6> 11 9
4 OGCOM_L 3A8> 10 8
3 GOCOM_H 3A6< 9 7
2 GOCOM_L 3A8< 8 6
1 OCXLED_H 3A6< 7 5
0 OCXLED_L 3A8< 6 4
5 3
4 2
3 1
2 0
TEST<15..0> 4C4<>
D D
1 DIR1 4B1<
0 DIR2 4B2<
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Thu Jul 02 14:42:11 2009 connector_power 3 of 5 5310990SCH 4 5 of 29

1 2 3 4 5 6 7 8
GANTRY 2-5
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U15 TP5
LT1764A
A F1
12V
TIN
ISOVCC A
RESETTABLE 2 4
24V_IN VIN VOUT
4B1< 3A1< FL15 1 5

TP2 SHDN_N SENSE_ADJ
BNX002_01
1.1A C106 C107 24V R44
30V C10 GND 3 3.32K
0.1U 0.1U TIN 22U 6 0.1W C17 C19 C22
50V 50V 1 B CB 2 TAB_GND ISOGND
35V 1% 470P 0.1U 22U
10% 10% 20% 35V TP17
GND_IN 3 4 C11 50V 16V
3A2> C8 5% 10% 10%
PSG CG 22U 1.21V TO 20V
10U TIN
G1 35V 35V R45
G1 1.05K
G2 G2 +80%-20% 20%
ISOGND ISOGND 0.1W
1%
40 DB (1MHZ TO 1GHZ) ISOGND

VOUT=1.21*(1+3.3/1.05)=5.0129
GND ISOGND
U36
PTN78020W 24V U16
SC001A2B91Z TP6
B TP3 B
VO_SENSE 5 F2 TIN 12V
24V 3 INHIBIT_N VO_ADJ 4 TIN VCC 5VA 3 ON_OFF TRIM 5 RESETTABLE
L1 1 VINP VOUTP 4
2 VI VO 6 2 VINN VOUTN 6
0.75A
22N
1 R41 C12 30V
C79 GND1 5% C132 1K
GND2 7 R74 1A 47U 12V C15 C18 C20 D6
22U 22U 0.1W 35V
35V 10K 1% 470P 0.1U 22U MMSD4148
10V 20% 35V
10% 0.1W 50V 50V 100V

0.1% +80%-20% 10%
2.5V TO 12.6V C116 C119 5% 10%
C121
470P 0.1U 22U
GND 50V 16V 35V
R250 5% 10% GND GND ISOGND
10K 10%
GND
0.1W
0.1%
ISOGND
GND
C C
U14 TP4
U8 TP1
LT1764A
LT1764A VCC 3V3
VCC 1V2 TIN
TIN
2 VIN VOUT 4
2 VIN VOUT 4
1 SHDN_N SENSE_ADJ 5
1 SHDN_N SENSE_ADJ 5 3V3
R42
R37 C9 3 1.74K
C2 3 0 GND
GND 22U 6 0.1W C13 C14 C16
22U 6 0.1W C5 C6 C7 TAB_GND
TAB_GND 35V 1% 22U
0.1W
35V +0.05 22U 470P 0.1U
470P 0.1U 20%
332
20% 50V 16V 35V
50V 16V 35V 10%
10% 1.21V TO 20V 5% 10%
1.21V TO 20V 5% 10%
R43
R39
1%
1K
R174
1K GND GND 0.1W
GND GND 0.1W POWER DESIGNATOR
2
1%
1%
VOUT=1.21*(1+1.74)=3.315
GREEN
GND
DS21
GND
VOUT=1.21*(1+0)=1.21
1
GND
GND
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-6 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
1V2 1V2 3V3
3V3A ISOVCC
FL3
1V2_PLLA 1V2_PLLD 3V3_CLK BLM21PG221SN1
L4 L5 L7 1 2
220 OHM C75 C76 C77
22N 22N 22N C92 C93
5% 5% 5% C91 0.1U 0.1U 0.1U
C51 C52 C53 C54 C56 C57 C267 C268 C269 0.1U 10U 16V 16V 16V
1A 1A 1A 1U
A 1U 2.2U 10N 1U 2.2U 10N 1U 2.2U 10N 10V
16V 35V 10% 10% 10% A
10% +80%-20%
10V 10V 50V 10V 10V 50V 10V 10V 50V 10%
10% 10% 10% 10% 10% 10% 10% 10% 10%
ISOGND
GND
GND GND GND
5VA
VCC
MH1
C90 MHP5_00TB8_00
C48 C50 C59 C67 C68 C69 C71 C73 C74 C80 C81 C82 C83 C84 C95 C96 C97 C98 C99 C100 C114 C85 C133 C134 0.1U
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 16V
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10%
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GANTRY
GND
GND
B GND B
3V3
1V2 MOUNT HOLES
TP16 TP7 TP8 TP9 TP10 TP12 TP13 MH2

MH3 MH4 MH6
MHP5_00TB8_00
C70 C72 C101 C104 C105 C108 C109 C110 C151 C152 C153 C154 C155 C156 MHP5_00TB8_00 MHP5_00TB8_00 MHP5_00TB8_00
0.1U 0.1U 0.1U 0.1U 10N 10N 10N 10N 4.7U 4.7U 4.7U 4.7U 4.7U 4.7U TIN TIN TIN TIN TIN TIN TIN
16V 16V 16V 16V 50V 50V 50V 50V 25V 25V 25V 25V 25V 25V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND GND GND GND
GND
GND GND
C C
3V3
MH5
MHP5_00TB8_00
C23 C24 C26 C28 C34 C35 C37 C38 C40 C41 C43 C44 C45 C49 C58 C60 C66 C111 C112 C113 C115 C117 C118 C120 C131
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND
GND
3V3
C122 C123 C124 C125 C126 C127 C128 C129 C130 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C157 C158 C159 C160
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
D D
REV 2 01July04
GND
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-7
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
DON'T MOUNT DON'T MOUNT
GANTRY R295 R297

A A
FL8 0 0
NFA31CC222R1E4 1W 1W
+0.05 +0.05
12B3> CN_INR 3 A1 B1 7 INR 8B1< FL12 FL13

VCC
12B3> CN_OUTR 4 A2 B2 8 OUTR 8B1< NFM55PC155F1H4 NFM55PC155F1H4
12B3> CN_FAST 5 A3 B3 9 FAST 8B1<
12B3> CN_EXLMR 6 A4 B4 10 EXLMR 8C1< 1 3 CN_5V 12B3< 1 3 CN_24V_GND 12B3<
1 1.5UF 1.5UF
GND1
GND2 2
GND
2
4
2
4
2200PF
GND
R305
R306
R307
R308
GND GND
1K GND
0.1W
1%
DON'T MOUNT DON'T MOUNT

B B
U9
R296 R299
74LVC_LCX244
0 0
1 OE_N<1> 1W 1W
+0.05 +0.05
8A4> INR 2 A1<1> Y1<1> 18 IN_R 12B5<
8A4> OUTR 4 A2<1> Y2<1> 16 OUT_R 12B5< FL11 FL10

8A4> FAST 6 A3<1> Y3<1> 14 FAST_R 12B5< 24V NFM55PC155F1H4 NFM55PC155F1H4
8A4> EXLMR 8 A4<1> Y4<1> 12 EXLM_R 12B5<
1 3 CN_24V 12B3< 1 3 CN_DGND 12B3<
19 OE_N<0>
1.5UF 1.5UF
8D8> PLSW 11 A1<0> Y1<0> 9 PLSW_R 12B5<
13 A2<0> Y2<0> 7 GND
2
4
2
4
15 A3<0> Y3<0> 5
17 A4<0> Y4<0> 3
R412
1K
0.1W VCC=3V3;GND=GND GND GND
C 1% GND C
GND
GND
R410
VCC 1K U49
0.1W 74VHCT_AHCT244
24V 1%
FL29
R281 1 OE_N NFA31CC222R1E4
4.99K U41 D32
0.1W 75452B MMSD4148 2 A1 Y1 18
1% 100V 12B5> B0_SRC 4 A2 Y2 16 3 A1 B1 7 B0 12B3<
12B5> A0_SRC 6 A3 Y3 14 4 A2 B2 8 A0 12B3<
1 A<1> 8 A4 Y4 12 5 A3 B3 9 CN_XLEDON_N 12B3<
12B5> CV_XRAYON_S 2 B<1> Y<1> 3 XLED_ON_N 8D5< 6 A4 B4 10 PLSW 8C1<
R36 R22
6 1K 1K 1
R249 A<0> 0.1W 0.1W VCC=VCC;GND=GND GND1 R163
1K 7 5 D33 2 1K
B<0> Y<0> 1% 1% GND2
0.1W MMSD4148 0.1W
1% 100V 1%
2200PF
VCC=VCC;GND=GND
GND
D GND
GND D
GND
GND
GND
XLED_ON_N
REV 2 01July04
8D4>
12B3> CN_PLSW
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:18 2010 gnt 1 of 5 5310990SCH 4 8 of 29

1 2 3 4 5 6 7 8
2-8 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC
FL27
U29
NFA31CC222R1E4
74LVC1G14
0.1W
1K
3V3 GPLS1
TP21
3 A1 B1 7
5 VCC
A 4 A2 B2 8 B3 12B3< A
R179
U52 R180 100
1%
5 A3 B3 9 B2 12B3< Y_N TIN
74VHCT_AHCT244 2B1^ GPLS1_N 2 A 4 GPLS1 12C5<
6 A4 B4 10 B1 12B3< IN
0.1W 1% C78 1 3
1 NC1 GND
1 GND1
OE_N<1> 2 10N
GND2 50V
2 A1<1> Y1<1> 18 10%
B3_SRC 4 16 2200PF GND
12B5> A2<1> Y2<1>
12B5> B2_SRC 6 A3<1> Y3<1> 14
GND
12B5> B1_SRC 8 A4<1> Y4<1> 12
GND
19 FL28
OE_N<0>
NFA31CC222R1E4
CUT-OFF FREQUENCY = 160KHZ
12B5> SL2_SRC 11 A1<0> Y1<0> 9
12B5> SL1_SRC 13 A2<0> Y2<0> 7
3 A1 B1 7 SL2 12B3< VCC
12B5> SL0_SRC 15 A3<0> Y3<0> 5
4 A2 B2 8 SL1 12B3< 24V
17 A4<0> Y4<0> 3
5 A3 B3 9 SL0 12B3<
6 A4 B4 10
R486 R21
1K VCC=VCC;GND=GND 1 4.99K U5 D1
0.1W GND1 0.1W 75452B MMSD4148
GANTRY
1% GND2 2 1% 100V
2200PF 1 A<1>
GND 2A1^ OCXLED 2 B<1> Y<1> 3 XLEDON_N 12B3<
GND IN
B R3 6 A<0>
B
1K 7 5 D2
B<0> Y<0>
0.1W MMSD4148
1% 100V
VCC=VCC;GND=GND
VCC
U27 GND
HCPL0631 U25 GND
51.1
R131 74LVC1G14
12C5> SGCOM-H R133 3V3
VCC 8 2K
0.1W 1% 0.1W 5
D69 VCC
100V 1 VO 1% R135 R282
7 2 Y_N 4 SGCOM
A 12B7<
51.1 2
R132
SGCOM-L GND 5 100 C42 1 3 51.1
12C5> NC1 GND
0.1W 0.1W
MMSD4148 10N
0.1W 1% 1% 50V 1%
10%
GND GND
C C
GND
GND
GND 24V
VCC VCC 24V
U26
R491 R487 U28
R398 U10 R489 1K DS26C31T 4.99K D21 D26
1K 4.99K 75452B
74VHCT_AHCT244 0.1W 0.1W MMSD4148 MMSD4148
0.1W 0.1W 1% 1% 100V 100V
1% 1% 12 EN_N 1 A<1>
19 OE_N 4 EN
12D5> XRAY_ON_S 2 B<1> Y<1> 3 XRAY_ON_N 12D3>
12B7> GSCOM 11 A1 Y1 9 1 I<3> OUTP<3> 2 R381 51.1 GSCOM-H 12C5< 6 A<0>
12B7> GDTRGSRC 13 A2 Y2 7 OUTN_N<3> 3 R382 51.1 GSCOM-L 12C5<
12D5> SYS_READY_S 7 B<0> Y<0> 5 SYS_READY_N 12D3<
15 A3 Y3 5 7 I<2> OUTP<2> 6 R383 51.1 GDTRIG-H 12C5<
17 A4 Y4 3 OUTN_N<2> 5 R384 51.1 GDTRIG-L 12D5<
9 I<1> OUTP<1> 10
11 R278 VCC=VCC;GND=GND
OUTN_N<1> 1K R434
VCC=VCC;GND=GND 15 I<0> OUTP<0> 14 1K D22 D27
0.1W
OUTN_N<0> 13 1% 0.1W MMSD4148 MMSD4148
GND 1%
R252 100V 100V
1K
0.1W VCC=VCC;GND=GND
1%
D GND
GND D
GND
GND
GND
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-9
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC
24V
U59
AXPLSA_H R27 51.1 HCPL0631
12C3>
0.1W 1% TP15 24V R34
R30 U45 2.49K
D3 VCC 8 2K
TIN 0.25W
100V 0.1W 74LVC-LCX14 1%
4 VO 1% R284
U40 D5
2
6 5 6 AXPLSA 12C5<
A 12C3> AXPLSA_L R28 51.1 3
A B
VCC 75452B MMSD4148 DS22 SBRK A
GND 5 51.1 100V HSMG-C190
0.1W 1% MMSD4148
0.1W GREEN
VCC=3V3;GND=GND 1
1% A<1>
12C5> SBRK 2 B<1> Y<1> 3 SBRK_N 12C3>
1
6 A<0>
GND
7 B<0> Y<0> 5
D28
MMSD4148
VCC=VCC;GND=GND 100V
VCC
U59
HCPL0631
AXPLSB_H R24 51.1 GND
12C3> TP14
R31
0.1W 1% 2K U45
D4 VCC 8 GND
0.1W TIN
100V 1% 74LVC-LCX14
1 VO R283
7 9 A B 8 AXPLSB 12C5<
AXPLSB_L R25 51.1 2
12C3>
GND 5 51.1 R33 U37
0.1W 1% MMSD4148 1K
0.1W 74VHCT_AHCT244
VCC=3V3;GND=GND 0.1W
1%
1%
B 1 OE_N<1>
B
GND
12C5> DR_EN_N 2 A1<1> Y1<1> 18 DRIVER_EN 12C3<
2B3^ IN RST_N 4 A2<1> Y2<1> 16 FAULT_RESET 12C3<
VCC
12C5> HOME_F 6 A3<1> Y3<1> 14 HOME_FLAG 12C3<
12C5> DV_NC_F 8 A4<1> Y4<1> 12 DV_NC 12C3<
U69
HCPL0631 19
AXPLSZ_H R269 51.1 OE_N<0>
12C3>
R271
0.1W 1% 2K U45 11 9
8 A1<0> Y1<0>
D8 VCC 0.1W 13 7
A2<0> Y2<0>
100V 1% 74LVC-LCX14 15 5
1 A3<0> Y3<0>
VO 17 A4<0> Y4<0> 3
7 3 A B 4 AXPLSZ 12C5<
AXPLSZ_L R270 51.1 2
12C3>
0.1W 1% MMSD4148 GND 5
VCC=VCC;GND=GND
VCC=3V3;GND=GND
GND
C VCC C
U69 3V3 GND
HCPL0631 3V3
12C3< ERROR_RTN R2 332
R230
0.1W 1% 2K U34
D24 VCC 8 R166 R122 U33
0.1W
100V 1% 74LVC-LCX14 1K 1K DS26LV31T
4 VO 0.1W 0.1W D12 D14 D18 D20
6 1 2 DV_ERROR 12C5< 1% 1%
A B
3 12 EN_N 100V 100V 100V 100V
MMSD4148 GND 5 4 EN
VCC=3V3;GND=GND
12C7< RESET_DTB 1 I<3> OUTP<3> 2 R169 51.1 RESET_DTB_P 12C7<
OUTN_N<3> 3 R170 51.1 RESET_DTB_N 12C7>
12C7< XRAY_DTB 7 I<2> OUTP<2> 6 R175 51.1 XRAY_DTB_P 12C7>
GND GND
OUTN_N<2> 5 R176 51.1 XRAY_DTB_N 12C7>
HCPL0631 WILL HAVE 6.9MA CURRENT 9 I<1> OUTP<1> 10
VCC
OUTN_N<1> 11
U35 15 I<0> OUTP<0> 14
R137 13
DTB_OUTA_P 51.1 HCPL0631 OUTN_N<0> D13 D17 D19 D23
12C7>
R168
0.1W 1% 1K
R178 U34 100V 100V 100V 100V
D29 VCC 8 2K 0.1W VCC=3V3;GND=GND
100V 0.1W 74LVC-LCX14 1%
4 VO 1% R285
D R177
51.1
6 3 A B 4 DTB_OUTA 12C7> D
12C7< DTB_OUTA_N 3
GND 5 51.1
0.1W 1% MMSD4148 GND GND
0.1W
REV 2 01July04
VCC=3V3;GND=GND
1%
GND GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-10 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
GND 3V3
0.1W
332
0.1W
332
A GND A
1%
R48
3V3
R79
R68
1%
ISOVCC
1K
CAN_TX
0.1W U67
GREEN
DS5
R47 74LVC_LCX244 VCC U19 U7
2
1% ISOVCC
CAN_RX
DS8
GREEN
2K HCPL0720-060 82C251 U23 R80 U67
0.1W ISOVCC HCPL0720-060 1K 74LVC_LCX244
1% VCC
1 OE_N 0.1W
VDD1 VDD2 1%
1
1 8 3 VCC
FPGA_CAN_TX 2 18 1 VDD1 VDD2 8 19
12C5<> A1 Y1 R51 51.1 OE_N
1
4 16 2 VI VO 6 R49 51.1 1 4
A2 Y2 TXD RXD R66 51.1
6 A3 Y3 14 0.1W 1% 8 RS VREF 5 2 VI VO 6 11 A1 Y1 9
8 12 4 5 0.1W 1% 13 7 R69 51.1 FPGA_CAN_RX
A4 Y4 A2 Y2 12C5<>
6 4 5 0.1W 1% 15 5
GND1 GND2 CANL A3 Y3 0.1W 1%
R50 7 17 3
47.5K CANH GND1 GND2 A4 Y4
VCC=3V3;GND=GND 0.1W
GND 1% GND 2
ISOGND VCC=3V3;GND=GND
ISOGND GND
GND
GND
R72 121
GANTRY
ISOGND 0.1W 1%
ISOGND CAN_L 12C3<>
CAN_H 12C3<>
B B
VCC
U35
R225
DTB_OUTB_P 51.1 HCPL0631
12C7<
0.1W 1%
R229 U34
D31 VCC 8 2K
100V 0.1W 74LVC-LCX14
1 VO 1% R287
R226 7 13 A B 12 DTB_OUTB 12C7>
DTB_OUTB_N 51.1 2
12C7<
GND 5 51.1
0.1W 1% MMSD4148
0.1W
VCC=3V3;GND=GND
1%
C GND C
VCC
U42
R217
DTB_SA_OP_P 51.1 HCPL0631
12C7<
0.1W 1%
R227 U34
D30 VCC 8 2K
100V 0.1W 74LVC-LCX14
1 VO<1> 1% R286
R224 7 5 A B 6 DTB_SA_OP 12C7<
DTB_SA_OP_N 51.1 2
12C7<
51.1
0.1W 1% MMSD4148
4 0.1W
VO<0> VCC=3V3;GND=GND
6 1%
3
5
GND
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-11
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
SLIP RING INTERFACE
2B3^ COVER_BUS[13..0]
IO 2B3^ SLIP_R[2..0]
IO
13 B0_SRC 8D5< 2 GDTRGSRC 9D1<
12 B1_SRC 9A1< 1 GSCOM 9D1<
11 B2_SRC 9A1< 0 SGCOM 9C6>
10 B3_SRC 9A1<
2A1^ GANTRY_COVER<18..0>
IO 9 OUT_R 8B4>
8 SL0_SRC 9B1<
18 CN_INR 8A1< 7 SL1_SRC 9B1<
17 CN_OUTR 8A1< 6 SL2_SRC 9B1<
16 CN_FAST 8A1< 5 PLSW_R 8C4>
15 CN_EXLMR 8A1< 4 EXLM_R 8C4>
14 CN_PLSW 8D5< 3 CV_XRAYON_S 8D1<
13 A0 8D8> 2 A0_SRC 8D5<
12 CN_XLEDON_N 8D8> 1 IN_R 8B4>
11 B0 8D8>
B 10 B1 9A4>
0 FAST_R 8B4> B
9 B2 9A4>
8 B3 9A4>
7 SL0 9B4>
6 SL1 9B4> DTB INTERFACE
5 SL2 9B4>
4 XLEDON_N 9B8>
3 CN_5V 8A6>
2 CN_DGND 8C8>
2A3^ DRIVER_BUS[10..0] 2B1^ DTB[9..0]

1 CN_24V 8C6> IO IO
0 CN_24V_GND 8A8> 10 AXPLSZ 10C5> 9 DTB_OUTA_P 10D1<
9 AXPLSB 10B4> 8 DTB_OUTA_N 10D1<
8 AXPLSA 10A5> 7 DTB_OUTB_P 11B3<
7 HOME_F 10B5< 6 DTB_OUTB_N 11C3<
6 SBRK 10A5< 5 DTB_SA_OP_P 11C3<
2B1^ GANTRY_DRIVER<13..0>
IO 5 DR_EN_N 10B5< 4 DTB_SA_OP_N 11D3<
4 DV_ERROR 10C5> 3 RESET_DTB_P 10D8>
13 DRIVER_EN 10B8> 3 GPLS1 9A8> 2 RESET_DTB_N 10D8>
12 FAULT_RESET 10B8> 2 FPGA_CAN_TX 11A1< 1 XRAY_DTB_P 10D8>
11 DV_NC 10B8> 1 FPGA_CAN_RX 11B8> 0 XRAY_DTB_N 10D8>
10 HOME_FLAG 10B8> 0 DV_NC_F 10B5<
9 ERROR_RTN 10C1<
C 8 CAN_H 11B6<> C
7 CAN_L 11B6<>
6 AXPLSA_H 10A1<
5 AXPLSA_L 10A1<
4 AXPLSB_H 10B1<
3 AXPLSB_L 10B1< 2B3^ DTB_BUS[4..0]
IO
2 AXPLSZ_H 10B1<
2B3^ SLIP_RING<5..0>
1 AXPLSZ_L 10C1< IO 4 DTB_OUTA 10D5>
0 SBRK_N 10A8> 3 DTB_OUTB 11C6>
5 GSCOM-H 9D5> 2 DTB_SA_OP 11D6>
4 GSCOM-L 9D5> 1 RESET_DTB 10D5<
3 SGCOM-H 9B1< 0 XRAY_DTB 10D5<
2 SGCOM-L 9C1<
1 GDTRIG-H 9D5>
0 GDTRIG-L 9D5>
2A1^ RELAY_INF[1..0]
IO
1 XRAY_ON_N 9C8>
0 SYS_READY_N 9D8> RELAY BUS
2A3^ RELAY_BUS[1..0]
IO
1 XRAY_ON_S 9C5<
0 SYS_READY_S 9D5<
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Fri Mar 27 08:42:29 2009 gnt 5 of 5 5310990SCH 4 12 of 29

1 2 3 4 5 6 7 8
2-12 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
OC
A A
VCC
U11
HCPL0631 U13
51.1
R104 3V3 74LVC1G14
13D8> OGCOM_H R106
VCC 8 2K
0.1W 1% 0.1W 5
D68 VCC
100V 4 VO 1% R108 R288
6 2 Y_N 4 OGCOM
A 51.1 13D6>
51.1 3
R105
OGCOM_L GND 5 100 C39 1 3
13D8> NC1 GND
0.1W
MMSD4148 10N
0.1W 1% 1% 50V
10%
GND
GND
GND GND
GANTRY
VCC
K4
GND G6J_2FL_Y_5VDC 3V3
VCC
R476 R481U24
4.99K 1K DS26C31T 1 R130
COILP
B 0.1W
1%
0.1W
1% 8 COILN
332 B
0.1W
12 R125 1%
R396 EN_N 4.99K 3 2
1K 4 D16 COM<1> CLOSED<1>
U53 EN 0.1W 4 SAFE-L
0.1W 100V OPEN<1> OUT 2B7^
74VHCT_AHCT244 1% 6 7
1% 1 2 OCXLED_H COM<0> CLOSED<0>
I OUTP R379 51.1 13D8< 5 DS14 1 2
3 OCXLED_L OPEN<0>
OUTN_N R380 51.1 13D8<
19 GREEN
OE_N MMSD4148 HSMG-C190
XGRDY
2B6^ OCXLED 11 A1 Y1 9 VCC=VCC;GND=GND

IN GND
13D6> GOCOM 13 A2 Y2 7
15 A3 Y3 5 C
17 3 R126
A4 Y4 GMT_SAFE B
U24 2B6^ IN Q3
DS26C31T
332
R123 E
VCC=VCC;GND=GND 1K 0.1W
BC817-25
12 0.1W 1%
EN_N
GND 4 1% R128
EN
7 I OUTP 6 R377 51.1 GOCOM_H 13D8< 4.99K

OUTN_N 5 R378 51.1 GOCOM_L 13D8< 0.1W
GND 1% GND
C C
VCC=VCC;GND=GND
2B7^ SAFE_OC_L
IN
R127 U6 VCC VCC
2B7^ EMRG_OC_L HCPL0631
IN
150
D15 R129
0.1W 8 2K
MMSZ5225BT1 VCC
1% 0.1W
3V
1 VO 1%
7 2B7^ OCCOM<5..0>
IO
2B7^ EMRG-L 2 2B6^ OC_BUS[1..0]
OUT GND GND
IO
5 5 OGCOM_H 13A2<
1 GOCOM 13B1< 4 OGCOM_L 13A2<
0 OGCOM 13A7> 3 GOCOM_H 13C4>
1
2 GOCOM_L 13C4>
JUMPER JP2
R397 U58 1 OCXLED_H 13B4>

1 2 3
VCC
2 1K 74LVC_LCX244 0 OCXLED_L 13B4>
0.1W
1%
R124 1
1K OE_N
3
0.1W
1% GND 2 A1 Y1 18 EMRG_LOOP_OPEN 2B6^
OUT
2B7^ RLIN_N 4 A2 Y2 16 RLIN_N_F 2B7^
IN OUT
6 A3 Y3 14
8 A4 Y4 12
D D
VCC=3V3;GND=GND
REV 2 01July04
GND
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:24 2010 oc 1 of 1 5310990SCH 4 13 of 29

1 2 3 4 5 6 7 8
GANTRY 2-13
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
TABLE
VCC
A VCC VCC A
R351
0.1W
0.1W
U38
1K
1K
4.99K D47 D53 VCC VCC VCC
0.1W 75452B
MMSD4148 MMSD4148
1% 100V 100V
R506 U62
R387
R388
1%
1%
16B6<> COUTDRV 1 A<1> 4.99K 75452B R279 D64 D10
2 3 R386 51.1 COUTPLS 0.1W 332
B<1> Y<1> 16B4< MMSD4148 MMSD4148
0.1W 1% 1% 0.1W 100V 100V
16B6<> CINDRV 6 A<0> 1 A<1> 1%
7 5 R391 51.1 CINPLS STEPSL 2 3 R231 51.1 STEPSEL
B<0> Y<0> 16B4< 16B6> B<1> Y<1> 16B4<
0.1W 1% 0.1W 1%
D50 D55 6 A<0>
VCC=VCC;GND=GND MMSD4148 MMSD4148 LATCH_EX 7 B<0> Y<0> 5 EX_OFF 16B4<
100V 100V
NOT MOUNT R387, R388
FROM U68 OUTPUT D65 D11
VCC=VCC;GND=GND MMSD4148 MMSD4148
NOT MOUNT R279 100V 100V
VCC
GND
GND
GND
0.1W
1K
0.1W
1K
B VCC B
U31
R148
R399 U68
1%
R146
1K 74LVC_LCX244 CRDLB CRDLA HCPL0631 U30

1%
R151 100 0.1W 74LVC1G14

16B3> CRDLPLS_B 1% TP18 TP19 R255 3V3
1% 0.1W 19 8 2K
C46 OE_N VCC 0.1W
3.3N TIN TIN 5 VCC
1%
50V 11 A1 Y1 9 CRDL_B 16B6> 16B3> LATCH R82 332 1 VO
10% 13 7 CRDL_A 7 LATCH_EX 2 Y_N 4 LATCH_F
A2 Y2 16B6> 0.1W 1% A 16B6>
15 A3 Y3 5 D7 2
17 A4 Y4 3 GND 5 1 NC1 GND 3
GND 100V
CRDLPLS_A R150 100
16B3>
1% 0.1W VCC=3V3;GND=GND
C47 MMSD4148 GND
GND
3.3N
50V
10%
GND
GND
C GND
C
U24
R9 VCC
1K DS26C31T
U53
0.1W U68
74VHCT_AHCT244
1% HCPL0631 U39
R275
12 74LVC1G14
EN_N TGCOM_P 51.1 3V3
1 4 16B3> R276
OE_N EN 8 2K
VCC
0.1W 1% 0.1W 5
TABLE_TX 2 18 15 14 R272 GTCOM_P D25 VCC
16B6< A1 Y1 I OUTP 51.1 16B3< 4 1%
4 16 13 GTCOM_N 100V VO R277 R289
A2 Y2 OUTN_N R273 51.1 16B3< 6 2 Y_N 4 TABLE_RX
6 14 A 16B6>
A3 Y3 R274 3
8 A4 Y4 12 51.1 GND 100 51.1
16B3> TGCOM_N 5 C1 1 NC1 GND 3
VCC=VCC;GND=GND 0.1W 0.1W
10N
0.1W 1% MMSD4148 1% 50V 1%
VCC=VCC;GND=GND 10%
EN_N AND EN ARE CONNECTED AT OTHER PLACES GND
GND GND
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:33 2010 tbl 1 of 3 5310990SCH 4 14 of 29

1 2 3 4 5 6 7 8
2-14 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VR1
AD586
VREF 24V
24V
8 NOISE_REDUCTION VOUT 6
A 2 VIN TRIM 5 R98
A
GND 4 C102 C103
ADC 20K
0.1W
0.1U 22U
C31 C32 16V 10V 1%
1U 1U 5V 10% +80%-20%
50V 50V 5.0V +/- 2.5MV VCC R99
10% 10% 20K
0.1W
1%
GND R90
10K
VREF 0.1W R100
1% ADC_VCC_2.5V 20K
0.1W
1%
GND
R354 R91 C30 R101
332 10K 0.1U 10K
5VA 0.1W 0.1W 16V 0.1W
U21 ADC_24V_3.0V
1% 1% 10% 1%
8
TLV2462
VP
3 4.69V 5VA
1
GANTRY
VOUT 2 C36 R102
0.1U 10K
VN
C27 R86 0.1W
GND 16V
1U 4.99K
4
10% 1%
10V 0.1W R88
10% 1% 10K
R81 0.1W VCC
B GND 1% ADC_5VA_2.5V
B
GND
1K VCC U22
0.1W C29
R89 ADS8344
1% GND 10K 0.1U
R87 0.1W 16V
10K 1% 10% VCC<1-0> C21 C33
0.1W 22U 22U
1% 1 CH0 10V 10V
R75 2 CH1 +80%-20% +80%-20% 3V3

16B3< CPPOT_H 3 CH2 GND
GND 4 CH3
10 5 CH4
0.1W 6 CH5 U12
4.99K
4.99K
0.1W
0.1W
1% CPV 7 GND
TP11 CH6 R395 74LVC_LCX244
5VA 8 1K
U21 CH7
R76 0.1W
8
TLV2462
15 R385 51.1
VP
16C3> CPPOT_M 5 TIN 17 DIN DOUT 1% 19 OE_N
R427
R428
1%
1%
7
1K C25 6 VOUT VREF 9 16 R232 51.1 11 9 ADC_BUSY
D9 COM BUSY A1 Y1 16B6<
0.1W
VN
R67 1U MMSD4148 11 VREF 13 A2 Y2 7 ADC_DATA_OUT 16B6<

1MEG 1% 10V 15 5
100V A3 Y3
4
51.1
C 0.1W
1%
10% 19 DCLK 17 A4 Y4 3 R184
0.1W
C
R77 18 CS_N R185
CPPOT_L 10 1%
16C3< GND SHDN_N GND<1-0>
R83 VCC=3V3;GND=GND
10
R92
0.1W 1K
1% 1K 0.1W 16 BITS-8 CHANNELS
GND 0.1W 1% DCLK=24*FSAMPLE GND
1% GND
NOTE:
GND
GND
U60
R394
1K 74VHCT_AHCT244
0.1W
1%
1 OE_N
16B6< ADC_DATA_IN 2 A1 Y1 18
16B6< ADC_CS 4 A2 Y2 16
16B6< ADC_DCLK 6 A3 Y3 14
8 A4 Y4 12
D D
R64
ADC CHIP INPUT FROM FPGA SHOULD ADJUST THE 51.1
R181
VCC=VCC;GND=GND 0.1W
REV 2 01July04
CURRENT TO MEET EMC REQUIREMENT R183
1%
GND
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:34 2010 tbl 2 of 3 5310990SCH 4 15 of 29

1 2 3 4 5 6 7 8
GANTRY 2-15
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
2C1^ TABLE_CONTROL<6..0>
IO
6 LATCH 14B4<
2C3^ TABLE_BUS[12..0]
5 CINPLS 14A4> IO
4 COUTPLS 14A4> 12 ADC_DATA_IN 15D1<
3 EX_OFF 14B8> 11 ADC_DCLK 15D1<
2 STEPSEL 14A8> 10 ADC_CS 15D1<
1 CRDLPLS_B 14B1< 9 ADC_BUSY 15C8>
0 CRDLPLS_A 14C1< 8 ADC_DATA_OUT 15C8>
7 COUTDRV 14A1<
6 CINDRV 14A1<
5 CRDL_B 14B4>
4 CRDL_A 14B4>
2C1^ TGCOM<3..0>
B IO 3 LATCH_F 14B8> B
2 STEPSL 14A5<
3 TGCOM_P 14C4< 1 TABLE_RX 14D8>
2 TGCOM_N 14D4< 0 TABLE_TX 14D1<
1 GTCOM_P 14D4>
0 GTCOM_N 14D4>
2C1^ CRADLE_POT<2..0>
IO
2 CPPOT_H 15B1>
1 CPPOT_M 15C1<
0 CPPOT_L 15C1>
C C
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Thu Jul 02 14:50:19 2009 tbl 3 of 3 5310990SCH 4 16 of 29

1 2 3 4 5 6 7 8
2-16 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
CPU
18B7> FPGA_INIT_DONE
24B8> CPLD_LED<3..0> 3V3
FLASH_D<7..0>
A 3V3 A
7
6
5
4
3
2
0
1
100
102
101
65
66
67
68
69
70
72
74
75
78
79
80
82
83
84
86
87
88
90
92
93
96
97
98
99
71
81
91
2C5^ CPLD_RESET_N R470 R195 R196 R198 R199 R200 R201
IN
18D6> CPLD_CLK 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
3V3 1% 1% 1% 1% 1% 1% 1%
IO_65
IO_66
IO_67
IO_68
IO_69
IO_70
IO_72
IO_74
IO_75
IO_78
IO_79
IO_80
IO_82
IO_83
IO_84
IO_86
IO_87
IO_88
IO_90
IO_92
IO_93
IO_96
IO_97
IO_98
IO_99
IO_71
IO_81
IO_91
IO_100
IO_101
IO_102
3V3
VCCIO<6-0> U2
VCC<3-0> IO_103 103 0 S29GL064N90BFI04
R190 IO_106 106 1
R188 4.99K 127 GCLRN IO_107 107 2
4.99K 0.1W 125 GCLK1 IO_108 108 3 G4 VCC
0.1W 1% 128 OE2_GCLK2 IO_109 109
1% 126 OE1 IO_110 110 F1 CE_N RY_NBY A3 FLASH_BUSY_N 21C5<
IO_111 111 G1 OE_N
18B7> CPLD_TDI 4 TDI IO_112 112 A4 WE_N
2B5^ 18B1< JTAG_TMS 20 TMS IO_113 113 B3 NWP_ACC
GANTRY
2B5^ 18B1< JTAG_TCK 89 TCK IO_116 116 FLASH_RESET_N B4 RESET_N
2C5^ OUT CPLD_TDO 104 TDO IO_117 117 F6 BYTE_N
CPLD IO_118 118
1 IO_1 IO_119 119 1 E1 A0 DQ0 E2 0 R189
FPGA_RESET_N 2 U1 120 2 D1 H2 1
21C4> IO_2 IO_120 A1 DQ1 R215
CONFIG_DATA0 5 EPM3256A_144-7 121 3 C1 E3 2
18B1< R155 51.1 IO_5 IO_121 A2 DQ2 R216 51.1
CONFIG_DCLK 0.1W 1% 6 122 4 A1 H3 3
18B1< R336 51.1 IO_6 IO_122 A3 DQ3 R219 0.1W
B 21C4> CONFIG_BOOT_SEL 0.1W 1% 7 IO_7 IO_131 131 5 B1 A4 DQ4 H4 4 R220 1%
B
18B1< CONFIG_N 8 IO_8 IO_132 132 6 D2 A5 DQ5 E4 5 R221
18B1<> CONFIG_DONE 9 IO_9 IO_133 133 R245 7 C2 A6 DQ6 H5 6 R222
18B1> CONFIG_STATUS_N 10 IO_10 IO_134 134 R118 R197 8 A2 A7 DQ7 E5 7 R223
21C4< RECFG_BOOT_APPL 11 IO_11 IO_136 136 R119 1K 9 B5 A8 DQ8 F2
21C4< RECFG_RQ_N 12 IO_12 IO_137 137 R120 0.1W 10 A5 A9 DQ9 G2
21B4> RECFG_REASON<0> 14 IO_14 IO_138 138 R121 1% 11 C5 A10 DQ10 F3
21B4> RECFG_REASON<1> 15 IO_15 IO_139 139 12 D5 A11 DQ11 G3 3V3
21C5<> FPGA_CPLD_IO<0> 16 IO_16 IO_140 140 51.1*5 13 B6 A12 DQ12 F4
21C5<> FPGA_CPLD_IO<1> 18 IO_18 IO_141 141 0.1W 14 A6 A13 DQ13 G5

21C5<> FPGA_CPLD_IO<2> 19 IO_19 IO_142 142 1% 15 C6 A14 DQ14 F5 0 R202
21C5<> FPGA_CPLD_IO<3> 21 IO_21 IO_143 143 GND 16 D6 A15 DQ15_A_1 G6 1 R203
21B1> FPGA_CPLD_WR_N 22 IO_22 17 E6 A16 2 R204
21B1> FPGA_CPLD_RD_N 23 IO_23 GND<16-0> 18 B2 A17 3 R205
19 C3 A18 4 R206
3V3 20 D4 A19 5 R207
IO_25
IO_27
IO_28
IO_29
IO_30
IO_32
IO_34
IO_35
IO_36
IO_37
IO_38
IO_39
IO_40
IO_42
IO_43
IO_44
IO_45
IO_46
IO_47
IO_48
IO_49
IO_53
IO_54
IO_55
IO_56
IO_60
IO_62
IO_63
21 D3 6
IO_31
IO_41
IO_61
A20 R208
22 C4 A21 VSS<1..0> 7 R209
10K
1%
GND
4.99K*8
25
27
28
29
30
32
34
35
36
37
38
39
40
42
43
44
45
46
47
48
49
53
54
55
56
60
62
63
31
41
61
0.1W
R187
0.1W
C GND 1% C
21B4< FPGA_WDOG_ERR_N
2B3^ OUT RST_N
21C5<> FPGA_CPLD_IO<4> ABOVE RESISTORS
21C5<> FPGA_CPLD_IO<5>
FPGA_CPLD_IO<6> SHOULD BE PLACED
21C5<>
21C5<> FPGA_CPLD_IO<7> NEAR THE FLASH
3V3
FLASH_D<7..0>
21B8<>
R280 FLASH_WE_N
1K 21C5>
FLASH_OE_N 21C5>
JP1 0.1W
1% FLASH_CS_N 21C5>
22
20
18
10
14
13
19
16
17
12
15
11
21
8
4
5
3
7
2
0
1
1 2 FLASH_A<22..0> 21C8<>
R107
R109
R134
R136
R138
R103
R110
R112
R113
R164
R165
R114
R167
R115
R116
R117
R111
JUMPER
R93
R95
R96
R16
R19
R97
GND
51.1
D 1%
D
0.1W
REV 2 01July04
THESE RESISTORS SHOULD BE PLACED
NEAR THE CPD
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:26 2010 cpu 1 of 8 5310990SCH 4 17 of 29

1 2 3 4 5 6 7 8
GANTRY 2-17
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
A A
R218
S4 4.99K
KSC121G 0.1W
1%
1 1 3 3
2 2 4 4
CPU_RESET
3V3 GND
(ONLY FOR DEBUG)
1V2 U4
1V2_PLLD 1V2_PLLA EP2C35F672C7N 3V3
R210 R211 R212 R213
10K 10K 10K 10K
0.1W 0.1W 0.1W 0.1W VCCINT<27..0> IO_E3_ASDO E3 R156
1% 1% 1% 1% VCCA_PLL<3..0> IO_D3_CSO_N D3 4.99K
VCCD_PLL<3..0> IO_B2_CRC_ERROR B2 0.1W
IO_B3_CLKUSR B3 1%
N4 CE_N IO_C5_DEV_CLR_N C5 CPU_RESET_N
B 17B1< CONFIG_STATUS_N R22 STATUS_N IO_AE25_INIT_DONE AE25 FPGA_INIT_DONE 17A1 CONFIG_N N7 CONFIG_N IO_AE24_CEO_N AE24
IO_AE4_DEV_OE AE4
2B5^ 17B1< JTAG_TMS L8 TMS
IN
2B5^ FPGA_TDI M8 TDI TDO M7 CPLD_TDI 17B1<
IN
2B5^ 17B1< JTAG_TCK M6 TCK
IN
GND<80..0>
17B1> CONFIG_DATA0 N3 DATA0 GNDA_PLL<3..0>
17B1> CONFIG_DCLK N6 DCLK GND_PLL1<1..0>
17B1<> CONFIG_DONE R23 CONF_DONE GND_PLL2<1..0>

P20 MSEL0 GND_PLL3<1..0>
P21 MSEL1 GND_PLL4<1..0>
NC1 AC24
R471 N21
R214 1K NC2
1K NC3 Y2
0.1W
0.1W 1% GND
1% SYM 1 OF 9
NOTE:
GND FPGA HIGH FREQUENCE SIGNALS SHOULD ADJUST THE

GND
C CURRENT TO MEET THE EMC REQUIREMENT
C
ACCORDING TO THE SIMULATION RESULT, 8MA MAX
OUTPUT CURRENT IS PREFECT FOR THIS DESIGN
CONNECT CLOCK DRIVER INPUT TO OUTPUT DIRECTLY IS USED TO RESOLVE EMC ISSUE
3V3_CLK
U3
2305 NOT MOUNT
Y1
R409 CLKOUT 8
4.99K R171 CLK1 3
0.1W 4 VCC VOUT 3 1 REF CLK2 2
1% 5 R173 0 FPGA_CLK
CLK3 21B5<
1 2 51.1 7 R172 CPLD_CLK
CLK4 0 17A1<
ENABLE GND 0.1W
1%
C55
24MHZ VCC=3V3;GND=GND
1U
10V GND
10%
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-18 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
3V3 GND
GND 3V3
U4
U4
EP2C35F672C7N
EP2C35F672C7N
BANK 1
BANK 2
R475 B1_VCCIO<5..0> R477
GANTRY
1K T4 1K B2_VCCIO<4..0>
IO_T4_VREFB1N0 J5
0.1W W6 0.1W IO_J5_VREFB2N0
IO_W6_VREFB1N1 L4
1% 1% IO_L4_VREFB2N1
P2 CLK2 IO_AA7_PLL1_OUTP AA7 R159 51.1 REFCLK_XI 24A3> N2 CLK0 IO_E5_PLL3_OUTP E5
P1 CLK3 IO_AA6_PLL1_OUTN AA6
B N1 CLK1 IO_F6_PLL3_OUTN F6 B
P3 IO_P3 IO_U6 U6 RLIN_N_F 2B5^
IN C2 IO_C2 IO_H3 H3
P4 IO_P4 IO_U7 U7
C3 IO_C3 IO_H4 H4
R2 IO_R2 IO_U5 U5
G5 IO_G5 IO_J3 J3 A0_SRC 24C3>
R3 IO_R3 IO_W4 W4 MDINT_N 24B3<
24B3> B3_SRC G6 IO_G6 IO_J4 J4
R4 IO_R4 IO_W3 W3 TX_CLK 24B3<
24B3> B2_SRC F3 IO_F3 IO_H2 H2
R5 IO_R5 IO_Y1 Y1 RX_CLK 24B3<
24B3> B1_SRC F4 IO_F4 IO_H1 H1
T10 IO_T10 IO_V5 V5 RX_DV 24B3<
24B3> B0_SRC D2 IO_D2 IO_J2 J2 IN_R 24C3<
T9 IO_T9 IO_V6 V6 RXD0 24B3<
24B3< OUT_R D1 IO_D1 IO_J1 J1

P7 IO_P7 IO_AA2 AA2 RXD1 24B3< F7 IO_F7 IO_K4 K4 FAST_R 24C3<
P6 IO_P6 IO_AA1 AA1 RXD2 24B3<
24C3> SL2_SRC J8 IO_J8 IO_K3 K3
T2 IO_T2 IO_Y3 Y3 RXD3 24B3<
24C3> SL1_SRC J7 IO_J7 IO_K1 K1
T3 IO_T3 IO_Y4 Y4
24B3> SL0_SRC H6 IO_H6 IO_K2 K2
R6 IO_R6 IO_R8 R8
E2 IO_E2 IO_N9 N9
R7 IO_R7 IO_T8 T8
24C3< PLSW_R E1 IO_E1 IO_P9 P9
24A3> MDC U2 IO_U2 IO_V7 V7
24C3< EXLM_R K6 IO_K6 IO_L7 L7
24A3> TX_EN U1 IO_U1 IO_AB2 AB2
K5 IO_K5 IO_L6 L6
U9 IO_U9 IO_AB1 AB1
24C3> CV_XRAYON_S G4 IO_G4 IO_L9 L9
U10 IO_U10 IO_AA4 AA4
G3 IO_G3 IO_L2 L2
24A3> TXD0 U3 IO_U3 IO_AA3 AA3
J6 IO_J6 IO_L3 L3
24A3> TXD1 U4 IO_U4 IO_AC2 AC2
K8 IO_K8 IO_L10 L10
24A3> TXD2 V1 IO_V1 IO_AC1 AC1
K7 IO_K7 IO_M4 M4
C 24A3> TXD3 V2 IO_V2 IO_AA5 AA5
F2 IO_F2 IO_M5 M5 R268 51.1 GDTRGSRC 20D2> 24A5>
C
24A3> TX_ER T7 IO_T7 IO_Y5 Y5
F1 IO_F1 IO_M3 M3 GSCOM 24A5>
24A3> MDIO T6 IO_T6 IO_AD2 AD2
G1 IO_G1 IO_M2 M2 SGCOM 24A5<
24A3> COL V4 IO_V4 IO_AD3 AD3
G2 IO_G2
24A3> CRS V3 IO_V3 IO_AE2 AE2
24A3< RX_ER W2 IO_W2 IO_AE3 AE3 SYM 3 OF 9
W1 IO_W 1 IO_AB3 AB3
IO_AB4 AB4
IO_AC3 AC3
SYM 2 OF 9
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-19
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
GND 3V3
U4 GND 3V3
EP2C35F672C7N
U4
EP2C35F672C7N
BANK 3
R478 B3_VCCIO<6..0>
1K D11 BANK 4
IO_D11_VREFB3N0
0.1W E8 R479 B4_VCCIO<7..0>
IO_E8_VREFB3N1 1K E20
1% IO_E20_VREFB4N0
0.1W D16 IO_D16_VREFB4N1
C13 CLK10 1%
D13 CLK11 B13 CLK8
A13 CLK9
24B5< ADC_DATA_IN R1 51.1 B12 IO_B12 IO_C9 C9
24B5< ADC_DCLK R140 51.1 C12 IO_C12 IO_D9 D9 SYS_READY_S 24D5>
24B5< TEST1 C23 IO_C23 IO_D17 D17 DTB_OUTA 24D3>
24B5< ADC_CS R141 51.1 B11 IO_B11 IO_G10 G10 XRAY_ON_S 24D5>
24B5< TEST2 C22 IO_C22 IO_C17 C17 DTB_OUTB 24D3>
24B5< ADC_BUSY C11 IO_C11 IO_F10 F10
24C3> DV_NC_F C21 IO_C21 IO_B18 B18 DTB_SA_OP 24D3<
24B5< ADC_DATA_OUT J11 IO_J11 IO_C8 C8
24C3< AXPLSZ D21 IO_D21 IO_A18 A18 RESET_DTB 24D3
24C3< AXPLSB B23 IO_B23 IO_G16 G16 XRAY_DTB 24D3
24C3< AXPLSA A23 IO_A23 IO_F16 F16 GPLS1 24C3<
F12 IO_F12 IO_B7 B7 CRDL_B 24B5>
24C3> HOME_F A22 IO_A22 IO_F15 F15
J14 IO_J14 IO_D6 D6 CRDL_A 24B5>
24C3> SBRK B22 IO_B22 IO_G15 G15
J13 IO_J13 IO_C7 C7 LATCH_F 24B5>
24C3> DR_EN_N B21 IO_B21 IO_B17 B17 TABLE_RX 24B5>
D12 IO_D12 IO_D7 D7 STEPSL 24B5>
24C3< DV_ERROR A21 IO_A21 IO_A17 A17 TABLE_TX 24B5< 24B5<
E12 IO_E12 IO_F9 F9
J18 IO_J18 IO_H16 H16
G11 IO_G11 IO_G9 G9
K17 IO_K17 IO_H15 H15
24D7> GOCOM A10 IO_A10 IO_H10 H10
J16 IO_J16 IO_E15 E15
24D7> OGCOM B10 IO_B10 IO_H8 H8

K16 IO_K16 IO_D15 D15
2B5^ OUT OCXLED D10 IO_D10 IO_J9 J9
D20 IO_D20 IO_C16 C16
C10 IO_C10 IO_K9 K9
B20 IO_B20 IO_B16 B16 DASTRG 24A7>
A9 IO_A9 IO_D5 D5
A20 IO_A20 IO_B15 B15
2B5^ EMRG_LOOP_OPEN B9 IO_B9 IO_C4 C4 GMT_SAFE 2B5^
IN OUT C19 IO_C19 IO_C15 C15 CRDL_PLS 24A7>
E10 IO_E10 IO_A6 A6
0 D19 IO_D19 IO_G13 G13
F11 IO_F11 IO_B6 B6
1 B19 IO_B19 IO_F13 F13 TRIG_PIN 24A7>
H12 IO_H12 IO_B5 B5
2 A19 IO_A19 IO_G14 G14
23D8> FPGA_UART1_RX H11 IO_H11 IO_A5 A5
3 E18 IO_E18 IO_F14 F14 8
23D3< FPGA_UART1_TX A8 IO_A8 IO_B4 B4 R139 51.1 FPGA_CAN_TX 24C3<> 4 D18 IO_D18 IO_D14 D14 9
B8 IO_B8 IO_A4 A4 FPGA_CAN_RX 24C3<> 5 G18 IO_G18 IO_A14 A14 10
IO_C6 C6
6 F18 IO_F18 IO_B14 B14 11
SYM 4 OF 9 7 J17 IO_J17
C H17 IO_H17 C
F17 IO_F17
G17 IO_G17
SYM 5 OF 9
GDTRGSRC LED<11..0> 24B8>

TP28
TIN
24A5> 19C8> GDTRGSRC
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-20 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
GND
3V3
R473 GND
1K U4
0.1W EP2C35F672C7N U4
1% 3V3 EP2C35F672C7N
3V3
BANK 5
R474
B5_VCCIO<5..0> BANK 6
10K
10K
1%
1%
J22 1K
IO_J22_VREFB5N0 0.1W B6_VCCIO<5..0>
L23 IO_L23_VREFB5N1 1% T21 IO_T21_VREFB6N0
GANTRY
V22 IO_V22_VREFB6N1
N25 F21
R243
0.1W
0.1W
CLK4 IO_F21_PLL2_OUTP
R186
N26 CLK5 IO_F20_PLL2_OUTN F20 P25 CLK6 IO_V21_PLL4_OUTP V21 R242 51.1 SDRAM_CLK 23B1<
18D6> FPGA_CLK P26 CLK7 IO_V20_PLL4_OUTN V20
G26 IO_G26 IO_N24 N24
B G25 IO_G25 IO_N23 N23 13 V23 IO_V23 IO_AC23 AC23 B
K22 IO_K22 IO_M25 M25 14 V24 IO_V24 IO_AD25 AD25
G24 IO_G24 IO_M24 M24 16 V25 IO_V25 IO_AD24 AD24 0 FLASH_D<7..0> 17C8<>
17C1< FPGA_CPLD_RD_N G23 IO_G23 IO_M21 M21 17 V26 IO_V26 IO_Y21 Y21 1
17C1< FPGA_CPLD_WR_N P18 IO_P18 IO_N20 N20 U21 IO_U21 IO_W 21 W 21 2
N18 IO_N18 IO_M20 M20 U20 IO_U20 IO_Y22 Y22 3
0 F26 IO_F26 IO_M19 M19 T19 IO_T19 IO_AA24 AA24
1 F25 IO_F25 IO_M23 M23 FPGA_WDOG_ERR_N 17C1< R19 IO_R19 IO_AA23 AA23
2 J20 IO_J20 IO_M22 M22 2 U24 IO_U24 IO_AB24 AB24 6
3 J21 IO_J21 IO_K26 K26 RECFG_REASON<1> 17B1> 3 U23 IO_U23 IO_AB23 AB23 7
4 F23 IO_F23 IO_K25 K25 RECFG_REASON<0> 17B1> 4 U25 IO_U25 IO_AC25 AC25 18
5 F24 IO_F24 IO_L19 L19 19 U26 IO_U26 IO_AC26 AC26 5
6 E25 IO_E25 IO_L25 L25 RECFG_RQ_N 17B1< T20 IO_T20 IO_AB26 AB26 20
7 E26 IO_E26 IO_L24 L24 RECFG_BOOT_APPL 17B1< T17 IO_T17 IO_AB25 AB25 10
D25 IO_D25 IO_J26 J26 CONFIG_BOOT_SEL 17B1> T18 IO_T18 IO_Y24 Y24 6
24C5< DSW1<7..0>
D26 IO_D26 IO_J25 J25 FPGA_RESET_N 17B1> 9 T25 IO_T25 IO_Y23 Y23 15
C24 IO_C24 IO_L20 L20 21 T24 IO_T24 IO_AA25 AA25 11
C25 IO_C25 IO_L21 L21 P17 IO_P17 IO_AA26 AA26 12
B25 IO_B25 IO_K24 K24 R17 IO_R17 IO_Y26 Y26 7
24C5< SW_SVON B24 IO_B24 IO_K23 K23 17B8> FLASH_BUSY_N T23 IO_T23 IO_Y25 Y25 8
24C5< SW_SVOFF E24 IO_E24 IO_K21 K21 17D8< FLASH_WE_N T22 IO_T22 IO_U22 U22 22
24C5< SW_JOG E23 IO_E23 IO_K19 K19 R20 IO_R20 IO_W24 W 24 4
24C5< SW_CNT H21 IO_H21 IO_K18 K18 FPGA_CPLD_IO<0> 17B1<> 17D8< FLASH_OE_N R24 IO_R24 IO_W23 W 23 5
C 24C5< SW_SYS G22 IO_G22 IO_H19 H19 FPGA_CPLD_IO<1> 17B1<> 17D8< FLASH_CS_N R25 IO_R25 IO_W25 W 25 0 C
24C5< SW_MNL G21 IO_G21 IO_H26 H26 FPGA_CPLD_IO<2> 17B1<> P24 IO_P24 IO_W26 W 26 1
24C5< SW_SLOW D23 IO_D23 IO_H25 H25 FPGA_CPLD_IO<3> 17C1<> P23 IO_P23
24C5< SW_FAST E22 IO_E22 IO_J24 J24 FPGA_CPLD_IO<4> 17C1<>
J23 FPGA_CPLD_IO<5> SYM 7 OF 9
IO_J23 17C1<>
IO_H24 H24 FPGA_CPLD_IO<6> 17C1<>
IO_H23 H23 FPGA_CPLD_IO<7> 17C1<>
SYM 6 OF 9
FLASH_A<22..0> 17D8<>
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-21
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
GND
3V3
U4 U4
EP2C35F672C7N EP2C35F672C7N
3V3
R472
1K BANK 7 BANK 8
B7_VCCIO<7..0> GND B8_VCCIO<6..0>
0.1W
1% Y18 IO_Y18_VREFB7N0 AC12 IO_AC12_VREFB8N0
AC16 IO_AC16_VREFB7N1 AC7 IO_AC7_VREFB8N1
23C1< SDRAM_DQM<1..0> AE14 CLK12 AD13 CLK14

AF14 CLK13 AC13 CLK15
1 SDRAM_DQM<1> AB18 IO_AB18 IO_AE15 AE15 SDRAM_WE_N 23B1< AE8 IO_AE8 IO_AF4 AF4 DIR1 24C7<
0 AC18 IO_AC18 IO_AD15 AD15 SDRAM_CAS_N 23B1< AF8 IO_AF8 IO_AC5 AC5 DIR2 24C7<
B 1 W 17 IO_W17 IO_AC14 AC14 SDRAM_CKE 23B1< W 11 IO_W 11 IO_AC6 AC6 0 B
2 V17 IO_V17 IO_AA13 AA13 W 12 IO_W12 IO_AD4 AD4 1
3 AA17 IO_AA17 IO_Y13 Y13 AC9 IO_AC9 IO_AD5 AD5 2
4 AA18 IO_AA18 IO_AA14 AA14 AC10 IO_AC10 IO_AE5 AE5 3
5 AD19 IO_AD19 IO_Y14 Y14 AE9 IO_AE9 IO_AF5 AF5 4
6 AC19 IO_AC19 IO_Y15 Y15 AF9 IO_AF9 IO_AD6 AD6 5
7 AF20 IO_AF20 IO_AA15 AA15 AD10 IO_AD10 IO_AD7 AD7 6
8 AE20 IO_AE20 IO_AB15 AB15 AC11 IO_AC11 IO_V10 V10 7
9 AB20 IO_AB20 IO_AC15 AC15 AE10 IO_AE10 IO_V9 V9 8
10 AC20 IO_AC20 IO_AE16 AE16 SDRAM_D<11> 11 AF10 IO_AF10 IO_W8 W8 9

11 AF21 IO_AF21 IO_AD16 AD16 AB12 IO_AB12 IO_W10 W 10 10
12 AE21 IO_AE21 IO_W15 W 15 SDRAM_D<12> 12 AD11 IO_AD11 IO_Y10 Y10 11
23B1<> SDRAM_A<12..0> AA20 IO_AA20 IO_W16 W 16 SDRAM_D<8> 8 AE11 IO_AE11 IO_AB8 AB8 12
U17 IO_U17 IO_AF17 AF17 SDRAM_D<15> 15 V14 IO_V14 IO_AC8 AC8 13
U18 IO_U18 IO_AE17 AE17 SDRAM_D<13> 13 V13 IO_V13 IO_AD8 AD8 14
V18 IO_V18 IO_AC17 AC17 V11 IO_V11 IO_AE6 AE6 15
W 19 IO_W19 IO_AD17 AD17 SDRAM_D<6> 6 U12 IO_U12 IO_AF6 AF6
AF22 IO_AF22 IO_AA16 AA16 SDRAM_D<0> 0 AA12 IO_AA12 IO_AA9 AA9
0 SDRAM_DQM<0> AE22 IO_AE22 IO_Y16 Y16 SDRAM_D<3> 3 Y12 IO_Y12 IO_AA10 AA10
23B1< SDRAM_BA<1> AC21 IO_AC21 IO_AF18 AF18 SDRAM_D<2> 2 AD12 IO_AD12 IO_AB10 AB10
23B1< SDRAM_BA<0> AD21 IO_AD21 IO_AE18 AE18 SDRAM_D<4> 4 AE12 IO_AE12 IO_AA11 AA11 TEST<15..0> 24C8<>
7 SDRAM_D<7> AD23 IO_AD23 IO_AF19 AF19 SDRAM_D<5> 5 AE13 IO_AE13 IO_Y11 Y11
1 SDRAM_D<1> AD22 IO_AD22 IO_AE19 AE19 SDRAM_D<14> 14 AF13 IO_AF13 IO_AE7 AE7
C 9 SDRAM_D<9> AC22 IO_AC22 IO_AF7 AF7 C
10 SDRAM_D<10> AB21 IO_AB21
SDRAM_CS_N AF23 SYM 9 OF 9
23B1< IO_AF23
23B1< SDRAM_RAS_N AE23 IO_AE23
SYM 8 OF 9
SDRAM_D<15..0> 23A7<>
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-22 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
A A
4.99K
4.99K
0.1W
0.1W
4.99K
4.99K
0.1W
0.1W
4.99K
4.99K
4.99K
0.1W
0.1W
0.1W
U47 SDRAM_D<15..0> 22C5<>
MT48LC16M16A2BG-75IT:D
1%
1% 3V3
1%
1%
1%
1%
1%
R262
R263
R264
R265
R254
R298
R261
VDD<2..0>
VDDQ<3..0>
22C1< SDRAM_CS_N G9 CS_N DQ0 A8 1 2 0 R234

22C1< SDRAM_RAS_N F8 RAS_N DQ1 B9 1 R235
22B4> SDRAM_CAS_N F7 CAS_N DQ2 B8 2 R236
22B4> SDRAM_WE_N F9 WE_N DQ3 C9 3 R237
22B4> SDRAM_CKE F3 CKE DQ4 C8 4 R238
D9
GANTRY
DQ5 5 R239
21B8> SDRAM_CLK F2 CLK DQ6 D8 6 R240
E9 7 51.1
DQ7 R241
SDRAM_BA<0> G7 E1 8 1%
22C2> BA0 DQ8 R244
SDRAM_BA<1> G8 D2 9 0.1W
22C2> BA1 DQ9 R251
DQ10 D1 10 R253
B 22C2<> SDRAM_A<12..0>
0 SDRAM_A<0> H7 A0 DQ11 C2 11 R257
B
1 SDRAM_A<1> H8 A1 DQ12 C1 12 R258
3V3 2 SDRAM_A<2> J8 A2 DQ13 B2 13 R260
3 SDRAM_A<3> J7 A3 DQ14 B1 14 R266
4 SDRAM_A<4> J3 A4 DQ15 A2 15 R267
5 SDRAM_A<5> J2 A5
4.99K
4.99K
6 SDRAM_A<6> H3 A6
1%
1%
7 SDRAM_A<7> H2 A7
8 SDRAM_A<8> H1 A8
9 SDRAM_A<9> G3 A9
10 SDRAM_A<10> H9 THESE RESISTORS SHOULD BE PLACED NEAR THE SDRAM
A10
11 SDRAM_A<11> G2 A11
R422
0.1W
0.1W
R421
12 SDRAM_A<12> G1 A12
22B1> SDRAM_DQM<1..0>
0 SDRAM_DQM<0> E8 DQML VSS<2..0>
1 SDRAM_DQM<1> F1 DQMH VSSQ<3..0>
GND
C RS232 C
3V3
U54
MAX3232C
C63 C64 C65 16 VCC

0.1U 0.1U 0.1U 2 VP
16V 16V 16V 6 VN
10% 10% 10%
C61 1 2 16V 1 C1P
0.1U 10% 3 C1M
4 C2P
C62 1 2 16V 5 C2M
GND 0.1U 10%
20C1> FPGA_UART1_TX 11 T1IN T1OUT 14 UART1_TX 24B7<
10 T2IN T2OUT 7
24B7> UART1_RX 13 R1IN R1OUT 12 FPGA_UART1_RX 20C1<
8 R2IN R2OUT 9
GND 15
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-23
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
ETHERNET INTERFACE
SLIP RING INTERFACE
MISC LED
2C4^ ETHERNET<19..0>
IO
A 19 MDC 19C1> 2B3^ IO
SLIP_R[2..0] 2C4^ LED_BUS[18..0] A
OUT
18 TX_EN 19C1>
17 TXD0 2 GDTRGSRC 18 DASTRG
19C1> 19C8> 20D2> 20C8>

16 TXD1 19C1> 1 GSCOM 19C8< 17 CRDL_PLS 20C8>
15 TXD2 19C1> 0 SGCOM 19C8> 16 TRIG_PIN 20C8>
14 TXD3 19C1> 15 11
13 TX_ER 19C1> 14 10
12 MDIO 19C1<> 13 9
11 COL 19C1< 12 8
10 CRS 19C1< 11 7
9 RX_ER 19C1< TABLE INTERFACE 10 6
8 REFCLK_XI 19B4> 9 5
7 MDINT_N 19B4> 8 4
2B3^ TABLE_BUS[12..0]
6 TX_CLK 19B4< IO 7 3
5 RX_CLK 19B4< 6 2
12 ADC_DATA_IN 20B1>
4 RX_DV 19B4< 5 1
11 ADC_DCLK 20B1>
3 RXD0 19B4< 4 0
10 ADC_CS 20B1>
2 RXD1 19B4< LED<11..0> 20C8>
9 ADC_BUSY 20B1<
1 RXD2 19B4< 8 ADC_DATA_OUT 20B1<
0 RXD3 19C4< 7 COUTDRV 20B4> 3 3
6 CINDRV 20B4> 2 2
5 CRDL_B 20B4< 1 1
4 CRDL_A 20B4< 0 0
3 LATCH_F 20B4< CPLD_LED<3..0> 17A1>
2 STEPSL 20B4>
GANTRY INTERFACE
B 1 TABLE_RX 20B8 24B5<
COVER_BUS[13..0] CONNECTOR
2B3^ IO MISC SWITCH
13 B0_SRC 19B5>
12 B1_SRC 19B5> 2C4^ SWITCH_BUS[18..0]
IN 2C5^ DEBUG[19..0]
11 B2_SRC 19B5> IO
10 B3_SRC 19B5> 18 TEST1 20B5< 19 UART1_TX 23D8>
9 OUT_R 19B5< 17 TEST2 20B5< 18 UART1_RX 23D3<

8 SL0_SRC 19C5> 16 TABLE_TX 20B8> 24B5< 17 15
7 SL1_SRC 19C5> 15 7
16 14
6 SL2_SRC 19C5> 14 6
15 13
5 PLSW_R 19C5< 13 5
14 12
4 EXLM_R 19C5< 12 4
13 11
3 CV_XRAYON_S 19C5> 11 3
12 10
2 A0_SRC 19B7> 10 2
11 9
1 IN_R 19B7< 9 1
10 8
0 FAST_R 19B7< 8 0
9 7
DSW1<7..0> 21C1< 8 6
7 5
7 SW_SVON 21C1< 6 4
6 SW_SVOFF 21C1<
C 2A3^ DRIVER_BUS[10..0] 5 SW_JOG 21C1<
5 3 C
IO 4 2
4 SW_CNT 21C1< 3 1
10 AXPLSZ 20B5< 3 SW_SYS 21C1< 2 0
9 AXPLSB 20B5< 2 SW_MNL 21C1<
8 AXPLSA 20B5< 1 SW_SLOW 21C1< TEST<15..0> 22C8<>
7 HOME_F 20B5> 0 SW_FAST 21C1<
6 SBRK 20B5>
5 DR_EN_N 20B5> 1 DIR1 22B8>
4 DV_ERROR 20B5< 0 DIR2 22B8>
3 GPLS1 20B8<
2 FPGA_CAN_TX 20C4> RELAY BUS
1 FPGA_CAN_RX 20C4<
0 DV_NC_F 20B5<
2A3^ RELAY_BUS[1..0]
IO
1 XRAY_ON_S 20B4>
0 SYS_READY_S 20B4>
OC BUS
DTB BUS
2B5^ OC_BUS[1..0]
IO
2B3^ DTB_BUS[4..0]
IO 1 GOCOM 20B1<
0 OGCOM 20B1<
4 DTB_OUTA 20B8<
3 DTB_OUTB 20B8<
2 DTB_SA_OP 20B8<
1 RESET_DTB 20B8>
D 0 XRAY_DTB 20B8> D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Thu Jul 02 14:50:17 2009 cpu 8 of 8 5310990SCH 4 24 of 29

1 2 3 4 5 6 7 8
2-24 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
SWITCHES
A GND
A
VCC
U11 R6
HCPL0631 2K R7 U58 VCC
VCC 0.1W 1K 74LVC_LCX244 U66
R4 1% 0.1W U57 ADM811
29D6> RESET_H VCC 8 1% 74LVC-LCX08
19 OE_N
51.1 1 4 2 CPLD_RESET_N
D42 VO VCC RESET_N OUT 2C5^
0.1W 7 11 9 1 3
MMSD4148 A1 Y1 A<3> Y<3>
1% 2 13 7 2 3 1
100V A2 Y2 B<3> MR_N GND
GND 5 15 5 4 6 R248
R5 A3 Y3 A<2> Y<2> 100K
29D6< RESET_L 17 A4 Y4 3 5 B<2> 0.1W
9 A<1> Y<1> 8 3.3V 1%
51.1 10 B<1> GND
0.1W GND 12 11
VCC=3V3;GND=GND A<0> Y<0>
1% GND 13
3V3 B<0>
SW 6 GND
GANTRY
AB-15AV-FA VCC=3V3;GND=GND
R8
4.99K GND
0.1W
O1 3 1%
2 COM R246 R247
B O2 1 B
G1 2K 1K
G1 C94
G2 0.1W 0.1W
G2
GND 1% 0.1U 1%
16V
10%
GND
GND
SW 7
AB-15AV-FA
U34
3V3 74LVC-LCX14
O1 3
2 COM R12 R17
SW 9 O2 1 9 8 TEST1 29A3<
C UB15SKW03N-C/UC
A B C
G1 2K C3 1K
G1 R10
G2 4.99K 0.1W 0.1W
G2 0.1U VCC=3V3;GND=GND
O2 2 0.1W 1% 16V 1%
ERST_OC_L 1 I1 1% 10%
2C6^ IN O1 3 ERST_L
OUT 2C6^
GND
SW 8 GND GND
AB-15AV-FA
3V3 U34
74LVC-LCX14
O1 3
2 COM R13 R18
O2 1 11 A B 10 TEST2 29A3<
G1 2K C4 1K
G1 R11
G2 4.99K 0.1W 0.1W
G2 0.1U VCC=3V3;GND=GND
0.1W 1% 16V 1%
1% 10%
GND
GND GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Mon Apr 12 17:34:36 2010 misc_part 1 of 5 5310990SCH 4 25 of 29

1 2 3 4 5 6 7 8
GANTRY 2-25
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
A A
SW 1
M2022
1%
1%
4.99K
R153 4.99K
O1 1
2 COM1
O2 3
0.1W
0.1W
R70
O3 4 R518 2K R528 1K
5 COM2 0.1W 1% 0.1W 1%
O4 6 R519 2K R529 1K
0.1W 1% 0.1W
1%
0.1U
0.1U
16V
16V
3V3
GND SW 3
7207SYCSE
10%
10%
C260
3V3
C255
1%
1%
4.99K
4.99K
O1 1
2 COM1
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
O2 3 U32
R182
GND
0.1W
0.1W
74LVC-LCX14
R71
4.99K
4.99K
4.99K
4.99K
4.99K
4.99K
4.99K
4.99K O3 4 R520 2K R530 1K

5 COM2 0.1W 1% 0.1W 1%
S1
B GDH08 O4 6 R521 2K R531 1K 1 A<5> B<5> 2 SW_SVON 29B3 B<4> 4 SW_SVOFF 29B3<
1%
R20
R23
R26
R29
R32
R35
R38
R40
1%
1%
1%
1%
1%
1%
1%
1%
5 6 SW_JOG
0.1U
0.1U
29B3<
16V
16V
A<3> B<3>
9 A<2> B<2> 8 SW_CNT 29B3<
1 I1 O1 16 0 3V3
GND 11 A<1> B<1> 10 SW_SYS 29B3<
SW 2 13 A<0> B<0> 12 SW_MNL 29B3<
10%
10%
2 I2 O2 15 1
C261
C256
M2022
1%
1%
3 I3 O3 14 2
4.99K
R256 4.99K
VCC=3V3;GND=GND
O1 1
4 I4 O4 13 3
2 COM1
GND
O2 3
5 12 4
0.1W
0.1W
I5 O5
R85
O3 4 R522 2K R532 1K
6 I6 O6 11 5 0.1W 1% 0.1W 1%
5 COM2
O4 6 R523 2K R533 1K
7 I7 O7 10 6 0.1W 1% 0.1W
1%
0.1U
0.1U
16V
16V
8 I8 O8 9 7
GND
DSW1<7..0> 29B4<
10%
10%
C262
C257
GND
C C
GND
3V3
SW 4
M2022
1%
1%
4.99K
4.99K
O1 1 U65
2 COM1 74LVC-LCX14
O2 3
R259
0.1W
0.1W
R94
O3 4 R524 2K R534 1K 1 2 SW_FAST
A<5> B<5> 29B3<
5 COM2 0.1W 1% 0.1W 1% 3 4 SW_SLOW
A<4> B<4> 29B3<
O4 6 R525 2K R535 1K 5 6
A<3> B<3>
0.1W 1% 0.1W 9 8
1% A<2> B<2>
0.1U
0.1U
16V
16V
11 A<1> B<1> 10
13 A<0> B<0> 12
GND
10%
10%
C263
C258
VCC=3V3;GND=GND
GND
GND
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-26 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
LED DISPLAY
3V3
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
332
332
332
332
332
332
3V3 GND
1%
1%
1%
1%
1%
1%
GND
R59
R60
R61
R62
R63
R65
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
332
332
332
332
332
332
R426
4.99K U18
10 MA DS1 1 2 ERRT
74VHCT_AHCT244
1%
1%
1%
1%
1%
1%
0.1W
YELLOW
R52
R53
R54
R55
R56
R58
R425 1%
4.99K U17
29B6> LED<4..0> 74VHCT_AHCT244 29B6> LED<11..5> 1 OE_N<1>
0.1W DS2 HWLP
1% MNLM 1 2
DS11 1 2 11 2 18
GANTRY
A1<1> Y1<1> GREEN
1 OE_N<1> GREEN 10 4 A2<1> Y2<1> 16
9 6 A3<1> Y3<1> 14
0 2 18 8 8 12 DS3 1 2 REQT
A1<1> Y1<1> REQM A4<1> Y4<1>
1 4 16 DS12 1 2
A2<1> Y2<1> GREEN
B 2 6 A3<1> Y3<1> 14 GREEN 19 OE_N<0> B
3 8 A4<1> Y4<1> 12
7 11 9 DS4 1 2 MNLT
FWLP A1<0> Y1<0>
19 DS13 1 2 6 13 7
OE_N<0> A2<0> Y2<0> GREEN
GREEN 5 15 A3<0> Y3<0> 5
4 11 A1<0> Y1<0> 9 29A6> CRDL_PLS 17 A4<0> Y4<0> 3
13 7 DS7 1 2 REQG
A2<0> Y2<0> ERRM
DASTRG 15 5 DS10 1 2
29A6> A3<0> Y3<0> GREEN
29B6> TRIG_PIN 17 A4<0> Y4<0> 3 YELLOW VCC=VCC;GND=GND
DATACHG
DS9 1 2
VCC=VCC;GND=GND
GREEN
DS6 1 2 ERRG
YELLOW
TRIG TP27
DS15 1 2
GREEN TIN
C C
TP26
TIN GND
CPLD_CODE_LED 3V3
HSMG-C190
R408 U44
1K CPLD_LOADING
74LVC_LCX244 R191
0.1W 332 1 2 DS17
29B6> CPLD_LED<3..0> 1%
19 0.1W 1%
OE_N GREEN
CPLD_LOADED
R192
3 CPLD_LED<3> 11 9 332 1 2
A1 Y1 DS18
2 CPLD_LED<2> 13 A2 Y2 7
1 CPLD_LED<1> 15 5 0.1W 1%
A3 Y3 GREEN
0 CPLD_LED<0> 17 3 APPL_FPGA
A4 Y4 R193
332 1 2 DS19
0.1W 1%
VCC=3V3;GND=GND GREEN
BOOT_FPGA
R194
332 1 2 DS20
0.1W 1%
GREEN
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 2-27
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
NOT MOUNT U20

ETHERNET PHY
A A
GND GND
U20 3V3
3V3A LXT972A
3V3 3V3
R160
R147 R152 51 VCCD 4.99K
1K 1K VCCA<1-0> 0.1W
0.1W 0.1W VCCIO<1-0> 1%
1% 1%
2C3^ RST_N 4 RESET_N MDIO 42 MDIO 29C3>
IN
12 ADDR0 MDINT_N 64 MDINT_N 29D3<
29C3> MDC 43 MDC COL 62 COL 29C3>
3 MDDIS CRS 63 CRS 29C3>
REFCLK_XI 1 55 R161 TX_CLK
29D3> REFCLK_XI TX_CLK 47 29D3<
2 XO RX_CLK 52 R162 47 RX_CLK 29D3<
29C3> TX_EN 56 TX_EN RX_DV 49 RX_DV 29D3<

29C3> TXD0 57 TXD0 RXD0 48 RXD0 29D3 TXD1 58 TXD1 RXD1 47 RXD1 29D3 TXD2 59 TXD2 RXD2 46 RXD2 29D3<
29C3> TXD3 60 TXD3 RXD3 45 RXD3 29D3<
29C3> TX_ER 54 TX_ER RX_ER 53 RX_ER 29C3<
2D6^ PHY_TDI 27 TDI TDO 28 PHY_TDO 2D6^

R142 R144 IN OUT
2D6^ JTAG_TMS 29 TMS
4.99K 4.99K IN C87 270P
2D6^ JTAG_TCK 30 TCK TPIP 23 TPIP 29C6> 28C2<
0.1W 0.1W IN C88 270P
1% 1% 2D6^ TRST_N 31 TRST_N TPIN 24 TPIN 29C6> 28D2<
IN
5 TXSLEW0 TPOP 19 TPOP 28C4> 29C6<

6 TXSLEW1 TPON 20 TPON 28D4> 29C6<
39 PWRDWN LED_CFG1 38 LED_CFG1 29C6>
R143 R145 33 PAUSE LED_CFG2 37 LED_CFG2 29C6>
1K 1K 17 RBIAS LED_CFG3 36 LED_CFG3 28D6<
0.1W 0.1W
1% 1% GND<14-0> R46 R84
R149 R154 R157 47 47
1K 1K 22.1K 0.25W 0.25W
0.1W 0.1W 0.1W 1% 1%
1% 1% 1%
GND
C C
GND GND GND C89
TIME SELECT 10N
25V
5%
3V3
CR1
SRV05_4
GND
0.1W
28B7< 29C6> TPIP 1 6 TPOP 28B7> 29C6<
332
VCC
1%
R293
2 5
DS16
LED_CFG3 1 2 PHY_FW_LED
28C7>
GND GREEN HSMG-C190
28B7< 29C6> TPIN 3 4 TPON 28C7> 29C6<
5V_STAND_OFF
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
2-28 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
MISC LED
MISC SWITCH
2C4^ SWITCH_BUS[18..0]
OUT 2C5^ LED_BUS[18..0]
OUT
18 TEST1 25C7> 18 DASTRG 27B1<
17 TEST2 25D7> 17 CRDL_PLS 27B5<
16 TABLE_TX
16 TRIG_PIN 27B1<
15 7
15 11
14 6
14 10
13 5
13 9
12 4
12 8
11 3
11 7
10 2
10 6
9 1
9 5
GANTRY
8 0
8 4
DSW1<7..0> 26C3> 7 3
6 2
7 SW_SVON 26B8> 5 1
6 SW_SVOFF 26B8> 4 0
5 SW_JOG 26B8>
B 4 SW_CNT 26B8>
LED<11..0> 27B1< 27B5
2 SW_MNL 26B8> 3 3
1 SW_SLOW 26D8> 2 2
0 SW_FAST 26C8> 1 1
0 0
CPLD_LED<3..0> 27C3<
ETHERNET INTERFACE
C 2C4^ IO
ETHERNET<19..0> C
2D6^ ETHERNET_INF[5..0]
IO
19 MDC 28B2<
18 TX_EN 28B2< 5 LED_CFG1 28C7>
17 TXD0 28B2< 4 LED_CFG2 28C7>
16 TXD1 28B2< 3 TPOP 28B7> 28C4>
15 TXD2 28B2< 2 TPON 28C7> 28D4>
14 TXD3 28B2< 1 TPIP 28B7< 28C2<
13 TX_ER 28B2< 0 TPIN 28B7< 28D2<
12 MDIO 28B7<>
11 COL 28B7>
10 CRS 28B7>
9 RX_ER 28B7>
8 REFCLK_XI 28B2<
7 MDINT_N 28B7>
6 TX_CLK 28B7>
5 RX_CLK 28B7>
4 RX_DV 28B7>
3 RXD0 28B7>
2 RXD1 28B7>
1 RXD2 28B7>
2D6^ RESET_INF[1..0]
0 RXD3 28B7> IN
1 RESET_H 25A2<
0 RESET_L 25B2<
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Fri Mar 27 09:54:13 2009 misc_part 5 of 5 5310990SCH 4 29 of 29

1 2 3 4 5 6 7 8
GANTRY 2-29
Brivo CT315
Brivo CT325
blank
2-30 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 3 - OGP BD ASSY
1 2 3 4 5 6 7 8
A A
NOTES:
REVISION ECR/ECO DATE SIGN OFF 1. THE VARIATION AND VERSION FOR THIS
1 ------ 24-FEB-09 YU MIAO PWA IS 5322679 REV01.
2. THIS COVER SHEET CONTROLS THE RE-
VISION STATUS OF THE ENTIRE DOCUMENT.
THE REVISION OF ALL SHEETS OF THIS
DOCUMENT WILL BE AT THE SAME LEVEL.
3. THIS SCHEMATIC MEETS THE SPECIFICA-
TIONS OF THE GLOBAL SCHEMATIC STANDARD
THIS IS A DUMMY DRAWING GUIDELINES 2299773GSP.
REFER TO 5132987SCH SCHEMATIC REVIEWER(S) AND APPROVER(S)
CAN BE FOUND WITHIN MY WORKSHOP.
INDUCTORS ARE IN HENRIES.
B B
C C
D D
REV 2 01July04
MADE BY DATE TITLE
YU MIAO 24-FEB-2009 OGPL BOARD ASSEMBLY
GE Healthcare
Company Restricted
B Size
CHECK APPROVE Block Path Block Sheet Dwg No Rev Sheet
Tue Apr 07 10:33:54 2009 LI GUOWANG XING ZHENFENG ogpl 1 of 1 5322679SCH 1 1 of 1
1 2 3 4 5 6 7 8
GANTRY 3-1
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A

A 10-MAR-05 LIU YUFEI
B 12-OCT-06 LI GUOWANG
C 13-JUN-07 LI GUOWANG
SHEET NAME SHEET NUM REV REV REV REV

TOP LEVEL DIAGRAM 2 A B C E
CONNECTOR & POWER SUPPLY 3-4 A B ADD FUSE F4-6 FOR COMPATIBILITY REFER TO REPORT
REMOVE C8
POS_LIHGT & FAN 5 A B HTR-RNEW-TG-049
B B
CLOCK AND RESET CIRCUIT 6 A B FPGA DIRECTLY OUTPUT 50M CLK TO SDRAM & CHANGE LINE RESISTOR FROM 33 TO 100 NAMED
SLIPING RING INTERFACE 7 A B USING INDIVIDUAL 26C31 FOR SGCOM & ADD RC CIRCUIT BETWEEN U15 & FPGA <<OGP2 ASSY 5132987
REV B
DAS INTERFACE 8 A B ADD RESISTOR BETWEEN U1/2 & FPGA
ISSUES AND
JEDI INTERFACE 9-10 A B USING 4245 TO CONVERT CAN RX & XRON TO LVTTL STANDARD IMPROVING 5132987
APERTURE INTERFACE 11 A B ADD RC CIRCUIT BETWEEN U21 & FPGA REV C REPORT>>
CPLD AND FALSH 12 A B ADD SIGNALS BETWEEN CPLD & FPAG, CHANGE FLASH & ADD PULL UP RESISTORS ON FLASH
FPGA 13-15 A B CLOCK REVISED
SDRAM 16 A B ADD PULL UP RESISTORS ON SDRAM
DEBUG CONNECTOR 17 A B DELETE THE FS2 I/F. ADD 2 DEBUG INTERFACE FOR FCT TEST
LEDS 18 A B CHANGE RESISTOR FROM 511 OHM TO 249 OHM
TEST POINTS AND SERIAL PORT 19 A B
C THERMAL SENSOR 20 A B C
JTAG INTERFACE & SWITCH 21 A B JTAG INTERFACE COMBINE
FPGA DECOUPLING CAPS 22 A B

SPARE GATES 23 A B
NOTE: GROUND TYPES
1. CHASSIS GROUND
THE DIFFERENCE BETWEEN EOL & RENEW PROJECT
2. 24V_GND_1, FOR TUBEFAN AND ISO_5V AND ISO_12V
1 THE CONNECTOR
3. 24V_GND_2, FOR COLLIMATER STEP MOTOR 2 THE LED FUNCTION NAME
4. GND, FOR MOST LOGIC DEVICES ON THE BORAD 3 THE TEMPERTURE SENSOR
D D
REV 2 01July04
GE Healthcare
Company Restricted
B Size
Sat Jul 05 13:21:50 2008 new_ogp 1 of 2 5132987SCH E 1 of 23

1 2 3 4 5 6 7 8
3-2 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
CONNECTORS I19
SHT 3-4
GSCOM_N
GSCOM_N
GSCOM_P
GSCOM_P
GDTRIG_N
GDTRIG_N
GDTRIG_P
A GDTRIG_P A
SGCOM_N
SGCOM_N
SGCOM_P
SGCOM_P
I20 FPGA_CPLD_FLASH I17

RESET_CLK
SHT 6
CLK_FPGA_24M SHT 12-21
CLK_FPGA_24M CLK_FPGA_24M
CLK_CPLD_24M
CLK_CPLD_24M CLK_CPLD_24M POS_LIGHT I1
RESET_N
RESET_N RESET_N
L_ON_P
CPLD_WATCHDOG FPGA_POSLIGHT_ON L_ON_P L_ON_P
CPLD_WATCHDOG CPLD_WATCHDOG FPGA_POSLIGHT_ON FPGA_POSLIGHT_ON
H_ON_P
FPGA_TUBE_FAN_P H_ON_P H_ON_P
FPGA_TUBE_FAN_P FPGA_TUBE_FAN_P
TUBE_FAN_ON
TUBE_FAN_ON TUBE_FAN_ON
SLIP_RING SHT 5
I3
SGCOM_P
FPGA_GD_TRIG_0
SGCOM_N FPGA_GD_TRIG_0 FPGA_GD_TRIG_0 DAS
FPGA_GD_TRIG_1 I15
GDTRIG_P FPGA_GD_TRIG_1 FPGA_GD_TRIG_1
GDTRIG_N FPGA_SG_COM_0 SHT 8
FPGA_GS_COM_0 FPGA_GS_COM_0 DSCOM_P
DSCOM_P DSCOM_P
B GSCOM_P
FPGA_GS_COM_1
FPGA_SG_COM_1
FPGA_GS_COM_1 DSCOM_N
DSCOM_N
DSCOM_N B
GSCOM_N
FPGA_SG_COM
FPGA_SG_COM FPGA_SG_COM
DTRIG_P
SHT 7 DTRIG_P DTRIG_P
FPGA_DTRIG DTRIG_N
FPGA_DTRIG FPGA_DTRIG DTRIG_N DTRIG_N
FPGA_DENBL DENBL_P
FPGA_DENBL FPGA_DENBL DENBL_P DENBL_P
FPGA_OFFSET DENBL_N
APERTURE FPGA_OFFSET FPGA_OFFSET DENBL_N DENBL_N
I6 FPGA_SD_COM GPLS2_P
FPGA_SD_COM FPGA_SD_COM GPLS2_P GPLS2_P
FPGA_XON GPLS2_N
FPGA_XON FPGA_XON GPLS2_N GPLS2_N
APT_HOFF XON_P
FPGA_GPLS2_OUT XON_P XON_P

APT_DIR FPGA_GPLS2_OUT FPGA_GPLS2_OUT XON_N
FPGA_DRESET XON_N XON_N
APT_PULS FPGA_DRESET FPGA_DRESET SDCOM_P
SDCOM_P SDCOM_P
APT_C_S SDCOM_N
SDCOM_N SDCOM_N
APT_C_D OFFSET_P
FPGA_DS_RX_0 OFFSET_P OFFSET_P
FPGA_DS_RX_0 FPGA_DS_RX_0 OFFSET_N
FPGA_DS_RX_1 OFFSET_N OFFSET_N
GPLS2_IN SHT 11 FPGA_DS_RX_1 FPGA_DS_RX_1 DRESET_P
DRESET_P DRESET_P
ENC_A DRESET_N
DRESET_N DRESET_N
ENC_B
PHOTO
FPGA_PHOTO
FPGA_APT_C_D FPGA_PHOTO FPGA_PHOTO
FPGA_ENA
FPGA_APT_C_S FPGA_ENA FPGA_ENA
C FPGA_APT_PULS FPGA_ENB
FPGA_ENB
FPGA_ENB
JEDI I16 C
FPGA_GPLS2_IN
FPGA_APT_DIR FPGA_GPLS2_IN FPGA_GPLS2_IN
FPGA_EXP_CMD_N EXPCMD_P
FPGA_APT_HOFF EXPCMD_P EXPCMD_P
FPGA_EXP_CMD_N FPGA_EXP_CMD_N EXPCMD_N
EXPCMD_N EXPCMD_N
FPGA_XRESET_N
FPGA_XRESET_N FPGA_XRESET_N
FPGA_CAN_TXD XRESET_P
FPGA_APT_HOFF FPGA_CAN_TXD FPGA_CAN_TXD XRESET_P XRESET_P
FPGA_APT_HOFF XRESET_N
FPGA_APT_DIR FPGA_XRON XRESET_N XRESET_N
FPGA_APT_DIR FPGA_XRON FPGA_XRON
FPGA_APT_PULS FPGA_CAN_RXD
FPGA_APT_PULS FPGA_CAN_RXD FPGA_CAN_RXD CAN_P
FPGA_APT_C_S CAN_P CAN_P
FPGA_APT_C_S CAN_N
FPGA_APT_C_D CAN_N CAN_N
FPGA_APT_C_D
SHT 9-10
XRON_P
XRON_P XRON_P
XRON_N
XRON_N XRON_N
PHOTO
PHOTO
ENC_B
ENC_B
ENC_A
ENC_A
GPLS2_IN
GPLS2_IN
APT_C_D
APT_C_D
APT_C_S
APT_C_S
APT_PULS
APT_PULS
APT_DIR
APT_DIR
D APT_HOFF
APT_HOFF D
REV 2 01July04
MISC I13
SHT 22-23
TOP LEVEL DIAGRAM GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:21:14 2007 new_ogp 2 of 2 5132987SCH E 2 of 23

1 2 3 4 5 6 7 8
GANTRY 3-3
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
POSITIONING LIGHT I/F

CN5
COLLIMATOR CONTROL INTERFACE
CN1
2B8^ IN
L_ON_P 1 1 JEDI I/F
GND 2 2
H_ON_P 3 CN9
2B8^ IN 3
2D8^ 3C6> APT_PULS 1 1 3B6< 24V_GND_1 4 4
A OUT
2 2
A
1 1 12V
2D8^ 3C6> APT_DIR 3 3
OUT 2C8^ IO
CAN_P 2 2 9 9
4
4 PIN 3 10 CAN_N
APT_HOFF 5 3 10 IO 2C8^
2D8^ 3C6> OUT 5 STRAIGHT XRESET_P 4 11
6 2C8^ OUT 4 11
6 FRICTIONLOCK_HEADER EXPCMD_P 5 12 XRESET_N
2C8^ OUT 5 12 OUT 2C8^
2C8^ XRON_P 6 6 13 13 EXPCMD_N 2C8^
IN OUT
7 7 14 14 XRON_N 2C8^
PIN IN
8 8 15 15
STRAIGHT
GND FRICTIONLOCK_HEADER
SLIPPING RING I/F
G1 G1
CN6 G2
46-237723P6 G2
1 1 2 2
3 4 SOCKET
3 4
5 6 24V_GND_1 STRAIGHT GND_CHASSIS
5 6 24V_GND_1
7 8 STD_DENSITY
7 8
POWER CONNECTOR 2A8^ 3B5< GDTRIG_P 9 9 10 10 GDTRIG_P 3B3< 2A8^
IN
CN2 2A8^ 3B5< GDTRIG_N 11 11 12 12 GDTRIG_N 3B3< 2A8^
IN
2A8^ 3B5< SGCOM_P 13 13 14 14 SGCOM_P 3B3< 2A8^
IN
2A8^ 3B5< SGCOM_N 15 15 16 16 SGCOM_N 3B3< 2A8^
1 1 5V 4A1< IN
GSCOM_P 17 17 18 18 GSCOM_P 3B3> 2A8^
2 2 2A8^ 3B5< OUT
GSCOM_N 19 19 20 20 GSCOM_N 3B3> 2A8^
3 3 24V_1 4C1< 2A8^ 3B5< OUT
4 4 TUBE FAN I/F
5 5 24V_2 4D1< GND
PIN
B 6 6
STRAIGHT
CN10 B
24V_GND_1
2B8^ TUBE_FAN_ON 1 1
PIN 24V_GND_2 IN
24V_GND_1 2 2
STRAIGHT 3A3<
MATE_N_LOK
PIN
STRAIGHT
FRICTIONLOCK_HEADER
APERTURE POWER I/F CONNECTOR

24VCC_2
CN7
1 1 APERTURE CONTROL RESERVE

COLLIMATOR FEEDBACK I/F
C800
20%
10U
50V
2 2 VCC
CN14
VCC
CN3
PIN 1 1
1 STRAIGHT APT_PULS 2
1 24V_GND_2 2D8^ 3A1> OUT 2
MATE_N_LOK
C 2D8^ IN
PHOTO 2 2
NOT MOUNTED
3 3 C
3 3 2D8^ 3A1> APT_DIR 4 4
OUT
4 4 5 5
2D8^ ENC_A 5 5 2D8^ 3A1> APT_HOFF 6 6
IN OUT
2D8^ ENC_B 6 6 7 7
IN
7 7 2D8^ APT_C_S 8 8
OUT
8 8 9 9
2D8^ APT_C_D 10 10
OUT
11 11
PIN
DAS I/F 12 12
GND STRAIGHT CN8
FRICTIONLOCK_HEADER
PIN
2B8^ DTRIG_P 1 1 STRAIGHT
OUT
2B8^ DENBL_P 2 14 DTRIG_N
OUT 2 14 OUT 2B8^ FRICTIONLOCK_HEADER
2B8^ SDCOM_P 3 15 DENBL_N
OUT 3 15 OUT 2B8^
2B8^ DSCOM_P 4 16 SDCOM_N
GPLS2 I/F IN 4 16 OUT 2C8^
2B8^ GPLS2_P 5 5 17 17 DSCOM_N 2B8^
OUT IN
2C8^ OFFSET_P 6 18 GPLS2_N
CN4 OUT 6 18 OUT 2B8^
2B8^ XON_P 7 19 OFFSET_N
VCC OUT 7 19 OUT 2C8^
2C8^ DRESET_P 8 20 XON_N
OUT 8 20 OUT 2B8^
9 21 DRESET_N
VCC 1 1
9 21 OUT 2C8^
10 10 22 22
2D8^ GPLS2_IN 2 2
IN 11 11 23 23
3 3 12 12 24 24
4 4 13 13 25 25
D G1 G1 D
GND PIN
G2 G2
STRAIGHT
REV 2 01July04
FRICTIONLOCK_HEADER GND
SOCKET
STRAIGHT GND_CHASSIS
STD_DENSITY CONNECTORS GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:20:34 2007 connectors 1 of 2 5132987SCH E 3 of 23

1 2 3 4 5 6 7 8
3-4 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
D37
MURS160 NOTE: MAX AREVAGE FORWARD RECTIFIED CURRENT IS 2A @125 DEGREE
NOTE: F1,F2,F3 ARE ALSO USED PREVIOUS FUSE U8009FF FOR FORWARD COMPATIBILITY CONSIDERATION
NOT MOUNTED
NOT MOUNTED
600V VCC
F1 VCC
FUSE VR2 1V5
125V LT1086
2.5A
A A
2
FL3 3 2
1
VIN VOUT1
C802
C803
20%
20%
20%
C801
35V
35V
35V
22U
22U
22U
BLM31P601SG VOUT2 4
1 2 1 ADJ R4 C11
C165
C175
121
10%
10%
470P
0.1U
5%
35V
50V
35V
C13
22U
22U
0.1W 16V
FL4 VCC 1% 10%
BLM31P601SG TANTALUN
5V
3B2> 1 2 C7 R5 GND
4.7U 24.9
GND 10V TANTALUN 0.1W
C9 C4 10% 1% 3V3
10%
35V
C51
22U
GND
220U
470P
0.1U 0.1U
20%
5%
50V
C12
50V
C3
16V 16V TANTALUN

10% 10%
F4 GND
RESETTABLE
GND GND GND GND GND D38
C805
20%
1.6A MURS160
35V
22U
C804
20%
35V
22U
72V
TANTALUN
VCC
600V
3V3
VR1
LT1086
NOT MOUNTED
GND
B 3 VIN VOUT1 2 B
VOUT2 4
F2 1 C10
ADJ R2
FUSE
C167
C177
C173
110
10%
10%
470P
0.1U
5%
35V
50V
35V
22U
22U
125V 0.1W 16V
0.1% 10% R611
FL5 BOTTOM SHIELD GND2
2.5A
2
1
1 2 C6 0
R3
NOTE: RATED CURRENT IS 1.5A 0.25W
2
1
4.7U 182
1.5A GND 10V GND 1% GND2

24VCC_1 0.1W
FL6 10% 1% GND
24V_1 R610
1 2 TOP SHIELD GND1
3B2> TANTALUN D39
MURS160
1.5A GND 0
C8 0.25W
10%
C164
100U
470P
24VCC_1
20%
5%
50V
50V
0.1U
C14
C50
50V
220U
0.1U 600V 1%
20%
50V
C2
16V U19 GND

10% ISO_VCC GND1
LT1085
F5 NOT MOUNTED, IT IS ONLY FOR GRIDDED GROUND
RESETTABLE 3 2
VIN VOUT1
24V_GND_1 24V_GND_1 24V_GND_1 VOUT2 4 R1
C20
C 24V_GND_1 24V_GND_1 1.6A 1 ADJ C
10%
0.1U
35V
C22
22U
R800
0.1W
470P
C171
72V
5%
50V
1%
1K
C8: NOT MOUNTED 16V 0
10% 0.25W
100U
1%
20%
C15
50V
TANTALUN GND
GND_CHASSIS
C820
0.125W
R801
3.01K
R164 TOP SHIELD GND1
1%
4.7U
NOT MOUNTED 10V 24V_GND_1
F3 24V_GND_1 10% 0
FUSE 0.25W
D40 1%
125V
FL7 MURS160
2
24V_GND_1
1
2.5A BLM31P601SG 24VCC_1 R165

1 2 U20
2
1
LT1085 600V 12V

1.5A 0
FL8 24VCC_2 0.25W
3 VIN VOUT1 2 1%
BLM31P601SG
24V_2 VOUT2 4
3B2> 1 2
1 ADJ C21 C23
R802 10U
C169
100U
0.1W
470P
20%
1.5A 0.1U R166
5%
50V
C16
1%
50V
1K
50V 35V
10%
10%
220U
470P
20%
5%
50V
50V
50V
10%
C19
C18
0.1U
0.1U
50V
C5
10%
C1
100U
20%
C52
50V
TANTALUN 0
0.25W
F6 C821
R803
1%
0.1W
RESETTABLE
8.66K
D D
1%
4.7U 1 R163-166 ARE USED FOR EASY ROUTING FOR GROUND
10V WITH GND-CHASSIS
10% 24V_GND_1
24V_GND_2 24V_GND_2 1.6A 24V_GND_2 24V_GND_2 24V_GND_2 2 IT ALSO ADD A EMC TEST OPTION
24V_GND_1
REV 2 01July04
72V
24V_GND_1 POWER SUPPLY GE Healthcare

Company Restricted
B Size
Fri Jun 15 10:17:40 2007 connectors 2 of 2 5132987SCH E 4 of 23

1 2 3 4 5 6 7 8
GANTRY 3-5
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3 3V3
A A
R80 R83
4.99K 332
0.1W 0.1W
1% 1% K1 VCC
LH1510AAB
3 NC1 S 6
1
5 L_ON_P 2B7^
DC OUT
GND 2
S1 4
3V3
MURS160
600V
D26
R78 3V3 3V3
R630
R631
1K
0.1W
0.1W
4.99K
4.99K
1%
1%
0.1W
1% GND
U18 R84 K2
74LVC_LCX244 R81 332 LH1510AAB
4.99K 0.1W 24VCC_1
0.1W 1%
19 OE_N 1% 3 NC1 S 6
B 1 B
2B6^ FPGA_POSLIGHT_ON 11 A1 Y1 9 5 H_ON_P 2B7^
IN DC OUT
13 A2 Y2 7 2
2B6^ FPGA_TUBE_FAN_P 15 A3 Y3 5 S1 4
IN
MURS160
17 A4 Y4 3
600V
D25
R79 VCC=3V3;GND=GND
1K
0.1W
1%
3V3 3V3
24V_GND_1
K3
GND R82 R85 LH1510AAB
4.99K 332
0.1W 0.1W
1% 1% 3 NC1 S 6
1
5 TUBE_FAN_ON 2B7^
DC OUT
2
MURS160
C S1 4 C
600V
3V3
D29
R57
1K U18 3V3
0.1W 74LVC_LCX244 LED FORWARD VOLTAGE IS 1.27V 24V_GND_1
1% I(FORWARD) IS 6MA
1 OE_N R=(3.3-1.27)/6MA=330 OHM
10%
C199
16V
0.1U
2 A1 Y1 18
4 A2 Y2 16
6 A3 Y3 14
8 A4 Y4 12
R58 VCC=3V3;GND=GND GND

1K
0.1W
1%
GND
D D
REV 2 01July04
POSITION LIGNT AND TUBE FAN GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:20:39 2007 pos_light 1 of 1 5132987SCH E 5 of 23

1 2 3 4 5 6 7 8
3-6 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
R67 R97
U41 1K
3V3 51.1
Y1 74LVC1G07 0.1W
FL9 0.1W
1% 1%
BLM21PG221SN1 R88 3V3
A 1 2 4 VCC VOUT 3 2 A Y 4 CLK_FPGA_24M
OUT 2A3^ A
C154 220 OHM C156 C53 1 2 51.1
ENABLE GND 0.1W

1U 1U 0.1U VCC=3V3;GND=GND C155 C158
10V 10V 16V 1%
10% 10% 10% 3V3 0.1U 0.1U
24MHZ 16V 16V
CERMAIC CERMAIC 10% 10%
R620 GND
1K
GND GND GND 1% R91
0.1W U42 1K
74LVC1G07 0.1W
3V3 1%
R95 GND
CLK_CPLD_24M
2 A Y 4 2A3^
OUT
51.1
0.1W
VCC=3V3;GND=GND 1%
B B
HARDWARE RESET SWITCH

VCC
S2
G3B15AH-XA
R94
4.99K
O1 3 0.1W
2 COM 1%
R92
O2 1
G1 G1 1K
G2 G2 1% C57
G3 R93
G3 0.1W 4.99K 0.1U
G4 G4 16V
0.1W
1% 10%
C GND 3V3 C
VCCA TRIG THRESHOLD IS 1V 1V5 GND
U24
1.5V*11/(4.99+11)=1.03V
R86 LTC1726ES8-2_5
4.99K GND R99
0.1W 3V3 3V3 IS DIRECTLY MEASURED 4.99K
1% TRIG THRESHOLD IS 3.135V 2 VCC25 0.1W
1 VCC3 1%
3 VCCA
R400
2B3^ CPLD_WATCHDOG 5 WDI RST_N 6 RESET_N 2A3^
IN OUT
7 WT
8 4 33.2
RT GND
0.1W
C55 1%
R87
11K 0.1U C56 C58 2.5V
0.1W 16V 10P 0.1U
1% 10% NOTE: 50V 16V
5% 10%
THE WATCHDOGTIMEOUT VALUE IS
GND GND TWT(US) = 21.8*CWT(PF)
WITH 10PF CAP TWT = 218 US GND GND GND
THE RESET TIMEOUT VALUE IS

TRT(US) = 3.3*CRT(PF)
WITH 0.1UF CAP, TRT= 330MS
D D
REV 2 01July04
CLOCK AND RESET CIRCUIT GE Healthcare
Company Restricted
B Size
Thu Jun 14 10:53:49 2007 reset_clk 1 of 1 5132987SCH E 6 of 23

1 2 3 4 5 6 7 8
GANTRY 3-7
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC
U12
R100 HCPL0631
2B2^ GDTRIG_P VCC
IN
R104
0.1W
U15
392
1%
47.5 8
VCC 74LVC-LCX14
0.1W
1% 1 VO<1> R108 R182 FPGA_GD_TRIG_0
R101 7 1 A B 2 2B3^
OUT
2B2^ GDTRIG_N 2
IN 100 51.1
A 47.5 0.1W 0.1W
A
4
470P
5%
50V
C63
0.1W 6 1% 1%
1% 3 VCC
5
GND
GND U15
R106
0.1W
74LVC-LCX14
392
1%
R109 R189
3 A B 4 FPGA_GD_TRIG_1 2B3^
OUT
GND
100 51.1
0.1W 0.1W
470P
VCC=3V3;GND=GND
5%
50V
C64
1% 1%
U13 VCC
R102 HCPL0631
2B2^ GSCOM_P VCC
IN GND
U15
R105
47.5 8
0.1W
VCC 74LVC-LCX14
1%
392
0.1W
1% 1 VO<1> R110 R193
R103 7 5 A B 6 FPGA_GS_COM_0 2B3^
OUT
2B2^ GSCOM_N 2
B IN 100 51.1 B
47.5 4 0.1W 0.1W
470P
5%
50V
C65
0.1W 6 1% 1%
1% 3
5 VCC
GND
GND U15
R107
0.1W
74LVC-LCX14
392
1%
R111 R191
9 A B 8 FPGA_GS_COM_1 2B3^
OUT
GND
100 51.1
0.1W 0.1W
470P
VCC=3V3;GND=GND
5%
50V
C66
1% 1%
GND
VCC
GND
U14
C VCC VCC C
R123
R98
0.1W
0.1W
DS26C31T
1%
1%
1K
1K
MMSD4148
MMSD4148
R125
12
100V
100V
EN_N 33.2
4 EN 0.1W
D30
D35
1%
2B3^ FPGA_SG_COM 1 I<3> OUTP<3> 2 SGCOM_P 2B2^
IN OUT THE BAUD RATE OF GS_COM IS 9600
OUTN_N<3> 3 SGCOM_N 2B2^
OUT
7 I<2> OUTP<2> 6
MMSD4148
MMSD4148
5 R141
OUTN_N<2>
9 10 33.2
I<1> OUTP<1>
100V
100V
11 0.1W
OUTN_N<1>
D34 1%
D36
15 I<0> OUTP<0> 14
OUTN_N<0> 13
R122
0.1W
1%
1K
VCC=VCC;GND=GND GND
GND
3V3 VCC
GND
10%
10%
10%
10%
C157
16V
16V
16V
16V
C60
C61
C62
0.1U
0.1U
0.1U
0.1U
D D
GND GND
REV 2 01July04
SLIPPING RING GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:21:09 2007 slip_ring 1 of 1 5132987SCH E 7 of 23

1 2 3 4 5 6 7 8
3-8 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC GND
VCC VCC VCC VCC VCC VCC VCC VCC
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
U1
R14
0.1W
R18
1%
1K
0.1W
DS26C31T
1%
1K
100V
100V
100V
100V
100V
100V
100V
100V
D13
D17
D21
D27
D31
D5
D9
D1
12 EN_N 33.2
4 EN 0.1W
1%
A 2B6^ IN
FPGA_DTRIG 1 I<3> OUTP<3> 2 R24 DTRIG_P
OUT 2B7^ A
OUTN_N<3> 3 R25 DTRIG_N 2B7^
OUT
2B6^ FPGA_DENBL 7 I<2> OUTP<2> 6 R26 DENBL_P 2B7^
IN OUT
OUTN_N<2> 5 R27 DENBL_N 2B7^

OUT
2B6^ FPGA_GPLS2_OUT 9 I<1> OUTP<1> 10 R28 GPLS2_P 2B7^
IN OUT
OUTN_N<1> 11 R29 GPLS2_N 2B7^
OUT
2B6^ FPGA_XON 15 I<0> OUTP<0> 14 R30 XON_P 2B7^
IN OUT
OUTN_N<0> 13 R31 XON_N 2B7^
OUT
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
R640
0.1W
1%
1K
VCC=VCC;GND=GND
UN-WORK
100V
100V
100V
100V
100V
100V
100V
100V
SIGNAL CONDITION
D10
D14
D18
D22
D28
D32
D2
D6
OFFSET -> H
GND SD_COM -> H

ENBL -> L
GND
GND GND GND GND GND GND GND GND XRON -> L
VCC
DTRIG -> H/L
VCC VCC VCC VCC VCC VCC GPLS2 -> H
U2
DRESET -> H
R17
R19
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
0.1W
0.1W
DS26C31T
1%
1%
1K
1K
100V
100V
100V
100V
100V
100V
B 12 EN_N B
D11
D15
D19
D23
D3
D7
4 EN
2B6^ FPGA_SD_COM 1 I<3> OUTP<3> 2 R32 SDCOM_P 2C7^

IN OUT
OUTN_N<3> 3 R33 SDCOM_N 2C7^
OUT
2B6^ FPGA_OFFSET 7 I<2> OUTP<2> 6 R34 OFFSET_P 2C7^
IN OUT
OUTN_N<2> 5 R35 OFFSET_N 2C7^
OUT
2B6^ FPGA_DRESET 9 I<1> OUTP<1> 10 R36 DRESET_P 2C7^
IN OUT
OUTN_N<1> 11 R37 DRESET_N 2C7^
OUT
15 I<0> OUTP<0> 14
13 33.2
OUTN_N<0>
0.1W
1%
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
MMSD4148
VCC=VCC;GND=GND
R8
0.1W
1%
1K
100V
100V
100V
100V
100V
100V
D12
D16
D20
D24
D4
D8
GND
GND GND GND GND GND GND
C C
U3 VCC
HCPL0631
VCC
U30
R20
8
0.1W
VCC 74LVC-LCX14
1%
392
R15
2B7^ DSCOM_P 1 VO<1> R22 R172
IN
7 1 A B 2 FPGA_DS_RX_0 2C6^
47.5 OUT
2
0.1W 100 51.1
1% 4 0.1W 0.1W
470P
5%
50V
C24
6 1% 1%
R16
2B7^ DSCOM_N 3
IN
5 VCC
47.5
GND
0.1W
1% GND U30
R21
0.1W
74LVC-LCX14
1%
392
R23 R171
3V3 VCC 3 A B 4 FPGA_DS_RX_1 2C6^
OUT
GND
100 51.1
0.1W 0.1W
D 1%
VCC=3V3;GND=GND
1%
D
10%
C102
470P
16V
5%
50V
C25
0.1U
REV 2 01July04
10%
10%
10%
16V
16V
16V
C26
C27
C28
0.1U
0.1U
0.1U
GND GND DAS GE Healthcare

Company Restricted
B Size
GND
Wed Jun 13 11:20:42 2007 das 1 of 1 5132987SCH E 8 of 23

1 2 3 4 5 6 7 8
GANTRY 3-9
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
0631'S RECOMMENDEDCURRENT IS 5-15MA ISO_VCC

A FORWARD VOLTAGE IS 1.5V @ 10MA A
R=(3.3V-1.5V-0.4V)/10MA=140 OHM
287 U7
R46
0.1W
0.1W MAX485E
1%
1K
1% ISO_VCC
R42 1 4
3V3
RO DI
DE 3
U5 6 EXPCMD_P
3V3 R43 ISO_VCC A OUT 2C7^
HCPL0631 7 EXPCMD_N
B OUT 2C7^
RE_N 2
U40
8
R301
VCC 74VHC_AHC14
0.1W
R40
392
1%
0.1W
1%
1K
1 GND=24V_GND_1;VCC=ISO_VCC
VO<1> R302
7 3 A B 4
2C6^ FPGA_EXP_CMD_N 2
IN ISO_VCC 33.2
3V3 R47 4 0.1W
3V3
VO<0> VCC=ISO_VCC;GND=24V_GND_1
6 1%
U40
R303
R49 3
0.1W
74VHC_AHC14
1%
392
5
287
R41
0.1W
GND R304
1%
1K
0.1W 1 2 ISO_VCC
1% A B
FPGA_XRESET_N 33.2
2C6^ IN 0.1W
VCC=ISO_VCC;GND=24V_GND_1
U23
R45
0.1W
1%
1%
1K
24V_GND_1 MAX485E
B B
1 RO DI 4
DE 3
A 6 XRESET_P 2C7^
OUT
B 7 XRESET_N 2C7^
OUT
RE_N 2
GND=24V_GND_1;VCC=ISO_VCC
VCC U6 ISO_VCC ISO_VCC

HCPL0720-060
8 VDD2 VDD1 1
10%
10%
10%
10%
10%
10%
16V
16V
16V
16V
16V
16V
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
C29
C31
C33
C35
C36
C37
R183 R510
10B5< CAN_RXD_TO4245 6 VO VI 2
33.2 5 4 33.2
0.1W 0.1W
GND2 GND1
1% 1% 24V_GND_1
U22
C 82C251 C
ISO_VCC
GND 24V_GND_1
3 VCC
R50
1 TXD RXD 4
VCC 8 RS VREF 5 121
VCC
0.1W
CANL 6 1% CAN_N 2C7^
IO
U4 ISO_VCC CANH 7 CAN_P 2C7^ VCC
IO
R44
0.1W
HCPL0720-060
47.5K
1%
R12
2
0.1W
GND
4.99K
1%
1 VDD1 VDD2 8
10%
10%
16V
16V
0.1U
0.1U
C30
C34
2C6^ FPGA_CAN_TXD 2 VI VO 6 24V_GND_1
IN
OPEN DRAIN OUTPUT FROM FPGA 4 5
GND1 GND2
GND
24V_GND_1
24V_GND_1
GND
D D
REV 2 01July04
JEDI GE Healthcare
Company Restricted
B Size
Fri Jun 15 10:56:19 2007 jedi 1 of 2 5132987SCH E 9 of 23

1 2 3 4 5 6 7 8
3-10 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
JEDI I/F BOARD OURPUT 3.6V FROM MAX485E

0631 RECOMMENDEDCURRENT IS 5-15MA
THE FORWARD VOLTAGE IS 1.5V @ 10MA
R=((3.6V-1.5V)/10MA)/2=105 OHM
VCC GND 3V3 VCC
U10
74LVC-LVX4245
B NOT MOUNTED VCC VCC B
U9
R39
R59
0.1W
0.1W
1%
1%
1
1K
1K
R60 HCPL0631 VCCA
XRON_P NOTE: T/R=H => A-> B
2C7^ IN VCCB<1-0>
R300
0.1W
R184
392
1%
110 8 22
VCC OE_N 51.1
0.1W
0.1% MMSD4148 2 T_R 0.1W
1 VO<1> R201 1%
10000P
R48
7 3 21 FPGA_XRON
10%
0.1W
100V
A<7> B<7> 2C6^
50V
10K
C38
1%
OUT
2 9C1> CAN_RXD_TO4245 4 A<6> B<6> 20 FPGA_CAN_RXD 2C6^
D33
100 OUT
5 A<5> B<5> 19
4 0.1W 6 18
10%
C300
VO<0> A<4> B<4> R192
10N
50V
6 1% 7 17
A<3> B<3> 1%
R61 3 8 A<2> B<2> 16 0.1W
2C7^ XRON_N 5 9 A<1> B<1> 15 51.1
IN
GND 10 A<0> B<0> 14
110
0.1W
R38
0.1W GND GND<2-0>

1%
1K
0.1% GND
R62
0.1W
1%
1K
C GND
GND C
GND
VCC
3V3
C39 C111
10%
10%
10%
10%
C110
16V
16V
16V
16V
0.1U 0.1U
C47
C17
C54
0.1U
0.1U
0.1U
0.1U
10%
16V
C49
0.1U 16V 16V

D 10% 10% D
REV 2 01July04
GND
GND
JEDI GE Healthcare
Company Restricted
B Size
Thu Jun 14 09:55:51 2007 jedi 2 of 2 5132987SCH E 10 of 23

1 2 3 4 5 6 7 8
GANTRY 3-11
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
GND GND
U8 VCC 3V3
74LVC-LVX4245
R65
1
0.1W
VCCA
R66
VOLTAGE TRANSLATING 3.3V->5
1%
1K
0.1W
1%
1K
VCCB<1-0>
FL1
A OE_N 22 NFA31CC222R1E4 A
T_R 2
2C2^ FPGA_APT_HOFF 21 B<7> A<7> 3 3 A1 B1 7 APT_HOFF 2B2^

IN OUT
2C2^ FPGA_APT_DIR 20 B<6> A<6> 4 4 A2 B2 8 APT_DIR 2B2^
IN OUT
2C2^ FPGA_APT_PULS 19 B<5> A<5> 5 5 A3 B3 9 APT_PULS 2B2^
IN OUT
2C2^ FPGA_APT_C_S 18 B<4> A<4> 6 6 A4 B4 10
IN
2C2^ FPGA_APT_C_D 17 B<3> A<3> 7
IN
16 B<2> A<2> 8 GND1 1
15 B<1> A<1> 9 GND2 2
14 B<0> A<0> 10
2200PF
GND<2-0>
R13
GND
0.1W
1%
1K
FL2
NFA31CC222R1E4
GND GND NOTE: T/R=L => B-> A
3 A1 B1 7 APT_C_S 2C2^
OUT
4 A2 B2 8 APT_C_D 2C2^
OUT
5 A3 B3 9
6 A4 B4 10
GND1 1 APERTURE CONTROL RESERVE

GND2 2
B B
2200PF GND NOT MOUNTED
74LVC-LCX14 74LVC-LCX14
GND
U21 U21 R173
VCC VCC VCC VCC VCC 3V3 VCC U11 1 A B 2 3 A B 4 FPGA_PHOTO 2C3^
OUT
74LVC-LVX4245
51.1
0.1W
0.125W
VCC=3V3;GND=GND VCC=3V3;GND=GND
R73
R76
R77
1K
0.1W
0.1W
0.125W
0.125W
0.125W
1%
R68
R69
R75
1%
1%
1%
332
1K
1 VCCA
1%
1%
1%
332
332
332
VCCB<1-0>
FL10
NFA31CC222R1E4 22 OE_N
2 T_R 74LVC-LCX14
C 2C2^ PHOTO 7 B1 A1 3 3 A<7> B<7> 21 U21 R174
C
IN
2C2^ ENC_A 8 B2 A2 4 4 A<6> B<6> 20 5 A B 6 FPGA_ENA 2C3^
IN OUT
2C2^ ENC_B 9 B3 A3 5 5 A<5> B<5> 19
IN 51.1
2C2^ GPLS2_IN 10 B4 A4 6 6 A<4> B<4> 18
IN 0.1W
7 A<3> B<3> 17 VCC=3V3;GND=GND
1 R74 C41 C42 C43 C44 8 16 1%
GND1 R70 A<2> B<2>
2 GND2 100 R71 10N 10N 10N 0.1U 9 A<1> B<1> 15
0.1W R72 50V 50V 50V 16V 10 A<0> B<0> 14
2200PF 1% 3.32K 10% 10% 10% 10%
0.1W GND<2-0> 74LVC-LCX14
GND 1%
R64
0.1W
1%
1K
U21 R180
9 A B 8 FPGA_ENB 2C3^
OUT
GND
GND 51.1
F=1/(2*PI*R*C)=1/(2*3.14*3300*1*10(-8))=4.48KHZ VCC=3V3;GND=GND
0.1W
1%
ENCODER FEEDBACK PHASE PULSE FREQUENCE IS ABOUT 600HZ
GND
VOLTAGE TRANSLATING 5V->3.3V

NOTE: T/R=H => A-> B
74LVC-LCX14
U21 R181
11 A B 10 FPGA_GPLS2_IN 2C3^
OUT
VCC
D 3V3 51.1 D
0.1W
VCC=3V3;GND=GND
1%
REV 2 01July04
10%
16V
0.1U
C48
10%
10%
10%
C113
16V
16V
16V
C45
C46
0.1U
0.1U
0.1U
APERTURE GE Healthcare
Company Restricted
B Size
GND Block Path Block Sheet Dwg No Rev Sheet
GND
Wed Jun 13 11:21:12 2007 aperture 1 of 1 5132987SCH E 11 of 23
1 2 3 4 5 6 7 8
3-12 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
14C7<> CPLD_ADDR<2..0> CPLD_DATA<7..0> 14C7<

3V3
3
0
2
0
2
4
5
6
7
1
1
3V3
CPLD_SPARE<4..0> 14C2<>
R811
10K
A A
3
0
2
4
1
0.1W
1% CPLD_LED<3..0> 18D2<
FPGA_INIT_DOWN R116 R117 R118 R119 R120 R121
13B7>
3
2
0
1
4.99K 4.99K 1K 4.99K 4.99K 4.99K
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
3V3 3V3 3V3 1% 1% 1% 1% 1% 1%
100
102
101
65
66
68
69
80
82
83
84
86
88
90
92
93
96
98
99
70
72
74
75
78
79
67
87
97
81
91
71
R112 R113
10K 10K U17
0.1W 0.1W S29GL064M90
IO_65
IO_66
IO_67
IO_68
IO_69
IO_70
IO_72
IO_74
IO_75
IO_78
IO_79
IO_80
IO_82
IO_83
IO_84
IO_86
IO_87
IO_88
IO_90
IO_92
IO_93
IO_96
IO_97
IO_98
IO_99
IO_71
IO_81
IO_91
IO_100
IO_102
IO_101
1% 1%
VCCIO<6-0>
VCC<3-0> IO_103 103 0
IO_106 106 1
2A3^ RESET_N 127 GCLRN IO_107 107 2
IN
2A3^ CLK_CPLD_24M 125 GCLK1 IO_108 108 3 FSH_RY_BY_N 14B7<
IN
128 OE2_GCLK2 IO_109 109 4
126 OE1 IO_110 110 5
IO_111 111 6
21C7> CPLD_TDI 4 TDI IO_112 112 7
13C3< 21B5> JTAG_TMS 20 TMS IO_113 113
13C3< 21B5> JTAG_TCK 89 TCK IO_116 116
21B5< CPLD_TDO 104 TDO IO_117 117 1 0
IO_118 118 2 1
2B3^ CPLD_WATCHDOG R810 51.1
B OUT 1 IO_1
U26
IO_119 119 3 2 B
14C7< 12D1< FPGA_WDOG_ERR_N 2 IO_2 IO_120 120 4 3
CONFIG_DATA0 R401 5 EPM3256A_144-7 121 R128 5 4
13C3< 51.1 IO_5 IO_121
CONFIG_DCLK 6 122 1K 6 5
13C3< R402 51.1 IO_6 IO_122
BOOT_SEL_OUT 7 131 0.1W 7 6
14C7< IO_7 IO_131
CONFIG_N 8 132 1% 8 7
13C3< IO_8 IO_132
13B8> CONFIG_DONE 9 IO_9 IO_133 133 9
13B8> CONFIG_STATUS_N 10 IO_10 IO_134 134 10
14C7< RECFG_BOOT_APPL 11 IO_11 IO_136 136 11
3V3
12D1< 14C7> RECFG_RQ_N 12 IO_12 IO_137 137 12

0 14 IO_14 IO_138 138 13
0 R132
14C7< RECFG_REASON<1..0> 1 15 IO_15 IO_139 139 14
1 R185
14C8< FPGA_RESET_N 16 IO_16 IO_140 140 R405 15
2 R187 4.99K *8
18 IO_18 IO_141 141 R406 16
3 R137 0.1W
12D1< 14C7> CPLD_WR_N 19 IO_19 IO_142 142 R407 GND 17
4 R197 1%
21 IO_21 IO_143 143 R408 18
5 R198
22 IO_22 19
33.2 X4 6 R199
2B3^ 15D7< IN FPGA_GD_TRIG_1 23 IO_23 GND<16-0> 20
0.1W 7 R200
21
FPGA_GD_TRIG_0 1% 22
2B3^ 19B2< 15D7< IN
IO_25
IO_27
IO_28
IO_29
IO_30
IO_32
IO_34
IO_35
IO_36
IO_37
IO_38
IO_39
IO_40
IO_42
IO_43
IO_44
IO_45
IO_46
IO_47
IO_48
IO_49
IO_53
IO_54
IO_55
IO_56
IO_60
IO_62
IO_63
IO_31
IO_41
IO_61
GND
14C7< 12D1< CPLD_RD_N
C S29GL064M C
25
27
28
29
40
42
43
44
45
46
47
48
49
53
54
55
56
60
62
63
30
32
34
35
36
37
38
39
31
41
61
GND
0
33.2 X 23
FSH_D<7..0> 14B7<>
0.1W
1%
3V3 3V3 3V3 3V3
FSH_WE_N 14C7>
R410
R412
R413
R414
R415
R416
R417
R418
R419
R420
R422
R423
R424
R425
R426
R427
R428
R429
R430
R432
R411
R421
R431
R115 R114 R126 R127 FSH_OE_N 14C7>

10K 10K 10K 10K
0.1W 0.1W 0.1W 0.1W FSH_CS_N 14C7>
14C7> RECFG_RQ_N 1% 1% 1% 1%
12B1<
20
22
10
12
13
14
15
16
17
18
19
11
21
3
0
2
4
5
6
8
9
7
1
FSH_A<22..0> 14A7<>
12B1< FPGA_WDOG_ERR_N
14C7<
14C7> CPLD_WR_N 3V3
3V3
12C1<
12C1< CPLD_RD_N
14C7<
10%
10%
16V
16V
C79
C80
0.1U
0.1U
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
0.1U
D D
REV 2 01July04
GND FLASH DECOUPLING
GND CPLD DECOUPLING
CPLD AND FLASH GE Healthcare

Company Restricted
B Size
Wed Jun 13 11:20:55 2007 fpga_cpld_flash 1 of 10 5132987SCH E 12 of 23

1 2 3 4 5 6 7 8
GANTRY 3-13
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
1V5 1V5_PLLA R142

4.99K
0.1W
L1 1%
S1
U34 U34
KT11B1JM
A 22N
74LVC-LCX14
74LVC-LCX14 A
5%
C81 1A C83 C85 1 1 3 3 11 10 13 12
A B A B
10%
1U 2.2U 10N
16V
C87
0.1U
10V 10V 50V 2 2 4 4
10% 10% 10%
CERMAIC
CERMAIC
GND CPU_RESET
ONLY FOR DEBUG
GND
1V5 1V5_PLLB
L2
22N 3V3
5%
C82 1A C84 C86
10%
1U 2.2U 10N
16V
C88
0.1U
10V 10V 50V

10% 10% 10% R143 R144
CERMAIC CERMAIC U16

FPGA 10K
0.1W
10K
0.1W
B 1V5_PLLB 1V5_PLLA 3V3 1V5 EP1C20F400C7N 1% 1% B
GND GND
VCCINT<19-0> CEO_N L2
PLL SUPLIES 3V3 VCCIO1<4-0> STATUS_N L17 CONFIG_STATUS_N 12B1<
VCCIO2<4-0>
PLACE CLOSE TO APPROPRIATE PINS VCCIO3<4-0> TDO L20 FPGA_TDO 21B5<
R600
D3
0.1W
VCCIO4<4-0> IO_D3_CLKUSR
1%
1K
R7 K4 VCCA_PLL1 IO_C3_INIT_DONE C3 FPGA_INIT_DOWN 12A1<>
10K K17 VCCA_PLL2 CONF_DONE L18 CONFIG_DONE 12B1<

0.1W IO_C4_DEV_CLRN C4
1% L5 CE_N IO_B3_DEV_OE B3
3V3 12B1> CONFIG_N K1 CONFIG_N IO_K2_NCSO K2
IO_L4_ASDO L4
12B1< 21B5> JTAG_TCK L19 TCK R140
R138 12B1< 21B5> JTAG_TMS L16 TMS IO_L8_PLL1_OUTP L8 SDRAM_CLK 16B1<
10K FPGA_TDI K18 TDI IO_M8_PLL1_OUTN M8
0.1W 21B5> L13 51.1
IO_L13_PLL2_OUTP
1% CONFIG_DATA0 K3 M13 0.1W
12B1> DATA0 IO_M13_PLL2_OUTN
CONFIG_DCLK L3 1%
12B1> DCLK
L1 MSEL0 GNDA_PLL1 K7
L6 MSEL1 GNDA_PLL2 K20
2A3^ CLK_FPGA_24M K5 CLK0 GNDG_PLL1 L7
C IN
K6 CLK1 GNDG_PLL2 L15 C
R129 L14
10K CLK2 GND<39-0>
K14 CLK3
0.1W
1% SYM 1 OF 3
GND
R130
R139
R131
0.1W
0.1W
0.1W
1%
1%
1%
1K
1K
1K
GND
GND GND GND
D D
REV 2 01July04
FPGA GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
3-14 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U16
EP1C20F400C7N
D4 IO_D4_VREF0B1 IO_D15_VREF0B2 D15

J8 IO_J8_VREF1B1 IO_F10_VREF1B2 F10
A U1 IO_U1_VREF2B1 IO_E6_VREF2B2 E6 TOP RIGHT OF CHIP A
TOP LEFT OF CHIP
T4 IO_T4_DPCLK0 IO_C6_DPCLK2 C6
F3 IO_F3_DPCLK1 IO_C15_DPCLK3 C15

FSH_A<22..0> 12D8>
2C3^ FPGA_APT_PULS C2 IO_C2 IO_C17 C17 0
OUT
2C3^ FPGA_APT_DIR D2 IO_D2 IO_B18 B18 1
OUT
2C3^ FPGA_APT_HOFF D1 IO_D1 IO_B17 B17 2
OUT
2C3^ FPGA_APT_C_S E4 IO_E4 IO_A17 A17 3
OUT
2C3^ FPGA_APT_C_D E5 IO_E5 IO_C16 C16 4
OUT
2C3^ FPGA_ENA E3 IO_E3 IO_B16 B16 5
IN
2C3^ FPGA_ENB E2 IO_E2 IO_D16 D16 6
IN
F4 IO_F4 IO_E16 E16 7
F5 IO_F5 IO_B15 B15 8
2C3^ FPGA_PHOTO F2 IO_F2 IO_A15 A15 9
IN
2C3^ FPGA_GPLS2_IN F1 IO_F1 IO_E15 E15 10
IN
F6 IO_F6 IO_F14 F14 11
21D4> FPGA_USER_PB G5 IO_G5 IO_A14 A14 12
G1 IO_G1 IO_B14 B14 13
G2 IO_G2 IO_E14 E14 14
G6 IO_G6 IO_E13 E13 15
G7 IO_G7 IO_C14 C14 16
G3 IO_G3 IO_D14 D14 17
G4 IO_G4 IO_A13 A13 18
H7 IO_H7 IO_B13 B13 19
H1 IO_H1 IO_C13 C13 20
B H2 IO_H2 IO_D13 D13 21 B
H3 IO_H3 IO_E12 E12 22
H4 IO_H4 IO_F12 F12 0 FSH_D<7..0> 12C8>
J1 IO_J1 IO_A12 A12 1
J2 IO_J2 IO_B12 B12 2
H5 IO_H5 IO_D12 D12 3
H6 IO_H6 IO_C12 C12 4 3V3
J3 IO_J3 IO_E11 E11 5
J4 IO_J4 IO_A11 A11 6
TOP OF CHIP
LEFT OF CHIP J5 IO_J5 IO_B11 B11 7 R145

J6 IO_J6 IO_D11 D11 FSH_RY_BY_N 12B8> 10K
J7 IO_J7 IO_C11 C11 FSH_CS_N 12D8> 0.1W
M2 IO_M2 IO_D10 D10 FSH_OE_N 12C8> 1%
M1 IO_M1 IO_C10 C10 FSH_WE_N 12C8>
M5 IO_M5 IO_A10 A10 FPGA_RESET_N 12C1>
M6 IO_M6 IO_B10 B10 BOOT_SEL_OUT 12B1<
M4 IO_M4 IO_E10 E10 RECFG_BOOT_APPL 12B1<
M3 IO_M3 IO_E9 E9 RECFG_RQ_N 12B1< 12D1<
M7 IO_M7 IO_C9 C9 0
N6 IO_N6 IO_D9 D9 1 RECFG_REASON<1..0> 12C1>
N1 IO_N1 IO_A9 A9 CPLD_WR_N 12C1< 12D1<
N2 IO_N2 IO_B9 B9 CPLD_RD_N 12C1< 12D1<
N4 IO_N4 IO_C8 C8 0
C N3 IO_N3 IO_D8 D8 1 C
N5 IO_N5 IO_A8 A8 2 CPLD_ADDR<2..0> 12A2<
CPLD_SPARE<4..0> N7 IO_N7 IO_B8 B8 FPGA_WDOG_ERR_N
12A4<> P7 E8 12B1< 12D1<
IO_P7 IO_E8
4 P2 IO_P2 IO_F8 F8
3 P1 IO_P1 IO_C7 C7
P6 IO_P6 IO_D7 D7
FPGA_SW3<3..0>
2 P5 IO_P5 IO_A7 A7 0 21B3>
1 P3 IO_P3 IO_B7 B7 1
0 P4 IO_P4 IO_E7 E7 2
R1 IO_R1 IO_F7 F7 3
CPLD_DATA<7..0>
18B1< FPGA_LED<7..0> 0 R2 IO_R2 IO_A6 A6 0 12A4<>
R6 IO_R6 IO_B6 B6 1
R5 IO_R5 IO_B5 B5 2
1 R3 IO_R3 IO_C5 C5 3
2 R4 IO_R4 IO_D6 D6 4
3 T2 IO_T2 IO_D5 D5 5
4 T3 IO_T3 IO_A4 A4 6
5 U4 IO_U4 IO_B4 B4 7
6 U2 IO_U2
7 U3 IO_U3
V2 IO_V2
V3 IO_V3 TOP LEFT OF CHIP
BOTTOM LEFT OF CHIP
SYM 2 OF 3
D D
REV 2 01July04
FPGA GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 3-15
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
EP1C20F400C7N
U16
D17 IO_D17_VREF0B3 IO_Y15_VREF0B4 Y15

K19 IO_K19_VREF1B3 IO_V10_VREF1B4 V10
BOTTOM_RIGHT OF CHIP U17 IO_U17_VREF2B3 IO_T7_VREF2B4 T7 BOTTOM LEFT OF CHIP
A A
F18 IO_F18_DPCLK4 IO_W15_DPCLK6 W15 33.2 X 8
T19 IO_T19_DPCLK5 IO_T6_DPCLK7 T6 0.1W
1%
2B5^ FPGA_TUBE_FAN_P W18 IO_W18 IO_W3 W3 R500 7
OUT
TEM1_SDA V18 IO_V18 IO_Y4 Y4 R501 6
20B6< TEM1_SCL V19 V4 5
IO_V19 IO_V4 R502
20B2< U20 W4 4
IO_U20 IO_W4 R503
U18 IO_U18 IO_T5 T5 R504 3
U19 IO_U19 IO_U5 U5 R505 2
T18 IO_T18 IO_V5 V5 R506 1
T17 IO_T17 IO_W5 W5 R507 0
FPGA_DEBUG_OUT<7..0>
R16 IO_R16 IO_W6 W6 17A2<
R19 IO_R19 IO_Y6 Y6
R20 IO_R20 IO_U6 U6
R17 IO_R17 IO_V6 V6 7
R18 IO_R18 IO_W7 W7 6
R15 IO_R15 IO_Y7 Y7 5
P14 IO_P14 IO_R7 R7 4
P18 IO_P18 IO_T8 T8 3
P17 IO_P17 IO_V7 V7 2
16B1< SDRAM_A<11..0> 11 P16 IO_P16 IO_U7 U7 1
10 P15 IO_P15 IO_V8 V8 0
FPGA_DEBUG_IN_A<7..0>
9 P19 IO_P19 IO_U8 U8 17B8<
8 P20 IO_P20 IO_W8 W8
7 N14 IO_N14 IO_Y8 Y8
B 6 N18 IO_N18 IO_U9 U9 B
5 N17 IO_N17 IO_V9 V9
4 N19 IO_N19 IO_T9 T9
3 N20 R9 NOTE: R63, R124, R179, R6, R9, R10 ARE ALL 33.2 OHM, 0.1W, 1%
IO_N20 IO_R9
2 N16 IO_N16 IO_Y9 Y9
1 N15 W9 NOTE: R11 IS 100 OHM, 0.1W, 1%
IO_N15 IO_W9
0 M18 IO_M18 IO_T10 T10
16B1< SDRAM_CS_N M17 IO_M17 IO_U10 U10
16B1< SDRAM_RAS_N M15 IO_M15 IO_W10 W10
RIGHT SIDE OF CHIP 16B1< SDRAM_CAS_N M16 IO_M16 IO_Y10 Y10 FPGA_RS232_COM1_RXD 19D6> BOTTOM OF CHIP
16B1< SDRAM_WE_N M20 IO_M20 IO_V11 V11 FPGA_RS232_COM1_TXD 19C2<
16B1< SDRAM_CKE M19 IO_M19 IO_U11 U11 FPGA_RS232_COM2_RXD 19D6>
16B1< SDRAM_BA1 M14 IO_M14 IO_W11 W11 FPGA_RS232_COM2_TXD 19D2<
16B1< SDRAM_BA0 J13 Y11 FPGA_DRESET
IO_J13 IO_Y11 33 R10 OUT 2B5^
16C1< SDRAM_DQM<3..0> 3 K16 IO_K16 IO_R11 R11
2 K15 IO_K15 IO_Y12 Y12 33 R9 FPGA_OFFSET 19A2< 2B5^
OUT
1 J18 IO_J18 IO_W12 W12 33 R6 FPGA_SD_COM 2B5^
OUT
0 J17 IO_J17 IO_T11 T11
16A6< SDRAM_DQ<31..0> 0 J14 IO_J14 IO_T12 T12
1 H14 U12 R179 FPGA_XON
IO_H14 IO_U12 33 OUT 2B5^
2 J20 IO_J20 IO_V12 V12 33 R124 FPGA_GPLS2_OUT 19B2< 2B5^
OUT
3 J19 IO_J19 IO_T13 T13
4 J15 IO_J15 IO_R13 R13
C 5 J16 Y13 R63 FPGA_DENBL C
IO_J16 IO_Y13 33 OUT 19A2< 2B5^
6 H20 W13 FPGA_DTRIG
IO_H20 IO_W13 51.1 R11 OUT 19A2< 2B5^
7 H19 IO_H19 IO_U13 U13 FPGA_DS_RX_1 2C5^
IN
8 H17 IO_H17 IO_V13 V13 FPGA_DS_RX_0 2C5^
IN
9 H18 IO_H18 IO_R14 R14
10 H16 IO_H16 IO_T14 T14
11 G17 W14 FPGA_EXP_CMD_N
IO_G17 IO_W14 OUT 19B2< 2C5^
12 G18 Y14 FPGA_CAN_TXD
IO_G18 IO_Y14 33.2 R511 OUT 2C5^
13 H15 IO_H15 IO_U14 U14 FPGA_CAN_RXD 2C5^
IN
14 G14 IO_G14 IO_V14 V14 FPGA_XRON 2C5^
IN
15 G19 V15 FPGA_XRESET_N
IO_G19 IO_V15 OUT 2C5^
16 G20 IO_G20 IO_U15 U15
17 G15 IO_G15 IO_T15 T15
18 G16 IO_G16 IO_T16 T16 R89
19 F20 W16 33 FPGA_SG_COM
IO_F20 IO_W16 OUT 2B3^
20 F19 IO_F19 IO_V16 V16 FPGA_GS_COM_1 2B3^
IN
21 F15 IO_F15 IO_V17 V17 FPGA_GS_COM_0 2B3^
IN
22 F16 IO_F16 IO_U16 U16 FPGA_GD_TRIG_1 12C1< 2B3^
IN
23 E19 IO_E19 IO_Y17 Y17 FPGA_GD_TRIG_0 12C1< 19B2< 2B3^
IN
24 E18 IO_E18 IO_W17 W17 FPGA_POSLIGHT_ON 2B5^
OUT
25 F17 IO_F17
26 E17 IO_E17
27 D20 IO_D20
28 D19 IO_D19
29 D18 IO_D18
30 C19 IO_C19
D TOP RIGHT OF CHIP 31 C18 IO_C18 BOTTOM RIGHT OF CHIP D
SYM 3 0F 3
REV 2 01July04
FPGA GE Healthcare
Company Restricted
B Size
Fri Jun 15 10:54:45 2007 fpga_cpld_flash 4 of 10 5132987SCH E 15 of 23

1 2 3 4 5 6 7 8
3-16 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
SDRAM
3V3
3V3 U28
MT48LC4M32B2
R241 R242 R243 R244 R245 R246 R247 SDRAM_DQ<31..0> 15C2<>
4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 4.99K 3V3
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W VDD<3-0> 33.2 NOT MOUNTED
1% 1% 1% 1% 1% 1% 1% VDDQ<7-0> 0.1W
1% 0 R248
15B2> SDRAM_CS_N 20 CS_N DQ0 2 R450 0
SDRAM_RAS_N 19 4 1 1 R249
15B2> RAS_N DQ1 R451 2 R250
15B2> SDRAM_CAS_N 18 CAS_N DQ2 5 R452 2
SDRAM_WE_N 17 7 3 3 R252
15B2> WE_N DQ3 R453 4 R253
DQ4 8 R454 4
SDRAM_CLK 68 10 5 5 R251
13C7> CLK DQ5 R455 6 R254
15C2> SDRAM_CKE 67 CKE DQ6 11 R456 6 7
DQ7 13 R457 7 R255
SDRAM_BA0 22 74 8 8 R256
15C2> BA0 DQ8 R458 9 R257
15C2> SDRAM_BA1 23 BA1 DQ9 76 R459 9 10
DQ10 77 R460 10 R258
0 25 79 11 11 R259
A0 DQ11 R461 12 R260
1 26 A1 DQ12 80 R462 12
B 2 27 A2 DQ13 82 R463 13 13
14
R261
R262 4.99K *32
B
3 60 A3 DQ14 83 R464 14
4 61 85 15 15 R263 0.1W
A4 DQ15 R465
NOTE: PAY ATTENTION TO THE CLOCK, IT IS 50M. 5 62 A5 DQ16 31 R466 16 16
17
R264
6 63 A6 DQ17 33 R467 17 R265 1%
7 64 34 18 18 R266
A7 DQ18 R468 19 R267
8 65 A8 DQ19 36 R469 19 20
9 66 A9 DQ20 37 R470 20 R268
10 24 39 21 21 R269
A10 DQ21 R471
11 21 40 22 22 R270
15B2> SDRAM_A<11..0> A11 DQ22 R472 23 R271
DQ23 42 R473 23 24
0 16 DQM0 DQ24 45 R474 24 R272
1 71 47 25 25 R273
DQM1 DQ25 R475 26 R274
2 28 DQM2 DQ26 48 R476 26 27
3 59 DQM3 DQ27 50 R477 27 R275
15C2> SDRAM_DQM<3..0> 51 28 R276
DQ28 R478 28 29
DQ29 53 R479 29 R277
3V3 54 30 30 R278
DQ30 R480 31 R279
DQ31 56 R481 31
3 R237
2 R238 4.99K *4 VSS<3-0> SDRAM DATA BUS PULL-UP RESISTORS
1 R239 0.1W VSSQ<7-0>
C 0 R240 1% C
GND
3V3
C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND
D D
REV 2 01July04
SDRAM GE Healthcare
B Size
Company Restricted
Tue Dec 25 15:55:56 2007 fpga_cpld_flash 5 of 10 5132987SCH D 16 of 23
1 2 3 4 5 6 7 8
GANTRY 3-17
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U27
74LVC_LCX244 DEBUG_IO_A
CN15
1 OE_N<1>
FPGA_DEBUG_OUT<7..0> DEBUG_IO<7..0>
15A7< 7 1 2
0 2 18 0 1 2
A1<1> Y1<1> 6 3 4
1 4 16 1 3 4
A2<1> Y2<1> 5 5 6
2 6 14 2 5 6
A3<1> Y3<1> 4 7 8
3 8 12 3 7 8
A4<1> Y4<1>
A 3 9 9 10 10 A
2 11 11 12 12
19 OE_N<0> 1 13 13 14 14
0 15 15 16 16
4 11 A1<0> Y1<0> 9 4
5 13 A2<0> Y2<0> 7 5
6 15 A3<0> Y3<0> 5 6
7 17 3 7 PIN
A4<0> Y4<0>
STRAIGHT
DUAL_ROW_HEADER
GND
R135 R136 VCC=3V3;GND=GND
1K 1K
0.1W 0.1W
1% 1%
GND GND
U35
74LVC_LCX244
R213
CN16 100 *4
R214
0.1W 33.2 X 8
R215 1
1% OE_N<1> 0.1W
DEBUG_IO<7> 2 1 R216
2 1 1%
INPUT_E 4 4 3 3 INPUT_A 2 A1<1> Y1<1> 18 R229 0
B INPUT_F 6 6 5 5 INPUT_B 4 A2<1> Y2<1> 16 R230 1 B
INPUT_G 8 8 7 7 INPUT_C 6 A3<1> Y3<1> 14 R231 2
INPUT_H 10 10 9 9 INPUT_D 8 A4<1> Y4<1> 12 R232 3
12 12 11 11
14 14 13 13 19 OE_N<0>
16 16 15 15
11 A1<0> Y1<0> 9 R233 4
13 A2<0> Y2<0> 7 R234 5
PIN 15 A3<0> Y3<0> 5 R235 6
STRAIGHT 17 A4<0> Y4<0> 3 R236 7

RIBBON_CABLE_STANDARD FPGA_DEBUG_IN_A<7..0>
15B7<
VCC VCC=3V3;GND=GND
3V3
GND
R218 R220
1K 1K
0.1W 0.1W
1% 1%
C C
R205
100 *4
R206 GND
1% GND
R207
0.1W
R208
3V3
C166
C168
C170
C172
C174
C176
C178
C180
10%
16V
C32
0.1U
10%
C163
16V
0.1U
10%
50V
10000P
GND
GND
D D
REV 2 01July04
DEBUG_IO FOR FCT GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
3-18 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
ALL NOTES SHOULD BE PLACE ON PCB

A A
I(LED)=(3.3-V(FD))/5MA=(3.3-2)/5=240 OHM
ERRS LOOPS REQS EXPCMD DENTG RINGS TEST SG_ERR
3V3 3V3 3V3 3V3 3V3 3V3 3V3 3V3
2
GND
DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS8
HSMY-C190 HSMG-C190 HSMG-C190 HSMG-C190 HSMG-C190 HSMY-C190 HSMG-C190 HSMY-C190
YELLOW GREEN GREEN GREEN GND GREEN YELLOW GREEN YELLOW
1
R147
R149
R153
R156
R159
R160
R162
R151
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
R146
1%
1%
1%
1%
1%
1%
1%
1%
249
249
249
249
249
249
249
249
1K R154
0.1W U29 1K U29
1% 74LVC_LCX244 0.1W 74LVC_LCX244
1%
1 OE_N 19 OE_N
0 2 A1 Y1 18 4 11 A1 Y1 9
1 4 A2 Y2 16 5 13 A2 Y2 7
2 6 A3 Y3 14 6 15 A3 Y3 5
B 3 8 A4 Y4 12 7 17 A4 Y4 3 B
FPGA_LED<7..0>
14C2<
POWER_ON LED
VCC
2
BOOT_FPGA APPL_FPGA CPLD_LOADED CPLD_LOADING DS18
HSMG-C190
3V3 3V3 3V3 3V3 GREEN
2
DS11 DS12 DS13 DS14

C C
1
HSMG-C190 HSMG-C190 HSMG-C190 HSMG-C190
R169
0.1W
GREEN GREEN GREEN GREEN
1%
287
1
R148
R150
R152
R155
I=(5-2)/(287*2)=5MA
0.1W
0.1W
0.1W
0.1W
1%
1%
1%
1%
249
249
249
249
R96
3
0.1W
1%
287
2
1
GND
0
CPLD_LED<3..0>
12A5<
3V3
D D
REV 2 01July04
10%
C101
16V
0.1U
LEDS GE Healthcare
Company Restricted
B Size
GND

1 2 3 4 5 6 7 8
GANTRY 3-19
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
TP1
2B5^ 15C7> FPGA_OFFSET
TP2 TP7 TP8 TP11 TP13 TP16 TP18 TP21

A A
2B5^ 15C7> FPGA_DTRIG
TP3 VCC 24VCC_1 24VCC_2 1V5 12V ISO_VCC
2B5^ 15C7> FPGA_DENBL
TP4
TP9 TP10 TP12 TP14 TP15 TP17 TP19 TP20
2C5^ 15C7> FPGA_EXP_CMD_N
TP5
3V3
B B
2B3^ 15D7< 12C1< FPGA_GD_TRIG_0 GND 24V_GND_1 24V_GND_2
TP6
2B5^ 15C7> FPGA_GPLS2_OUT
DEBUGGING I/F
CN11
3V3 19C6> RS232_COM1_TXD 1

19D2< RS232_COM1_RXD 2
3
PIN
U33
STRAIGHT
C MAX3232C
WIRE_TO_BOARD
C
GND
C105 C106 C107 16 VCC

0.1U 0.1U 0.1U 2 VP
16V 16V 16V 6 VN
10% 10% 10% C108 NOT MOUNTED
0.1U 1 C1P
16V 3 C1M RESERVE
10% C109 4 C2P
0.1U 5 CN12
C2M
GND 16V
FPGA_RS232_COM1_TXD 10% 11 14 RS232_COM1_TXD
15B7> T1IN T1OUT 19C6< RS232_COM2_TXD
FPGA_RS232_COM2_TXD 10 7 RS232_COM2_TXD 19D6> 1
15C7> T2IN T2OUT 19C6> RS232_COM2_RXD
RS232_COM1_RXD 13 12 FPGA_RS232_COM1_RXD 2
19C6< R1IN R1OUT 15B7< 19D2<
RS232_COM2_RXD 8 9 FPGA_RS232_COM2_RXD 3
19D6< R2IN R2OUT 15C7<
GND 15
PIN
GND STRAIGHT
WIRE_TO_BOARD
GND
D D
REV 2 01July04
RS232 INTERFACE & TEST POINT GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
3-20 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
3V3 3V3
3V3
R177
R175 U31 4.99K
4.99K DS1631U 0.1W
0.1W R700 1%
1% 8 VDD SDA 1 TEM1_SDA 15A2<
TEM1_SCL 51.1
15A2< 2 SCL TOUT 3
0.1W
7 1%
A0
6 A1
5 A2 GND 4
B B
GND GND
U31 SHOULD BE PLACED NEAR U19 (LM2805)

3V3
3V3
3V3
C R178
C
R176 U32 4.99K
4.99K DS1631U 0.1W
0.1W R701 1%
1% 8 VDD SDA 1
2 3 51.1
SCL TOUT
0.1W
7 1% 3V3
A0
6 A1
5 A2 GND 4
C104 C103
0.1U 0.1U
16V 16V
10% 10%
GND GND
THE SENSOR SHOULD BE PLACED NEAR VR1(3V3) GND
D D
REV 2 01July04
TEMPEARTURE SENSOR
GE Healthcare
Company Restricted
B Size

1 2 3 4 5 6 7 8
GANTRY 3-21
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
FPGA/CPLD JTAG
3V3
A A
0.12W
R186
10K
5%
S3
CHS_04TB 3V3
1 I1 O1 8 0
GND R133 R134
2 I2 O2 7 1 10K 10K
R281
10K 0.1W 0.1W 3V3 3V3
3 I3 O3 6 2 0.1W 1% 1%
1% CN13 R280
4 I4 O4 5 3 1K
0.1W
12B1< 13C3< JTAG_TCK 1 1 2 2 1%
OFF ON 13B7> FPGA_TDO 3 3 4 4
GND 12B1< 13C3<
JTAG_TMS 5 5 6 6
7 7 8 8
FPGA_SW3<3..0>
14C7< 13C3< FPGA_TDI 9 9 10 10
PIN
B STRAIGHT
GND B
SELECT THE FIRMWARE VERSION TRUTH TABLE OF SW6: DUAL_ROW_HEADER_BREAK
S4
BIT4 BIT3 BIT2 BIT1 SYSTEM NAME
CHS_04TB
OFF OFF OFF ON MDAS BE/1/2 GDAS BE1/2
OFF OFF ON OFF TBD(RESERVE)
FPGA_TDO 1 I1 O1 8JTAG_TDO
12B1> CPLD_TDO 2 I2 O2 7
3 I3 O3 6 CPLD_TDI 12B1<
4 I4 O4 5
NOTE FOR BSCAN: BIT1 IS OFF , BIT2 & BIT3 ARE ON

FOR CODELAB:BIT1 IS ON, BIT2 & 3 ARE OFF
C C
PIN 3V3
STRAIGHT
SINGLE_ROW_HEADER_BREAK
R188 U34 3V3
4.99K 74LVC-LCX14
0.1W
1%
2
1
R190 C40
J4
3 A B 4 FPGA_USER_PB 14B2>
0.1U
10K 16V
NOTE:ONLY FOR DEBUGGING C112 10%
0.1W
0.1U VCC=3V3;GND=GND
1% 16V
INSTEAD OF THE PUSH BUTTON
10%
GND
GND
GND
D D
REV 2 01July04
JTAG & SWITCHES GE Healthcare
Company Restricted
B Size
Thu Jun 14 10:57:51 2007 fpga_cpld_flash 10 of 10 5132987SCH E 21 of 23

1 2 3 4 5 6 7 8
3-22 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
3V3
C114 C117 C120 C123 C126 C129 C132 C135 C138 C140 C142 C144 C146 C148 C150 C152
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND
1V5
B B
C115 C118 C121 C124 C127 C130 C133 C136 C139 C141 C143 C145 C147 C149 C151 C153
10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N 10N
50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GND
1V5
MH1 MH5
MH5_00 MH5_00_M4WASHER
C116 C119 C122 C125 C128 C131 C134 C137
C C
1
4.7U 4.7U 4.7U 4.7U 4.7U 4.7U 4.7U 4.7U
16V 16V 16V 16V 16V 16V 16V 16V
+-20% +-20% +-20% +-20% +-20% +-20% +-20% +-20% MH6
MH2 MH5_00_M4WASHER
MH5_00
1
1
GND CERAMIC
MH7
MH3 MH5_00_M4WASHER
MH5_00
1
1
MH8
MH5_00_M4WASHER
1
MH4
MH5_00
1
THESE MOUNTING HOLE ARE EMPTY MOUNTING HOLE
D D
REV 2 01July04
FPGA DECOUPLING CAPS & MOUNTING HOLE GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:21:03 2007 misc 1 of 2 5132987SCH E 22 of 23

1 2 3 4 5 6 7 8
GANTRY 3-23
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
U15 U15 U21

74LVC-LCX14 74LVC-LCX14 74LVC-LCX14
11 A B 10 13 A B 12 13 A B 12
VCC=3V3;GND=GND VCC=3V3;GND=GND VCC=3V3;GND=GND
GND GND GND
U30
U30 U30 U30
74LVC-LCX14
13 A B 12
5 A B 6 9 A B 8 11 A B 10
B B
VCC=3V3;GND=GND
GND GND GND

GND
U34 U34 U34

5 A B 6 9 A B 8 1 A B 2
GND GND
GND
C U40
C
U40 U40
74VHC_AHC14 U40
74VHC_AHC14 74VHC_AHC14
74VHC_AHC14
5 A B 6
9 A B 8 11 A B 10
13 A B 12
VCC=ISO_VCC;GND=24V_GND_1 VCC=ISO_VCC;GND=24V_GND_1
24V_GND_1 24V_GND_1 24V_GND_1 24V_GND_1
D D
REV 2 01July04
SPARE COMPONENTS & GATES GE Healthcare
Company Restricted
B Size
Wed Jun 13 11:21:04 2007 misc 2 of 2 5132987SCH E 23 of 23

1 2 3 4 5 6 7 8
3-24 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
SECTION 4 - DTB BD ASSY

4-1 DTB DB ASSY (5270966)
1 2 3 4
REVISION ECR/ECO DATA SIGN OFF

PAGE NAME
A
1 DEC-2008 LI GuoWang A
April_2009
SHEET 2 TOP VIEW
2 Li Guowang
3 Dec 2009 Li Guowang SHEET 3 MPC8245 OF TOP VIEW
SHEET 4 FPGA OF TOP VIEW

SHEET 5 POWER
SHEET 6 MPC8245_SYS
SHEET 7 MPC8245_CONFIG
SHEET 8 MPC8245_MEM
SHEET 9 BUS_BUFFERS
SHEET 10 MPC8245_PCI
B
SHEET 11 MPC8245_PWR B
Version 3 update SHEET 12 SDRAM

SHEET 13 FLASH
SHEET 14 FET_PHY
SHEET 15 UART_PHY
CPU core voltage change from 1.9V to 1.94V
SHEET 16 FPGA_CONFIG
SHEET 17 FPGA 1 OF 3
SHEET 20 LEDS
C SHEET 21 TAXI C
SHEET 22 SPARE PARTS
Title
D D
DTB
Size Number Revision
A4 5270966 REV:3
Date: 2008-12-10 Sheet 1 of 22
File: D:\DESIGN-TASK\..\1.SchDoc Drawn By:
1 2 3 4
GANTRY 4-1
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
B B
U_MPC8245 OF TOP VIEW U_FPGA OF TOP VIEW

3.SchDoc 4.SchDoc
BD[0..15] BD[0..15]
BA[22..0] BA[22..0]
RCS2_N RCS2_N
U_TAXI
RCS3_N RCS3_N
21.SchDoc
BFOE_N BFOE_N
BWE_N BWE_N TXEN_N TXEN_N
AS_N AS_N CYSC_D CYSC_D

AS_N_CLK AS_N_CLK CARDET CARDET
B_PORST_N B_PORST_N TXDATA[7..0] TXDATA[7..0]
WD_RST_N WD_RST_N RXDATA[7..0] RXDATA[7..0]
XRAY_ON_IN XRAY_ON_IN TCMD[3..0] TCMD[3..0]
ERROR_A-B_INT ERROR_A-B_INT LFI_N LFI_N
DSREQ_AB_INT DSREQ_AB_INT RXCLK RXCLK
SIMU_XRAY_ON_OUT SIMU_XRAY_ON_OUT VLTN VLTN
RESET_N_BY_JIG RESET_N_BY_JIG RXSC_D RXSC_D
SAFETY_LOOP_OPEN_N SAFETY_LOOP_OPEN_N RCMD[3..0] RCMD[3..0]
CLK_33M CLK_33M TAXI_CLK_22M TAXI_CLK_22M
TXCLK TXCLK
NAND_CLE NAND_CLE
NAND_ALE NAND_ALE
B_PORST_N
NAND_CE_N NAND_CE_N
NAND_RE_N NAND_RE_N
NAND_WE_N NAND_WE_N
C NAND_R/B# NAND_R/B# C
RCS1_N RCS1_N
DTB_INT DTB_INT
U_POWER
5.SchDoc
D D
TOP VIEW
Title
DTB
A3 5270966 REV :3
Date: 2008-12-10 Sheet 2 of 22
Approved Document - 5270966SCH_r3.pdf Page 3 of 23 File: D:\DESIGN-TASK\..\2.SchDoc Drawn By:
1 2 3 4 5 6 7 8
4-2 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U_UART_PHY
15.SchDoc
SAFETY_LOOP_OPEN_N
2[3C] SAFETY_LOOP_OPEN_N SAFETY_LOOP_OPEN_N
SIMU_XRAY_ON_OUT
2[3C] SIMU_XRAY_ON_OUT SIMU_XRAY_ON_OUT
RESET_N_BY_JIG
2[3C] RESET_N_BY_JIG RESET_N_BY_JTG
XRAY_ON_IN
2[3C] XRAY_ON_IN XRAY_ON_IN
B_PORST_N SIN1
2[3B] B_PORST_N
CLK_33M SOUT1
2[3C] CLK_33M
A TGPL_RST_N A
U_MPC8245_SYS
6.SchDoc
ERROR_A-B_INT
2[3C] ERROR_A-B_INT ERROR_A-B_INTTGPL_RST_N
DTB_INT
2[3C] DTB_INT DTB_INT CLK_33M
DSREQ_AB_INT
2[3C] DSREQ_AB_INT DSREQ_AB_INT PCI_SYNC U_MPC8245_PCI
PCICLK0 10.SchDoc
WD_RST_N PCI_SYNC SOUT1
2[3C] WD_RST_N WD_RST_N IRQ~0

SIN1
PORST_N
PCI_C/BE_N[3..0]
PCI_GNT0_N
MAA[2..1]
PCI_REQ0_N
QACK_N
PCI_FRAME
PMAA[2..0]
PCI_DEVSEL
MCP_N
PCI_IRDY
PLLCFG[4..0]
PCI_TRDY
PCI_STOP
PCI_PERR
PCI_SERR
U_POR CONFIGRATION PCI_PAR
7.SchDoc PCI_AD[31..0]
PLLCFG[4..0]
MCP_N
PMAA[2..0]
QACK_N
MAA[2..1] U_FET_PHY
14.SchDoc
B CKE B
PCI_AD[31..0]
FOE_N
PCI_PAR
A[22..0]
PCI_SERR
D[0..63]
PCI_PERR
RCS0_N
PCI_STOP
PCI_TRDY
PCI_IRDY
PCI_DEVSEL
PCI_FRAME
PCI_REQ0_N
PCI_GNT0_N
PCI_C/BE_N[3..0]
U_MPC8245_MEM U_SDRAM
PCICLK0
8.SchDoc 12.SchDoc
D[0..63] D[0..63] IRQ~0
AS_N
2[3B] AS_N AS_N A[22..0] A[22..0] PORST_N
AS_N_CLK
2[3B] AS_N_CLK AS_N_CLK CKE CKE
DQM[7..0] DQM[7..0]
FOE_N SDCS0_N SDCS0_N
SDCAS_N SDCAS_N
SDRAS_N SDRAS_N
WE_N WE_N
RCS3_N SDCLK[3..0] SDCLK[3..0]
RCS2_N
RCS1_N
RCS0_N
U_BUS_BUFFERS
C 9.SchDoc C
D[0..63]
U_MPC8245_PWR
A[22..0] PORST_N
11.SchDoc
WE_N B_PORST_N
RCS0_N
RCS1_N
2[3C] RCS1_N RCS1_N
RCS2_N
2[3B] RCS2_N RCS2_N BWE_N
RCS3_N
2[3B] RCS3_N RCS3_N BFOE_N
BA[22..0]
FOE_N BD[0..15]
U_FLASH
13.SchDoc
RCS0_N BD[0..15]
BA[22..0]
NAND_R/B# BFOE_N
2[3C] NAND_R/B# NAND_R/B#
NAND_RE_N BWE_N
2[3C] NAND_RE_N NAND_RE_N
NAND_WE_N
2[3C] NAND_WE_N NAND_WE_N B_PORST_N
NAND_ALE
2[3C] NAND_ALE NAND_ALE
NAND_CLE
2[3C] NAND_CLE NAND_CLE
NAND_CE_N
2[3C] NAND_CE_N NAND_CE_N
BD[0..15]
2[3B] BD[0..15]
D BA[22..0] D
2[3B] BA[22..0]
BFOE_N
2[3B] BFOE_N
BWE_N
MPC8245 OF TOP VIEW
2[3B] BWE_N
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 3 of 22
1 2 3 4 5 6 7 8
GANTRY 4-3
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U_LED_BUFFERS U_FPGA 1 OF 3
A 20.SchDoc 17.SchDoc A
TXEN_N
FPGA_LED[23..0] FPGA_LED[23..0] TXEN_N TXEN_N 2[5B]
CYSC_D
CYSC_D CYSC_D 2[5B]
CARDET
CARDET CARDET 2[5B]
TXDATA[7..0]
TXDATA[7..0] TXDATA[7..0] 2[5B]
RXDATA[7..0]
RXDATA[7..0] RXDATA[7..0] 2[5C]
TCMD[3..0]
TCMD[3..0] TCMD[3..0] 2[5C]
LFI_N
LFI_N LFI_N 2[5C]
RXCLK
RXCLK RXCLK 2[5C]
VLTN
FPGA_ASDO VLTN VLTN 2[5C]
RXSC_D
FPGA_CS_N RXSC_D RXSC_D 2[5C]
RCMD[3..0]
RCMD[3..0] RCMD[3..0] 2[5C]
TAXI_CLK_22M
INIT_DONE TAXI_CLK_22M TAXI_CLK_22M 2[5C]
TXCLK
TXCLK TXCLK 2[5C]
U_FPGA 2 OF 3
18.SchDoc
ERROR_A-B_INT
ERROR_A-B_INT ERROR_A-B_INT 2[4C]
DTB_INT
DTB_INT DTB_INT 2[4C]
DSREQ_AB_INT
DSREQ_AB_INT DSREQ_AB_INT 2[4C]
WD_RST_N
WD_RST_N WD_RST_N 2[4C]
ERROR_OUT[2..0]
BA[22..0]
DISWDT_N BA[22..0] BA[22..0] 2[4B]
BD[0..15]
FEEDWDT_N BD[0..15] BD[0..15] 2[4B]
B B_PORST_N B
ENWDT_N B_PORST_N B_PORST_N 2[4B]
AS_N
AS_N AS_N 2[4B]
BFOE_N
BFOE_N BFOE_N 2[4B]
BWE_N
BWE_N BWE_N 2[4B]
RCS3_N
RCS3_N RCS3_N 2[4B]
RCS2_N
SIMU_XRAY_ON_OUT
ERROR_OUT0 SIMU_XRAY_ON_OUT 2[4C]
RESET_N_BY_JIG
ERROR_OUT1 RESET_N_BY_JIG 2[4C]
SAFETY_LOOP_OPEN_N
SAFETY_LOOP_OPEN_N SAFETY_LOOP_OPEN_N 2[4C]
XRAY_ON_IN
XRAY_ON_IN XRAY_ON_IN 2[4C]
NAND_CLE
NAND_CLE NAND_CLE 2[4C]
NAND_ALE
NAND_ALE NAND_ALE 2[4C]
NAND_RE_N
NAND_RE_N NAND_RE_N 2[4C]
NAND_WE_N
NAND_WE_N NAND_WE_N 2[4C]
NAND_CE_N
NAND_CE_N NAND_CE_N 2[4C]
NAND_R/B#
NAND_R/B# NAND_R/B# 2[4C]
RCS1_N
RCS1_N RCS1_N 2[4C]
U_FPGA_CONFIG
16.SchDoc
ENWDT_N BA[20..0]
FEEDWDT_N BD[0..15]
DISWDT_N BFOE_N
C BWE_N C
RCS2_N
INIT_DONE RCS2_N RCS2_N 2[4B]
FPGA_STATUS_N
FPGA_CONF_DONE
FPGA_DCLK
FPGA_DATA0
FPGA_CONFIG_N
U_FPGA 3 OF 3
19.SchDoc
CLK_33M
FPGA_CONFIG_N CLK_33M CLK_33M 2[4C]
AS_N_CLK
FPGA_DATA0 AS_N_CLK AS_N_CLK 2[4B]
FPGA_DCLK
FPGA_CONF_DONE
FPGA_STATUS_N
FPGA_CS_N
FPGA_ASDO
D D
FPGA OF TOP VIEW
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 4 of 22
1 2 3 4 5 6 7 8
4-4 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC P2 LT1764 3V3

2 4
A IN OUT A
C121 C125 R174 C129 C133
Vo = 1.21V * (1+1.74K/1K) = 3.32V
GND
22u 104 1 5 1.74K 104 22u
10V 16V SHDN SENSE 0.1W 16V 10V
10% 10% 1% 10% 10%
3
R175
1K
0.1W
1%
VCC P3 LT1764 VDD25

2
IN OUT
4 Vo = 1.21V * (1+1.07K/1K) = 2.50V
C128 C130
C122 104 R176 104 C134 C137 C138
GND
22u 16V 1 5 1.07K 16V 104 104
SHDN SENSE 10% 22u
10V 10% 0.1W 10V 16V 16V
10% 1% 10% 10% 10%
3
R177
1K
0.1W
B 1% B
24V
VCC P4 LT1764 1V9_CORE

2 4 Vo = 1.21V * (1+0.604K/1K) = 1.94V DS25
IN OUT HSMG-C190
C123 C126 R178 C131 C135 24V
GND
22u 104 1 5 604 104 22u
10V 16V SHDN SENSE 0.1W 16V 10V R192
10% 10% 1% 10% 10%
511
3
0.1W
R179 1%
1K
0.1W R193
1%
511
0.1W
1%
R194
511
VCC P5 LT1764 1V5 0.1W
2 4 1%
IN OUT Vo = 1.21V(1+0.237K/1K) = 1.497V
C C124 C127 R180 C132 C136 R195 C
GND
22u 104 1 5 237 104 22u 511
10V 16V SHDN SENSE 0.1W 16V 10V 0.1W
10% 10% 1% 10% 10%
1%
3
R181 R196
1K 511
0.1W 0.1W
1%
1%
R197
511
0.1W
FB5 1%
BLM31P500S
24V 3V3 VDD25 1V9_CORE 1V5 TP6
J1 F1 24V FB10 P1 FB6 VCC TP2 TP
2 6 TP3 TP4 TP5
24V POWER ON
1 VIN VOUT TP1
2 TP
1.1A/30V C110 BLM31P500S C112 C114 5 C95 BLM31P500S C116 C118 TP TP TP
SENSE TP
Header 2 220u 220u 104 330u 104 100u
GND
GND
50V 50V 50V 16V 16V 16V

20% 20% 20% 3 4 10% 10% 10%
INHIBIT ADJ
VCC TP9 TP10 TP11
R69 3V3
TP TP TP
1
7
21.0K
0.1W TP7
PTN78060W 1%
TP
D
TP8
TP
POWER D
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 5 of 22
1 2 3 4 5 6 7 8
GANTRY 4-5
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
3V3
3V3
R30 R31 R32
R26 R27 R28 R29 10K 1K 10K
A A
10K 10K 10K 10K 0.1W 0.1W 0.1W
R11 R13 R14 R18 R20 0.1W 0.1W 0.1W 0.1W 1% 1% 1%
10K 10K 10K 10K 10K 1% 1% 1% 1%
0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1%
U1D J6
IRQ~0 C19 J2 COP_TDO
14[2C] IRQ~0 IRQ0/SINT DA15 1 2
B21 F1 COP_TDI COP_TRST~
IRQ1/SCLK DA14 3 4
DTB_INT AC22 AF19
18[6B] DTB_INT IRQ2/SRST DA13 5 6

DSREQ_AB_INT AE24 AF17 COP_TCK C_SDMA14
18[6B] DSREQ_AB_INT IRQ3/SFRAME~ DA12 7 8
ERROR_A-B_INT A23 AD26 COP_TMS
18[6B] ERROR_A-B_INT IRQ4/LINT~ DA11 9 10
COP_SRST~
SYSTEM COP_HRST~
11 12
RTL8139_INT ------> IRQ0 CPU_HRST~ A19
HRST~/CPU~ DA2
C25
13
15
14
16
㄀14䩜࠾ᮁ
ERROR_A-B_INT ------>IRQ1 A20 B15
HRST~/CTRL~ CKO/DA1
LAST_VIEW_INT ------>IRQ2 F2 QACK_N Header 8X2
1K QACK~/DA0 QACK_N 7[3C]
DSREQ_A_INT ------>IRQ3 0.1W
DSREQ_B_INT ------>IRQ4 R15 1% D16 A16 10K
NMI MIV~
VLTN-----> ? A18 0.1W
SMI~ 1%
R16 AF2 MAA0 R25
3V3 MAA0 3V3
10K AF1 MAA1
MAA1
0.1W Y2 AE1 MAA2
R12 1% RTC MAA2
AD21 MAA[2..1] U3B
OSC_IN MAA[2..1] 7[3C]
4K7 AD18 PMAA0 COP_HRST~ 4
PMAA0
0.1W PLLCFG0 A22 AF18 PMAA1 6 CPU_HRST~
PLLCFG0/DA10 PMAA1
1% PLLCFG1 B19 AE19 PMAA2 PORST_N 5
PLLCFG1/DA9 PMAA2
PLLCFG2 A21 PMAA[2..0]
PLLCFG2/DA8 PMAA[2..0] 7[3B] SN74LV08PW
PLLCFG3 B18
PLLCFG3/DA7
PLLCFG4 B17 A17 MCP_N U3C
B PLLCFG4/DA6 MCP~ MCP_N 7[3A] B
PLLCFG[4..0] PORST_N 9
7[3A] PLLCFG[4..0]
BCOP_TRST~ AE23 8 BCOP_TRST~
TRST~
COP_TMS AE22 COP_TRST~ 10
TMS
COP_TCK AF22
TCK SN74LV08PW
COP_TDI AF23 AE20
TDI SDA
COP_TDO AC21 AF21
TDO SCL C52
R17 AD22
3V3 TEST0~
4K7 3V3 GND
0.1W MPC8245 R22 R24
104
1% 10K 10K 16V
0.1W 0.1W 10%
1% 1%
3V3
R229 PCICLK0
PCICLK0 14[2C]
3V3 33.2
0.1W
C50 U2 1%
3V3 X1 104 6 2
16V VDD CLK2 R58
8 1 10% 4 3 CLK_33M
VCC NC GND CLK1 CLK_33M 19[7B]
C49 5 33.2
104 CLK3
7 0.1W
16V CLK4
10% 4 5 R57 1 8 1%
GND OUT REF CLKOUT
33.2 R228
33MHz 0.1W IDT2305 PCI_SYNC
C 1% PCI_SYNC 10[4C] C
33.2
3V3 0.1W
1%
R19
10K
0.1W
1%
SW1
6 U3A
5 1
4 3
WD_RST_N 2
G3B15
SN74LV08PW
3V3
3V3 U4
18[6B] WD_RST_N
4
ADM811
2 PORST_N
RST PORST_N 14[5A], 9[2B]
VCC
R183
U3D
10K 12 R23
GND
0.1W 11 R21 3 100K

1% MR 0.1W
TGPL_RST_N 13
15[7C] TGPL_RST_N
SN74LV08PW
100
0.1W
C51
104
1% NOTE : TO FPGA & TAXI
1
1% 16V
10%
D
MPC8245_SYS D
Title
DTB
A3 5270966 REV :3
Date: 2008-12-10 Sheet 6 of 22
1 2 3 4 5 6 7 8
4-6 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
CONFIG
SIGNAL NAME CFG_Resistance NOT MOUNTED
R140 R142 R147 R150 R154 R158 R162 R164 R168 R171
A 10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K 10K
0.1W 0.1W
D32, FOE R139, R145 R139, R145 A
1% 1% 1% 1% 1% 1% 1% 1% 1% 1%
MAA1 R148 R148
PLLCFG[4..0] MAA2 R152
6[2B] PLLCFG[4..0]
PLLCFG0
PLLCFG1
PLLCFG2
MCP_N, CKE R159,R163 R159,R163
PLLCFG3 PMAA0,PMAA1 R165, R169 R165

PLLCFG4
6[5B] MCP_N
MCP_N
CKE
PMAA2 R172 R172
12[3D], 8[6B] CKE
PMAA0 QACK_N R157 R157
PMAA1
PMAA[2..0]
PMAA2 RCS0_N R161 R161
6[5B] PMAA[2..0]
SDMA/AR1 R166
R138 R143 R146 R151 R155 R159 R163 R165 R169 R172
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
SDMA/AR0 R170
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1% 1% 1% 1%
SPEED
B CPU CLOCK R138 R143 R146 R151 R155 B
300MHz MOUNTED MOUNTED MOUNTED MOUNTED NOT

333MHz NOT MOUNTED NOT MOUNTED NOT
3V3 USE 333MHz for DTB

R141 R144 R149 R153 R156 R160 R167

10K 10K 10K 10K 10K 10K 10K
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1%
D[0..63]
12[3D], 8[1D], 9[6A] D[0..63]
D32
8[6B], 9[2B] FOE_N
MAA[2..1] FOE_N
6[5B] MAA[2..1]
MAA1
MAA2
QACK_N
6[5B] QACK_N
RCS0_N
13[3B], 8[6B], 9[2A] RCS0_N
A1
A0
A[22..0]
12[3A], 8[6A], 9[2B] A[22..0]
C R139 R145 R148 R152 R157 R161 R166 R170 C

1K 1K 1K 1K 1K 1K 1K 1K
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1% 1%
See detail on UM page 118
D
MPC8245_CONFIG D
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 7 of 22
1 2 3 4 5 6 7 8
GANTRY 4-7
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U1A
C-D0 AC17 AB1 C-DQM0
MDH0 DQM0
C-D1 AF16 AB2 C-DQM1
MDH1 MEMORY DQM1
C-D2 AE16 K3 C-DQM2
MDH2 DQM2 A[22..0]
C-D3 AE14 K2 C-DQM3 RP8 A[22..0] 12[3A], 7[3C], 9[2B]
MDH3 DQM3
C-D4 AF14 AC1 C-DQM4 C-PAR5/AR14 1 8 A14
A MDH4 DQM4 A
C-D5 AC13 AC2 C-DQM5 C-PAR4/AR15 2 7 A15 RP19
MDH5 DQM5
C-D6 AE12 K1 C-DQM6 C-PAR0/AR19 3 6 A19 C-SDCAS~ 1 8 SDCAS_N
MDH6 DQM6 SDCAS_N 12[3D]
C-D7 AE11 J1 C-DQM7 C-PAR1/AR18 4 5 A18 C-SDRAS~ 2 7 SDRAS_N
MDH7 DQM7 SDRAS_N 12[3D]
C-D8 AE10 C-DQM5 3 6 DQM5
MDH8 33R
C-D9 AE9 Y4 C-SDCS0~ C-DQM4 4 5 DQM4 DQM[7..0]
MDH9 CS~0 0.063W DQM[7..0] 12[3B]
C-D10 AE8 AA3
MDH10 CS~1 5% 33R
C-D11 AC7 AA4
MDH11 CS~2 RP9 0.063W
C-D12 AE7 AC4
MDH12 CS~3 C-SDMA/AR0 1 8 A0 5%

C-D13 AE6 M2
MDH13 CS~4 C-SDMA/AR1 2 7 A1 RP20
C-D14 AF5 L2
MDH14 CS~5 C-SDMA/AR2 3 6 A2 C-DQM1 1 8 DQM1
C-D15 AC5 M1
C-D16 E4 L1
MDH16 CS~7 C-SDCS0~ 3 6 SDCS0_N
C-D17 A2 33R SDCS0_N 12[3D]
MDH17 C-WE~ 4 5 WE_N
C-D18 B3 0.063W WE_N 12[3D], 9[2B]
MDH18
C-D19 D4 P2 C-SDBA0/AR11 5% 33R
MDH19 SDBA0
C-D20 B4 P1 C-SDBA1/AR20 0.063W
MDH20 SDBA1 RP10
C-D21 B5 D14 C-SDMA14 5%
MDH21 SDMA14/CHKSTOP_IN C-SDMA/AR6 1 8 A6
C-D22 D6 B14 C-SDMA13/AR23 RP21
MDH22 SDMA13/TBEN C-SDMA/AR5 2 7 A5
C-D23 C6 B16 C-SDMA12/AR22 C-SDBA1/AR20 1 8 A20
MDH23 SDMA12/SRESET~ C-SDMA/AR4 3 6 A4
C-D24 B7 N1 C-SDMA11/AR21 C-RCS0_N 2 7 RCS0_N RCS0_N 13[3B], 7[3C], 9[2A]
MDH24 SDMA11 C-SDMA/AR7 4 5 A7
C-D25 C9 R1 C-SDMA/AR10 C-SDMA11/AR21 3 6 A21
MDH25 SDMA10
C-D26 A9 R2 C-SDMA/AR9 33R C-RCS1_N 4 5 RCS1_N
MDH26 SDMA9 RCS1_N 18[6B], 9[2A]
C-D27 B10 T1 C-SDMA/AR8 0.063W
MDH27 SDMA8 33R
C-D28 A11 T2 C-SDMA/AR7 5%
MDH28 SDMA7 0.063W
C-D29 A13 U4 C-SDMA/AR6 RP11
MDH29 SDMA6 5%
C-D30 B13 U2 C-SDMA/AR5 C-SDMA/AR8 1 8 A8
MDH30 SDMA5 RP22
C-D31 A15 U1 C-SDMA/AR4 C-SDMA/AR9 2 7 A9
MDH31 SDMA4 C-DQM3 1 8 DQM3
C-D32 AD17 V1 C-SDMA/AR3 C-SDMA/AR10 3 6 A10
B MDL0 SDMA3 C-DQM6 2 7 DQM6 B
C-D33 AE17 V3 C-SDMA/AR2 C-SDBA0/AR11 4 5 A11
MDL1 SDMA2 C-DQM2 3 6 DQM2
C-D34 AE15 W1 C-SDMA/AR1
MDL2 SDMA1 33R C-DQM7 4 5 DQM7
C-D35 AF15 W2 C-SDMA/AR0
MDL3 SDMA0 0.063W
C-D36 AC14 33R
MDL4 5%
C-D37 AE13 B20 C-DRDY~ 0.063W
MDL5 DRDY~
C-D38 AF13 Y1 C-AS~ RP12 5%
MDL6 AS~
C-D39 AF12 H1 C-FOE~ 1 8 RP23
MDL7 FOE~
C-D40 AF11 N4 C-RCS0_N C-PAR6/AR13 2 7 A13 C-CKE 1 8 CKE
MDL8 RCS~0 CKE 12[3D], 7[3A]
C-D41 AF10 N2 C-RCS1_N 3 6 C-FOE~ 2 7 FOE_N
MDL9 RCS~1 FOE_N 7[3C], 9[2B]
C-D42 AF9 AF20 C-RCS2_N C-PAR7/AR12 4 5 A12 C-SDCLK2 3 6 SDCLK2
MDL10 TRIG_IN/RCS~2
C-D43 AD8 AC18 C-RCS3_N C-SDCLK1 4 5 SDCLK1

MDL11 TRIG_OUT/RCS~3 33R
C-D44 AF8 AD2 C-SDCAS~
MDL12 SDCAS~ 0.063W 33R
C-D45 AF7 AD1 C-SDRAS~
MDL13 SDRAS~ 5% 0.063W
C-D46 AF6 AA1 C-WE~
MDL14 WE~ 5%
C-D47 AE5 H2 C-CKE RP13
MDL15 CKE RP24
C-D48 B1 C-SDMA13/AR23 1 8
MDL16 C-SDCLK3 1 8 SDCLK3
C-D49 A1 AF3 C-PAR0/AR19 2 7
MDL17 PAR0 C-SDCLK0 2 7 SDCLK0
C-D50 A3 AE3 C-PAR1/AR18 C-SDMA14 3 6 SDMA14
MDL18 PAR1 C-PAR2/AR17 3 6 A17 SDCLK[3..0]
C-D51 A4 G4 C-PAR2/AR17 C-SDMA12/AR22 4 5 A22 SDCLK[3..0] 12[3B]
MDL19 PAR2 C-PAR3/AR16 4 5 A16
C-D52 A5 E2 C-PAR3/AR16
MDL20 PAR3 33R
C-D53 A6 AE4 C-PAR4/AR15 33R
MDL21 PAR4 0.063W
C-D54 A7 AF4 C-PAR5/AR14 0.063W
MDL22 PAR5 5%
C-D55 D7 D2 C-PAR6/AR13 5%
MDL23 PAR6
C-D56 A8 C2 C-PAR7/AR12 RP25
MDL24 PAR7
C-D57 B8 1 8
MDL25
C-D58 A10 D1 C-SDCLK0 2 7
MDL26 SDRAM_CLK0
C-D59 D10 G1 C-SDCLK1 C-RCS2_N 3 6 RCS2_N
MDL27 SDRAM_CLK1 RCS2_N 16[2B], 18[6B], 9[2B]
C C-D60 A12 G2 C-SDCLK2 C-RCS3_N 4 5 RCS3_N C
MDL28 SDRAM_CLK2 RCS3_N 18[6B], 9[2B]
C-D61 B11 E1 C-SDCLK3
MDL29 SDRAM_CLK3 33R 3V3
C-D62 B12 C1 R1 100
MDL30 SDRAM_SYNC_OUT 0.063W
C-D63 A14
MDL31 SDRAM_SYNC_IN
H3
5% R2 NOT MOUNTED 10K
33.2 0.063W
MPC8245 R2 0.1W AS_N RP30 5%
C-AS~ RCS2_N 1 8
AS_N 18[6B]
SDRAM Clock Trace must be same 1% RCS3_N
RCS0_N
2
3
7
6
33.2 RCS1_N 4 5
R78 0.1W AS_N_CLK
AS_N_CLK 19[7B]
1% 10K
0.1W
C-DRDY~ R3 1%
10K
0.1W
C-AS~ R4 1%
C-D10
C-D11
C-D12
C-D13
C-D14
C-D15
C-D16
C-D17
C-D18
C-D19
C-D20
C-D21
C-D22
C-D23
C-D24
C-D25
C-D26
C-D27
C-D28
C-D29
C-D30
C-D31
C-D32
C-D33
C-D34
C-D35
C-D36
C-D37
C-D38
C-D39
C-D40
C-D41
C-D42
C-D43
C-D44
C-D45
C-D46
C-D47
C-D48
C-D49
C-D50
C-D51
C-D52
C-D53
C-D54
C-D55
C-D56
C-D57
C-D58
C-D59
C-D60
C-D61
C-D62
C-D63
10K
C-D0
C-D1
C-D2
C-D3
C-D4
C-D5
C-D6
C-D7
C-D8
C-D9
0.1W
C-FOE~ R5 1%
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
10K
0.1W
RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP14 RP15 RP16 RP17 RP18 RP26 RP27 RP28 RP29 R6 1%
C-WE~
33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R 33R
0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
D
MPC8245_MEM D
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Title
DTB
D[0..63]
D[0..63] 12[3D], 7[3C], 9[6A]
A3 5270966 REV :3
Date: 2008-12-10 Sheet 8 of 23
1 2 3 4 5 6 7 8
4-8 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
BD[0..15] U7 D[0..63]
13[6A], 16[2C], 18[6C] BD[0..15] D[0..63] 12[3D], 7[3C], 8[1D]
BD0 47 2 D0
A0 B0
BD1 46 3 D1
A1 B1
BD2 44 5 D2
A2 B2
BD3 43 6 D3
A3 B3
BD4 41 8 D4
A4 B4
C63 BD5 40 9 D5
A5 B5
A BD6 38 11 D6 A
3V3 A6 B6
BD7 37 12 D7
104 A7 B7
BWE_N 1
16V T/R1
10% 48
OE1
BD8 36 13 D8
A8 B8
U6A BD9 35 14 D9
A9 B9
RCS0_N 1 BD10 33 16 D10
13[3B], 7[3C], 8[6B] RCS0_N A10 B10
3 BD11 32 17 D11
A11 B11
RCS1_N 2 BD12 30 19 D12
18[6B], 8[6B] RCS1_N A12 B12
BD13 29 20 D13
SN74LV08PW A13 B13
BD14 27 22 D14
A14 B14
U6C BD15 26 23 D15
33.2 A15 B15
9 0.1W BWE_N 24
T/R2
8 R98 1% 25 4
OE2 GND
10 3V3 10
7
GND
15 Integrated 30 ohm termination resistors
SN74LV08PW VCC GND
C60 C61 C62 C64 18
VCC GND
21 to reduce line noise
U6B 31 28
VCC GND
RCS2_N 4 104 104 104 104 42 34
16[2B], 18[6B], 8[6C] RCS2_N 16V 16V 16V 16V VCC GND
6 10% 10% 10% 10% 39
GND
RCS3_N 5 45
18[6B], 8[6C] RCS3_N GND
SN74LV08PW 74ALVC162245A
A[22..0] U9
12[3A], 7[3C], 8[6A] A[22..0]
A0 47 2 BA0
B 1A0 1Y0 B
A1 46 3 BA1
1A1 1Y1
A2 44 5 BA2
1K 1A2 1Y2
0.1W A3 43 6 BA3
1A3 1Y3
R48 1% 1
1OE
A20 41 8 BA20
2A0 2Y0
A21 40 9 BA21
2A1 2Y1
A22 38 11 BA22
1K 2A2 2Y2
0.1W 37 12
2A3 2Y3
R49 1% 48
2OE
WE_N 36 13 BWE_N
12[3D], 8[6A] WE_N 3A0 3Y0 BWE_N 13[3B], 16[2C], 18[6B]
FOE_N 35 14 BFOE_N
7[3C], 8[6B] FOE_N 3A1 3Y1 BFOE_N 13[3B], 16[2C], 18[6B]
PORST_N 33 16 B_PORST_N
14[5A], 6[5D] PORST_N 3A2 3Y2 B_PORST_N 13[3C], 18[3A], 21[3B]
32 17
3A3 3Y3
R75 1K 25
3OE
0.1W 30 19
1% 4A0 4Y0
29 20
4A1 4Y1
27 22
4A2 4Y2
26 23
4A3 4Y3
R173 1K 24
4OE
0.1W 4
1% GND
7 10
VCC GND
18 15
VCC GND
3V3 31 21
VCC GND
42 28
VCC GND
C69 C100 C101 C111 34
GND
39
GND
104 104 104 104 45
GND
C 16V 16V 16V 16V C
10% 10% 10% 10% 74LVC162244A
U8
A4 47 2 BA4
1A0 1Y0
A5 46 3 BA5
1A1 1Y1
A6 44 5 BA6
1A2 1Y2
A7 43 6 BA7
1A3 1Y3
R50 1K 1
1OE
0.1W A8 41 8 BA8
1% 2A0 2Y0
A9 40 9 BA9
2A1 2Y1
A10 38 11 BA10
2A2 2Y2
A11 37 12 BA11
2A3 2Y3
R51 1K 48
2OE
0.1W A12 36 13 BA12
1% 3A0 3Y0
A13 35 14 BA13
3A1 3Y1
A14 33 16 BA14
3A2 3Y2
A15 32 17 BA15
3A3 3Y3
R52 1K 25
3OE
0.1W A16 30 19 BA16
1% 4A0 4Y0
A17 29 20 BA17
4A1 4Y1
A18 27 22 BA18
4A2 4Y2
A19 26 23 BA19
4A3 4Y3
R53 1K 24 BA[22..0]
4OE BA[22..0] 13[3A], 18[3B]
0.1W 4
1% GND
7 10
VCC GND
18 15
D 3V3
C65 C66 C67 C68

31
42
VCC
VCC
VCC
GND
GND
GND
GND
21
28
34
39
Integrated 30 ohm termination resistors
to reduce line noise
BUS_BUFFERS D
GND Title
104 104 104 104 45
16V 16V 16V 16V GND
10% 10% 10% 10%
74LVC162244A
A3 REV : 3
Date: DTB
2008-12-10 Sheet 9 of 22
1 2 3 4 5 6 7 5270966 8
GANTRY 4-9
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
IDSEL R8
1K
0.1W
1%
PCI_AD[31..0] U1B
14[1A] PCI_AD[31..0]
PCI_AD31 V25 J24 PCI_FRAME
AD31 PCI FRAME~ PCI_FRAME 14[2C]
PCI_AD30 U25 H26 PCI_DEVSEL 10K 3V3
AD30 DEVSEL~ PCI_DEVSEL 14[2C] 0.063W
PCI_AD29 U26 K25 PCI_IRDY RP32 5%
AD29 IRDY~ PCI_IRDY 14[2C]
PCI_AD28 U24 K26 PCI_TRDY PCI_PERR 1 8
AD28 TRDY~ PCI_TRDY 14[2C]
PCI_AD27 U23 2 7
AD27
PCI_AD26 T25 J26 PCI_LOCK PCI_PAR 3 6
AD26 LOCK~
PCI_AD25 T26 H25 PCI_STOP PCI_SERR 4 5
AD25 STOP~ PCI_STOP 14[2C]
PCI_AD24 R25 G26 PCI_PERR
AD24 PERR~ PCI_PERR 14[2C]
PCI_AD23 R26 F26 PCI_SERR
AD23 SERR~ PCI_SERR 14[2C] 10K
PCI_AD22 N26
AD22 0.063W
PCI_AD21 N25 AC26 INTA~ RP35 5%
AD21 INTA~
PCI_AD20 N23 PCI_STOP 1 8
AD20
PCI_AD19 M26 PCI_DEVSEL 2 7
B AD19 B
PCI_AD18 M25 AB26 PCI_REQ0_N PCI_LOCK 3 6
AD18 REQ~0 PCI_REQ0_N 14[2C]
PCI_AD17
PCI_AD16
L25
L26
AD17
AD16
REQ~1
REQ~2
AA25
AA26
PCI_REQ1#
PCI_REQ2#
PCI_IRDY 4 5
PULLUPS
PCI_AD15 F24 Y25 PCI_REQ3#
AD15 REQ~3
PCI_AD14 E26 Y26 PCI_REQ4# IDSEL0=AD22
AD14 REQ~4/DA4 10K
PCI_AD13 E25
AD13 0.063W
PCI_AD12 E23 V26 PCI_GNT0_N RP34 5%
AD12 GNT~0 PCI_GNT0_N 14[2C]
PCI_AD11 D26 W23 PCI_GNT1# PCI_REQ2# 1 8
AD11 GNT~1
AD10 GNT~2
PCI_AD9 C26 W25 PCI_GNT3# PCI_REQ4# 3 6
AD9 GNT~3
PCI_AD8 A26 W26 PCI_GNT4# PCI_GNT4# 4 5

AD8 GNT~4/DA5
PCI_AD7 B26
AD7
PCI_AD6 A24
AD6
PCI_AD5 B24 AC25 SOUT1 10K
AD5 SOUT1/PCICLK0 SOUT1 15[1C] 0.063W
PCI_AD4 D19 AB25 SIN1 RP33 5%
AD4 SIN1/PCICLK1 SIN1 15[1C]
PCI_AD3 B23 AE26 PCI_GNT1# 1 8
AD3SOUT2/RTS~1/PCICLK2 R7
PCI_AD2 B22 AF25 PCI_GNT2# 2 7
AD2 SIN2/CTS~1/PCICLK3 3V3
PCI_AD1 D22 AF26 10K PCI_REQ3# 3 6
AD1 DA3/PCICLK4
PCI_AD0 C22 0.1W INTA~ 4 5
AD0
1%
PCI_PAR G25
14[1B] PCI_PAR PAR
AD25
PCI_SYNC_OUT
IDSEL P26 10K
IDSEL 0.063W
PCI_C/BE_N[3..0] AB23 PCI_SYNC RP31 5%
14[1B] PCI_C/BE_N[3..0] PCI_SYNC_IN PCI_SYNC 6[5C]
PCI_C/BE_N3 P25 PCI_TRDY 1 8
C/BE~3
PCI_C/BE_N2 K23 PCI_GNT0# 2 7
C/BE~2
PCI_C/BE_N1 F23 PCI_REQ0# 3 6
C/BE~1
C PCI_C/BE_N0 A25 PCI_GNT3# 4 5 C
C/BE~0
MPC8245
D
MPC8245_PCI D
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 10of 22
1 2 3 4 5 6 7 8
4-10 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
1V9_CORE
R9
C6 C11 10
3V3 U1C 2u2 2u2 0.1W
A 35V 35V 1% A
Y3 C17 10% 10%
GVDD AVDD
V4 AF24
GVDD POWER AVDD2
U3
GVDD
R3 AA2
GVDD GND R10
P4 AA23
GVDD GND
N3 AC12 C7 C12 10
GVDD GND 2u2 2u2
L4 AC15 0.1W
GVDD GND 35V 35V
K4 AC24 10% 1%
GVDD GND 10%
H4 AC3
GVDD GND
G3 AC6
GVDD GND
E3 AC9
GVDD GND
D9 AD11
GVDD GND
D5 AD14
GVDD GND
D13 AD16
GVDD GND
C7 AD19
GVDD GND
C5 AD23
GVDD GND
C3 AD4
GVDD GND
C12 AE18
GVDD GND
C10 AE2
GVDD GND
AD7 AE21
GVDD GND
AD5 AE25
GVDD GND
AD3 B2
GVDD GND
AD15 B25
GVDD GND
AD13 B6 3V3
GVDD GND
AD10 B9
GVDD GND
AC8 C11
GVDD GND C2 C3 C4 C5 C8 C9 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47
AC11 C13 C1
GVDD GND
B AC10 C16 B
GVDD GND 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 100u
AB4 C23 104 100u
GVDD GND 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
AB3 C4 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GVDD GND
C8
GND
AC20 D12
LVDD1 GND
AC23 D15
LVDD2 GND
D20 D18
LVDD3 GND
D23 D21
LVDD4 GND
G23 D24
LVDD5 GND
P23 D3 1V9_CORE
LVDD6 GND
Y23 F25
LVDD7 GND
3V3 F4 C46 C48
GND C10 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44
Y24 H24
OVDD GND
T23 J25 104 104 104 104 104 104 104 104 104 104 100u 100u
OVDD GND 104 104 104 104 104 104 104
P24 J4 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
OVDD GND 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
M24 L24
OVDD GND
K24 L3
OVDD GND
J23 M23
OVDD GND
G24 M4
OVDD GND
E24 N24
OVDD GND
C24 P3
OVDD GND
C20 R23
OVDD GND
C14 R4
OVDD GND
AD24 T24 3V3 D1 D2 D5 1V9_CORE
OVDD GND
AD20 T3 1 2
OVDD GND
AB24 V2
OVDD GND
1V9_CORE V23 1N4148 1N4148 1N4148
GND
AA24 W3
C VDD GND D3 C
AC16
VDD
AC19
VDD
AD12
VDD
AD6 1N4148
VDD D4
AD9
VDD
C15
VDD
C18
VDD
C21 1N4148
VDD
D11
VDD
D8 NOTE : In order to protect device in case of
VDD
F3
H23
VDD power on (3.3V/1.9V) sequence.
VDD
J3
VDD
L23
VDD
M3
VDD
R24
VDD
T4
VDD
V24
VDD
W4
VDD
MPC8245
D
MPC8245_PWR D
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 11of 22
1 2 3 4 5 6 7 8
GANTRY 4-11
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
3V3
C149 C151 C153 C155 C157 C159 C161

C139 C141 C143 C145 C147 104 104 104 104 104 104
104 104 104 104 104 104 16V 16V 16V 16V 16V 16V
16V 16V 16V 16V 16V 16V 10% 10% 10% 10% 10% 10%
10% 10% 10% 10% 10% 10%
A[22..0]
A 7[3C], 8[6A], 9[2B] A[22..0] A
3V3
3V3
A9
A7
D3
B3
C7
E7
J9
A9
A7
D3
B3
C7
E7
J9
U31
U29
MT48LC16M16A2BG
MT48LC16M16A2BG
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7 A0
A0 A1 H8
A1 H8 A1
A1 A2 J8 A8 D48
A2 J8 A8 D32 A2 DQ0
A2 DQ0 A3 J7 B9 D49
A3 J7 B9 D33 A3 DQ1
A3 DQ1 A4 J3 B8 D50
A4 J3 B8 D34 A4 DQ2
A4 DQ2 A5 J2 C9 D51
A5 J2 C9 D35 A5 DQ3
A5 DQ3 A6 H3 C8 D52
A6 H3 C8 D36 A6 DQ4
A6 DQ4 A7 H2 D9 D53
A7 H2 D9 D37 A7 DQ5
A7 DQ5 A8 H1 D8 D54
A8 H1 D8 D38 A8 DQ6
A8 DQ6 A9 G3 E9 D55
A9 G3 E9 D39 A9 DQ7
A9 DQ7 A10 H9 E1 D56
A10 H9 E1 D40 A10/AP DQ8
A10/AP DQ8 A21 G2 D2 D57
A21 G2 D2 D41 A11 DQ9
A11 DQ9 A22 G1 D1 D58
A22 G1 D1 D42 A12 DQ10
A12 DQ10 C2 D59
C2 D43 DQ11
DQ11 A11 G7 C1 D60
A11 G7 C1 D44 BA0 DQ12
BA0 DQ12 A20 G8 B2 D61
A20 G8 B2 D45 BA1 DQ13
BA1 DQ13 B1 D62
B1 D46 DQ14
DQ14 SDCS0_N G9 A2 D63
SDCS0_N G9 A2 D47 CS DQ15
CS DQ15 SDCAS_N F7
SDCAS_N F7 CAS
CAS SDRAS_N F8
SDRAS_N F8 RAS
RAS WE_N F9 E2
WE_N F9 E2 WE NC
WE NC DQM6 E8
DQM4 E8 LDQM
LDQM DQM7 F1 A3
B DQM5 F1 A3 UDQM VSSQ B
8[6A] DQM[7..0] UDQM VSSQ B7
B7 VSSQ
8[6C] SDCLK[3..0] VSSQ SDCLK3 F2 C3
VSS
VSS
VSS
SDCLK2 F2 C3 CLK VSSQ
VSS
VSS
VSS
CLK VSSQ CKE F3 D7
CKE F3 D7 CKE VSSQ
CKE VSSQ
A1
E3
J1
A1
E3
J1
3V3
3V3
C152 C154 C156 C158 C160 C162
C140 C142 C144 C146 C148 C150 104 104 104 104 104 104
104 104 104 104 104 104 16V 16V 16V 16V 16V 16V
16V 16V 16V 16V 16V 16V 10% 10% 10% 10% 10% 10%
10% 10% 10% 10% 10% 10%
3V3
3V3
A9
A7
D3
B3
C7
E7
J9
A9
A7
D3
B3
C7
E7
J9
U32
U30
MT48LC16M16A2BG
MT48LC16M16A2BG
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7 A0
A0 A1 H8
A1 H8 A1
A1 A2 J8 A8 D16
A2 J8 A8 D0 A2 DQ0
C A2 DQ0 A3 J7 B9 D17 C
A3 J7 B9 D1 A3 DQ1
A3 DQ1 A4 J3 B8 D18
A4 J3 B8 D2 A4 DQ2
A4 DQ2 A5 J2 C9 D19
A5 J2 C9 D3 A5 DQ3
A5 DQ3 A6 H3 C8 D20
A6 H3 C8 D4 A6 DQ4
A6 DQ4 A7 H2 D9 D21
A7 H2 D9 D5 A7 DQ5
A7 DQ5 A8 H1 D8 D22
A8 H1 D8 D6 A8 DQ6
A8 DQ6 A9 G3 E9 D23
A9 G3 E9 D7 A9 DQ7
A9 DQ7 A10 H9 E1 D24
A10 H9 E1 D8 A10/AP DQ8
A10/AP DQ8 A21 G2 D2 D25
A21 G2 D2 D9 A11 DQ9
A11 DQ9 A22 G1 D1 D26
A22 G1 D1 D10 A12 DQ10
A12 DQ10 C2 D27
C2 D11 DQ11
DQ11 A11 G7 C1 D28
A11 G7 C1 D12 BA0 DQ12
BA0 DQ12 A20 G8 B2 D29
A20 G8 B2 D13 BA1 DQ13
BA1 DQ13 B1 D30
B1 D14 DQ14
8[6A] SDCS0_N CS DQ15 SDCAS_N F7
SDCAS_N F7 CAS
8[6A] SDCAS_N CAS SDRAS_N F8
SDRAS_N F8 RAS
8[6A] SDRAS_N RAS WE_N F9 E2
WE_N F9 E2 WE NC
8[6A], 9[2B] WE_N WE NC DQM2 E8
DQM0 E8 LDQM
LDQM DQM3 F1 A3
DQM1 F1 A3 UDQM VSSQ
UDQM VSSQ B7
B7 VSSQ
VSSQ SDCLK1 F2 C3
VSS
VSS
VSS
VSS
VSS
VSS
CLK VSSQ CKE F3 D7

CKE F3 D7 CKE VSSQ
7[3A], 8[6B] CKE CKE VSSQ
A1
E3
J1
A1
E3
J1
D[0..63]
D 7[3C], 8[1D], 9[6A] D[0..63]
DQM[7..0]
SDCLK[3..0]
Title
SDRAM D
DTB

SDRAM 128MB A3
Date:
File:
2008-12-10
5270966
D:\DESIGN-TASK\..\12.SchDoc
Sheet 12of 22
Drawn By:
REV : 3
1 2 3 4 5 6 7 8
4-12 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
BA[22..0]
18[3B], 9[6D] BA[22..0] U12 BD[0..15]
BD[0..15] 16[2C], 18[6C], 9[3A]
BA1 E1 E2 BD7
A0 DQ0
BA2 D1 H2 BD6
A1 DQ1
BA3 C1 E3 BD5
A2 DQ2
BA4 A1
A3 DQ3
H3 BD4 Big Endian
BA5 B1 H4 BD3
A4 DQ4
BA6 D2 E4 BD2
A5 DQ5
BA7 C2 H5 BD1
A6 DQ6
BA8 A2 E5 BD0
A7 DQ7
BA9 B5
A8
BA10 A5 F2
A9 DQ8
BA11 C5 G2
A10 DQ9
BA12 D5 F3
A11 DQ10
BA13 B6 G3
A12 DQ11
BA14 A6 F4
A13 DQ12
BA15 C6 G5
A14 DQ13
BA16 D6 F5
A15 DQ14
BA17 E6 G6 BA0
A16 DQ15/A-1
BA18 B2
A17 R71
BA19 C3 F6
A18 BYTE#
BA20 D4 A3
A19 RY/BY# 1K
BA21 D3 0.1W
A20 1%
BA22 C4
A21
B 3V3 B
RCS0_N F1 G4
7[3C], 8[6B], 9[2A] RCS0_N CE# VCC
BFOE_N G1 C85
16[2C], 18[6B], 9[6B] BFOE_N OE# 104
BWE_N A4 16V
16[2C], 18[6B], 9[6B] BWE_N WE#
B3 H1 10%
R70 WP#/ACC VSS
B4 H6
3V3 RESET# VSS
4.99K
0.1W S29GL064N-90BFIR40
1%
BOOT FLASH
U25 HY27US08121A
NAND_CE_N 9 29 BD7
18[6A] NAND_CE_N CE I/O0
C NAND_RE_N 8 30 BD6 C
18[6A] NAND_RE_N RE I/O1
NAND_WE_N 18 31 BD5
18[6A] NAND_WE_N WE I/O2
NAND_CLE 16 32 BD4
18[6A] NAND_CLE CLE I/O3
NAND_ALE 17 41 BD3
18[6A] NAND_ALE ALE I/O4
42 BD2
I/O5
B_PORST_N 19 43 BD1
18[3A], 21[3B], 9[6B] B_PORST_N WP I/O6
NAND_R/B# 7 44 BD0
18[6A] NAND_R/B# R/B I/O7
3V3 12 13
VDD VSS
37 36
VDD VSS
3V3 C113 C115
R242 104 104
16V 16V
10K 10% 10% NAND FLASH
0.1W
1%
Title
FLASH D
DTB
A3 5270966 REV :3
Date: 2008-12-10 Sheet 13of 22
1 2 3 4 5 6 7 8
GANTRY 4-13
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
27P
50V
C80 10%
Y1
25MHz
A PCI_AD[31..0] U10 A
10[1B] PCI_AD[31..0]
PCI_AD31 33 121 C275
PCI_AD31 X1
PCI_AD30 34 122 27P
PCI_AD30 X2 50V
PCI_AD29 36
PCI_AD29 10%
PCI_AD28 37 27 PORST_N
PCI_AD28 RST# PORST_N 6[5D], 9[2B]
PCI_AD27 39
PCI_AD27
PCI_AD26 40 U11 3V3
PCI_AD26
PCI_AD25 42 106 1 8
PCI_AD25 EECS CS VCC

PCI_AD24 43 111 2 7 C81
PCI_AD24 EESK SK NC 104
PCI_AD23 47 109 3 6
PCI_AD22 49
PCI_AD23
PCI_AD22
AUX/EEDI
EEDO
108 4
DI
DO
NC
GND
5
16V
10% ONLY FOR DEBUG
PCI_AD21 50
PCI_AD21
PCI_AD20 53 117 ACT_LED- 93C46
PCI_AD20 LED0
PCI_AD19 55 115 LNK_LED-
PCI_AD19 LED1
PCI_AD18 57 114
PCI_AD18 LED2
PCI_AD17 58 U17 3V3
PCI_AD17
PCI_AD16 59 1 ETH_TXD+ 1 8
PCI_AD16 TXD+ CS VCC
PCI_AD15 79 2 ETH_TXD- 2 7 C104
PCI_AD15 TXD- SK NC 104
PCI_AD14 82 3 6 16V
PCI_AD14 DI NC
PCI_AD13 83 4 5 10%
PCI_AD13 DO GND
PCI_AD12 85
PCI_AD12
PCI_AD11 86 5 ETH_RXIN+ 93C46
PCI_AD11 RXIN+
PCI_AD10 87 6 ETH_RXIN-
PCI_AD10 RXIN-
PCI_AD9 89
PCI_AD9
PCI_AD8 90
PCI_AD8
PCI_AD7 93
PCI_AD7
PCI_AD6 95
PCI_AD6
PCI_AD5 96
B PCI_AD5 B
PCI_AD4 97
PCI_AD4
PCI_AD3 98
PCI_AD3
PCI_AD2 102 8
PCI_AD2 CTRL25 5K6
PCI_AD1 103 0.1W 3V3
PCI_AD1
PCI_AD0 104 127 R55 1%
PCI_AD0 RSET FB8
R60 301 BLM21PG331SN1
PCI_PAR 76 65 0.1W
10[1C] PCI_PAR PCI_PAR CLKRUN# 4.99k 1K 330ohm
PCI_C/BE_N[3..0] 0.1W LNK_LED- R66 1%
10[1C] PCI_C/BE_N[3..0] 0.1W
PCI_C/BE_N3 44 31 R56 1% 3V3 1%
PCI_C/BE#3 PME# 301
PCI_C/BE_N2 60 23
PCI_C/BE#2 ISOLATE# 0.1W
PCI_C/BE_N1 77 105 1% 3V3

PCI_C/BE#1 LWAKE R61 ACT_LED- R67
PCI_C/BE_N0 92
PCI_C/BE#0 10K
26 FB7
VDD33 0.1W FB9
PCI_FRAME 61 41 1% BLM21PG331SN1
10[4B] PCI_FRAME PCI_FRAME# VDD33 BLM21PG331SN1
PCI_DEVSEL 68 56 330ohm
10[4B] PCI_DEVSEL PCI_DEVSEL# VDD33 3V3 C276 C277 J3 330ohm
PCI_IRDY 63 71 104 104
10[4B] PCI_IRDY PCI_IRDY# VDD33 R59 16V 16V
PCI_TRDY 67 84
10[4B] PCI_TRDY PCI_TRDY# VDD33 4.99K 10% 10% C53
PCI_STOP 69 94
10[4B] PCI_STOP PCI_STOP# VDD33 0.1W 9 10
PCI_PERR 70 107 1%
10[4B] PCI_PERR PCI_PERR# VDD33
PCI_SERR 75 3 AVDD1 104
10[4B] PCI_SERR PCI_SERR# AVDD33 7 8
PCI_AD22 R54 46 7 AVDD2 16V
PCI_IDSEL# AVDD33
100 IRQ~0 25 20 AVDD3 10%
IDSEL0=AD22 6[2A] IRQ~0 PCI_INTA# AVDD33 1
0.1W PCI_REQ0_N 30 32 CT
1% 10[4B] PCI_REQ0_N PCI_REQ# VDD25 ETH_TXD+ 2
PCI_GNT0_N 29 54 FB4 TD+
10[4B] PCI_GNT0_N PCI_GNT# VDD25 ETH_TXD- 3
SELECT PCI ID 78 VDD25 BLM21PG331SN1 TD-
VDD25 330ohm ETH_RXIN+ 4
PCICLK0 28 99 RD+
6[5C] PCICLK0 PCI_CLK VDD25 ETH_RXIN- 5 11
12 RD-
AVDD25 6 12
C 4 C78 CT C
GND
81 17 104
GND GND 16V C84 104 JP011821U
91 21 10%
GND GND
100 35
GND GND
101 38
GND GND
119 51
GND GND CH_GND
123 52
ETH_TXD-
ETH_TXD+
ETH_RXIN-
ETH_RXIN+
GND GND R234
124 66 R68
GND GND VCC
128 80 0
GND GND ETH_TXD+ ETH_TXD- 0
RTL8100CL-LF GND CH_GND
6
5
4
GND CH_GND
3V3 U24
SRV05-4 R235 R236
C71 C72 C73 C74 C75 C77 C97 R62 R63 R64 R65
104 104 104 104 104 104 104 0 0
16V 16V 16V 16V 16V 16V 16V 51.1 51.1 51.1 51.1
10% 10% 10% 10% 10% 0.1W 0.1W 0.1W 0.1W
1
2
3
10% 10% ETH_RXIN+ ETH_RXIN- GND CH_GND GND CH_GND
1% 1% 1% 1%
R237
R238
C82 C83
104 104 0
16V 16V 0
10% 10% GND CH_GND
GND CH_GND
FB1 FB2 FB3

BLM21PG331SN1 BLM21PG331SN1 BLM21PG331SN1
AVDD1 AVDD2 AVDD3

D
3V3
330ohm C70
104
16V
10%
3V3
330ohm C76
104
16V
10%
3V3
330ohm C79
104
16V
10%
FET_PHY D
Title
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 14of 22
1 2 3 4 5 6 7 8
4-14 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3 3V3 3V3 3V3 3V3 3V3
D6 D8 D10 D12 D14 D16

1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
OUTA_P OUTA_N OUTB_P OUTB_N OUTC_P OUTC_N
A A
D7 D9 D11 D13 D15 D17
1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
3V3
C168 3V3
R186
R185
1K 104
1K 16V
0.1W 0.1W 10%
1% 1% U35
4 16 33R
OE VDD 0.063W
12 RP42 5%
OE
SIMU_XRAY_ON_OUT 1 2 OUTA_P 1 8 422_OUTA_P
18[6B] SIMU_XRAY_ON_OUT IN A OUT A
3 OUTA_N 2 7 422_OUTA_N
OUT A
RESET_N_BY_JIG 7 6 OUTB_P 3 6 422_OUTB_P
18[6B] RESET_N_BY_JIG IN B OUT B
5 OUTB_N 4 5 422_OUTB_N
OUT B
SAFETY_LOOP_OPEN_N 9 10 OUTC_P 1 8 422_OUTC_P
18[6B] SAFETY_LOOP_OPEN_N IN C OUT C
11 OUTC_N 2 7 422_OUTC_N
OUT C
15 14 3 6
3V3 IN D OUT D
13 4 5
R191 OUT D
8 RP43 33R
1K GND
R243 0.1W 0.063W
B 1% DS26LV31AT 5% B
1K
0.1W
1%
C165 3V3
R244
1K
104 0.1W
16V 1%
10% U34
16
MAX3232
C163 104 1 2
C1+ V+ 104 VCC
16V
VCC
10% C169 16V

3 C167
C1- 104 10%
C166 51.1 R189 R190 U26A U26B
C164 104 4 6 16V 0.1W
C2+ V- 10% 422_INA_P R187 1% U36 1K 1K
16V R79 1 2 3 4 R230 TGPL_RST_N
10% 1 8 0.1W 0.1W TGPL_RST_N 6[2D]
5 104 51.1 + VCC 100 51.1
C2- 16V 1% 1% 0.1W 0.1W
10% 0.1W C117
422_INA_N R188 1% 2 7 1% 74LVC14A PW 74LVC14A PW 1%
SOUT1 11 14 COM_TXD - V01 470P
10[4C] SOUT1 T1IN T1OUT 16V
10 7
T2IN T2OUT 422_INB_N R201 3 6 10% U26C
- V02
51.1
SIN1 12 13 COM_RXD 0.1W
GND
10[4C] SIN1 R1OUT R1IN 1% 4 5 R231 5 6 R232 XRAY_ON_IN

9 8 + GND XRAY_ON_IN 18[6B]
R2OUT R2IN 422_INB_P R202 100 51.1
51.1 HCPL-0631 0.1W C119 0.1W
0.1W 1% 470P 74LVC14A PW 1%
15
1% 16V 7 14
GND VDD 3V3
10%
C120
C C
104
16V
J5 10%
COM_TXD
1
COM_RXD
2
J4
3
422_OUTA_P 422_OUTA_N
1 2
Header 3 422_OUTB_P 422_OUTB_N
3 4
WIRE TO BOARD 422_OUTC_P 422_OUTC_N
5 6
422_INA_P 422_INA_N
7 8
RS-232 CONSOLE 422_INB_P
9 10
422_INB_N
Header 5X2
FOR DEBUGGING
RS-422
D D
Title
UART_PHY
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 15of 22
1 2 3 4 5 6 7 8
GANTRY 4-15
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
3V3
3V3 C103
BA[20..0] U20 104 R105

13[3A], 18[3B], 9[6D] BA[20..0] 50V
BA8 1 16 10% 10K
A VCC
BA9 2 0.1W
B 1%
BA10 3 15
C Y0
14
Y1
R99 6 13
3V3 OE1 Y2
1K 4 12 FPGA_DCLK
0.1W OE2A Y3 FPGA_DCLK 19[6B]
5 11 ENWDT_N
1% OE2B Y4 ENWDT_N 18[6B]
10 FEEDWDT_N
Y5 FEEDWDT_N 18[6B]
RCS2_N 9 DISWDT_N
18[6B], 8[6C], 9[2B] RCS2_N Y6 DISWDT_N 18[6B]
8 7 CONFIG_FPGA_N
GND Y7
SN74LV138PWLE
B B
3V3
U16B SN74LV32D R103 R107

CONFIG_FPGA_N 4 U18 3V3 104
50V 10K 10K
6 1 20 10% 0.1W 0.1W
OE VDD 1% 1%
BWE_N 5 11
13[3B], 18[6B], 9[6B] BWE_N CLK
C105
C102 BD5 3 2 FPGA_CONFIG_N
D0 Q0 FPGA_CONFIG_N 19[6B]
BD4 4 5
3V3 D1 Q1
BD3 7 6 FPGA_DATA0
104 D2 Q2 FPGA_DATA0 19[6B]
8 9
50V D3 Q3
10% 13 12
D4 Q4
BD[0..15] 14 15
13[6A], 18[6C], 9[3A] BD[0..15] R101 D5 Q5
17 16
1K D6 Q6
18 19
0.1W D7 Q7
1%
10
GND
C C
MC74LVX374M
U16C
CONFIG_FPGA_N 9
8
BFOE_N 10 3V3
13[3B], 18[6B], 9[6B] BFOE_N 104
U19 50V
SN74LV32D 1 20 10%
OE1 VCC
19 C106
OE2
FPGA_STATUS_N 2 18 BD2
19[4B] FPGA_STATUS_N A1 Y1
FPGA_CONF_DONE 4 16 BD1
19[4B] FPGA_CONF_DONE A2 Y2
INIT_DONE 6 14 BD0
17[4C] INIT_DONE A3 Y3
8 12
A4 Y4
11 9
R102 A5 Y5
13 7
1K A6 Y6
15 5
0.1W A7 Y7
1% 17 3
A8 Y8
10
GND
74LVC244A
FPGA_CONFIG
Title
D
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 16of 22
1 2 3 4 5 6 7 8
4-16 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U13A U13B
T3 C4
IO, LVDS0n IO, LVDS24p (DEV_CLRn)
BANK 1
BANK 2
T2 B3
IO, LVDS0p IO, LVDS24n (DEV_OE)
R3 B4
IO, LVDS1n IO, LVDS26p (DQ1T7)
R2 A4
IO, LVDS1p IO, LVDS26n (DQ1T6)
A P4 D5 A
IO IO, LVDS27p (DQ1T5)
R1 C5
IO, VREF2B1 IO, LVDS27n (DQ1T4)
P3 G8
IO, LVDS2n (DQ1L7) IO, LVDS25p
P2 F8
IO, LVDS2p (DQ1L6) IO, LVDS25n
P5 TXEN_N B5
IO, DPCLK0 (DQS1L) TXEN_N 21[4B] IO, DPCLK2 (DQS1T)
N4 CARDET A6
IO, LVDS3n (DQ1L5) CARDET 21[6D] IO, VREF2B2
N3 VLTN C6 CYSC_D
IO, LVDS3p (DQ1L4) VLTN 21[6C] IO, LVDS28p CYSC_D 21[1C]
N6 RXSC_D B6
IO, LVDS4n RXSC_D 21[6C] IO, LVDS28n
N5 RXCLK D6
IO, LVDS4p RXCLK 21[6C] IO, LVDS29p
N7 LFI_N E6 TCMD[3..0]
IO, LVDS5n LFI_N 21[6D] IO, LVDS29n TCMD[3..0] 21[1C]
M6 C7 TCMD0
IO, LVDS5p IO, LVDS30p
N2 D7 TCMD1
IO, LVDS6n IO, LVDS30n
N1 B7 TCMD2
IO, LVDS6p IO, LVDS31p (DQ1T3)
M4 A7 TCMD3
IO, LVDS7n IO, LVDS31n (DQ1T2)
M5 RCMD[3..0] E7
IO, LVDS7p (DQ1L3) RCMD[3..0] 21[5C] IO, LVDS32p (DQ1T1)
M2 RCMD3 E8
IO, LVDS8n (DQ1L2) IO, LVDS32n (DQ1T0)
M3 RCMD2 B8
IO, LVDS8p (DQ1L1) IO, LVDS33p
M1 RCMD1 A8 TXDATA[7..0]
IO (DQ1L0) IO, LVDS33n TXDATA[7..0] 21[1C]
L4 RCMD0 C8 TXDATA7
IO, LVDS9n IO, LVDS34p
L5 D8 TXDATA6
IO, LVDS9p IO, LVDS34n
L3 B9 TXDATA5
L2 A9 TXDATA4
L6 RXDATA[7..0] C9 TXDATA3
IO, LVDS11n RXDATA[7..0] 21[5C] IO, LVDS36p
L7 RXDATA7 D9 TXDATA2
IO, LVDS11p (DM1L) IO, LVDS36n (DM1T)
K5 R94 33.2 TXCLK E10
IO, PLL1_OUTn TXCLK 21[1C] IO, VREF1B2
K4 R74 33.2 0.1W TAXI_CLK_22M F9 TXDATA1
IO, PLL1_OUTp TAXI_CLK_22M 21[1C] IO, LVDS37p
K6 0.1W FPGA_ASDO G9 TXDATA0
IO (ASDO) FPGA_ASDO 19[6B] IO, LVDS37n
J1 FPGA_CS_N A10
IO (nCSO) FPGA_CS_N 19[4B] IO, LVDS38p
B H6 B10 B
IO, VREF1B1 IO, LVDS38n
H5 RXDATA6 D10
IO, LVDS12n (DM0L) IO, LVDS39p
H4 RXDATA5 C10
H3 RXDATA4 E11 FPGA_LED[23..0]
IO, LVDS13n IO FPGA_LED[23..0] 20[1A]
H2 RXDATA3 A11 FPGA_LED23
IO, LVDS13p IO, LVDS40p (DM0T)
H1 RXDATA2 B11 FPGA_LED22
IO (DQ0L7) IO, LVDS40n
G6 RXDATA1 D11 FPGA_LED21
G5 RXDATA0 C11 FPGA_LED20
G4 A12 FPGA_LED19
G3 B12 FPGA_LED18
F7 C12 FPGA_LED17

F6 D12 FPGA_LED16
G2 C13 FPGA_LED15
G1 D13 FPGA_LED14
F5 A13 FPGA_LED13
F4 B13 FPGA_LED12
F3 F10 FPGA_LED11
F2 G10 FPGA_LED10
E5 FPGA_TP7 F11 FPGA_LED3
E4 FPGA_TP6 G11 FPGA_LED2
F1 FPGA_TP5 E13 FPGA_LED9
IO, DPCLK1 (DQS0L) IO
E2 FPGA_TP4 C14
IO, LVDS21n (DQ0L1) IO, VREF0B2
E3 FPGA_TP3 3V3 B14 FPGA_LED8
IO, LVDS21p (DQ0L0) IO, DPCLK3 (DQS0T)
D1 FPGA_TP2 D14 FPGA_LED7
D4 C15 FPGA_LED6
IO, VREF0B1 R72 IO, LVDS47n (DQ0T2)
D2 FPGA_TP1 A15 FPGA_LED5
IO, LVDS22n 10K IO, LVDS48p (DQ0T1)
D3 B15 FPGA_LED4
IO, LVDS22p (CLKUSR) 0.1W IO, LVDS48n (DQ0T0)
C2 FPGA_TP0 1% B16 FPGA_LED1
C IO, LVDS23n (CRC_ERROR) IO, LVDS50p C
C3 INIT_DONE C16 FPGA_LED0
IO, LVDS23p (INIT_DONE) INIT_DONE 16[2C] IO, LVDS50n
EP1C12F324C8 EP1C12F324C8
104 3V3
50V
C86 10%
U14 PIN1 FPGA_TP7

20
74LVC244A J9 PIN3 FPGA_TP6

FPGA_TP7 2 18 PIN5 FPGA_TP5
1A0 1Y0 1 2
VCC

1A1 1Y1 3 4
1A2 1Y2 5 6
1A3 1Y3 7 8
1 PIN13 FPGA_TP1
1OE 9 10
2A0 2Y0 11 12
FPGA_TP2 15 5 PIN2 GND
2A1 2Y1 13 14
2A2 2Y2 15 16
GND
2A3 2Y3
19 Header 8X2 PIN8 GND
2OE
PIN10 GND
R73 PIN12 GND
10
1K PIN14 GND
0.1W PIN16 GND
1%
D D
Title
FPGA 1 of 3
ONLY FOR DEBUG DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 17of 22
1 2 3 4 5 6 7 8
GANTRY 4-17
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U13C U13D
D17 T15 NAND_CE_N
BANK 3 IO, LVDS51p IO, LVDS76n NAND_CE_N 13[3C]
BANK 4
C17 U16 NAND_RE_N
IO, LVDS51n IO, LVDS76p NAND_RE_N 13[3C]
D15 U15 NAND_WE_N
IO, LVDS52p IO, LVDS78n (DQ0B0) NAND_WE_N 13[3C]
D16 V15 NAND_CLE
A IO, LVDS52n IO, LVDS78p (DQ0B1) NAND_CLE 13[3C] A
E14 R14 NAND_ALE
IO, VREF0B3 IO, LVDS79n (DQ0B2) NAND_ALE 13[3C]
D18 T14 NAND_R/B#
IO (DQ0R0) IO, LVDS79p (DQ0B3) NAND_R/B# 13[3C]
E15 U14
IO, LVDS53p (DQ0R1) IO, DPCLK6 (DQS0B)
E16 P13
IO, LVDS53n (DQ0R2) IO, VREF0B4
E17 B_PORST_N N11
IO, DPCLK4 (DQS0R) B_PORST_N 13[3C], 21[3B], 9[6B] IO, LVDS77p
F15 M11
IO, LVDS54p (DQ0R3) IO, LVDS77n
F16 P12
IO, LVDS54n IO
F14 N10

F13 M10
F17 R13
F18 T13
F12 U13
IO, LVDS57p IO, LVDS82n (DQ0B4)
G12 V13
IO, LVDS57n IO, LVDS82p (DQ0B5)
G16 R12
G15 T12
G14 U12 SAFETY_LOOP_OPEN_N
IO, LVDS59p IO, LVDS84n SAFETY_LOOP_OPEN_N 15[4B]
G13 V12 RESET_N_BY_JIG
IO, LVDS59n (DQ0R4) IO, LVDS84p RESET_N_BY_JIG 15[4B]
G17 V11 SIMU_XRAY_ON_OUT
IO, LVDS60p (DQ0R5) IO, LVDS85n SIMU_XRAY_ON_OUT 15[4B]
G18 U11
IO, LVDS60n (DQ0R6) IO, LVDS85p (DM0B)
H18 T11 XRAY_ON_IN
IO (DQ0R7) IO, LVDS86n XRAY_ON_IN 15[7C]
H17 R11
H16 P10 WD_RST_N
IO, LVDS61n IO WD_RST_N 6[2D]
H15 R10 ENWDT_N
IO, LVDS62p IO, LVDS87n ENWDT_N 16[6B]
H14 T10 FEEDWDT_N
IO, LVDS62n IO, LVDS87p FEEDWDT_N 16[6B]
H13 V10 DISWDT_N
IO, LVDS63p (DM0R) IO, LVDS88n DISWDT_N 16[6B]
J13 U10
J14 P9 DSREQ_AB_INT
IO, VREF1B3 IO, VREF1B4 DSREQ_AB_INT 6[2A]
K15 T9 DTB_INT
B IO, PLL2_OUTp IO, LVDS90n DTB_INT 6[2A] B
K16 R9 ERROR_A-B_INT
IO, PLL2_OUTn IO, LVDS90p (DM1B) ERROR_A-B_INT 6[2A]
L14 M9
IO IO, LVDS89p
L15 N9
L16 V9
IO, LVDS64n (DM1R) IO, LVDS91n
L13 U9
M13 R8
L17 BA[22..0] T8 RCS1_N
IO, LVDS66p BA[22..0] 13[3A], 9[6D] IO, LVDS92p RCS1_N 8[6B], 9[2A]
L18 BA13 V8 AS_N
IO, LVDS66n IO, LVDS93n AS_N 8[6C]
M16 BA12 U8 RCS2_N
IO (DQ1R0) IO, LVDS93p RCS2_N 16[2B], 8[6C], 9[2B]
M15 BA11 R7 RCS3_N
IO, LVDS67p (DQ1R1) IO, LVDS94n (DQ1B0) RCS3_N 8[6C], 9[2B]
M14 BA10 T7 BFOE_N

IO, LVDS67n (DQ1R2) IO, LVDS94p (DQ1B1) BFOE_N 13[3B], 16[2C], 9[6B]
M17 BA9 V7 BWE_N
IO, LVDS68p (DQ1R3) IO, LVDS95n (DQ1B2) BWE_N 13[3B], 16[2C], 9[6B]
M18 BA8 U7 BD15
N15 BA7 R6 BD14
N16 BA6 T6 BD13
N12 BA5 P7 BD12
N13 BA4 P6 BD11
N17 BA3 U6 BD10
N18 BA2 V6 BD9
N14 BA1 M8 BD8
IO, LVDS72p (DQ1R4) IO, LVDS101p
P14 BA0 N8 BD7
IO, LVDS72n (DQ1R5) IO, LVDS101n
P15 R5
IO, DPCLK5 (DQS1R) IO, VREF2B4
P17 R4 BD6
IO (DQ1R6) IO, DPCLK7 (DQS1B)
P16 U5 BD5
IO, VREF2B3 IO, LVDS99n (DQ1B6)
R16 T5 BD4
IO, LVDS73p IO, LVDS99p (DQ1B7)
R15 U4 BD3
R18 SW_D T4 BD2
C R17 SW_C V4 BD1 C
T17 SW_B U3 BD0
T16 SW_A BD[0..15]
IO, LVDS75n BD[0..15] 13[6A], 16[2C], 9[3A]
EP1C12F324C8
EP1C12F324C8
RP44
5 4
6 3
7 2
8 1
3V3
8
7
6
5
10K
0.063W S1
5% CHS-04TB
1/2SLICE
1
2
3
4
D D
Title
FPGA 2 of 3
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 18of 22
1 2 3 4 5 6 7 8
4-18 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3 1V5 Not mounted

U13F 1V5
L3 22N
E1 A17 U13G
VCCIO1 VCCINT
G7 A2 A1 K11 3V3 U13E C87 C89 C92 C94
VCCIO1 VCCINT GND GND
M7 B1 A16 K8 FPGA_TDI J17 105 2.2u 104 103 U13H
A VCCIO1 VCCINT GND GND TDI 16V 16V 16V 50V A
P1 B18 A18 K9 R84 FPGA_TDO K13 10% 10% J5 K1
VCCIO1 VCCINT GND GND TDO 10% 10% VCCA_PLL1 GNDA_PLL1
H10 A3 L10 10K FPGA_TCK K18 J6
VCCINT GND GND 0.1W TCK GNDG_PLL1
A14 J9 B17 L11 FPGA_TMS K14
VCCIO2 VCCINT GND GND 1% TMS
A5 K10 B2 L8 J12 J18
VCCIO2 VCCINT GND GND VCCA_PLL2 GNDG_PLL2
E12 L9 C1 T1 K3 K12
VCCIO2 VCCINT GND GND MSEL0 GNDA_PLL2
E9 U1 C18 T18 R83 R86 1K K7
VCCIO2 VCCINT GND GND 0.1W MSEL1
U18 H11 U17 1V5 EP1C12F324C8
VCCINT GND GND L4 22N
P18 V17 H8 U2 0 3V3 FPGA_DCLK 1% L1
VCCIO3 VCCINT GND GND 0.1W DCLK

M12 V2 H9 V1 1% FPGA_DATA0 H7 C88 C90 C91 C93
VCCIO3 VCCINT GND GND DATA0
H12 J10 V16 R85 105 2.2u 104 103
VCCIO3 GND GND 16V 16V 16V 50V
E18 J11 V18 10K FPGA_CE_N J7
VCCIO3 GND GND 0.1W nCE 10% 10% 10% 10%
J8 V3 K2
GND GND 1% nCEO
V5 FPGA_CONFIG_N J2
VCCIO4 nCONFIG
V14 EP1C12F324C8 FPGA_STATUS_N L12
VCCIO4 nSTATUS
P8 K17
VCCIO4 CONF_DONE
P11
VCCIO4
EP1C12F324C8
EP1C12F324C8
16[2C] FPGA_STATUS_N U13I
FPGA_CONF_DONE
16[2C] FPGA_CONF_DONE CLK_33M J3
6[5C] CLK_33M CLK0, LVDSCLK1p
3V3 (FPGA I/O 3.3V 0.1U) AS_N_CLK J4
8[6C] AS_N_CLK CLK1, LVDSCLK1n
J15
CLK2, LVDSCLK2p
J16
3V3 X2 CLK3, LVDSCLK2n
C172 C177 C183 C189 C195 C201 C207 C213 C219 C225 C231 C237
8 1
104 103 104 103 104 103 104 103 104 103 104 103 VCC NC EP1C12F324C8
16V 50V 16V 50V 16V 50V 16V 50V 16V 50V 16V 50V C170
104 R95 R96 R240 R97
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 16V 1K 1K
4 5 R239 1K 1K
10% GND OUT 0.1W 0.1W 0.1W 0.1W
B 33.2 1% 1% 1% 1% B
1V5 (FPGA INT 1.5V 0.1U) 3V3
44MHz 0.1W
GND
1%
C174 C178 C184 C190 C196 C202 C208 C214 C220 R89 R91
104 103 104 103 104 103 104 103 104 10K 10K
16V 50V 16V 50V 16V 50V 16V 50V 16V 0.1W 0.1W
10% 10% 10% 10% 10% 10% 10% 10% 10% 1% 1%
J8
2 1
FPGA_DCLK
FPGA_DCLK 16[6B]
R96\R95 NOT MOUNTED
FPGA_CONF_DONE
3V3 4 3
GND FPGA_CE_N FPGA_CONFIG_N
6 5 FPGA_CONFIG_N 16[6C]
FPGA_CS_N FPGA_DATA0
17[4B] FPGA_CS_N 8 7 FPGA_DATA0 16[6C]
FPGA_ASDO
10 9 FPGA_ASDO 17[4B]
R87 Header 5X2
3V3 10K CONFIG JTAG HEADER
0.1W
1%
R80 R82
10K 10K
0.1W 0.1W
1% 1%
J7
FPGA_TCK
2 1
FPGA_TDO
3V3 4 3
FPGA_TMS
6 5
R77 10K 8 7
0.1W FPGA_TDI
1% 10 9
Header 5X2 R81
C FPGA JTAG HEADER 10K C
0.1W
1%
U15 3V3
2 3
DATA VCC
6
1
DCLK
nCS
VCC
VCC
7
8 Not mounted
5 C96 C98
ASDI
104 104
4 16V 16V
GND 10% 10%
R88 R90 R92 R93
0 0 0 0 EPCS4SI8
0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1%
FPGA_DATA0
FPGA_DCLK
FPGA_CS_N
FPGA_ASDO
ONLY FOR DEBUG

D
Title
FPGA 3 of 3 D
DTB
A3 5270966 REV :3
Date: 2008-12-10 Sheet 19of 22
1 2 3 4 5 6 7 8
GANTRY 4-19
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
FPGA_LED[23..0] 3V3
17[6B] FPGA_LED[23..0]
R130 DS17
1/2 SLICE
3V3 511
R112 DS1 0.1W
VLTN 1%
511 HSMG-C190
0.1W
1% HSMG-C190 R131 DS18
HEART_BEAT
511
R113 DS2 0.1W
REQ_A 1%
511 HSMG-C190
0.1W
1% HSMG-C190
104 104 3V3
50V 3V3 50V R132 DS19
10% BUFF_OVERRUN
C107 R114 DS3 C109 10% 511
READ_A
511 0.1W
20
U21 0.1W U23 1% HSMG-C190
20
74LVC244A 1% HSMG-C190 74LVC244A
FPGA_LED0 2 18 FPGA_LED16 2 18 R133 DS20
1A0 1Y0 1A0 1Y0 SCAN_ABORT
VCC
VCC
FPGA_LED1 4 16 R115 DS4 FPGA_LED17 4 16 511
1A1 1Y1 VIEW_A 1A1 1Y1
FPGA_LED2 6 14 511 FPGA_LED18 6 14 0.1W
1A2 1Y2 1A2 1Y2 1%
FPGA_LED3 8 12 0.1W FPGA_LED19 8 12 HSMG-C190
1A3 1Y3 1% 1A3 1Y3
1 HSMG-C190 1
1OE 1OE
FPGA_LED4 17 3 FPGA_LED20 17 3
2A0 2Y0 2A0 2Y0
2A1 2Y1 R116 DS5 2A1 2Y1
FPGA_LED6 13 7 END_NG_A FPGA_LED22 13 7
2A2 2Y2 511 2A2 2Y2
GND
GND
2A3 2Y3 0.1W 2A3 2Y3 NFS
19 1% 19 511
B 2OE HSMG-C190 2OE B
0.1W
R108 R110 R128 R129 1% HSMG-C190
R117 DS6
10
10
1K 1K FIFO_FULL_A 1K 1K
0.1W 0.1W 511 0.1W 0.1W R135 DS22
1% 1% 0.1W 1% 1% OTHER ERR
1% HSMG-C190 511
0.1W
1% HSMG-C190
R118 DS7
FEC_ERR_A
511 R136 DS23
0.1W RESERVED_A
1% HSMG-C190 511
0.1W
1% HSMG-C190
R119 DS8
CONTINUE_ERR_A
511 R137 DS24
0.1W RESERVED_B
1% HSMG-C190 511
0.1W
1% HSMG-C190
R120 DS9
CLR_A/B
511
0.1W
1% HSMG-C190
R121 DS10
REQ_B
511
C 0.1W C
104 1% HSMG-C190
50V 3V3
C108 10%
R122 DS11
READ_B
U22 511
20
74LVC244A 0.1W
1% HSMG-C190
FPGA_LED8 2 18
1A0 1Y0
VCC
FPGA_LED9 4 16
1A1 1Y1 R123 DS12
FPGA_LED10 6 14 VIEW_B
1A2 1Y2 511
FPGA_LED11 8 12
1A3 1Y3 0.1W
1 1%
1OE HSMG-C190
FPGA_LED12 17 3
2A0 2Y0
FPGA_LED13 15 5
2A1 2Y1 R124 DS13
FPGA_LED14 13 7 END_NG_B
2A2 2Y2 511
FPGA_LED15 11 9
GND
2A3 2Y3 0.1W

19 1%
2OE HSMG-C190
R109 R111
R125 DS14
10
1K 1K FIFO_FULL_B
0.1W 0.1W 511
1% 1% 0.1W
1% HSMG-C190
R126 DS15
FEC_ERR_B
511
0.1W
1% HSMG-C190
D R127
511
0.1W
1%
DS16
HSMG-C190
CONTINUE_ERR_B
Title
LEDS D
DTB
A3 5270966 REV :3
Date: 2008-12-10 Sheet 20of 22
1 2 3 4 5 6 7 8
4-20 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
R104 1K
0.1W
1% RP37
RXDATA0 5 4 R33 TCMD0
R100 1K RXDATA1 6 3
0.1W 4K7
1% RXDATA2 7 2
0.1W
RXDATA3 8 1 1%
R106 1K
VCC
0.1W 10K R34
1% 0.063W TCMD1
R198 1K 5% VCC 4K7
VCC
A 0.1W 0.1W A
1% RP38 1%
RXDATA4 5 4
R199 1K R35
VCC RXDATA5 6 3 TCMD2
0.1W
1% RXDATA6 7 2
RXDATA7 8 1 4K7
1K 0.1W
VCC R200 1%
0.1W 10K
1% 0.063W R36
R203 1K 5% TCMD3
VCC
0.1W 4K7
1% RP39
RCMD1 5 4 0.1W
1K 1%
VCC R204 RCMD0 6 3
0.1W
1% RCMD2
RCMD3
7
8
2
1
NOT MOUNTED
R205 1K
VCC
0.1W 10K
1% 0.063W
R206 1K 5%
VCC
0.1W
1%
R207 1K R40 R44
SERIALIN_P SERIALOUT_N
0.1W
B_PORST_N 13[3C], 18[3A], 9[6B]

1% 130 130
0.1W R42 0.1W R46
R208 1K 1% 84.5 1% 84.5
0.1W 0.1W 0.1W
1% 1% 1%
C56 C59
R209 1K VCC VCC
0.1W 104 104
17[4A]
1% 50V R43 50V R47
B 10% 84.5 10% 84.5 B
R210 1K 0.1W 0.1W
VCC 1% 1%
0.1W R41 R45
SERIALIN_N SERIALOUT_P
TXEN_N
1%
R211 1K 130 130
VCC C252 C257 C261 C264 C266 C99 0.1W 0.1W
0.1W 1%
1% 103 103 103 103 103 103 1%
50V 50V 50V 50V 50V 50V
R213 1K 10% 10% 10% 10% 10% 10%
VCC
TXEN_N
0.1W
B_PORST_N
1%
R212 1K
VCC
0.1W
1% VCC
VCC
U5
C180 C186 C192 C198
50
27
49
28
24
25
75
74
51
77
73
67
16
69
18
71
14
17
35
55
62
64
CY7C9689-AI
1
104 104 104 104

R37 16V 16V 16V 16V
EXTFIFO
TXBISTEN
RXEN
VDD
VDD
VDD
VDD
VDD
VDD
ENCBYP
FIFOBYP
RXMODE(1)
RXMODE(0)
RESET
RXBISTEN
TXRST
RFEN
TXHALT
TXEN
BYTE8/10
TEST
SPDSEL
RANGESEL
RXRST
CE
4.99K 10% 10% 10% 10%

0.1W 80
1% VDDA VCC
CYSC_D 20 87 VCC L1
17[6A] CYSC_D TXSC/D VDDA
TAXI_CLK_22M 12 88 GND C55
17[4B] TAXI_CLK_22M REFCLK VDDA 10u 1uH C57 J2
TXCLK 68 95
17[4B] TXCLK TXCLK VDDA R76 16V 104 1
TXDATA[7..0] 96 10% 50V RXVEE
17[6B] TXDATA[7..0] VDDA 10K SERIALIN_P 2
TXDATA0 22 98 10% RD
TXDATA(0) VDDA 0.1W 33.2 SERIALIN_N 3
TXDATA1 30 0.1W RD
TXDATA(1) 1% R226 4
TXDATA2 32 65 1% RXSC_D SD
TXDATA(2) RXSC/D RXSC_D 17[4A] 5
TXDATA3 34 8 R227 RXCLK RXVCC
TXDATA(3) RXCLK RXCLK 17[4A] 6
C TXDATA4 36 33.2 TXVCC C
TXDATA(4) 0.1W VCC SERIALOUT_N 7
TXDATA5 40 61 R214 33.2 RXDATA0 1% L2 TD
TXDATA(5) RXDATA(0) SERIALOUT_P 8
TXDATA6 42 59 R215 33.2 RXDATA1 TD
TXDATA(6) RXDATA(1) 9
G1
G2
TCMD[3..0] TXDATA7 44 53 R216 33.2 RXDATA2 C54 1uH C58 TXVEE
17[6A] TCMD[3..0] TXDATA(7) RXDATA(2) 10u 104
TCMD3 46 48 R217 33.2 RXDATA3 16V 50V
TXDATA(8)/TXCMD(3) RXDATA(3) 10% 10%
TCMD2 54 47 R218 33.2 RXDATA4
G1
G2
TXDATA(9)/TXCMD(2) RXDATA(4)
TCMD0 56 45 R219 33.2 RXDATA5
TXCMD(0) RXDATA(5) HFBR-5205T
TCMD1 58 43 R220 33.2 RXDATA6 RXDATA[7..0]
TXCMD(1) RXDATA(6) RXDATA[7..0] 17[4B]
41 R221 33.2 RXDATA7 RCMD[3..0]
RXDATA(7) RCMD[3..0] 17[4B]
60 33 R222 33.2 RCMD3
TXEMPTY RXDATA(8)/RXCMD(3)
70 31 R223 33.2 RCMD2
TXHALF RXDATA(9)/RXCMD(2)
72 29 R224 33.2 RCMD0
TXFULL RXCMD(0)
23 R225 33.2 RCMD1
RXCMD(1)
6 VLTN
VLTN VLTN 17[4A]
76
VSSA
79 3 LFI_N
VSSA LFI LFI_N 17[4A]
83 21
VSSA RXEMPTY
84 19
VSSA RXHALF
91 10
VSSA RXFULL
92
CURSETA
CURSETB
VSSA
99 100 CARDET
OUTA+
OUTB+
OUTA-
OUTB-
VSSA CARDET CARDET 17[4A]

INA+
INB+
INA-
INB-
DLB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A/B
R241
4
2
11
13
15
26
37
38
39
52
57
63
66
90
89
97
82
81
78
93
94
86
85
10K
0.1W
R38 R39 VCC 1%
D 10K 10K SERIALIN_P D
0.1W
1%
0.1W
1% SERIALIN_N
Title
TAXI
SERIALOUT_P DTB
SERIALOUT_N Size Number Revision
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 21of 22
1 2 3 4 5 6 7 8
GANTRY 4-21
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
U16A
1
3
2
R184 SN74LV32D
U26D U16D
1K
R233 0.1W 12
9 8
1% 11
1K 13
0.1W 74LVC14A PW
1% SN74LV32D
B B
U6D SN74LV08PW
12
R182 11
1K 13
0.1W
C 1% C
Title
SPARE PARTS D
DTB
A3 5270966 REV : 3
Date: 2008-12-10 Sheet 22of 22
1 2 3 4 5 6 7 8
4-22 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
4-2 DTB DB ASSY (5270966-2)
1 2 3 4
REVISION ECR/ECO DATA SIGN OFF

PAGE NAME
A
1 JAN-2010 LI GuoWang A
SHEET 2 TOP VIEW
SHEET 3 POWER
SHEET 4 MPC8245_SYS
SHEET 5 MPC8245_CONFIG
SHEET 6 MPC8245_MEM
SHEET 7 BUS_BUFFERS
SHEET 8 MPC8245_PCI
SHEET 9 MPC8245_PWR
SHEET 10 SDRAM
B
SHEET 11 FLASH B
SHEET 12 FET_PHY
SHEET 13 UART_PHY
SHEET 14 FPGA_CONFIG
SHEET 18 LEDS
SHEET 19 TAXI
SHEET 20 SPARE PARTS
C C
Title
D D
DTB
A4 5270966-2 REV: 1
Date: 2010/1/12 Sheet 1 of 20
File: D:\DESIGN-TASK\..\1.SchDoc Drawn By:
1 2 3 4
Approved Document - 5270966-2SCH_r1.pdf Page 2 of 21
GANTRY 4-23
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U_4
U_5 4.SchDoc U_17
5.SchDoc 17.SchDoc U_18
PORST_N
18.SchDoc
CLK_33M CLK_33M FPGA_CONF_DONE
PCICLK0 FPGA_STATUS_N FPGA_LED[23..0]
A PCI_SYNC FPGA_TMS A
PLLCFG[4..0] PLLCFG[4..0] FPGA_TCK
MCP_N MCP_N WD_RST_N CPLD_TDI
PMAA[2..0] PMAA[2..0] DSREQ_AB_INT CPLD_TDO
U_15
QACK_N QACK_N ERROR_A-B_INT FPGA_DATA0
15.SchDoc
FOE_N MAA[2..1] MAA[2..1] IRQ~0 AS_N_CLK FPGA_DCLK
RCS0_N D[0..63] DTB_INT FPGA_CONFIG_N FPGA_LED[23..0] CARDET
CKE A[22..0] TGPL_RST_N TAXI_CLK_22M
CYSC_D
RXSC_D
TXEN_N
U_6 U_10
TCMD[3..0]
6.SchDoc 10.SchDoc U_14
RCMD[3..0]
14.SchDoc
CKE A[22..0] A[22..0] INIT_DONE TXDATA[7..0]
D[0..63] D[0..63] BD[0..15] FPGA_CONFIG_N RXDATA[7..0]
CKE BWE_N FPGA_DCLK VLTN
RCS0_N DQM[7..0] BFOE_N FPGA_DATA0 TXCLK
RCS1_N SDCS0_N CPLD_TDO RXCLK
RCS2_N SDCAS_N CPLD_TDI LFI_N
RCS3_N SDRAS_N BA[20..0] FPGA_TCK
FOE_N WE_N RCS2_N FPGA_TMS
AS_N SDCLK[3..0] FPGA_STATUS_N
U_19
DQM[7..0] B_PORST_N FPGA_CONF_DONE
19.SchDoc
SDCS0_N INIT_DONE
SDCAS_N LFI_N
SDRAS_N ENWDT_N RXCLK
WE_N FEEDWDT_N TXCLK
SDCLK[3..0] DISWDT_N VLTN
B AS_N_CLK AS_N TO_CPLD_2 RXDATA[7..0] B
TO_CPLD_1 TXDATA[7..0]
RCMD[3..0]
TCMD[3..0]
B_PORST_N TXEN_N
RXSC_D
CYSC_D
TAXI_CLK_22M
CARDET
U_7 U_11
7.SchDoc 11.SchDoc
U_16
PORST_N RCS0_N RCS0_N NAND_R/B#

16.SchDoc
WE_N RCS1_N NAND_CE_N
FOE_N RCS2_N NAND_RE_N RCS3_N WD_RST_N
A[22..0] RCS3_N NAND_WE_N BFOE_N DSREQ_AB_INT
D[0..63] NAND_CLE BWE_N ERROR_A-B_INT
NAND_ALE BD[0..15] DTB_INT
B_PORST_N B_PORST_N AS_N TO_CPLD_1
BWE_N BWE_N B_PORST_N TO_CPLD_2
BFOE_N BFOE_N NAND_R/B# DISWDT_N
BA[22..0] BA[22..0] NAND_CE_N FEEDWDT_N
BD[0..15] BD[0..15] NAND_RE_N ENWDT_N
NAND_WE_N
NAND_CLE
NAND_ALE
BA[22..0]
RCS2_N RESET_N_BY_JIG
RCS1_N SIMU_XRAY_ON_OUT
C XRAY_ON_IN SAFETY_LOOP_OPEN C
U_8 U_13
8.SchDoc 13.SchDoc
PCI_PAR SOUT1 SOUT1
PCI_SERR SIN1 SIN1 XRAY_ON_IN
PCI_PERR TGPL_RST_N
PCI_STOP SAFETY_LOOP_OPEN
PCI_TRDY PCI_SYNC SIMU_XRAY_ON_OUT
PCI_IRDY RESET_N_BY_JIG
PCI_DEVSEL
PCI_FRAME
PCI_C/BE_N[3..0]
PCI_REQ0_N
PCI_GNT0_N
PCI_AD[31..0]
U_12
12.SchDoc
PCI_AD[31..0] IRQ~0
PCI_GNT0_N
PCI_REQ0_N
PCI_C/BE_N[3..0]
PCI_FRAME PORST_N
PCI_DEVSEL PCICLK0
PCI_IRDY
D PCI_TRDY D
PCI_STOP
PCI_PERR
PCI_SERR
Title
PCI_PAR
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 2 of 20
Approved Document - 5270966-2SCH_r1.pdf Page 3 of 21 File: D:\DESIGN-TASK\..\2.SchDoc Drawn By:
1 2 3 4 5 6 7 8
4-24 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
VCC P2 LT1764 3V3

2 4
A IN OUT A
C121 C125 R174 C129 C133
Vo = 1.21V * (1+1.74K/1K) = 3.32V
GND
22u 104 1 5 1.74K 104 22u
10V 16V SHDN SENSE 0.1W 16V 10V
10% 10% 1% 10% 10%
3
R175
1K
0.1W
1%
VCC P3 LT1764 VDD25

2
IN OUT
4 Vo = 1.21V * (1+1.07K/1K) = 2.50V
C128 C130
C122 104 R176 104 C134 C137 C138
GND
22u 16V 1 5 1.07K 16V 104 104
SHDN SENSE 10% 22u
10V 10% 0.1W 10V 16V 16V
10% 1% 10% 10% 10%
3
R177
1K
0.1W
B 1% B
24V
VCC P4 LT1764 1V9_CORE

2
IN OUT
4 Vo = 1.21V * (1+0.604K/1K) = 1.94V DS25
HSMG-C190
C123 C126 R178 C131 C135 24V
GND
22u 104 1 5 604 104 22u
10V 16V SHDN SENSE 0.1W 16V 10V R192
10% 10% 1% 10% 10%
511
3
0.1W
R179 1%
1K
0.1W R193
1%
511
0.1W
1%
R194
511
VCC P5 LT1764 1V5 0.1W
2 4 1%
IN OUT Vo = 1.21V(1+0.237K/1K) = 1.497V
C C124 C127 R180 C132 C136 R195 C
GND
22u 104 1 5 237 104 22u 511
10V 16V SHDN SENSE 0.1W 16V 10V 0.1W
10% 10% 1% 10% 10%
1%
3
R181 R196
1K 511
0.1W 0.1W
1%
1%
R197
511
0.1W
FB5 1%
BLM31P500S
24V 3V3 VDD25 1V9_CORE 1V5 TP6
J1 F1 24V FB10 P1 FB6 VCC TP2 TP
2 6 TP3 TP4 TP5
24V POWER ON
1 VIN VOUT TP1
2 TP
1.1A/30V C110 BLM31P500S C112 C114 5 C95 BLM31P500S C116 C118 TP TP TP
SENSE TP
Header 2 220u 220u 104 330u 104 100u
GND
GND
50V 50V 50V 16V 16V 16V

20% 20% 20% 3 4 10% 10% 10%
INHIBIT ADJ
VCC TP9 TP10 TP11
R69 3V3
TP TP TP
1
7
21.0K
0.1W TP7
PTN78060W 1%
TP TP8
D TP
POWER D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 3 of 20
1 2 3 4 5 6 7 8
GANTRY 4-25
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
3V3
3V3
R30 R31 R32
R26 R27 R28 R29 10K 1K 10K
A A
10K 10K 10K 10K 0.1W 0.1W 0.1W
R11 R13 R14 R18 R20 0.1W 0.1W 0.1W 0.1W 1% 1% 1%
10K 10K 10K 10K 10K 1% 1% 1% 1%
0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1%
U1D J6
IRQ~0 C19 J2 COP_TDO
2[3A] IRQ~0 IRQ0/SINT DA15 1 2
B21 F1 COP_TDI COP_TRST~
IRQ1/SCLK DA14 3 4
DTB_INT AC22 AF19
2[3A] DTB_INT IRQ2/SRST DA13 5 6

DSREQ_AB_INT AE24 AF17 COP_TCK C_SDMA14
2[3A] DSREQ_AB_INT IRQ3/SFRAME~ DA12 7 8
ERROR_A-B_INT A23 AD26 COP_TMS
2[3A] ERROR_A-B_INT IRQ4/LINT~ DA11 9 10
COP_SRST~
SYSTEM COP_HRST~
11
13
12
14
RTL8139_INT ------> IRQ0 CPU_HRST~ A19
HRST~/CPU~ DA2
C25
15 16
ㅜ14䪸࢚ᯝ
ERROR_A-B_INT ------>IRQ1 A20 B15
HRST~/CTRL~ CKO/DA1
LAST_VIEW_INT ------>IRQ2 F2 QACK_N Header 8X2
1K QACK~/DA0 QACK_N 2[3A]
DSREQ_A_INT ------>IRQ3 0.1W
DSREQ_B_INT ------>IRQ4 R15 1% D16 A16 10K
NMI MIV~
VLTN-----> ? A18 0.1W
SMI~ 1%
R16 AF2 MAA0 R25
3V3 MAA0 3V3
10K AF1 MAA1
MAA1
0.1W Y2 AE1 MAA2
R12 1% RTC MAA2
AD21 MAA[2..1] U3B
OSC_IN MAA[2..1] 2[3A]
4K7 AD18 PMAA0 COP_HRST~ 4
PMAA0
0.1W PLLCFG0 A22 AF18 PMAA1 6 CPU_HRST~
PLLCFG0/DA10 PMAA1
1% PLLCFG1 B19 AE19 PMAA2 PORST_N 5
PLLCFG1/DA9 PMAA2
PLLCFG2 A21 PMAA[2..0]
PLLCFG2/DA8 PMAA[2..0] 2[3A] SN74LV08PW
PLLCFG3 B18
PLLCFG3/DA7
PLLCFG4 B17 A17 MCP_N U3C
B PLLCFG4/DA6 MCP~ MCP_N 2[3A] B
PLLCFG[4..0] PORST_N 9
2[3A] PLLCFG[4..0]
BCOP_TRST~ AE23 8 BCOP_TRST~
TRST~
COP_TMS AE22 COP_TRST~ 10
TMS
COP_TCK AF22
TCK SN74LV08PW
COP_TDI AF23 AE20
TDI SDA
COP_TDO AC21 AF21
TDO SCL C52
R17 AD22
3V3 TEST0~
4K7 3V3 GND
0.1W MPC8245 R22 R24
104
1% 10K 10K 16V
0.1W 0.1W 10%
1% 1%
3V3
R229 PCICLK0
PCICLK0 2[3A]
3V3 51.1
0.1W
C50 U2 1%
3V3 X1 104 6 2
16V VDD CLK2 R58
8 1 10% 4 3 CLK_33M
VCC NC GND CLK1 CLK_33M 2[3A]
C49 5 51.1
104 CLK3
7 0.1W
16V CLK4
10% 4 5 R57 1 8 1%
GND OUT REF CLKOUT
51.1 R228
33MHz 0.1W IDT2305 PCI_SYNC
C 1% PCI_SYNC 2[3A] C
51.1
3V3 0.1W
1%
R19
10K U2 WILL NOT MOUNTED,THE 33M CLK is connect to U2's pin 1,2, & 8 on PWB
0.1W
1%
SW1
6 U3A
5 1
4 3
WD_RST_N 2
G3B15
SN74LV08PW
3V3
3V3 U4
2[3A] WD_RST_N
4
ADM811
2 PORST_N
RST PORST_N 2[3A]
VCC
R183
U3D
10K 12 R23
GND
0.1W 11 R21 3 100K

1% MR 0.1W
TGPL_RST_N 13 C51
2[3A] TGPL_RST_N
SN74LV08PW
100
0.1W 104
1% NOTE : TO FPGA & TAXI
1
1% 16V
10%
D
MPC8245_SYS D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 4 of 20
1 2 3 4 5 6 7 8
4-26 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
CONFIG
SIGNAL NAME CFG_Resistance NOT MOUNTED
R140 R142 R147 R150 R154 R158 R162 R164 R168 R171
A 10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K
0.1W
10K 10K
0.1W 0.1W
D32, FOE R139, R145 R139, R145 A
1% 1% 1% 1% 1% 1% 1% 1% 1% 1%
MAA1 R148 R148
PLLCFG[4..0] MAA2 R152
2[2A] PLLCFG[4..0]
PLLCFG0
PLLCFG1 MCP_N, CKE R159,R163 R159,R163
PLLCFG2
PLLCFG3
PMAA0,PMAA1 R165, R169 R165

PLLCFG4
MCP_N PMAA2 R172 R172
2[2A] MCP_N
CKE
2[1A] CKE
PMAA0 QACK_N R157 R157
PMAA1
PMAA2 RCS0_N R161 R161
PMAA[2..0]
2[2A] PMAA[2..0]
SDMA/AR1 R166
R138 R143 R146 R151 R155 R159 R163 R165 R169 R172
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
SDMA/AR0 R170
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1% 1% 1% 1%
SPEED
B CPU CLOCK R138 R143 R146 R151 R155 B
300MHz MOUNTED MOUNTED MOUNTED MOUNTED NOT

333MHz NOT MOUNTED NOT MOUNTED NOT
3V3 USE 333MHz AT REV:1

R141 R144 R149 R153 R156 R160 R167

10K 10K 10K 10K 10K 10K 10K
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1%
D[0..63]
2[2A] D[0..63]
D32
2[1A] FOE_N Driver capability Configuration
MAA[2..1] FOE_N
2[2A] MAA[2..1]
MAA1
MAA2 PMAA0 PMAA1
QACK_N
2[2A] QACK_N
RCS0_N 0 0 ✺кR165 ✺кR169 ‫⮉؍‬
2[1A] RCS0_N
A1
A0 0 1 ✺кR165 ᣶䲔R169 40⅗
A[22..0] 1 0 ᣶䲔R165 ✺кR169 20⅗
2[2A] A[22..0]
1 1 ᣶䲔R165 ᣶䲔R169 6⅗
C R139 R145 R148 R152 R157 R161 R166 R170 C
1K 1K 1K 1K 1K 1K 1K 1K R164\R168н㾱ࣘ
0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W
1% 1% 1% 1% 1% 1% 1% 1%
See detail on UM page 118
D
MPC8245_CONFIG D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 5 of 20
1 2 3 4 5 6 7 8
GANTRY 4-27
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U1A
C-D0 AC17 AB1 C-DQM0
MDH0 DQM0
C-D1 AF16 AB2 C-DQM1
C-D2 AE16
MDH1
MDH2
MEMORY DQM1
DQM2
K3 C-DQM2
A[22..0]
C-D3 AE14 K2 C-DQM3 RP8 A[22..0] 2[2A]
MDH3 DQM3
C-D4 AF14 AC1 C-DQM4 C-PAR5/AR14 1 8 A14
A MDH4 DQM4 A
C-D5 AC13 AC2 C-DQM5 C-PAR4/AR15 2 7 A15 RP19
MDH5 DQM5
C-D6 AE12 K1 C-DQM6 C-PAR0/AR19 3 6 A19 C-SDCAS~ 1 8 SDCAS_N
MDH6 DQM6 SDCAS_N 2[2B]
C-D7 AE11 J1 C-DQM7 C-PAR1/AR18 4 5 A18 C-SDRAS~ 2 7 SDRAS_N
MDH7 DQM7 SDRAS_N 2[2B]
C-D8 AE10 C-DQM5 3 6 DQM5
MDH8 51.1
C-D9 AE9 Y4 C-SDCS0~ C-DQM4 4 5 DQM4 DQM[7..0]
MDH9 CS~0 0.063W DQM[7..0] 2[2B]
C-D10 AE8 AA3
MDH10 CS~1 5% 51.1
C-D11 AC7 AA4
MDH11 CS~2 RP9 0.063W
C-D12 AE7 AC4
MDH12 CS~3 C-SDMA/AR0 1 8 A0 5%

C-D13 AE6 M2
MDH13 CS~4 C-SDMA/AR1 2 7 A1 RP20
C-D14 AF5 L2
C-D15 AC5 M1
C-D16 E4 L1
MDH16 CS~7 C-SDCS0~ 3 6 SDCS0_N
C-D17 A2 51.1 SDCS0_N 2[2B]
MDH17 C-WE~ 4 5 WE_N
C-D18 B3 0.063W WE_N 2[2B]
MDH18
C-D19 D4 P2 C-SDBA0/AR11 5% 51.1
MDH19 SDBA0
C-D20 B4 P1 C-SDBA1/AR20 0.063W
MDH20 SDBA1 RP10
C-D21 B5 D14 C-SDMA14 5%
MDH21 SDMA14/CHKSTOP_IN C-SDMA/AR6 1 8 A6
C-D22 D6 B14 C-SDMA13/AR23 RP21
MDH22 SDMA13/TBEN C-SDMA/AR5 2 7 A5
C-D23 C6 B16 C-SDMA12/AR22 C-SDBA1/AR20 1 8 A20
MDH23 SDMA12/SRESET~ C-SDMA/AR4 3 6 A4
C-D24 B7 N1 C-SDMA11/AR21 C-RCS0_N 2 7 RCS0_N RCS0_N 2[2B]
MDH24 SDMA11 C-SDMA/AR7 4 5 A7
C-D25 C9 R1 C-SDMA/AR10 C-SDMA11/AR21 3 6 A21
MDH25 SDMA10
C-D26 A9 R2 C-SDMA/AR9 51.1 C-RCS1_N 4 5 RCS1_N
MDH26 SDMA9 RCS1_N 2[2B]
C-D27 B10 T1 C-SDMA/AR8 0.063W
MDH27 SDMA8 51.1
C-D28 A11 T2 C-SDMA/AR7 5%
MDH28 SDMA7 0.063W
C-D29 A13 U4 C-SDMA/AR6 RP11
MDH29 SDMA6 5%
C-D30 B13 U2 C-SDMA/AR5 C-SDMA/AR8 1 8 A8
MDH30 SDMA5 RP22
C-D31 A15 U1 C-SDMA/AR4 C-SDMA/AR9 2 7 A9
MDH31 SDMA4 C-DQM3 1 8 DQM3
C-D32 AD17 V1 C-SDMA/AR3 C-SDMA/AR10 3 6 A10
B MDL0 SDMA3 C-DQM6 2 7 DQM6 B
C-D33 AE17 V3 C-SDMA/AR2 C-SDBA0/AR11 4 5 A11
MDL1 SDMA2 C-DQM2 3 6 DQM2
C-D34 AE15 W1 C-SDMA/AR1
MDL2 SDMA1 51.1 C-DQM7 4 5 DQM7
C-D35 AF15 W2 C-SDMA/AR0
MDL3 SDMA0 0.063W
C-D36 AC14 51.1
MDL4 5%
C-D37 AE13 B20 C-DRDY~ 0.063W
MDL5 DRDY~
C-D38 AF13 Y1 C-AS~ RP12 5%
MDL6 AS~
C-D39 AF12 H1 C-FOE~ 1 8 RP23
MDL7 FOE~
C-D40 AF11 N4 C-RCS0_N C-PAR6/AR13 2 7 A13 C-CKE 1 8 CKE
MDL8 RCS~0 CKE 2[1A]
C-D41 AF10 N2 C-RCS1_N 3 6 C-FOE~ 2 7 FOE_N
MDL9 RCS~1 FOE_N 2[2B]
C-D42 AF9 AF20 C-RCS2_N C-PAR7/AR12 4 5 A12 C-SDCLK2 3 6 SDCLK2
MDL10 TRIG_IN/RCS~2
C-D43 AD8 AC18 C-RCS3_N C-SDCLK1 4 5 SDCLK1
MDL11 TRIG_OUT/RCS~3 51.1

C-D44 AF8 AD2 C-SDCAS~
MDL12 SDCAS~ 0.063W 51.1R
C-D45 AF7 AD1 C-SDRAS~
MDL13 SDRAS~ 5% 0.063W
C-D46 AF6 AA1 C-WE~
MDL14 WE~ 5%
C-D47 AE5 H2 C-CKE RP13
MDL15 CKE RP24
C-D48 B1 C-SDMA13/AR23 1 8
MDL16 C-SDCLK3 1 8 SDCLK3
C-D49 A1 AF3 C-PAR0/AR19 2 7
MDL17 PAR0 C-SDCLK0 2 7 SDCLK0
C-D50 A3 AE3 C-PAR1/AR18 C-SDMA14 3 6 SDMA14
C-D51 A4 G4 C-PAR2/AR17 C-SDMA12/AR22 4 5 A22
C-D52 A5 E2 C-PAR3/AR16
MDL20 PAR3 51.1 SDCLK[3..0]
C-D53 A6 AE4 C-PAR4/AR15 51.1 SDCLK[3..0] 2[2B]
MDL21 PAR4 0.063W
C-D54 A7 AF4 C-PAR5/AR14 0.063W
MDL22 PAR5 5%
C-D55 D7 D2 C-PAR6/AR13 5%
MDL23 PAR6
C-D56 A8 C2 C-PAR7/AR12 RP25
MDL24 PAR7
C-D57 B8 1 8
MDL25
C-D58 A10 D1 C-SDCLK0 2 7
MDL26 SDRAM_CLK0
C-D59 D10 G1 C-SDCLK1 C-RCS2_N 3 6 RCS2_N
MDL27 SDRAM_CLK1 RCS2_N 2[2B]
C C-D60 A12 G2 C-SDCLK2 C-RCS3_N 4 5 RCS3_N C
MDL28 SDRAM_CLK2 RCS3_N 2[2B]
C-D61 B11 E1 C-SDCLK3
MDL29 SDRAM_CLK3 51.1 3V3
C-D62 B12 C1 R1 100
MDL30 SDRAM_SYNC_OUT 0.063W
C-D63 A14 H3
MDL31 SDRAM_SYNC_IN 5% 10K
51.1 0.063W
MPC8245 R2 0.1W AS_N RP30 5%
C-AS~ RCS2_N 1 8
SDRAM Clock Trace must be same 1%
AS_N 2[2B]
RCS3_N
RCS0_N
2
3
7
6
51.1 RCS1_N 4 5
R78 0.1W AS_N_CLK
AS_N_CLK 2[2B]
1% 10K
0.1W
R3 1%
R78 NOT MOUNTED C-DRDY~
10K
0.1W
C-AS~ R4 1%
C-D10
C-D11
C-D12
C-D13
C-D14
C-D15
C-D16
C-D17
C-D18
C-D19
C-D20
C-D21
C-D22
C-D23
C-D24
C-D25
C-D26
C-D27
C-D28
C-D29
C-D30
C-D31
C-D32
C-D33
C-D34
C-D35
C-D36
C-D37
C-D38
C-D39
C-D40
C-D41
C-D42
C-D43
C-D44
C-D45
C-D46
C-D47
C-D48
C-D49
C-D50
C-D51
C-D52
C-D53
C-D54
C-D55
C-D56
C-D57
C-D58
C-D59
C-D60
C-D61
C-D62
C-D63
10K
C-D0
C-D1
C-D2
C-D3
C-D4
C-D5
C-D6
C-D7
C-D8
C-D9
0.1W
C-FOE~ R5 1%
10K
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
0.1W
RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP14 RP15 RP16 RP17 RP18 RP26 RP27 RP28 RP29 R6 1%
C-WE~
51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1 51.1
0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W 0.063W
5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
D D
MPC8245_MEM
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Title
DTB
D[0..63]
D[0..63] 2[2B]
A3 5270966-2 REV :1
Date: 2010/1/12 Sheet 6 of 20
1 2 3 4 5 6 7 8
4-28 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
BD[0..15] U7 D[0..63]
2[2A] BD[0..15] D[0..63] 2[2A]
BD0 47 2 D0
A0 B0
BD1 46 3 D1
A1 B1
BD2 44 5 D2
A2 B2
BD3 43 6 D3
A3 B3
BD4 41 8 D4
A4 B4
C63 BD5 40 9 D5
A5 B5
A BD6 38 11 D6 A
3V3 A6 B6
BD7 37 12 D7
104 A7 B7
BWE_N 1
16V T/R1
10% 48
OE1
BD8 36 13 D8
A8 B8
U6A BD9 35 14 D9
A9 B9
RCS0_N 1 BD10 33 16 D10
2[1A] RCS0_N A10 B10
BD11 D11
3 32 17
A11 B11
RCS1_N 2 BD12 30 19 D12
2[1A] RCS1_N A12 B12
BD13 29 20 D13
SN74LV08PW A13 B13
BD14 27 22 D14
A14 B14
U6C BD15 26 23 D15
51.1 A15 B15
9 0.1W BWE_N 24
T/R2
8 R98 1% 25 4
OE2 GND
10 3V3 10
7
GND
15 Integrated 30 ohm termination resistors
SN74LV08PW VCC GND
C60 C61 C62 C64 18
VCC GND
21 to reduce line noise
U6B 31 28
VCC GND
RCS2_N 4 104 104 104 104 42 34
2[1A] RCS2_N 16V 16V 16V 16V VCC GND
6 10% 10% 10% 10% 39
GND
RCS3_N 5 45
2[1A] RCS3_N GND
SN74LV08PW 74ALVC162245A
A[22..0] U9
2[2A] A[22..0]
A0 47 2 BA0
B 1A0 1Y0 B
A1 46 3 BA1
1A1 1Y1
A2 44 5 BA2
1K 1A2 1Y2
0.1W A3 43 6 BA3
1A3 1Y3
R48 1% 1
1OE
A20 41 8 BA20
2A0 2Y0
A21 40 9 BA21
2A1 2Y1
A22 38 11 BA22
1K 2A2 2Y2
0.1W 37 12
2A3 2Y3
R49 1% 48
2OE
WE_N 36 13 BWE_N
2[1A] WE_N 3A0 3Y0 BWE_N 2[2A]
FOE_N 35 14 BFOE_N
2[1A] FOE_N 3A1 3Y1 BFOE_N 2[2A]

PORST_N 33 16 B_PORST_N
2[1A] PORST_N 3A2 3Y2 B_PORST_N 2[2A]
32 17
3A3 3Y3
R75 1K 25
3OE
0.1W 30 19
1% 4A0 4Y0
29 20
4A1 4Y1
27 22
4A2 4Y2
26 23
4A3 4Y3
R173 1K 24
4OE
0.1W 4
1% GND
7 10
VCC GND
18 15
VCC GND
3V3 31 21
VCC GND
42 28
VCC GND
C69 C100 C101 C111 34
GND
39
GND
104 104 104 104 45
GND
C 16V 16V 16V 16V C
10% 10% 10% 10% 74LVC162244A
U8
A4 47 2 BA4
1A0 1Y0
A5 46 3 BA5
1A1 1Y1
A6 44 5 BA6
1A2 1Y2
A7 43 6 BA7
1A3 1Y3
R50 1K 1
1OE
0.1W A8 41 8 BA8
1% 2A0 2Y0
A9 40 9 BA9
2A1 2Y1
A10 38 11 BA10
2A2 2Y2
A11 37 12 BA11
2A3 2Y3
R51 1K 48
2OE
0.1W A12 36 13 BA12
1% 3A0 3Y0
A13 35 14 BA13
3A1 3Y1
A14 33 16 BA14
3A2 3Y2
A15 32 17 BA15
3A3 3Y3
R52 1K 25
3OE
0.1W A16 30 19 BA16
1% 4A0 4Y0
A17 29 20 BA17
4A1 4Y1
A18 27 22 BA18
4A2 4Y2
A19 26 23 BA19
4A3 4Y3
R53 1K 24 BA[22..0]
4OE BA[22..0] 2[2A]
0.1W 4
1% GND
7 10
VCC GND
18 15
D 3V3
C65 C66 C67 C68

31
42
VCC
VCC
VCC
GND
GND
GND
GND
21
28
34
39
Integrated 30 ohm termination resistors
to reduce line noise
BUS_BUFFERS D
GND Title
104 104 104 104 45
16V 16V 16V 16V GND DTB
10% 10% 10% 10%
74LVC162244A
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 7 of 20
1 2 3 4 5 6 7 8
GANTRY 4-29
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
IDSEL R8
1K
0.1W
1%
PCI_AD[31..0] U1B
14[1A] PCI_AD[31..0]
PCI_AD31 V25 J24 PCI_FRAME
AD31 PCI FRAME~ PCI_FRAME 14[2C]
PCI_AD30 U25 H26 PCI_DEVSEL 10K 3V3
AD30 DEVSEL~ PCI_DEVSEL 14[2C] 0.063W
PCI_AD29 U26 K25 PCI_IRDY RP32 5%
AD29 IRDY~ PCI_IRDY 14[2C]
PCI_AD28 U24 K26 PCI_TRDY PCI_PERR 1 8
AD28 TRDY~ PCI_TRDY 14[2C]
PCI_AD27 U23 2 7
AD27
PCI_AD26 T25 J26 PCI_LOCK PCI_SERR 3 6
AD26 LOCK~
PCI_AD25 T26 H25 PCI_STOP PCI_PAR 4 5
AD25 STOP~ PCI_STOP 14[2C]
PCI_AD24 R25 G26 PCI_PERR
AD24 PERR~ PCI_PERR 14[2C]
PCI_AD23 R26 F26 PCI_SERR
AD23 SERR~ PCI_SERR 14[2C] 10K
PCI_AD22 N26
AD22 0.063W
PCI_AD21 N25 AC26 INTA~ RP35 5%
AD21 INTA~
PCI_AD20 N23 PCI_STOP 1 8
AD20
PCI_AD19 M26 PCI_DEVSEL 2 7
B AD19 B
PCI_AD18 M25 AB26 PCI_REQ0_N PCI_LOCK 3 6
AD18 REQ~0 PCI_REQ0_N 14[2C]
PCI_AD17 L25 AA25 PCI_REQ1# PCI_IRDY 4 5
PCI_AD16 L26
AD17
AD16
REQ~1
REQ~2
AA26 PCI_REQ2# PULLUPS
PCI_AD15 F24 Y25 PCI_REQ3#
AD15 REQ~3
PCI_AD14 E26 Y26 PCI_REQ4# IDSEL0=AD22
AD14 REQ~4/DA4 10K
PCI_AD13 E25
AD13 0.063W
PCI_AD12 E23 V26 PCI_GNT0_N RP34 5%
AD12 GNT~0 PCI_GNT0_N 14[2C]
PCI_AD11 D26 W23 PCI_GNT1# INTA~ 1 8
AD11 GNT~1
AD10 GNT~2
PCI_AD9 C26 W25 PCI_GNT3# PCI_REQ2# 3 6
AD9 GNT~3
PCI_AD8 A26 W26 PCI_GNT4# PCI_REQ4# 4 5
AD8 GNT~4/DA5
PCI_AD7 B26
AD7
PCI_AD6 A24
AD6
PCI_AD5 B24 AC25 SOUT1 10K
AD5 SOUT1/PCICLK0 SOUT1 15[1C] 0.063W
PCI_AD4 D19 AB25 SIN1 RP33 5%
AD4 SIN1/PCICLK1 SIN1 15[1C]
PCI_AD3 B23 AE26 PCI_REQ3# 1 8
AD3SOUT2/RTS~1/PCICLK2 R7
PCI_AD2 B22 AF25 PCI_GNT1# 2 7
AD2 SIN2/CTS~1/PCICLK3 3V3
PCI_AD1 D22 AF26 10K PCI_GNT2# 3 6
AD1 DA3/PCICLK4
PCI_AD0 C22 0.1W PCI_GNT4# 4 5
AD0
1%
PCI_PAR G25
14[1B] PCI_PAR PAR
AD25
PCI_SYNC_OUT
IDSEL P26 10K
IDSEL 0.063W
PCI_C/BE_N[3..0] AB23 PCI_SYNC RP31 5%
14[1B] PCI_C/BE_N[3..0] PCI_SYNC_IN PCI_SYNC 6[5C]
PCI_C/BE_N3 P25 PCI_TRDY 1 8
C/BE~3
PCI_C/BE_N2 K23 PCI_GNT0# 2 7
C/BE~2
PCI_C/BE_N1 F23 PCI_REQ0# 3 6
C/BE~1
C PCI_C/BE_N0 A25 PCI_GNT3# 4 5 C
C/BE~0
MPC8245
D
MPC8245_PCI D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 8 of 20
1 2 3 4 5 6 7 8
4-30 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
1V9_CORE
R9
C6 C11 10
3V3 U1C 2u2 2u2 0.1W
A 35V 35V 1% A
Y3 C17 10% 10%
GVDD AVDD
V4 AF24
U3
GVDD
GVDD
POWER AVDD2
R3 AA2
GVDD GND R10
P4 AA23
GVDD GND
N3 AC12 C7 C12 10
GVDD GND 2u2 2u2
L4 AC15 0.1W
GVDD GND 35V 35V 1%
K4 AC24 10% 10%

GVDD GND
H4 AC3
GVDD GND
G3 AC6
GVDD GND
E3 AC9
GVDD GND
D9 AD11
GVDD GND
D5 AD14
GVDD GND
D13 AD16
GVDD GND
C7 AD19
GVDD GND
C5 AD23
GVDD GND
C3 AD4
GVDD GND
C12 AE18
GVDD GND
C10 AE2
GVDD GND
AD7 AE21
GVDD GND
AD5 AE25
GVDD GND
AD3 B2
GVDD GND
AD15 B25
GVDD GND
AD13 B6 3V3
GVDD GND
AD10 B9
GVDD GND
AC8 C11
GVDD GND C2 C3 C4 C5 C8 C9 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C33 C35 C37 C39 C41 C43 C45 C47
AC11 C13 C1
GVDD GND
B AC10 C16 B
GVDD GND 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 100u
AB4 C23 104 100u
GVDD GND 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
AB3 C4 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
GVDD GND
C8
GND
AC20 D12
LVDD1 GND
AC23 D15
LVDD2 GND
D20 D18
LVDD3 GND
D23 D21
LVDD4 GND
G23 D24
LVDD5 GND
P23 D3 1V9_CORE
LVDD6 GND
Y23 F25
LVDD7 GND
3V3 F4 C46 C48

GND C10 C14 C16 C18 C20 C22 C24 C26 C28 C30 C32 C34 C36 C38 C40 C42 C44
Y24 H24
OVDD GND
T23 J25 104 104 104 104 104 104 104 104 104 104 100u 100u
OVDD GND 104 104 104 104 104 104 104
P24 J4 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 10V 10V
OVDD GND 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
M24 L24
OVDD GND
K24 L3
OVDD GND
J23 M23
OVDD GND
G24 M4
OVDD GND
E24 N24
OVDD GND
C24 P3
OVDD GND
C20 R23
OVDD GND
C14 R4
OVDD GND
AD24 T24 3V3 D1 D2 D51V9_CORE
OVDD GND
AD20 T3 1 2
OVDD GND
AB24 V2
OVDD GND
1V9_CORE V23 1N4148 1N4148 1N4148
GND
AA24 W3
C VDD GND D3 C
AC16
VDD
AC19
VDD
AD12
VDD
AD6 1N4148
VDD D4
AD9
VDD
C15
VDD
C18
VDD
C21 1N4148
VDD
D11
VDD
D8
VDD NOTE : In order to protect device in case of
F3
H23
VDD power on (3.3V/1.9V) sequence.
VDD
J3
VDD
L23
VDD
M3
VDD
R24
VDD
T4
VDD
V24
VDD
W4
VDD
MPC8245
D
MPC8245_PWR D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 9 of 20
1 2 3 4 5 6 7 8
GANTRY 4-31
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
3V3
C149 C151 C153 C155 C157 C159 C161

C139 C141 C143 C145 C147 104 104 104 104 104 104
104 104 104 104 104 104 16V 16V 16V 16V 16V 16V
16V 16V 16V 16V 16V 16V 10% 10% 10% 10% 10% 10%
10% 10% 10% 10% 10% 10%
A[22..0]
A 2[3A] A[22..0] A
3V3
3V3
A9
A7
D3
B3
C7
E7
J9
A9
A7
D3
B3
C7
E7
J9
U31
U29
MT48LC16M16A2BG
MT48LC16M16A2BG
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7 A0
A0 A1 H8
A1 H8 A1
A1 A2 J8 A8 D48
D32
A2 J8 A8 A2 DQ0
A2 DQ0 A3 J7 B9 D49
A3 J7 B9 D33 A3 DQ1
A3 DQ1 A4 J3 B8 D50
A4 J3 B8 D34 A4 DQ2
A4 DQ2 A5 J2 C9 D51
A5 J2 C9 D35 A5 DQ3
A5 DQ3 A6 H3 C8 D52
A6 H3 C8 D36 A6 DQ4
A6 DQ4 A7 H2 D9 D53
A7 H2 D9 D37 A7 DQ5
A7 DQ5 A8 H1 D8 D54
A8 H1 D8 D38 A8 DQ6
A8 DQ6 A9 G3 E9 D55
A9 G3 E9 D39 A9 DQ7
A9 DQ7 A10 H9 E1 D56
A10 H9 E1 D40 A10/AP DQ8
A10/AP DQ8 A21 G2 D2 D57
A21 G2 D2 D41 A11 DQ9
A11 DQ9 A22 G1 D1 D58
A22 G1 D1 D42 A12 DQ10
A12 DQ10 C2 D59
C2 D43 DQ11
DQ11 A11 G7 C1 D60
A11 G7 C1 D44 BA0 DQ12
BA0 DQ12 A20 G8 B2 D61
A20 G8 B2 D45 BA1 DQ13
BA1 DQ13 B1 D62
B1 D46 DQ14
CS DQ15 SDCAS_N F7
SDCAS_N F7 CAS
CAS SDRAS_N F8
SDRAS_N F8 RAS
RAS WE_N F9 E2
WE_N F9 E2 WE NC
WE NC DQM6 E8
DQM4 E8 LDQM
LDQM DQM7 F1 A3
B DQM5 F1 A3 UDQM VSSQ B
2[3B] DQM[7..0] UDQM VSSQ B7
B7 VSSQ
2[3B] SDCLK[3..0] VSSQ SDCLK3 F2 C3
VSS
VSS
VSS
CLK VSSQ CKE F3 D7
VSS
VSS
VSS
CKE F3 D7 CKE VSSQ
CKE VSSQ
A1
E3
J1
A1
E3
J1
3V3
3V3
C152 C154 C156 C158 C160 C162

C140 C142 C144 C146 C148 C150 104 104 104 104 104 104
104 104 104 104 104 104 16V 16V 16V 16V 16V 16V
16V 16V 16V 16V 16V 16V 10% 10% 10% 10% 10% 10%
10% 10% 10% 10% 10% 10%
3V3
3V3
A9
A7
D3
B3
C7
E7
J9
A9
A7
D3
B3
C7
E7
J9
U32
U30
MT48LC16M16A2BG
MT48LC16M16A2BG
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
A0 H7 A0
A0 A1 H8
A1 H8 A1
A1 A2 J8 A8 D16
A2 J8 A8 D0 A2 DQ0
C A2 DQ0 A3 J7 B9 D17 C
A3 J7 B9 D1 A3 DQ1
A3 DQ1 A4 J3 B8 D18
A4 J3 B8 D2 A4 DQ2
A4 DQ2 A5 J2 C9 D19
A5 J2 C9 D3 A5 DQ3
A5 DQ3 A6 H3 C8 D20
A6 H3 C8 D4 A6 DQ4
A6 DQ4 A7 H2 D9 D21
A7 H2 D9 D5 A7 DQ5
A7 DQ5 A8 H1 D8 D22
A8 H1 D8 D6 A8 DQ6
A8 DQ6 A9 G3 E9 D23
A9 G3 E9 D7 A9 DQ7
A9 DQ7 A10 H9 E1 D24
A10 H9 E1 D8 A10/AP DQ8
A10/AP DQ8 A21 G2 D2 D25
A21 G2 D2 D9 A11 DQ9
A11 DQ9 A22 G1 D1 D26
A22 G1 D1 D10 A12 DQ10
A12 DQ10 C2 D27
C2 D11 DQ11
DQ11 A11 G7 C1 D28
A11 G7 C1 D12 BA0 DQ12
BA0 DQ12 A20 G8 B2 D29
A20 G8 B2 D13 BA1 DQ13
BA1 DQ13 B1 D30
B1 D14 DQ14
2[3B] SDCS0_N CS DQ15 SDCAS_N F7
SDCAS_N F7 CAS
2[3B] SDCAS_N CAS SDRAS_N F8
SDRAS_N F8 RAS
2[3B] SDRAS_N RAS WE_N F9 E2
WE_N F9 E2 WE NC
2[3B] WE_N WE NC DQM2 E8
DQM0 E8 LDQM
LDQM DQM3 F1 A3
DQM1 F1 A3 UDQM VSSQ
UDQM VSSQ B7
B7 VSSQ
VSSQ SDCLK1 F2 C3
VSS
VSS
VSS
CLK VSSQ CKE F3 D7
VSS
VSS
VSS
CKE F3 D7 CKE VSSQ

2[3B] CKE CKE VSSQ
A1
E3
J1
A1
E3
J1
D D[0..63] D
2[3B] D[0..63]
DQM[7..0]
SDCLK[3..0]
Title
SDRAM
DTB
Approved Document - 5270966-2SCH_r1.pdf Page 11 of 21

SDRAM 128MB A3
Date:
File:
2010/1/12
5270966-2
D:\DESIGN-TASK\..\10.SchDoc
Sheet 10 of 20
Drawn By:
REV : 1
1 2 3 4 5 6 7 8
4-32 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
BA[22..0]
18[3B], 9[6D] BA[22..0] U12 BD[0..15]
BD[0..15] 16[3B], 18[6C], 9[3A]
BA1 E1 E2 BD7
A0 DQ0
BA2 D1 H2 BD6
A1 DQ1
BA3
C1 E3 BD5
A2 DQ2
BA4 A1
A3 DQ3
H3 BD4 Big Endian
BA5 B1 H4 BD3
A4 DQ4
BA6 D2 E4 BD2
A5 DQ5
BA7 C2 H5 BD1
A6 DQ6
BA8 A2 E5 BD0
A7 DQ7
BA9 B5
A8
BA10 A5 F2
A9 DQ8
BA11 C5 G2
A10 DQ9
BA12 D5 F3
A11 DQ10
BA13 B6 G3
A12 DQ11
BA14 A6 F4
A13 DQ12
BA15 C6 G5
A14 DQ13
BA16 D6 F5
A15 DQ14
BA17 E6 G6 BA0
A16 DQ15/A-1
BA18 B2
A17 R71
BA19 C3 F6
A18 BYTE#
BA20 D4 A3
A19 RY/BY# 1K
BA21 D3 0.1W
A20 1%
BA22 C4
A21
B 3V3 B
RCS0_N F1 G4
7[3C], 8[6B], 9[2A] RCS0_N CE# VCC
BFOE_N G1 C85
16[3B], 18[6B], 9[6B] BFOE_N OE# 104
BWE_N A4 16V
16[3B], 18[6B], 9[6B] BWE_N WE#
B3 H1 10%
R70 WP#/ACC VSS
B4 H6
3V3 RESET# VSS
4.99K
0.1W S29GL064N-90BFIR40
1%
BOOT FLASH
U25 HY27US08121A
NAND_CE_N 9 29 BD7
18[6A] NAND_CE_N CE I/O0
C NAND_RE_N 8 30 BD6 C
18[6A] NAND_RE_N RE I/O1
NAND_WE_N 18 31 BD5
18[6A] NAND_WE_N WE I/O2
NAND_CLE 16 32 BD4
18[6A] NAND_CLE CLE I/O3
NAND_ALE 17 41 BD3
18[6A] NAND_ALE ALE I/O4
42 BD2
I/O5
B_PORST_N 19 43 BD1
16[3C], 18[3A], 21[3B], 9[6B] B_PORST_N WP I/O6
NAND_R/B# 7 44 BD0
18[6A] NAND_R/B# R/B I/O7
3V3 12 13
VDD VSS
37 36
VDD VSS
3V3 C113 C115
R242 104 104
10K
16V
10%
16V
10% NAND FLASH
0.1W
1%
Title
FLASH D
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 11 of 20
1 2 3 4 5 6 7 8
GANTRY 4-33
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
27P
50V
C80 10%
Y1
25MHz
A PCI_AD[31..0] U10 A
10[1B] PCI_AD[31..0]
PCI_AD31 33 121 C275
PCI_AD31 X1
PCI_AD30 34 122 27P
PCI_AD30 X2 50V
PCI_AD29 36
PCI_AD29 10%
PCI_AD28 37 27 PORST_N
PCI_AD28 RST# PORST_N 6[5D], 9[2B]
PCI_AD27 39
PCI_AD27
PCI_AD26 40 U17 3V3
PCI_AD26
PCI_AD25 42 106 1 8
PCI_AD25 EECS CS VCC

PCI_AD24 43 111 2 7 1K C104
PCI_AD24 EESK SK NC 104
PCI_AD23 47 109 3 6 R83 0.1W 16V
PCI_AD23 AUX/EEDI DI ORG
PCI_AD22 49 108 4 5 1% 10%
PCI_AD22 EEDO DO GND
PCI_AD21 50
PCI_AD21
PCI_AD20 53 117 ACT_LED- AT93C46
PCI_AD20 LED0
PCI_AD19 55 115 LNK_LED-
PCI_AD19 LED1
PCI_AD18 57 114
PCI_AD18 LED2
PCI_AD17 58
PCI_AD17
PCI_AD16 59 1 ETH_TXD+
PCI_AD16 TXD+
PCI_AD15 79 2 ETH_TXD-
PCI_AD15 TXD-
PCI_AD14 82
PCI_AD14
PCI_AD13 83
PCI_AD13
PCI_AD12 85
PCI_AD12
PCI_AD11 86 5 ETH_RXIN+
PCI_AD11 RXIN+
PCI_AD10 87 6 ETH_RXIN-
PCI_AD10 RXIN-
PCI_AD9 89
PCI_AD9
PCI_AD8 90
PCI_AD8
PCI_AD7 93
PCI_AD7
PCI_AD6 95
PCI_AD6
PCI_AD5 96
B PCI_AD5 B
PCI_AD4 97
PCI_AD4
PCI_AD3 98
PCI_AD3
PCI_AD2 102 8
PCI_AD2 CTRL25 5K6
PCI_AD1 103 0.1W 3V3
PCI_AD1
PCI_AD0 104 127 R55 1%
PCI_AD0 RSET FB8
R60 301 BLM21PG331SN1
PCI_PAR 76 65 0.1W
10[1C] PCI_PAR PCI_PAR CLKRUN# 4.99K 1K 330ohm
PCI_C/BE_N[3..0] 0.1W LNK_LED- R66 1%
10[1C] PCI_C/BE_N[3..0] 0.1W
PCI_C/BE_N3 44 31 R56 1% 3V3 1%
PCI_C/BE#3 PME# 301
PCI_C/BE_N2 60 23
PCI_C/BE#2 ISOLATE# 0.1W
PCI_C/BE_N1 77 105 3V3
PCI_C/BE#1 LWAKE ACT_LED- R67 1%

PCI_C/BE_N0 92 R61
PCI_C/BE#0 10K
26 FB7
VDD33 0.1W FB9
PCI_FRAME 61 41 1% BLM21PG331SN1
10[4B] PCI_FRAME PCI_FRAME# VDD33 BLM21PG331SN1
PCI_DEVSEL 68 56 330ohm
10[4B] PCI_DEVSEL PCI_DEVSEL# VDD33 3V3 C276 C277 J3 330ohm
PCI_IRDY 63 71 104 104
10[4B] PCI_IRDY PCI_IRDY# VDD33 R59 16V 16V
PCI_TRDY 67 84
10[4B] PCI_TRDY PCI_TRDY# VDD33 4.99K 10% 10% C53
PCI_STOP 69 94
10[4B] PCI_STOP PCI_STOP# VDD33 0.1W 9 10
PCI_PERR 70 107 1%
10[4B] PCI_PERR PCI_PERR# VDD33
PCI_SERR 75 3 AVDD1 104
10[4B] PCI_SERR PCI_SERR# AVDD33 7 8
PCI_AD22 R54 46 7 AVDD2 16V
PCI_IDSEL# AVDD33
100 IRQ~0 25 20 AVDD3 10%
IDSEL0=AD22 6[2A] IRQ~0 PCI_INTA# AVDD33 1
0.1W PCI_REQ0_N 30 32 CT
1% 10[4B] PCI_REQ0_N PCI_REQ# VDD25 ETH_TXD+ 2
PCI_GNT0_N 29 54 FB4 TD+
10[4B] PCI_GNT0_N PCI_GNT# VDD25 ETH_TXD- 3
SELECT PCI ID 78 VDD25 BLM21PG331SN1 TD-
VDD25 330ohm ETH_RXIN+ 4
PCICLK0 28 99 RD+
6[5C] PCICLK0 PCI_CLK VDD25 ETH_RXIN- 5 11
12 RD-
AVDD25 6 12
C 4 C78 CT C
GND
81 17 104
GND GND 16V C84 104 JP011821U
91 21 10%
GND GND
100 35
GND GND
101 38
GND GND
119 51
GND GND CH_GND
123 52
GND GND
ETH_TXD-
ETH_TXD+
ETH_RXIN-
ETH_RXIN+
124 66 R234
GND GND VCC R68
128 80 0
GND GND ETH_TXD+ ETH_TXD- 0
RTL8100CL-LF GND CH_GND
6
5
4
GND CH_GND
3V3 U24
SRV05-4 R235 R236
C71 C72 C73 C74 C75 C77 C97 R62 R63 R64 R65
104 104 104 104 104 104 104 0 0
16V 16V 16V 16V 16V 16V 16V 51.1 51.1 51.1 51.1
10% 10% 10% 10% 10% 10% 10% 0.1W 0.1W 0.1W 0.1W
1
2
3
1% 1% 1% 1% ETH_RXIN+ ETH_RXIN- GND CH_GND GND CH_GND
R237
R238
C82 C83
104 104 0
16V 16V 0
10% 10% GND CH_GND
GND CH_GND
Not mounted
FB1 FB2 FB3
BLM21PG331SN1 BLM21PG331SN1 BLM21PG331SN1
AVDD1 AVDD2 AVDD3

D
3V3
330ohm C70
104
16V
10%
3V3
330ohm C76
104
16V
10%
3V3
330ohm C79
104
16V
10%
FET_PHY D
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 12 of 20
1 2 3 4 5 6 7 8
4-34 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3 3V3 3V3 3V3 3V3 3V3
D6 D8 D10 D12 D14 D16

1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
OUTA_P OUTA_N OUTB_P OUTB_N OUTC_P OUTC_N
A A
D7 D9 D11 D13 D15 D17
1N4148 1N4148 1N4148 1N4148 1N4148 1N4148
3V3
C168 3V3
R186
R185
1K 104
1K 16V
0.1W 0.1W 10%
1% 1% U35
4 16 51.1
OE VDD 0.063W
12 RP42 5%
OE
SIMU_XRAY_ON_OUT 1 2 OUTA_P 1 8 SIMU_XRAY_ON_OUT_P
18[6B] SIMU_XRAY_ON_OUT IN A OUT A
3 OUTA_N 2 7 SIMU_XRAY_ON_OUT_N
OUT A
RESET_N_BY_JIG 7 6 OUTB_P 3 6 RESET_N_BY_JIG_P
18[6B] RESET_N_BY_JIG IN B OUT B
5 OUTB_N 4 5 RESET_N_BY_JIG_N
OUT B
SAFETY_LOOP_OPEN 9 10 OUTC_P 1 8 SAFETY_LOOP_OPEN_P
18[6B] SAFETY_LOOP_OPEN IN C OUT C
11 OUTC_N 2 7 SAFETY_LOOP_OPEN_N
OUT C
15 14 3 6
IN D OUT D
13 4 5
R244 R900 R901 R191 OUT D
8 RP43 51.1
1K 1K 1K 1K GND
0.1W 0.063W
B 0.1W 0.1W 0.1W 1% DS26LV31AT 5% B
1% 1% 1%
C165 3V3
104
16V U34
10%
16
MAX3232
C163 104 1 2
C1+ V+ 104 VCC
16V
VCC
10% C169 16V

3 C167
C1- 104 10%
C166 51.1 R189 R190 U26A U26B
C164 104 4 6 16V 0.1W
C2+ V- 10% TGPL_RST_N_P R187 1% U36 1K 1K
16V R79 1 2 3 4 R230 TGPL_RST_N
10% 1 8 0.1W 0.1W TGPL_RST_N 6[2D]
5 104 51.1 + VCC 100 51.1
C2- 16V 1% 1% 0.1W 0.1W
10% 0.1W C117
TGPL_RST_N_N R188 1% 2 7 1% 74LVC14A PW 74LVC14A PW 1%
SOUT1 11 14 COM_TXD - V01 470P
10[4C] SOUT1 T1IN T1OUT 16V
10 7
T2IN T2OUT XRAY_ON_N R201 3 6 10% U26C
- V02
51.1
SIN1 12 13 COM_RXD 0.1W
GND
10[4C] SIN1 R1OUT R1IN 1% 4 5 R231 5 6 R232 XRAY_ON_IN

9 8 + GND XRAY_ON_IN 18[6B]
R2OUT R2IN XRAY_ON_P R202 100 51.1
51.1 HCPL-0631 0.1W C119 0.1W
0.1W 1% 470P 74LVC14A PW 1%
15
1% 16V 7 14
GND VDD 3V3
10%
C120
C C
104
16V
J5 10%
COM_TXD
1
COM_RXD
2
J4
3
SIMU_XRAY_ON_OUT_P SIMU_XRAY_ON_OUT_N
1 2
Header 3 RESET_N_BY_JIG_P RESET_N_BY_JIG_N
3 4
WIRE TO BOARD SAFETY_LOOP_OPEN_P SAFETY_LOOP_OPEN_N
5 6
TGPL_RST_N_P TGPL_RST_N_N
7 8
RS-232 CONSOLE XRAY_ON_P
9 10
XRAY_ON_N
Header 5X2
FOR DEBUGGING
RS-422
D D
Title
UART_PHY
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 13 of 20
1 2 3 4 5 6 7 8
GANTRY 4-35
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3
R105
10K
0.1W
1%
U20A
A FPGA_DCLK 2 A
19[4A] FPGA_DCLK IO
BANK A
ENWDT_N 3
18[6B] ENWDT_N IO
FEEDWDT_N 5
18[6B] FEEDWDT_N IO
DISWDT_N 6
18[6B] DISWDT_N IO
TO_CPLD_1 42
18[3A] TO_CPLD_1 IO
TO_CPLD_2 43
18[3A] TO_CPLD_2 IO
AS_N 44
18[6B], 8[6C] AS_N IO
EPM3064ATC44-4
BA[20..0] U20B
13[3A], 18[3B], 9[6D] BA[20..0]
BA8 8
IO
BANK B
BA9 10
IO
BA10 12
IO
RCS2_N 13
18[6B], 8[6C], 9[2B] RCS2_N IO
BWE_N 14
13[3B], 18[6B], 9[6B] BWE_N IO
BFOE_N 15
13[3B], 18[6B], 9[6B] BFOE_N IO
EPM3064ATC44-4
BD[0..15] U20C
13[6A], 18[6C], 9[3A] BD[0..15]
BD6 25
IO
BANK C
BD5 23
B IO B
BD4 22
IO
BD3 21
IO
BD2 20
IO
BD1 19
IO
BD0 18
IO
3V3
EPM3064ATC44-4
R107 R103 R89

10K 10K 10K
0.1W
0.1W 0.1W 1%
1% 1%
U20D
FPGA_CONFIG_N 35
19[4A] FPGA_CONFIG_N IO
BANK D
FPGA_DATA0 34
19[4A] FPGA_DATA0 IO
FPGA_STATUS_N 33
19[4B] FPGA_STATUS_N IO
FPGA_CONF_DONE 31
19[4B] FPGA_CONF_DONE IO
INIT_DONE 28
17[4C] INIT_DONE IO
B_PORST_N 27
13[3C], 18[3A], 21[3B], 9[6B] B_PORST_N IO
EPM3064ATC44-4
C C
U20E
37
INPUT/GCLK1
40
INPUT/OE2/GCLK2
38 3V3 U20G 3V3
R902 INPUT/OE1
39 29 41
INPUT/GCLRn VCCIO(2.5V OR 3.3V) VCCINT(3.3V ONLY)
1K 9 17
C105 C106 VCCIO(2.5V OR 3.3V) VCCINT(3.3V ONLY) C102 C103
0.1W EPM3064ATC44-4
104 104 EPM3064ATC44-4 104 104
1%
50V 50V 50V 50V
10% 10% 10% 10%
U20F
CPLD_TDI 1
19[4A] CPLD_TDI IO/TDI
CPLD_TDO 32
19[3C] CPLD_TDO IO/TDO
FPGA_TCK 26 U20H
19[3C] FPGA_TCK IO/TCK
FPGA_TMS 7 4 16
19[3C] FPGA_TMS IO/TMS GNDIO GNDINT
11 36
GNDIO GNDINT
EPM3064ATC44-4 24
GNDIO
30
GNDIO
EPM3064ATC44-4
D D
FPGA_CONFIG
Title
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 14 of 20
1 2 3 4 5 6 7 8
4-36 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U13A U13B
T3 C4
IO, LVDS0n IO, LVDS24p (DEV_CLRn)
BANK 1
BANK 2
T2 B3
IO, LVDS0p IO, LVDS24n (DEV_OE)
R3 B4
R2 A4
A P4 D5 A
R1 C5
IO, VREF2B1 IO, LVDS27n (DQ1T4)
P3 G8
P2 F8
P5 TXEN_N B5
IO, DPCLK0 (DQS1L) TXEN_N 21[4B] IO, DPCLK2 (DQS1T)
N4 CARDET A6
IO, LVDS3n (DQ1L5) CARDET 21[6D] IO, VREF2B2
N3 VLTN C6 CYSC_D
IO, LVDS3p (DQ1L4) VLTN 21[6C] IO, LVDS28p CYSC_D 21[1C]
N6 RXSC_D B6
IO, LVDS4n RXSC_D 21[6C] IO, LVDS28n
N5 RXCLK D6
IO, LVDS4p RXCLK 21[6C] IO, LVDS29p
N7 LFI_N E6 TCMD[3..0]
IO, LVDS5n LFI_N 21[6D] IO, LVDS29n TCMD[3..0] 21[1C]
M6 C7 TCMD0
N2 D7 TCMD1
N1 B7 TCMD2
IO, LVDS6p IO, LVDS31p (DQ1T3)
M4 A7 TCMD3
IO, LVDS7n IO, LVDS31n (DQ1T2)
M5 RCMD[3..0] E7
IO, LVDS7p (DQ1L3) RCMD[3..0] 21[5C] IO, LVDS32p (DQ1T1)
M2 RCMD3 E8
IO, LVDS8n (DQ1L2) IO, LVDS32n (DQ1T0)
M3 RCMD2 B8
IO, LVDS8p (DQ1L1) IO, LVDS33p
M1 RCMD1 A8 TXDATA[7..0]
IO (DQ1L0) IO, LVDS33n TXDATA[7..0] 21[1C]
L4 RCMD0 C8 TXDATA7
L5 D8 TXDATA6
L3 B9 TXDATA5
L2 A9 TXDATA4
L6 RXDATA[7..0] C9 TXDATA3
IO, LVDS11n RXDATA[7..0] 21[5C] IO, LVDS36p
L7 RXDATA7 D9 TXDATA2
IO, LVDS11p (DM1L) IO, LVDS36n (DM1T)
K5 R94 33.2 TXCLK E10
IO, PLL1_OUTn TXCLK 21[1C] IO, VREF1B2
K4 R74 33.2 0.1W TAXI_CLK_22M F9 TXDATA1
IO, PLL1_OUTp TAXI_CLK_22M 21[1C] IO, LVDS37p
K6 0.1W G9 TXDATA0
IO (ASDO) IO, LVDS37n
J1 A10
IO (nCSO) IO, LVDS38p
B H6 B10 B
IO, VREF1B1 IO, LVDS38n
H5 RXDATA6 D10
IO, LVDS12n (DM0L) IO, LVDS39p
H4 RXDATA5 C10
H3 RXDATA4 E11 FPGA_LED[23..0]
IO, LVDS13n IO FPGA_LED[23..0] 20[1A]
H2 RXDATA3 A11 FPGA_LED23
IO, LVDS13p IO, LVDS40p (DM0T)
H1 RXDATA2 B11 FPGA_LED22
IO (DQ0L7) IO, LVDS40n
G6 RXDATA1 D11 FPGA_LED21
G5 RXDATA0 C11 FPGA_LED20
G4 A12 FPGA_LED19
G3 B12 FPGA_LED18
F7 C12 FPGA_LED17
F6 D12 FPGA_LED16
G2 C13 FPGA_LED15
G1 D13 FPGA_LED14
F5 A13 FPGA_LED13
F4 B13 FPGA_LED12
F3 F10 FPGA_LED11
F2 G10 FPGA_LED10
E5 FPGA_TP7 F11 FPGA_LED3
E4 FPGA_TP6 G11 FPGA_LED2
F1 FPGA_TP5 E13 FPGA_LED9
IO, DPCLK1 (DQS0L) IO
E2 FPGA_TP4 C14
IO, LVDS21n (DQ0L1) IO, VREF0B2
E3 FPGA_TP3 3V3 B14 FPGA_LED8
IO, LVDS21p (DQ0L0) IO, DPCLK3 (DQS0T)
D1 FPGA_TP2 D14 FPGA_LED7
D4 C15 FPGA_LED6
IO, VREF0B1 R72 IO, LVDS47n (DQ0T2)
D2 FPGA_TP1 A15 FPGA_LED5
IO, LVDS22n 10K IO, LVDS48p (DQ0T1)
D3 B15 FPGA_LED4
IO, LVDS22p (CLKUSR) 0.1W IO, LVDS48n (DQ0T0)
C2 FPGA_TP0 1% B16 FPGA_LED1
C IO, LVDS23n (CRC_ERROR) IO, LVDS50p C
C3 INIT_DONE C16 FPGA_LED0
IO, LVDS23p (INIT_DONE) INIT_DONE 16[3C] IO, LVDS50n
EP1C12F324C8 EP1C12F324C8
104 3V3
50V
C86 10% FPGA_TP0 : A_TRIG_TOGGLE
FPGA_TP1 : B_TRIG_TOGGLE
U14 FPGA_TP2 : A_TOGGLE_CPU
20
74LVC244A J9 FPGA_TP3 : B_TOGGLE_CPU

FPGA_TP7 2 18 FPGA_TP4 : IRQ3_INT_A_TP
1A0 1Y0 1 2
VCC
FPGA_TP6 4 16 FPGA_TP5 : IRQ3_INT_B_TP

1A1 1Y1 3 4
FPGA_TP5 6 14 FPGA_TP6 : IRQ4_N
1A2 1Y2 5 6
FPGA_TP4 8 12 FPGA_TP7 : XRAY_ON_TP
1A3 1Y3 7 8
1 SAFETY_LOOP_OPEN_N
1OE 9 10
FPGA_TP3 17 3 MPC_BUF_OVERRUN
2A0 2Y0 11 12
FPGA_TP2 15 5 DEBUG_TRIGGER
2A1 2Y1 13 14
FPGA_TP1 13 7
2A2 2Y2 15 16
FPGA_TP0 11 9
GND
2A3 2Y3
19 Header 8X2
2OE
R73
10
1K
0.1W
1%
D D
Title
FPGA 1 of 3
ONLY FOR DEBUG DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 15 of 20
1 2 3 4 5 6 7 8
GANTRY 4-37
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
U13C U13D
D17 TO_CPLD_1 T15 NAND_CE_N
IO, LVDS51p TO_CPLD_1 2[6B] IO, LVDS76n NAND_CE_N 2[6B]
BANK 3
BANK 4
C17 TO_CPLD_2 U16 NAND_RE_N
IO, LVDS51n TO_CPLD_2 2[6B] IO, LVDS76p NAND_RE_N 2[6B]
D15 U15 NAND_WE_N
IO, LVDS52p IO, LVDS78n (DQ0B0) NAND_WE_N 2[6B]
D16 V15 NAND_CLE
A IO, LVDS52n IO, LVDS78p (DQ0B1) NAND_CLE 2[6B] A
E14 R14 NAND_ALE
IO, VREF0B3 IO, LVDS79n (DQ0B2) NAND_ALE 2[6B]
D18 T14 NAND_R/B#
IO (DQ0R0) IO, LVDS79p (DQ0B3) NAND_R/B# 2[6B]
E15 U14
IO, LVDS53p (DQ0R1) IO, DPCLK6 (DQS0B)
E16 P13
IO, LVDS53n (DQ0R2) IO, VREF0B4
E17 B_PORST_N N11
IO, DPCLK4 (DQS0R) B_PORST_N 2[5B] IO, LVDS77p
F15 M11
IO, LVDS54p (DQ0R3) IO, LVDS77n
F16 P12
IO, LVDS54n IO
F14 N10

F13 M10
F17 R13
F18 T13
F12 U13
G12 V13
G16 R12
G15 T12
G14 U12 SAFETY_LOOP_OPEN
IO, LVDS59p IO, LVDS84n SAFETY_LOOP_OPEN 2[5B]
G13 V12 RESET_N_BY_JIG
IO, LVDS59n (DQ0R4) IO, LVDS84p RESET_N_BY_JIG 2[5B]
G17 V11 SIMU_XRAY_ON_OUT
IO, LVDS60p (DQ0R5) IO, LVDS85n SIMU_XRAY_ON_OUT 2[5B]
G18 U11
IO, LVDS60n (DQ0R6) IO, LVDS85p (DM0B)
H18 T11 XRAY_ON_IN
IO (DQ0R7) IO, LVDS86n XRAY_ON_IN 2[6B]
H17 R11
H16 P10 WD_RST_N
IO, LVDS61n IO WD_RST_N 2[6B]
H15 R10 ENWDT_N
IO, LVDS62p IO, LVDS87n ENWDT_N 2[6B]
H14 T10 FEEDWDT_N
IO, LVDS62n IO, LVDS87p FEEDWDT_N 2[6B]
H13 V10 DISWDT_N
IO, LVDS63p (DM0R) IO, LVDS88n DISWDT_N 2[6B]
J13 U10
J14 P9 DSREQ_AB_INT
IO, VREF1B3 IO, VREF1B4 DSREQ_AB_INT 2[6B]
K15 T9 DTB_INT
B IO, PLL2_OUTp IO, LVDS90n DTB_INT 2[6B] B
K16 R9 ERROR_A-B_INT
IO, PLL2_OUTn IO, LVDS90p (DM1B) ERROR_A-B_INT 2[6B]
L14 M9
IO IO, LVDS89p
L15 N9
L16 V9
IO, LVDS64n (DM1R) IO, LVDS91n
L13 U9
M13 R8
L17 BA[22..0] T8 RCS1_N
IO, LVDS66p BA[22..0] 2[5B] IO, LVDS92p RCS1_N 2[6B]
L18 BA13 V8 AS_N
IO, LVDS66n IO, LVDS93n AS_N 2[5B]
M16 BA12 U8 RCS2_N
IO (DQ1R0) IO, LVDS93p RCS2_N 2[5B]
M15 BA11 R7 RCS3_N
IO, LVDS67p (DQ1R1) IO, LVDS94n (DQ1B0) RCS3_N 2[5B]
M14 BA10 T7 BFOE_N
IO, LVDS67n (DQ1R2) IO, LVDS94p (DQ1B1) BFOE_N 2[5B]

M17 BA9 V7 BWE_N
IO, LVDS68p (DQ1R3) IO, LVDS95n (DQ1B2) BWE_N 2[5B]
M18 BA8 U7 BD15
N15 BA7 R6 BD14
N16 BA6 T6 BD13
N12 BA5 P7 BD12
N13 BA4 P6 BD11
N17 BA3 U6 BD10
N18 BA2 V6 BD9
N14 BA1 M8 BD8
IO, LVDS72p (DQ1R4) IO, LVDS101p
P14 BA0 N8 BD7
P15 R5
IO, DPCLK5 (DQS1R) IO, VREF2B4
P17 R4 BD6
IO (DQ1R6) IO, DPCLK7 (DQS1B)
P16 U5 BD5
IO, VREF2B3 IO, LVDS99n (DQ1B6)
R16 T5 BD4
IO, LVDS73p IO, LVDS99p (DQ1B7)
R15 U4 BD3
R18 SW_D T4 BD2
C R17 SW_C V4 BD1 C
T17 SW_B U3 BD0
T16 SW_A BD[0..15]
IO, LVDS75n BD[0..15] 2[5B]
EP1C12F324C8
EP1C12F324C8
RP44
5 4
6 3
7 2
8 1
3V3
10K
8
7
6
5
0.063W S1
5% CHS-04TB
1
2
3
4
D D
Title
FPGA 2 of 3
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 16 of 20
1 2 3 4 5 6 7 8
4-38 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
3V3 1V5
U13F U13G 1V5

L3 22N
E1 A17 A1 K11
G7 A2 A16 K8 U13E C87 C89 C92 C94
M7 B1 A18 K9 FPGA_TDI J17 105 2.2u 104 103 U13H
A VCCIO1 VCCINT GND GND TDI 16V 16V 16V 50V A
P1 B18 A3 L10 CPLD_TDI K13 10% 10% J5 K1
VCCIO1 VCCINT GND GND 16[3C] CPLD_TDI TDO 10% 10% VCCA_PLL1 GNDA_PLL1
H10 B17 L11 FPGA_TCK K18 J6
VCCINT GND GND TCK GNDG_PLL1
A14 J9 B2 L8 FPGA_TMS K14
VCCIO2 VCCINT GND GND TMS
A5 K10 C1 T1 J12 J18
VCCIO2 VCCINT GND GND 10K VCCA_PLL2 GNDG_PLL2
E12 L9 C18 T18 R84 K3 K12
VCCIO2 VCCINT GND GND 3V3 MSEL0 GNDA_PLL2
E9 U1 H11 U17 R86 1K K7
VCCIO2 VCCINT GND GND 0.1W 0.1W MSEL1
U18 H8 U2 1V5 EP1C12F324C8
VCCINT GND GND 1% L4 22N
P18 V17 H9 V1 FPGA_DCLK 1% L1
VCCIO3 VCCINT GND GND 16[3A] FPGA_DCLK DCLK

M12 V2 J10 V16 FPGA_DATA0 H7 C88 C90 C91 C93
VCCIO3 VCCINT GND GND 16[3C] FPGA_DATA0 DATA0
H12 J11 V18 105 2.2u 104 103
VCCIO3 GND GND R87 16V 16V 16V 50V
E18 J8 V3 FPGA_CE_N J7
VCCIO3 GND GND nCE 10% 10% 10% 10%
10K K2
nCEO
V5 EP1C12F324C8 0.1W FPGA_CONFIG_N J2
VCCIO4 16[3C] FPGA_CONFIG_N
R85 nCONFIG
V14 1% FPGA_STATUS_N L12
VCCIO4 3V3 nSTATUS
P8 10K K17
VCCIO4 CONF_DONE
P11 0.1W
VCCIO4
1% EP1C12F324C8
EP1C12F324C8
16[3C] FPGA_STATUS_N U13I
FPGA_CONF_DONE
16[3C] FPGA_CONF_DONE CLK_33M J3
6[5C] CLK_33M CLK0, LVDSCLK1p
3V3 (FPGA I/O 3.3V 0.1U) AS_N_CLK J4
8[6C] AS_N_CLK CLK1, LVDSCLK1n
J15
CLK2, LVDSCLK2p
J16
3V3 X2 CLK3, LVDSCLK2n
C172 C177 C183 C189 C195 C201 C207 C213 C219 C225 C231 C237
8 1
104 103 104 103 104 103 104 103 104 103 104 103 VCC NC EP1C12F324C8
16V 50V 16V 50V 16V 50V 16V 50V 16V 50V 16V 50V C170
104 R95 R96 R240 R97
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 16V 1K 1K
4 5 R239 1K 1K
10% GND OUT 0.1W 0.1W 0.1W 0.1W
B 1% 1% 1% 1% B
1V5 (FPGA INT 1.5V 0.1U) 51.1
44MHz 0.1W
GND
1%
C174 C178 C184 C190 C196 C202 C208 C214 C220
104 103 104 103 104 103 104 103 104
16V 50V 16V 50V 16V 50V 16V 50V 16V
10% 10% 10% 10% 10% 10% 10% 10% 10%
R96\R95\R240 NOT
GND
MOUNTED
3V3
R80 R82
10K 10K
0.1W 0.1W
1% 1%
J7
FPGA_TCK
2 1 FPGA_TCK 16[3D]
CPLD_TDO
3V3 4 3 CPLD_TDO 16[3C]
FPGA_TMS
6 5 FPGA_TMS 16[3D]
R77 10K 8 7
0.1W FPGA_TDI
1% 10 9
Header 5X2 R81
C FPGA JTAG HEADER 10K C
0.1W
1%
D D
Title
FPGA 3 of 3
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 17 of 20
1 2 3 4 5 6 7 8
GANTRY 4-39
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
A A
FPGA_LED[23..0] 3V3
17[6B] FPGA_LED[23..0]
R130 DS17
1/2 SLICE
3V3 511
R112 DS1 0.1W
VLTN 1%
511 HSMG-C190
0.1W
1% HSMG-C190 R131 DS18
HEART_BEAT
511
R113 DS2 0.1W
REQ_A 1%
511 HSMG-C190
0.1W
1% HSMG-C190
104 104 3V3
50V 3V3 50V R132 DS19
10% BUFF_OVERRUN
C107 R114 DS3 C109 10% 511
READ_A
511 0.1W
U21 0.1W U23 1% HSMG-C190
20
20
74LVC244A 1% HSMG-C190 74LVC244A
1A0 1Y0 1A0 1Y0 SCAN_ABORT
VCC
VCC
FPGA_LED1 4 16 R115 DS4 FPGA_LED17 4 16 511
1A1 1Y1 VIEW_A 1A1 1Y1
FPGA_LED2 6 14 511 FPGA_LED18 6 14 0.1W
1A2 1Y2 1A2 1Y2 1%
FPGA_LED3 8 12 0.1W FPGA_LED19 8 12 HSMG-C190
1A3 1Y3 1% 1A3 1Y3
1 HSMG-C190 1
1OE 1OE
2A0 2Y0 2A0 2Y0
2A1 2Y1 R116 DS5 2A1 2Y1
FPGA_LED6 13 7 END_NG_A FPGA_LED22 13 7
2A2 2Y2 511 2A2 2Y2
GND
GND
2A3 2Y3 0.1W 2A3 2Y3 NFS
19 1% 19 511
B 2OE HSMG-C190 2OE B
0.1W
R108 R110 R128 R129 1% HSMG-C190
R117 DS6
10
10
1K 1K FIFO_FULL_A 1K 1K
0.1W 0.1W 511 0.1W 0.1W R135 DS22
1% 1% 0.1W 1% 1% OTHER ERR
1% HSMG-C190 511
0.1W
1% HSMG-C190
R118 DS7
FEC_ERR_A
511 R136 DS23
0.1W HEART_BEAT
1% HSMG-C190 511
0.1W
1% HSMG-C190
R119 DS8
CONTINUE_ERR_A
511 R137 DS24
0.1W SAFETY_LOOP_TST
1% HSMG-C190 511
0.1W
1% HSMG-C190
R120 DS9
CLR_A/B
511
0.1W
1% HSMG-C190
R121 DS10
REQ_B
511
C 0.1W C
104 1% HSMG-C190
50V 3V3
C108 10%
R122 DS11
READ_B
U22 511
20
74LVC244A 0.1W
1% HSMG-C190
FPGA_LED8 2 18
1A0 1Y0
VCC
FPGA_LED9 4 16
1A1 1Y1 R123 DS12
FPGA_LED10 6 14 VIEW_B
1A2 1Y2 511
FPGA_LED11 8 12
1A3 1Y3 0.1W
1 1%
1OE HSMG-C190
FPGA_LED12 17 3
2A0 2Y0
FPGA_LED13 15 5
2A1 2Y1 R124 DS13
FPGA_LED14 13 7 END_NG_B
2A2 2Y2 511
FPGA_LED15 11 9
GND
2A3 2Y3 0.1W

19 1%
2OE HSMG-C190
R109 R111
R125 DS14
10
1K 1K FIFO_FULL_B
0.1W 0.1W 511
1% 1% 0.1W
1% HSMG-C190
R126 DS15
FEC_ERR_B
511
0.1W
1% HSMG-C190
D R127
511
0.1W
1%
DS16
HSMG-C190
CONTINUE_ERR_B
Title
LEDS D
DTB
A3 5270966-2 REV : 1
Date: 2010/1/12 Sheet 18 of 20
1 2 3 4 5 6 7 8
4-40 GANTRY
Brivo CT315
Brivo CT325
REV 5 5306515-1EN
1 2 3 4 5 6 7 8
R104 1K
0.1W
1% RP37
RXDATA0 5 4 R33 TCMD0
R100 1K RXDATA1 6 3
0.1W 4K7
1% RXDATA2 7 2
0.1W
RXDATA3 8 1 1%
R106 1K
VCC
0.1W 10K R34
1% 0.063W TCMD1
R198 1K 5% VCC 4K7
VCC
A 0.1W 0.1W A
1% RP38 1%
RXDATA4 5 4
R199 1K R35
VCC RXDATA5 6 3 TCMD2
0.1W
1% RXDATA6 7 2
RXDATA7 8 1 4K7
1K 0.1W
VCC R200 1%
0.1W 10K
1% 0.063W R36 TCMD3
R203 1K 5%
VCC
0.1W 4K7
1% RP39
RCMD1 5 4 0.1W
1K 1%
VCC R204 RCMD0 6 3
0.1W
RCMD2 7 2
1%
RCMD3 8 1
NOT MOUNTED
R205 1K
VCC
0.1W 10K
1% 0.063W
R206 1K 5%
VCC
0.1W
B_PORST_N 13[3C], 16[3C], 18[3A], 9[6B]

1%
R207 1K R40 R44
SERIALIN_P SERIALOUT_N
0.1W
1% 130 130
0.1W R42 0.1W R46
R208 1K 1% 84.5 1% 84.5
0.1W 0.1W 0.1W
1% 1% 1%
C56 C59
R209 1K

BRIVO CT315/325 Schematic Diagrams: GE Healthcare

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BRIVO CT315/325 Schematic Diagrams: GE Healthcare

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GE Healthcare

• THIS SERVICE MANUAL IS AVAILABLE IN ENGLISH ONLY.

ATTENTION • Ce manuel de service n'est disponible qu'en anglais.

ATENÇÃO • Este manual de assistência técnica só se encontra disponível em inglês.

ОСТОРОЖНО! • Данное руководство по обслуживанию предлагается только на

ATENCION • Este manual de servicio sólo existe en inglés.

DIKKAT • Bu servis kilavuzunun sadece ingilizcesi mevcuttur.

경고 • 본 서비스 지침서는 영어로만 이용하실 수 있습니다 .

ATENŢIE • Acest manual de service este disponibil numai în limba engleză.

IMPORTANT! . . . X-RAY PROTECTION

LITHIUM BATTERY CAUTIONARY STATEMENTS

OMISSIONS & ERRORS

PDU Added new section for Adapter. (Sec. 3)

4 01/17/2011 Gantry Updated DTB BD Assy SCH figure. (Sec. 4)

Added new Gantry Assy SCH figure for EMC. (Sec. 1)

DAS Updated GDAS Convertor PWA from 2364354 to 5955032. (Sec. 2)

PDU Added RMT Control Loop figure. (Sec. 1)

2 11/06/2009 Gantry Updated TGP Board SCH figure. (Sec. 2)

DAS Updated DAS PS figure. (Sec. 3)

1 07/22/2009 Initial release.

SECTION 1 - SYSTEM ASSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SECTION 1 - SYSTEM ASSY

1-1 SYSTEM POWER & GROUND CABLING

1-2 SYSTEM SIGNAL CABLING

Comm Line Table.RL2

DTB.J3 DAS Data (CAT5)

SECTION 1 - OC ASSY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SECTION 2 - SCAN CONTROL BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Scan Control Box

SECTION 2 - SCAN CONTROL BOX

B ------ 12-SEP-08 --- VISION STATUS OF THE ENTIRE DOCUMENT.

Mon Apr 27 13:28:53 2009 scancontrolbox 1 of 16 5337819SCH 3 1 of 16

4A1> OGCOM_H 3 3 4 4 OGCOM_L 4A1> 4C5> OCMIC_N 2 2 17C7> OCSPEAK_N 2 2

14B6> PATVOL_B_F 2 S 5 16B7> OCVOL_B_F 2 S 5

Wed Apr 22 13:35:54 2009 scancontrolbox 2 of 16 5337819SCH 3 2 of 16

Approved Document - 5337819SCH_r3.pdf Page 3 of 17

SERVICE AND DEBUG

1.1A RSV 10 9 FPGA_ASD

7C6> USB_AD1 1 2 GO_RXD 8D1> 12C2< S1 R38 AS CONFIGRATION

12C6> 4A3< OGCOM_H_F 1 2 GOCOM_H_F 4A3> 12A1< RSV GND

JD11 OG_TXD_T 1 2 OG_TXD

Wed Apr 22 13:36:03 2009 scancontrolbox 3 of 16 5337819SCH 3 3 of 16

Approved Document - 5337819SCH_r3.pdf Page 4 of 17

FL5 BLM18PG221SN1 FL23

2C6< OCVOL_A 1 2 OCVOL_A_F 16B7>

Thu Mar 26 19:53:58 2009 scancontrolbox 4 of 16 5337819SCH 3 4 of 16

Approved Document - 5337819SCH_r3.pdf Page 5 of 17

DIGITAL POWER& RESET

3 VIN VOUT1 2 8 VIN VOUT 2

0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U

25V 25V 25V 25V 25V 25V 25V 25V

DECOUPLING CAPACITORS FOR FPGA

Fri Jan 16 09:59:26 2009 scancontrolbox 5 of 16 5337819SCH 3 5 of 16

Approved Document - 5337819SCH_r3.pdf Page 6 of 17

MH3 MH5 MH9 MH12 MH16 MH19 MH26

MH32 MH33 MH34 MH41 MH40

MH1 MH8 MH15 MH28 MH27 MH22 MH29 MH35

Thu Apr 02 00:08:03 2009 scancontrolbox 6 of 16 5337819SCH 3 6 of 16

Approved Document - 5337819SCH_r3.pdf Page 7 of 17

USB AND UART INTERFACE

AD0 24 USB_AD0 3B1<

VCC BD0 8D5<

BD1 39 USB_D1 8D5<

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