DIGITAL AUDIO MOSFET IRF6775MTRPbF

Features Key Parameters

• Latest MOSFET Silicon technology VDS 150 V
m:
• Key parameters optimized for Class-D audio amplifier
applications
RDS(on) typ. @ VGS = 10V 47
• Low RDS(on) for improved efficiency Qg typ. 25.0 nC
• Low Qg for better THD and improved efficiency
RG(int) max. 3.0
• Low Qrr for better THD and lower EMI
• Low package stray inductance for reduced ringing and lower EMI
• Can deliver up to 250W per channel into 4Ω Load in
Half-Bridge Configuration Amplifier 5
• Dual sided cooling compatible & ) &
5
· Compatible with existing surface mount technologies
· RoHS compliant containing no lead or bromide
·Lead-Free (Qualified up to 260°C Reflow) DirectFET™ ISOMETRIC
MZ
Applicable DirectFET Outline and Substrate Outline (see p. 6, 7 for details)
SQ SX ST SH MQ MX MT MN MZ
Description
This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the
latest processing techniques to achieve low on-resistance per silicon area. Furthermore, gate charge, body-diode reverse
recovery and internal gate resistance are optimized to improve key Class-D audio amplifier performance factors such as
efficiency, THD, and EMI.

The IRF6775MPbF device utilizes DirectFETTM packaging technology. DirectFETTM packaging technology offers lower parasitic
inductance and resistance when compared to conventional wirebonded SOIC packaging. Lower inductance improves EMI
performance by reducing the voltage ringing that accompanies fast current transients. The DirectFETTM package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection
soldering techniques, when application note AN-1035 is followed regarding the manufacturing method and processes. The
DirectFETTM package also allows dual sided cooling to maximize thermal transfer in power systems, improving thermal resis-
tance and power dissipation. These features combine to make this MOSFET a highly efficient, robust and reliable device for
Class-D audio amplifier applications.

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 150 V
VGS Gate-to-Source Voltage ± 20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 28
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V 4.9 A
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V 3.9
IDM Pulsed Drain Current c 39
PD @TC = 25°C Maximum Power Dissipation 89 W
PD @TA = 25°C Power Dissipation e 2.8
PD @TA = 70°C Power Dissipation e 1.8
EAS Single Pulse Avalanche Energy d 33 mJ
IAR Avalanche Current c 5.6 A
Linear Derating Factor e 0.022 W/°C
TJ Operating Junction and -40 to + 150 °C
TSTG Storage Temperature Range
Thermal Resistance
Parameter Typ. Max. Units
RθJA Junction-to-Ambient ek ––– 45 °C/W
RθJA Junction-to-Ambient hk 12.5 –––
RθJA Junction-to-Ambient ik 20 –––
RθJC Junction-to-Case jk ––– 1.4
RθJ-PCB Junction-to-PCB Mounted 1.4 –––
Notes  through ‰ are on page 2

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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.17 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 47 56 mΩ VGS = 10V, ID = 5.6A f
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 100μA
IDSS Drain-to-Source Leakage Current ––– ––– 20 μA VDS = 150V, VGS = 0V
––– ––– 250 VDS = 120V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG(int) Internal Gate Resistance ––– ––– 3.0 Ω

Dynamic @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 11 ––– ––– S VDS = 50V, ID = 5.6A
Qg Total Gate Charge ––– 25 36 VDS = 75V
Qgs1 Pre-Vth Gate-to-Source Charge ––– 5.8 ––– VGS = 10V
Qgs2 Post-Vth Gate-to-Source Charge ––– 1.4 ––– ID = 5.6A
Qgd Gate-to-Drain Charge ––– 6.6 ––– nC See Fig. 6 and 17
Qgodr Gate Charge Overdrive ––– 11 –––
Qsw Switch Charge (Qgs2 + Qgd) ––– 8.0 –––
td(on) Turn-On Delay Time ––– 5.9 ––– VDD = 75V
tr Rise Time ––– 7.8 ––– ID = 5.6A
td(off) Turn-Off Delay Time ––– 5.8 ––– ns RG = 6.0Ω
tf Fall Time ––– 15 ––– VGS = 10V f
Ciss Input Capacitance ––– 1411 ––– VGS = 0V
Coss Output Capacitance ––– 193 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 40 ––– pF ƒ = 1.0MHz
Coss Output Capacitance ––– 1557 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 93 ––– VGS = 0V, VDS = 120V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 175 ––– VGS = 0V, VDS = 0V to 120V g
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 28 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 39 integral reverse G

(Body Diode)c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 5.6A, VGS = 0V f
trr Reverse Recovery Time ––– 62 ––– ns TJ = 25°C, IF = 5.6A, VDD = 25V
Qrr Reverse Recovery Charge ––– 164 ––– nC di/dt = 100A/μs f

Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.53mH, RG = 25Ω, IAS = 11.2A.
ƒ Surface mounted on 1 in. square Cu board.
„ Pulse width ≤ 400μs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80% VDSS.
† Used double sided cooling , mounting pad with large heatsink.
‡ Mounted on minimum footprint full size board with
metalized back and with small clip heatsink.
ˆ TC measured with thermal couple mounted to top
(Drain) of part.
‰ Rθ is measured at TJ of approximately 90°C.

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 IRF6775MTRPbF
100 100
VGS VGS
TOP 15V TOP 15V
10V 10V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

9.0V 9.0V
8.0V 8.0V
7.0V 7.0V
6.5V 6.5V
6.0V 6.0V
BOTTOM 5.5V BOTTOM 5.5V

10 10

5.5V

5.5V

≤ 60μs PULSE WIDTH ≤ 60μs PULSE WIDTH

Tj = 25°C Tj = 150°C
1 1
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 2.5
ID = 5.6A

RDS(on) , Drain-to-Source On Resistance

VDS = 25V
≤ 60μs PULSE WIDTH VGS = 10V
ID, Drain-to-Source Current(Α)

10 2.0

(Normalized)

1 1.5

TJ = 150°C
0.1 TJ = 25°C 1.0
TJ = -40°C

0.01
0.5
3.0 4.0 5.0 6.0 7.0 8.0
-60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 20
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED ID= 5.6A
VGS, Gate-to-Source Voltage (V)

Crss = Cgd VDS= 120V

16 VDS= 75V
10000 Coss = Cds + Cgd
VDS= 30V
C, Capacitance (pF)

12
Ciss
1000

8
Coss
100
4
Crss

10 0
1 10 100 1000 0 10 20 30 40

VDS , Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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100 100
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)

ID, Drain-to-Source Current (A)

100μsec
10 10

1msec
TJ = 150°C
DC
1 TJ = 25°C 1
TJ = -40°C
Tc = 25°C
Tj = 150°C 10msec
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 0.1 1 10 100 1000
VSD , Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area
30 5.0

VGS(th) Gate threshold Voltage (V)

25 4.5 ID = 100μA
ID = 250μA
ID , Drain Current (A)

20 4.0

15 3.5

10 3.0

5 2.5

0 2.0
25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150

TC , CaseTemperature (°C) TJ , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature

100

D = 0.50
10 0.20
Thermal Response ( Z thJA )

0.10
0.05
1 0.02
0.01
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
τJ τA 1.2801 0.000322
τJ τA
0.1 τ1 τ2 τ3 τ4 8.7256 0.164798
τ1 τ2 τ3 τ4
21.750 2.25760
Ci= τi/Ri 13.251 69
Ci= τi/Ri
SINGLE PULSE
0.01
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient ƒ

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 IRF6775MTRPbF
100

RDS (on) , Drain-to-Source On Resistance (mΩ)

( Ω)
140
VGS = 10V
RDS (on), Drain-to -Source On Resistance m
ID = 5.6A
90
120
TJ = 125°C
80
100
TJ = 125°C
70

80
60

60 TJ = 25°C
50
TJ = 25°C

40
40
4 6 8 10 12 14 16
0 5 10 15 20
VGS, Gate-to-Source Voltage (V) ID , Drain Current (A)

Fig 12. On-Resistance vs. Gate Voltage Fig 13. On-Resistance vs. Drain Current

15V 140

EAS, Single Pulse Avalanche Energy (mJ)

I D
120 TOP 1.1A
L DRIVER 1.4A
VDS
100 BOTTOM 11A

RG D.U.T +
V
- DD
80
IAS A
VGS
20V
tp 0.01Ω 60

Fig 15a. Unclamped Inductive Test Circuit 40

20
V(BR)DSS
tp 0
25 50 75 100 125 150

Starting TJ, Junction Temperature (°C)

Fig 14. Maximum Avalanche Energy vs. Drain Current

I AS

Fig 15b. Unclamped Inductive Waveforms

RD
VDS

VDS
VGS
D.U.T. 90%
RG
+
- VDD
10%
10V VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 % td(on) tr td(off) tf

Fig 16a. Switching Time Test Circuit Fig 16b. Switching Time Waveforms
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 IRF6775MTRPbF

Id
Vds

Vgs

L
VCC
DUT
0
Vgs(th)
1K
S
20K

Qgodr Qgd Qgs2 Qgs1

Fig 17a. Gate Charge Test Circuit Fig 17b. Gate Charge Waveform

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+
***
VGS=10V
ƒ Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD
*
RG • dv/dt controlled by RG VDD Re-Applied
+
• Driver same type as D.U.T. ** Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* Use P-Channel Driver for P-Channel Measurements *** VGS = 5V for Logic Level Devices
** Reverse Polarity for P-Channel

Fig 18. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

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DirectFET™ Substrate and PCB Layout, MZ Outline
(Medium Size Can, Z-Designation).
Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This
includes all recommendations for stencil and substrate designs.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

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 IRF6775MTRPbF
DirectFET™ Outline Dimension, MZ Outline
(Medium Size Can, Z-Designation).
Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This
includes all recommendations for stencil and substrate designs.

DIMENSIONS
METRIC IMPERIAL
CODE MIN MAX MAX MAX
A 6.25 6.35 0.246 0.250
B 4.80 5.05 0.189 0.201
C 3.85 3.95 0.152 0.156
D 0.35 0.45 0.014 0.018
E 0.68 0.72 0.027 0.028
F 0.68 0.72 0.027 0.028
G 0.93 0.97 0.037 0.038
H 0.63 0.67 0.025 0.026
J 0.28 0.32 0.011 0.013
K 1.13 1.26 0.044 0.050
L 2.53 2.66 0.100 0.105
M 0.616 0.676 0.0235 0.0274
R 0.020 0.080 0.0008 0.0031
P 0.08 0.17 0.003 0.007
DirectFET™ Part Marking
GATE MARKING

LOGO
PART NUMBER
BATCH NUMBER

DATE CODE
Line above the last character of
the date code indicates "Lead-Free"

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

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 IRF6775MTRPbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).

NOTE: Controlling dimensions in mm

Std reel quantity is 4800 parts. (ordered as IRF6775TRPBF). For 1000 parts on 7"
reel, order IRF6775TR1PBF
REEL DIMENSIONS
STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 1000)
METRIC IMPERIAL METRIC IMPERIAL
CODE MIN MAX MIN MAX MIN MAX MIN MAX
A 330.0 N.C 12.992 N.C 177.77 N.C 6.9 N.C
B 20.2 N.C 0.795 N.C 19.06 N.C 0.75 N.C
C 12.8 13.2 0.504 0.520 13.5 12.8 0.53 0.50
D 1.5 N.C 0.059 N.C 1.5 N.C 0.059 N.C
E 100.0 N.C 3.937 N.C 58.72 N.C 2.31 N.C
F N.C 18.4 N.C 0.724 N.C 13.50 N.C 0.53
G 12.4 14.4 0.488 0.567 11.9 12.01 0.47 N.C
H 11.9 15.4 0.469 0.606 11.9 12.01 0.47 N.C

LOADED TAPE FEED DIRECTION

DIMENSIONS
METRIC IMPERIAL
NOTE: CONTROLLING
CODE MIN MAX MIN MAX
DIMENSIONS IN MM
A 7.90 8.10 0.311 0.319
B 3.90 4.10 0.154 0.161
C 11.90 12.30 0.469 0.484
D 5.45 5.55 0.215 0.219
E 5.10 5.30 0.201 0.209
F 6.50 6.70 0.256 0.264
G 1.50 N.C 0.059 N.C
H 1.50 1.60 0.059 0.063

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

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 IRF6775MTRPbF

Revision History
Date Comments
• Updated SOA curve figure 8 to extend x axis to 150V because this device is 150V, on page 4.
2/26/2014
• Updated datasheet with new IR corporate template.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/
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