PD - 97357

IRLB3036PbF
HEXFET® Power MOSFET
Applications
l DC Motor Drive D VDSS 60V
l High Efficiency Synchronous Rectification in SMPS
RDS(on) typ. 1.9mΩ
l Uninterruptible Power Supply
max. 2.4mΩ
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
ID (Silicon Limited) 270A c
S ID (Package Limited) 195A
Benefits
l Optimized for Logic Level Drive
l Very Low RDS(ON) at 4.5V VGS
l Superior R*Q at 4.5V VGS
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
TO-220AB
SOA
IRLB3036PbF
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) c
270
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) c
190
A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 195
IDM Pulsed Drain Current d 1100
PD @TC = 25°C Maximum Power Dissipation 380 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ±16 V
dv/dt Peak Diode Recovery f 8.0 V/ns
TJ Operating Junction and
-55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x x
10lb in (1.1N m)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 290 mJ
IAR Avalanche Current d A
EAR Repetitive Avalanche Energy g See Fig. 14, 15, 22a, 22b
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.40
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient (PCB Mount) jk ––– 62

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IRLB3036PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.061 ––– V/°C Reference to 25°C, ID = 5mA d
––– 1.9 2.4 VGS = 10V, ID = 165A g
RDS(on) Static Drain-to-Source On-Resistance
––– 2.2 2.8
mΩ
VGS = 4.5V, ID = 140A g
VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 VDS = 60V, VGS = 0V
µA
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
RG(int) Internal Gate Resistance ––– 2.0 ––– Ω

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 340 ––– ––– S VDS = 10V, ID = 165A
Qg Total Gate Charge ––– 91 140 ID = 165A
Qgs Gate-to-Source Charge ––– 31 ––– VDS = 30V
Qgd Gate-to-Drain ("Miller") Charge ––– 51 –––
nC
VGS = 4.5V g
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 40 ––– ID = 165A, VDS =0V, VGS = 4.5V
td(on) Turn-On Delay Time ––– 66 ––– VDD = 39V
tr Rise Time ––– 220 ––– ID = 165A
ns
td(off) Turn-Off Delay Time ––– 110 ––– RG = 2.1Ω
tf Fall Time ––– 110 ––– VGS = 4.5V g
Ciss Input Capacitance ––– 11210 ––– VGS = 0V
Coss Output Capacitance ––– 1020 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 500 ––– pF ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) i ––– 1430 ––– VGS = 0V, VDS = 0V to 48V i
Coss eff. (TR) Effective Output Capacitance (Time Related) h ––– 1880 ––– VGS = 0V, VDS = 0V to 48V h
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– MOSFET symbol D
270
(Body Diode) showing the
A
ISM Pulsed Source Current ––– ––– integral reverse G

(Body Diode) e 1100

p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 165A, VGS = 0V g
trr Reverse Recovery Time ––– 62 ––– TJ = 25°C VR = 51V,
ns
––– 66 ––– TJ = 125°C IF = 165A
Qrr Reverse Recovery Charge ––– 310 ––– TJ = 25°C di/dt = 100A/µs g
nC
––– 360 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 4.4 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
‚ Repetitive rating; pulse width limited by max. junction
temperature.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.021mH
RG = 25Ω, IAS = 165A, VGS =10V. Part not recommended for use
above this value .
„ ISD ≤ 165A, di/dt ≤ 430A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
† Coss eff. (TR) is a fixed capacitance that gives the same charging time as
Coss while VDS is rising from 0 to 80% VDSS.
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
‰ Rθ is measured at TJ approximately 90°C.

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 IRLB3036PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
4.5V 4.5V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

4.0V 4.0V
100 3.5V 3.5V
3.3V 3.3V
3.0V 3.0V
BOTTOM 2.7V BOTTOM 2.7V

10 100

1 2.7V
2.7V

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
0.1 10
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 165A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

T J = 175°C
100 2.0
(Normalized)

10 1.5

T J = 25°C
1 1.0

VDS = 25V
≤60µs PULSE WIDTH
0.1 0.5
1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100120140160180

VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 5.0
VGS = 0V, f = 1 MHZ
ID= 165A VDS= 48V
C iss = C gs + C gd, C ds SHORTED
C rss = C gd VDS= 30V
VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd
4.0

Ciss
C, Capacitance (pF)

10000
3.0

Coss
2.0
1000 Crss

1.0

100 0.0
1 10 100 0 20 40 60 80 100 120
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRLB3036PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

T J = 175°C
ISD, Reverse Drain Current (A)

100 1000
100µsec

1msec
10 T J = 25°C 100
Limited by
package
10msec
1 10
Tc = 25°C DC
Tj = 175°C
VGS = 0V Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

300 75
Id = 5mA

250 Limited By Package

70
ID, Drain Current (A)

200

150 65

100
60
50

0 55
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
3.0 1200
EAS , Single Pulse Avalanche Energy (mJ)

ID

2.5 TOP 27A

1000
50A
BOTTOM 165A
2.0 800
Energy (µJ)

1.5 600

1.0 400

0.5 200

0.0 0
-10 0 10 20 30 40 50 60 70 25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRLB3036PbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50

0.1 0.20

0.10 R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
τJ τC 0.01115 0.000009
0.05 τJ τ
τ1 τ2
0.08360 0.000080
τ1 τ3 τ4
τ2 τ3 τ4
0.01 0.02 0.18950 0.001295
0.01 Ci= τi/Ri
Ci i/Ri
0.11519 0.006726

Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000
Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Tj = 150°C and
Avalanche Current (A)

0.01 Tstart =25°C (Single Pulse)

100

0.05
0.10
10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

300 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
250 ID = 165A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
200
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
150 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
100 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
50 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRLB3036PbF
3.0 14
IF = 110A
VGS(th) , Gate threshold Voltage (V)

12 V R = 51V
2.5
TJ = 25°C
TJ = 125°C
10
2.0

IRRM (A)
8
ID = 250µA
1.5 ID = 1.0mA
ID = 1.0A 6

1.0
4

0.5 2
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 100 200 300 400 500
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

12 900
IF = 165A IF = 110A
800 V R = 51V
V R = 51V
10 TJ = 25°C
TJ = 25°C 700
TJ = 125°C TJ = 125°C
600
8
IRRM (A)

QRR (A)

500

6 400

300
4
200

2 100
0 100 200 300 400 500 0 100 200 300 400 500
diF /dt (A/µs) diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

600
IF = 165A
V R = 51V

500 TJ = 25°C
TJ = 125°C
QRR (A)

400

300

200
0 100 200 300 400 500
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRLB3036PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRLB3036PbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/2008
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